JP2005340663A - Capacitor - Google Patents

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JP2005340663A
JP2005340663A JP2004160099A JP2004160099A JP2005340663A JP 2005340663 A JP2005340663 A JP 2005340663A JP 2004160099 A JP2004160099 A JP 2004160099A JP 2004160099 A JP2004160099 A JP 2004160099A JP 2005340663 A JP2005340663 A JP 2005340663A
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capacitor
main surface
electrode
multilayer body
dummy
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Tadakatsu Asano
忠克 浅野
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Kyocera Corp
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Kyocera Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitor for reinforcing the adhesion strength of an external electrode by increasing an area for connecting a dummy electrode to the external electrode. <P>SOLUTION: In the capacitor, an internal electrode layer 2 is interposed between adjacent dielectric layers inside a laminate 1 in which a plurality of dielectric layers are laminated, an arc-shaped chamfering section is formed at the corner section between the side and main surface of the laminate 1, and the external electrode 3 connected to one end of the internal electrode layer 2 is deposited from the side to the main surface of the laminate 1. In the capacitor, the dummy electrode 5 for annularly exposing the outer-periphery section 6 is interposed at the chamfering section of the laminate 1, or from the chamfering section to the main surface between the dielectric layers positioned near the main surface of the laminate 1, and the external electrode 3 is connected to the entire exposed section of the dummy electrode 5. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、多連型積層セラミックコンデンサ等の高密度集積回路に用いられるコンデンサに関するものである。   The present invention relates to a capacitor used in a high-density integrated circuit such as a multi-layer monolithic ceramic capacitor.

従来より、高密度集積回路には多連型積層セラミックコンデンサ等のコンデンサが用いられている。   Conventionally, capacitors such as multi-layer monolithic ceramic capacitors have been used in high-density integrated circuits.

かかるコンデンサは、例えば、複数個の誘電体層を積層してなる積層体の内部で、隣接する誘電体層間に内部電極層を介在させるとともに、前記積層体の側面と主面との間の角部に断面円弧状の面取り部を形成し、前記積層体の側面から主面にかけて、前記内部電極層の一端に接続される外部電極を被着させた構造のものが知られている（例えば、特許文献１参照）。   Such a capacitor has, for example, an internal electrode layer interposed between adjacent dielectric layers in a multilayer body formed by laminating a plurality of dielectric layers, and an angle between a side surface and a main surface of the multilayer body. A chamfered portion having a circular arc cross section is formed in the portion, and an external electrode connected to one end of the internal electrode layer is attached from the side surface to the main surface of the laminate (for example, known) Patent Document 1).

尚、上述した従来のコンデンサは、積層体の主面近傍に位置する誘電体層間に、前記外部電極に接続されるダミー電極を介在させ、金属同士の結合を増やすことにより、積層体と外部電極との接着強度を強めるようにしている。   In the conventional capacitor described above, a dummy electrode connected to the external electrode is interposed between the dielectric layers located in the vicinity of the main surface of the multilayer body, and the coupling between the multilayer body and the external electrode is increased by increasing the bond between the metals. It is trying to strengthen the adhesive strength.

また、コンデンサの外部電極を形成する方法としては、積層体の表面に導出された内部電極層の一端及びダミー電極の一端を起点として無電解メッキ膜を析出させ、無電解メッキ膜を積層体の側面に連続的に形成する方法が知られている（例えば、特許文献２参照）。
特開平９−１２９４７６号公報 特開２００４−４００８５号公報 In addition, as a method of forming the external electrode of the capacitor, an electroless plating film is deposited starting from one end of the internal electrode layer and one end of the dummy electrode led to the surface of the multilayer body, and the electroless plating film is formed on the multilayer body. A method of continuously forming the side surface is known (see, for example, Patent Document 2).
JP-A-9-129476 Japanese Patent Laid-Open No. 2004-40085

しかしながら従来のコンデンサは、積層体の主面には内部電極層が導出していないので、積層体の主面における外部電極の接着強度が側面における接着強度に比して弱いものであった。   However, in the conventional capacitor, since the internal electrode layer is not led out to the main surface of the multilayer body, the adhesive strength of the external electrode on the main surface of the multilayer body is weaker than the adhesive strength on the side surface.

また、特に外部電極が無電解メッキ膜を含む場合、誘電体層と外部電極との結合を強くすることが困難であるため、積層体の主面における外部電極の接着強度は、外部電極と内部電極層との接続がないことから非常に弱くなり、回路基板上に半田等を介して搭載した場合の接着強度が不足することになる。   In particular, when the external electrode includes an electroless plating film, it is difficult to strengthen the bond between the dielectric layer and the external electrode. Therefore, the adhesion strength of the external electrode on the main surface of the laminate is Since there is no connection with the electrode layer, it becomes very weak, and the adhesive strength when mounted on the circuit board via solder or the like is insufficient.

本発明は、上述の問題点に鑑みて案出されたものであり、その目的は、ダミー電極と外部電極とを接続する面積を増やし外部電極の接着強度を強くしたコンデンサを提供することにある。   The present invention has been devised in view of the above-described problems, and an object thereof is to provide a capacitor in which the area for connecting the dummy electrode and the external electrode is increased and the adhesive strength of the external electrode is increased. .

本発明のコンデンサは、複数個の誘電体層を積層してなる積層体の内部で、隣接する誘電体層間に内部電極層を介在させるとともに、前記積層体の側面と主面との間の角部に曲面状の面取り部を形成し、前記積層体の側面から主面にかけて、前記内部電極層の一端に接続される外部電極を被着させたコンデンサにおいて、前記積層体の主面近傍に位置する誘電体層間に、前記積層体の面取り部、もしくは面取り部から主面にかけて外周部を環状に露出させたダミー電極を介在させるとともに、該ダミー電極の露出部全体にわたって前記外部電極を接続したことを特徴とするものである。   In the capacitor of the present invention, an internal electrode layer is interposed between adjacent dielectric layers inside a laminate formed by laminating a plurality of dielectric layers, and an angle between the side surface of the laminate and the main surface is set. In a capacitor in which a curved chamfered portion is formed in a part and an external electrode connected to one end of the internal electrode layer is attached from the side surface to the main surface of the multilayer body, the capacitor is positioned near the main surface of the multilayer body. A dummy electrode having an outer peripheral portion exposed annularly from the chamfered portion or the chamfered portion to the main surface of the laminate, and the external electrode connected to the entire exposed portion of the dummy electrode. It is characterized by.

また本発明のコンデンサは、前記外部電極が、前記積層体の表面に導出された内部電極層の一端及び前記ダミー電極の外周部を起点として析出された無電解メッキ膜を含んで形成されており、該無電解メッキ膜が前記積層体の側面から主面にかけて連続的に形成されていることを特徴とするものである。   In the capacitor of the present invention, the external electrode includes an electroless plating film deposited from one end of the internal electrode layer led to the surface of the laminate and the outer periphery of the dummy electrode. The electroless plating film is formed continuously from the side surface to the main surface of the laminate.

更に本発明のコンデンサは、前記積層体の主面近傍において前記誘電体層と前記ダミー電極とが交互に積層されており、これらダミー電極の外周部が前記積層体の表面に年輪状をなすように露出されていることを特徴とするものである。   Furthermore, in the capacitor of the present invention, the dielectric layers and the dummy electrodes are alternately laminated in the vicinity of the main surface of the multilayer body, and the outer peripheral portion of the dummy electrodes forms an annual ring shape on the surface of the multilayer body. It is exposed to.

また更に本発明のコンデンサは、前記積層体の積層方向に係るダミー電極の厚みＴ１と、前記積層体の面取り部に露出されるダミー電極の露出幅Ｗ１とが“Ｗ１＞Ｔ１”の関係式を満たすように設定されていることを特徴とするものである。 Furthermore, in the capacitor of the present invention, the thickness T 1 of the dummy electrode in the stacking direction of the stacked body and the exposed width W 1 of the dummy electrode exposed at the chamfered portion of the stacked body are “W 1 > T 1 ”. It is set to satisfy the relational expression of

更にまた本発明のコンデンサは、前記ダミー電極の露出幅Ｗ１と、前記積層体の側面に導出される内部電極層の導出幅Ｗ２とが“Ｗ１＞Ｗ２”の関係式を満たすように設定されていることを特徴とするものである。 Furthermore, in the capacitor of the present invention, the exposed width W 1 of the dummy electrode and the derived width W 2 of the internal electrode layer derived on the side surface of the multilayer body satisfy the relational expression “W 1 > W 2 ”. It is characterized by being set to.

また更に本発明のコンデンサは、前記積層体の主面近傍において前記誘電体層と前記ダミー電極とが交互に積層されており、前記積層体の縦断面において前記積層体の表面に導出された隣接するダミー電極の端部間の最短距離Ｄ１と前記積層体の同一側面に導出された隣接する内部電極層の端部間の最短距離Ｄ２とが“Ｄ１＜Ｄ２”の関係式を満たすように設定されていることを特徴とするものである。 Furthermore, in the capacitor according to the present invention, the dielectric layers and the dummy electrodes are alternately stacked in the vicinity of the main surface of the multilayer body, and adjacent to the surface of the multilayer body in the longitudinal section of the multilayer body. the relationship between the shortest distance D 2 between the ends of the internal electrode layers adjacent derived the shortest distance D 1 of the between the ends of the dummy electrodes on the same side of the stack "D 1 <D 2" It is set so that it may satisfy | fill.

本発明のコンデンサによれば、積層体の主面近傍に位置する誘電体層間に、積層体の面取り部、もしくは面取り部から主面にかけて外周部を環状に露出させたダミー電極を介在させるとともに、ダミー電極の露出部全体にわたって外部電極を接続したことから、環状に露出したダミー電極がダミー電極と外部電極とを接続する面積を増やすので、外部電極の接着強度を強くすることができる。   According to the capacitor of the present invention, between the dielectric layers located in the vicinity of the main surface of the multilayer body, a chamfered portion of the multilayer body, or a dummy electrode having an outer peripheral portion exposed annularly from the chamfered portion to the main surface, Since the external electrode is connected over the entire exposed portion of the dummy electrode, the annularly exposed dummy electrode increases the area for connecting the dummy electrode and the external electrode, so that the adhesive strength of the external electrode can be increased.

また本発明のコンデンサによれば、外部電極が、積層体の表面に導出された内部電極層の一端及びダミー電極の外周部を起点として析出された無電解メッキ膜を含んで形成されており、無電解メッキ膜が積層体の側面から主面にかけて連続的に形成されていることから、外部電極を精度良く形成できるとともに、外部電極が被着される部分の金属同士の結合が増え、外部電極の接着強度を強くすることができる。   Further, according to the capacitor of the present invention, the external electrode is formed including an electroless plating film deposited from one end of the internal electrode layer led to the surface of the laminate and the outer periphery of the dummy electrode, Since the electroless plating film is continuously formed from the side surface to the main surface of the laminate, the external electrode can be formed with high precision, and the bonding between the metals on the portion where the external electrode is attached increases, and the external electrode The adhesive strength of the can be increased.

更に本発明のコンデンサによれば、積層体の主面近傍において誘電体層とダミー電極とが交互に積層されており、これらダミー電極の外周部が前記積層体の表面に年輪状をなすように露出されていることから、ダミー電極の外周部と外部電極とが接続する面積が効率的に増えるので、外部電極の接着強度をより強くすることができる。   Furthermore, according to the capacitor of the present invention, the dielectric layers and the dummy electrodes are alternately laminated in the vicinity of the main surface of the multilayer body so that the outer peripheral portion of the dummy electrodes forms an annual ring shape on the surface of the multilayer body. Since it is exposed, the area where the outer peripheral portion of the dummy electrode is connected to the external electrode is efficiently increased, so that the adhesive strength of the external electrode can be further increased.

また更に本発明のコンデンサによれば、積層体の積層方向に係るダミー電極の厚みＴ１と、積層体の面取り部に露出されるダミー電極の露出幅Ｗ１とが“Ｗ１＞Ｔ１”の関係式を満たすように設定されていることから、ダミー電極と外部電極とを接続する面積が増えるので、外部電極の接着強度を高くすることができる。 Furthermore, according to the capacitor of the present invention, the thickness T 1 of the dummy electrode in the stacking direction of the stacked body and the exposed width W 1 of the dummy electrode exposed at the chamfered portion of the stacked body are “W 1 > T 1 ”. Since the area for connecting the dummy electrode and the external electrode is increased, the adhesive strength of the external electrode can be increased.

更にまた本発明のコンデンサは、ダミー電極の露出幅Ｗ１と、積層体の側面に導出される内部電極層の導出幅Ｗ２とが“Ｗ１＞Ｗ２”の関係式を満たすように設定されていることから、積層体の主面近傍でダミー電極と外部電極とを接続する面積が増えるので、回路基板上に半田等を介して搭載した場合の接着強度を高くすることになる。 Furthermore, the capacitor of the present invention is set so that the exposed width W 1 of the dummy electrode and the derived width W 2 of the internal electrode layer derived on the side surface of the multilayer body satisfy the relational expression “W 1 > W 2 ”. As a result, the area where the dummy electrode and the external electrode are connected increases in the vicinity of the main surface of the laminate, so that the adhesive strength when mounted on the circuit board via solder or the like is increased.

また更に本発明のコンデンサは、積層体の主面近傍において誘電体層とダミー電極とが交互に積層されており、積層体の縦断面において積層体の表面に導出された隣接するダミー電極の端部間の最短距離Ｄ１と積層体の同一側面に導出された隣接する内部電極層の端部間の最短距離Ｄ２とが“Ｄ１＜Ｄ２”の関係式を満たすように設定されていることから、積層体の主面近傍でダミー電極と外部電極とを接続する面積が増えるので、回路基板上に半田等を介して搭載した場合の接着強度を高くすることになる。 Furthermore, in the capacitor of the present invention, dielectric layers and dummy electrodes are alternately laminated in the vicinity of the main surface of the multilayer body, and the end of the adjacent dummy electrode led to the surface of the multilayer body in the longitudinal section of the multilayer body. the shortest distance D 2 between the ends of the internal electrode layers "D 1 <D 2" is set so as to satisfy the relational expression of an adjacent derived on the same side of the minimum distance D 1 and the laminate between parts As a result, the area for connecting the dummy electrode and the external electrode increases in the vicinity of the main surface of the laminate, so that the adhesive strength when mounted on the circuit board via solder or the like is increased.

以下、本発明を添付図面に基づいて詳細に説明する。   Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

は本発明の一実施形態にかかるコンデンサを上方からみた平面図であり、図２はその断面図である。同図に示すコンデンサは、複数個の誘電体層を積層してなる積層体１の内部に内部電極層２が介在され、積層体１の側面から主面にかけては外部電極３が被着された構造を有している。   These are the top views which looked at the capacitor | condenser concerning one Embodiment of this invention from upper direction, FIG. 2 is the sectional drawing. In the capacitor shown in the figure, an internal electrode layer 2 is interposed in a laminated body 1 formed by laminating a plurality of dielectric layers, and an external electrode 3 is deposited from the side surface to the main surface of the laminated body 1. It has a structure.

積層体１を構成する誘電体層は、材質としては例えば、ＢａＴｉＯ３、ＣａＴｉＯ３、ＳｒＴｉＯ３等を主成分とする高誘電率の誘電体材料が用いられ、その厚みは例えば１層あたり１μm〜３μmに設定される。また積層体１における誘電体層の積層数は、例えば２０層〜２０００層に設定される。 The dielectric layer constituting the multilayer body 1 is made of, for example, a dielectric material having a high dielectric constant mainly composed of BaTiO 3 , CaTiO 3 , SrTiO 3, etc., and has a thickness of, for example, 1 μm to 1 layer. Set to 3 μm. Further, the number of laminated dielectric layers in the laminated body 1 is set to 20 to 2000 layers, for example.

また積層体１の側面と主面との間の角部には、カケ等の不具合が発生しないように、断面円弧状の面取り部が形成される。面取り部の円弧の半径は例えば３０〜８０μｍに設定される。   In addition, a chamfered portion having an arcuate cross section is formed at a corner portion between the side surface and the main surface of the laminate 1 so as not to cause defects such as chipping. The radius of the arc of the chamfered portion is set to 30 to 80 μm, for example.

内部電極層２は、積層体１の内部で隣接する誘電体層間に介在され、材質としては例えば、Ｎｉ、Ｃｕ、Ｃｕ−Ｎｉ、Ａｇ−Ｐｄ等の金属を主成分とする導体材料が用いられ、その厚みは例えば０．５μm〜２μmに設定される。誘電体層を介して対向する一対の内部電極層２は、対向する領域で静電容量が形成され、その一端はそれぞれ積層体１の異なる側面に導出される。尚、本実施形態のコンデンサにおいて、誘電体層を介して対向する一対の内部電極層２はそれぞれ対向する側面に導出される。   The internal electrode layer 2 is interposed between adjacent dielectric layers inside the multilayer body 1, and as the material, for example, a conductive material mainly composed of a metal such as Ni, Cu, Cu—Ni, Ag—Pd is used. The thickness is set to 0.5 μm to 2 μm, for example. The pair of internal electrode layers 2 facing each other through the dielectric layer has a capacitance formed in the facing region, and one end thereof is led out to a different side surface of the laminate 1. In the capacitor of this embodiment, the pair of internal electrode layers 2 facing each other through the dielectric layer are led out to the facing side surfaces.

積層体１の側面から主面にかけて被着される外部電極３は、材質としては例えば、導電率が低く半田に浸食されにくいＣｕ等の導体材料が用いられ、その厚みは例えば５〜１０μｍ設定される。また外部電極３は、側面に導出した内部電極層２の一端に接続され、積層体１の内部で形成される静電容量と電気的に接続される。尚、本実施形態のコンデンサにおいて、外部電極３の表面には、回路基板に半田で搭載される場合に半田が塗れやすくするために、半田、Ｓｎ等のロウ材層４（図１では図示せず）が被覆形成される。ロウ材層４は、例えば、４〜５μｍの厚みに設定される。   The external electrode 3 deposited from the side surface to the main surface of the multilayer body 1 is made of, for example, a conductor material such as Cu having low conductivity and not easily eroded by solder, and the thickness thereof is set to 5 to 10 μm, for example. The The external electrode 3 is connected to one end of the internal electrode layer 2 led out to the side surface, and is electrically connected to a capacitance formed inside the stacked body 1. In the capacitor according to the present embodiment, the surface of the external electrode 3 has a solder material layer 4 such as solder or Sn (not shown in FIG. ) Is formed. The brazing material layer 4 is set to a thickness of 4 to 5 μm, for example.

図３に本実施形態のコンデンサから外部電極３を除いた平面図を示す。積層体１の主面近傍に位置する誘電体層間には、静電容量の形成に対する関与が少ないダミー電極５が複数個形成され、積層体１の面取り部、もしくは面取り部から主面にかけて外周部６を環状に露出させたダミー電極５が介在され、ダミー電極５の露出部全体にわたって外部電極３が接続される。環状に露出したダミー電極５の外周部６がダミー電極５と外部電極３とを接続する面積を増やすので、回路基板上に半田等を介して搭載した場合の外部電極３の接着強度を強くすることができる。   FIG. 3 is a plan view in which the external electrode 3 is removed from the capacitor of this embodiment. A plurality of dummy electrodes 5 that are less involved in the formation of capacitance are formed between the dielectric layers located in the vicinity of the main surface of the multilayer body 1, and the chamfered portion of the multilayer body 1, or the outer peripheral portion from the chamfered portion to the main surface A dummy electrode 5 having an annularly exposed 6 is interposed, and the external electrode 3 is connected over the entire exposed portion of the dummy electrode 5. The outer peripheral portion 6 of the dummy electrode 5 exposed in an annular shape increases the area for connecting the dummy electrode 5 and the external electrode 3, so that the adhesion strength of the external electrode 3 when mounted on the circuit board via solder or the like is increased. be able to.

また本実施形態のコンデンサにおいては、図３に示されるように、積層体１の主面近傍において誘電体層とダミー電極５とが交互に積層されており、これらダミー電極５の外周部６が積層体１の表面に年輪状をなすように露出される。ダミー電極５の外周部６と外部電極３とが接続する面積が効率的に増えるので、外部電極３の接着強度をより強くすることができる。   In the capacitor of this embodiment, as shown in FIG. 3, dielectric layers and dummy electrodes 5 are alternately stacked in the vicinity of the main surface of the multilayer body 1, and the outer peripheral portion 6 of these dummy electrodes 5 is The surface of the laminate 1 is exposed so as to form an annual ring. Since the area where the outer peripheral portion 6 of the dummy electrode 5 and the external electrode 3 are connected efficiently increases, the adhesive strength of the external electrode 3 can be further increased.

図４に図２の部分拡大図を示す。図４に示すように、積層体１の積層方向に係るダミー電極５の厚みＴ１と、積層体１の面取り部に露出されるダミー電極３の露出幅Ｗ１とが“Ｗ１＞Ｔ１”の関係式を満たすように設定される。本実施形態のコンデンサにおいては、例えば、積層体１の積層方向に係るダミー電極５の厚みＴ１が１．２μｍのとき、積層体１の面取り部に露出されるダミー電極３の露出幅Ｗ１は、１．５〜３μｍになるようにした。これにより、ダミー電極５と外部電極３とを接続する面積が増えるので、外部電極３の接着強度をより高くすることができる。更に本実施形態のコンデンサにおいては、露出部Ｗ１が積層体１の主面側に近づくにつれて広くなるようにした。 FIG. 4 shows a partially enlarged view of FIG. As shown in FIG. 4, the thickness T 1 of the dummy electrode 5 in the stacking direction of the stacked body 1 and the exposed width W 1 of the dummy electrode 3 exposed at the chamfered portion of the stacked body 1 are “W 1 > T 1. "Is set to satisfy the relational expression". " In the capacitor of the present embodiment, for example, when the thickness T 1 of the dummy electrode 5 according to the laminating direction of the multilayer body 1 is 1.2 [mu] m, the exposed width W 1 of the dummy electrode 3 which is exposed to the chamfered portion of the laminated body 1 Was set to 1.5 to 3 μm. Thereby, since the area which connects the dummy electrode 5 and the external electrode 3 increases, the adhesive strength of the external electrode 3 can be made higher. Furthermore, in the capacitor of the present embodiment, the exposed portion W 1 is made wider as it approaches the main surface side of the multilayer body 1.

一方、ダミー電極５の露出幅Ｗ１と、積層体１の側面に導出される内部電極層２の導出幅Ｗ２とは、“Ｗ１＞Ｗ２”の関係式を満たすように設定される。本実施形態のコンデンサにおいては、例えば、積層体１の側面に導出される内部電極層２の導出幅Ｗ２は、上記内部電極層２の厚みと略同一の１．２μｍに設定し、このとき、ダミー電極３の露出幅Ｗ１は、１．５〜３μｍになるようにした。このことによっても、積層体１の主面近傍でダミー電極５と外部電極３とを接続する面積が増えるので、接着強度をより強くすることになる。 On the other hand, the exposed width W 1 of the dummy electrode 5 and the derived width W 2 of the internal electrode layer 2 derived on the side surface of the multilayer body 1 are set so as to satisfy the relational expression “W 1 > W 2 ”. . In the capacitor of the present embodiment, for example, the derived width W 2 of the internal electrode layer 2 derived on the side surface of the multilayer body 1 is set to 1.2 μm, which is substantially the same as the thickness of the internal electrode layer 2. exposed width W 1 of the dummy electrode 3 was set to 1.5～3Myuemu. This also increases the area where the dummy electrode 5 and the external electrode 3 are connected in the vicinity of the main surface of the laminate 1, thereby further increasing the adhesive strength.

更に、積層体１の主面近傍において誘電体層とダミー電極５とが交互に積層されており、積層体１の縦断面において積層体１の表面に導出された隣接するダミー電極５の端部間の最短距離Ｄ１と積層体１の同一側面に導出された隣接する内部電極層２の端部間の最短距離Ｄ２とが“Ｄ１＜Ｄ２”の関係式を満たすように設定される。このことによっても、積層体１の主面近傍でダミー電極５と外部電極３とを接続する面積が増えるので、回路基板上に半田等を介して搭載した場合の接着強度を強めることになる。本実施形態のコンデンサにおいては、ダミー電極５の端部間には誘電体層が１層分介在しているのに対して内部電極層２の端部間には誘電体層が２層分介在されるようにした。 Furthermore, dielectric layers and dummy electrodes 5 are alternately stacked in the vicinity of the main surface of the stacked body 1, and end portions of adjacent dummy electrodes 5 led out to the surface of the stacked body 1 in the longitudinal section of the stacked body 1. the shortest distance D 2 between the ends of the internal electrode layer 2 adjacent to the shortest distance derived D 1 and on the same side of the stack 1 between are set to satisfy the relationship of "D 1 <D 2" The This also increases the area where the dummy electrode 5 and the external electrode 3 are connected in the vicinity of the main surface of the laminate 1, so that the adhesive strength when mounted on the circuit board via solder or the like is increased. In the capacitor according to the present embodiment, one dielectric layer is interposed between the end portions of the dummy electrode 5, whereas two dielectric layers are interposed between the end portions of the internal electrode layer 2. It was made to be.

本実施形態のコンデンサは、以下の製造方法により製作される。   The capacitor of this embodiment is manufactured by the following manufacturing method.

先ず、ＢａＴｉＯ３、ＣａＴｉＯ３、ＳｒＴｉＯ３等を主成分とする誘電体材料の粉末に適当な有機溶剤、ガラスフリット、有機バインダ等を添加・混合して泥漿状のセラミックスラリを作製し、得られたセラミックスラリを従来周知のドクターブレード法等によって所定形状、所定厚みの誘電体層となるセラミックグリーンシートを形成し、得られたセラミックグリーンシートの主面に、Ｎｉ、Ｃｕ、Ｃｕ−Ｎｉ、Ａｇ−Ｐｄ等の金属材料の粉末に適当な有機溶剤、有機バインダ等を添加・混合して得た導体ペーストを従来周知のスクリーン印刷等によって所定パターンに塗布し、容量形成電極となる導体パターン及びダミー導体となる導体パターンを形成する。なお、上記導体パターンは、所定パターンのメッキ等の電鋳法を用いて形成した膜を被着・転写させておくことにより形成するようにしても良い。 First, a slurry-like ceramic slurry is prepared by adding and mixing a suitable organic solvent, glass frit, organic binder, etc. to a dielectric material powder mainly composed of BaTiO 3 , CaTiO 3 , SrTiO 3, etc. A ceramic green sheet having a predetermined shape and a predetermined thickness is formed from the ceramic slurry using a conventionally known doctor blade method, and Ni, Cu, Cu-Ni, Ag are formed on the main surface of the obtained ceramic green sheet. -Conductor paste obtained by adding and mixing a suitable organic solvent, organic binder, etc. to a powder of a metal material such as Pd in a predetermined pattern by screen printing or the like known in the past, and a conductor pattern and dummy serving as a capacitance forming electrode A conductor pattern to be a conductor is formed. The conductor pattern may be formed by depositing and transferring a film formed using an electroforming method such as plating of a predetermined pattern.

次に、導体パターンが形成されたセラミックグリーンシートを所定の枚数だけ支持台上に積層し、積層された導体パターン及びセラミックグリーンシートを加圧加熱することにより、大型積層体を形成し、大型積層体を所定の寸法で切断することにより、未焼成積層ブロックを形成する。   Next, a predetermined number of ceramic green sheets on which conductor patterns are formed are laminated on a support base, and a large laminate is formed by pressurizing and heating the laminated conductor patterns and ceramic green sheets. A green laminate block is formed by cutting the body into predetermined dimensions.

そして、得られた未焼成積層体を例えば１１００℃〜１４００℃の温度で焼成し、更に、得られた積層ブロックをバレル研磨等により側面と主面との角部に面取り部を形成し、得られた積層体１の表面に露出した内部電極層２及びダミー電極５の一端を起点として、Ｃｕの無電解メッキ膜を積層体１の側面から主面にかけて連続的に形成されるまで析出させることにより、外部電極３が被着・形成される。   And the obtained unbaked laminated body is baked at a temperature of, for example, 1100 ° C. to 1400 ° C., and the obtained laminated block is further chamfered at the corners of the side surface and the main surface by barrel polishing, etc. Starting from one end of the internal electrode layer 2 and the dummy electrode 5 exposed on the surface of the laminated body 1, a Cu electroless plating film is deposited until it is continuously formed from the side surface to the main surface of the laminated body 1. Thus, the external electrode 3 is deposited and formed.

本実施形態のコンデンサにおいては、ダミー電極５が積層体１の側面と主面との角部に介在されており、上記バレル研磨を行った際に、積層体１の面取り部、もしくは面取り部から主面にかけてダミー電極５が露出される。その上、誘電体層がＢａＴｉＯ３等からなるためにＮｉ等からなるダミー電極５よりも削られやすいので、ダミー電極３の外周部６が積層体１の面取り部、もしくは面取り部から主面にかけて露出される。これにより、外部電極３を形成する無電解メッキ膜がダミー電極５の外周部６を起点にして析出されるので、外部電極を精度良く形成できるとともに、外部電極３が被着される部分の金属同士の結合が増え、外部電極３の接着強度を強くすることができる。外周部６は、主面側に近いものほど上記バレル研磨によって削られる量が多く径が小さくなるので、複数個の外周部６が重なって露出する場合には、図３に示すような年輪状をなすように露出されるようになる。 In the capacitor of this embodiment, the dummy electrode 5 is interposed at the corner between the side surface and the main surface of the multilayer body 1, and when the barrel polishing is performed, the dummy electrode 5 is removed from the chamfered portion or the chamfered portion of the multilayer body 1. The dummy electrode 5 is exposed over the main surface. In addition, since the dielectric layer is made of BaTiO 3 or the like, it is easier to scrape than the dummy electrode 5 made of Ni or the like, so that the outer peripheral portion 6 of the dummy electrode 3 extends from the chamfered portion or the chamfered portion to the main surface of the laminate 1. Exposed. As a result, the electroless plating film for forming the external electrode 3 is deposited starting from the outer peripheral portion 6 of the dummy electrode 5, so that the external electrode can be formed with high accuracy and the metal on the portion where the external electrode 3 is deposited. Bonding between the two increases, and the adhesive strength of the external electrode 3 can be increased. As the outer peripheral portion 6 is closer to the main surface side, the amount of scraping by the barrel polishing is larger and the diameter is smaller. Therefore, when a plurality of outer peripheral portions 6 are overlapped and exposed, an annual ring shape as shown in FIG. It will be exposed to form.

また、主面近傍のダミー電極５の厚みにより、積層方向においてダミー電極５が形成された領域の内部電極層２は、積層体の中央部に向かって断面が屈曲した形状となっている。このことが更に、バレル研磨を行った際にダミー電極５の主面側を露出させやすくしている。   Further, depending on the thickness of the dummy electrode 5 in the vicinity of the main surface, the internal electrode layer 2 in the region where the dummy electrode 5 is formed in the stacking direction has a shape whose cross section is bent toward the center of the stack. This further facilitates exposing the main surface side of the dummy electrode 5 when barrel polishing is performed.

尚、本発明は上述した実施形態に限定されるものではなく、本発明の要旨を逸脱しない範囲において種々の変更、改良等が可能である。   In addition, this invention is not limited to embodiment mentioned above, A various change, improvement, etc. are possible in the range which does not deviate from the summary of this invention.

例えば、本実施形態のコンデンサにおいては、図１の平面図では外部電極３が同一側面に２個形成され、一つの積層体内に２個のコンデンサ素子を有した多連型セラミックコンデンサが示されているが、外部電極３は同一側面に２個形成するに限らず、３個以上形成してもよい。   For example, in the capacitor of this embodiment, the plan view of FIG. 1 shows a multiple-type ceramic capacitor in which two external electrodes 3 are formed on the same side surface and two capacitor elements are provided in one laminated body. However, the number of external electrodes 3 is not limited to two on the same side, but may be three or more.

また、本実施形態においては、外部電極３の表面に直接、半田等のロウ材層を被膜・形成したが、半田の浸食をより抑えるために外部電極３とロウ材層との間にＮｉ等の中間層を形成しても良い。尚、中間層の厚みは、例えば２〜３μｍに設定される。   In the present embodiment, a brazing material layer such as solder is formed directly on the surface of the external electrode 3, but Ni or the like is interposed between the external electrode 3 and the brazing material layer in order to further suppress solder erosion. The intermediate layer may be formed. Note that the thickness of the intermediate layer is set to, for example, 2 to 3 μm.

本発明のコンデンサの一実施形態を示す平面図である。It is a top view which shows one Embodiment of the capacitor | condenser of this invention. 本発明のコンデンサの一実施形態を示す断面図である。It is sectional drawing which shows one Embodiment of the capacitor | condenser of this invention. 本発明のコンデンサの一実施形態から外部電極を除いた平面図である。It is a top view which removed the external electrode from one Embodiment of the capacitor | condenser of this invention. 図２の部分拡大図である。FIG. 3 is a partially enlarged view of FIG. 2.

符号の説明Explanation of symbols

１・・・積層体
２・・・内部電極層
３・・・外部電極
４・・・ロウ材層
５・・・ダミー電極
６・・・外周部 DESCRIPTION OF SYMBOLS 1 ... Laminated body 2 ... Internal electrode layer 3 ... External electrode 4 ... Brazing material layer 5 ... Dummy electrode 6 ... Outer peripheral part

Claims (6)

複数個の誘電体層を積層してなる積層体の内部で、隣接する誘電体層間に内部電極層を介在させるとともに、前記積層体の側面と主面との間の角部に曲面状の面取り部を形成し、前記積層体の側面から主面にかけて、前記内部電極層の一端に接続される外部電極を被着させたコンデンサにおいて、
前記積層体の主面近傍に位置する誘電体層間に、前記積層体の面取り部、もしくは面取り部から主面にかけて外周部を環状に露出させたダミー電極を介在させるとともに、該ダミー電極の露出部全体にわたって前記外部電極を接続したことを特徴とするコンデンサ。 An internal electrode layer is interposed between adjacent dielectric layers in a multilayer body formed by laminating a plurality of dielectric layers, and a curved chamfer is formed at a corner between the side surface and the main surface of the multilayer body. Forming a portion, from the side surface of the laminate to the main surface, in a capacitor to which an external electrode connected to one end of the internal electrode layer is deposited,
Between the dielectric layers located in the vicinity of the main surface of the multilayer body, a chamfered portion of the multilayer body, or a dummy electrode having an outer peripheral portion annularly exposed from the chamfered portion to the main surface, and an exposed portion of the dummy electrode A capacitor characterized in that the external electrodes are connected throughout. 前記外部電極が、前記積層体の表面に導出された内部電極層の一端及び前記ダミー電極の外周部を起点として析出された無電解メッキ膜を含んで形成されており、該無電解メッキ膜が前記積層体の側面から主面にかけて連続的に形成されていることを特徴とする請求項１に記載のコンデンサ。 The external electrode is formed including an electroless plating film deposited from one end of the internal electrode layer led to the surface of the laminate and the outer periphery of the dummy electrode, and the electroless plating film The capacitor according to claim 1, wherein the capacitor is continuously formed from a side surface to a main surface of the laminate. 前記積層体の主面近傍において前記誘電体層と前記ダミー電極とが交互に積層されており、これらダミー電極の外周部が前記積層体の表面に年輪状をなすように露出されていることを特徴とする請求項１または請求項２に記載のコンデンサ。 The dielectric layers and the dummy electrodes are alternately stacked in the vicinity of the main surface of the multilayer body, and the outer peripheral portions of the dummy electrodes are exposed so as to form an annual ring on the surface of the multilayer body. The capacitor according to claim 1 or 2, wherein the capacitor is characterized in that: 前記積層体の積層方向に係るダミー電極の厚みＴ１と、前記積層体の面取り部に露出されるダミー電極の露出幅Ｗ１とが“Ｗ１＞Ｔ１”の関係式を満たすように設定されていることを特徴とする請求項１乃至請求項３のいずれかに記載のコンデンサ。 The thickness T 1 of the dummy electrode in the stacking direction of the stacked body and the exposed width W 1 of the dummy electrode exposed at the chamfered portion of the stacked body are set so as to satisfy the relational expression “W 1 > T 1 ”. The capacitor according to claim 1, wherein the capacitor is provided. 前記ダミー電極の露出幅Ｗ１と、前記積層体の側面に導出される内部電極層の導出幅Ｗ２とが“Ｗ１＞Ｗ２”の関係式を満たすように設定されていることを特徴とする請求項１乃至請求項４のいずれかに記載のコンデンサ。 Wherein the exposed width W 1 of the dummy electrodes, and deriving the width W 2 of the inner electrode layers which are led out to the side surface of the laminated body is set so as to satisfy the relationship of "W 1> W 2" The capacitor according to any one of claims 1 to 4. 前記積層体の主面近傍において前記誘電体層と前記ダミー電極とが交互に積層されており、前記積層体の縦断面において前記積層体の表面に導出された隣接するダミー電極の外周部間の最短距離Ｄ１と前記積層体の同一側面に導出された隣接する内部電極層の端部間の最短距離Ｄ２とが“Ｄ１＜Ｄ２”の関係式を満たすように設定されていることを特徴とすることを特徴とする請求項１乃至請求項５のいずれかに記載のコンデンサ。 The dielectric layers and the dummy electrodes are alternately stacked in the vicinity of the main surface of the multilayer body, and between the outer peripheral portions of adjacent dummy electrodes led to the surface of the multilayer body in the longitudinal section of the multilayer body. it is set so as to satisfy the relational expression and the shortest distance D 2 between the ends of the internal electrode layers adjacent derived on the same side of the shortest distance D 1 and the laminate is "D 1 <D 2" The capacitor according to claim 1, wherein the capacitor is characterized in that
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JP2006332601A (en) * 2005-04-27 2006-12-07 Kyocera Corp Multilayer electronic component
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