JP2005327946A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2005327946A
JP2005327946A JP2004145740A JP2004145740A JP2005327946A JP 2005327946 A JP2005327946 A JP 2005327946A JP 2004145740 A JP2004145740 A JP 2004145740A JP 2004145740 A JP2004145740 A JP 2004145740A JP 2005327946 A JP2005327946 A JP 2005327946A
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semiconductor device
die pad
substrate
semiconductor element
exposed
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Noboru Takeuchi
登 竹内
Kenichi Ito
健一 伊東
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can be surely connected to a substrate, even if dust or foreign matters pinched in between the semiconductor device and the substrate at the mounting of the substrate. <P>SOLUTION: The semiconductor device includes a semiconductor element 2, a die pad 1 on which the semiconductor element 2 is mounted, a plurality of electrode terminals 5 electrically connected to the semiconductor element 2, a resin seal 7 for sealing the semiconductor element 2, the die pad 1, and the electrode terminals 5 with resin. Part of the electrode terminals 5 is exposed from the resin seal 7 as an external terminal, and another part of the external terminal facing an substrate 16 to be mounted is projected, to form a projection 6c. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は半導体装置に関するものであり、高密度実装が可能な小型で薄型の面実装用樹脂封止型半導体装置の技術に係るものである。   The present invention relates to a semiconductor device, and relates to a technology of a small and thin surface-mounted resin-encapsulated semiconductor device capable of high-density mounting.

近年、電子機器の小型化、高密度化に対応するために、半導体装置の小型、薄型化が進んでいる。小型、薄型の樹脂封止型半導体装置として実質的に片面封止されたＱＦＮ（Ｑｕａｄ Ｆｌａｔ Ｎｏｎ―ｌｅａｄｅｄ Ｐａｃｋａｇｅ）やＳＯＮ（Ｓｍａｌｌ Ｏｕｔｌｉｎｅ Ｎｏｎ―ｌｅａｄｅｄ Ｐａｃｋａｇｅ）と称される半導体装置が開発されている。   In recent years, in order to cope with the downsizing and high density of electronic devices, semiconductor devices have been made smaller and thinner. Semiconductor devices called QFN (Quad Flat Non-Leaded Package) or SON (Small Outline Non-Leaded Package), which are substantially sealed on one side, have been developed as small and thin resin-encapsulated semiconductor devices.

また、その製造方法は、組立コストを低減するため複数の半導体装置を一括して樹脂封止し、ダイシング加工によって個々の半導体装置に分割する工法が主流になりつつある。
以下に従来の半導体装置、例えば特許文献１（特開２０００―２４３８９１号公報）で提案されているものを図９を用いて説明する。図９は従来のＱＦＮ型の樹脂封止型半導体装置を示す図であり、図９（ａ）は概略的な構成を示す平面図であり、図９（ｂ）は概略的な構成を示す断面図であり、図９（ｃ）は概略的な構成を示す背面図である。 In addition, a manufacturing method in which a plurality of semiconductor devices are collectively resin-sealed and divided into individual semiconductor devices by dicing is becoming the mainstream of the manufacturing method in order to reduce assembly costs.
A conventional semiconductor device, for example, one proposed in Patent Document 1 (Japanese Patent Laid-Open No. 2000-243891) will be described below with reference to FIG. FIG. 9 is a diagram showing a conventional QFN type resin-encapsulated semiconductor device, FIG. 9A is a plan view showing a schematic configuration, and FIG. 9B is a cross-sectional view showing the schematic configuration. FIG. 9C is a rear view showing a schematic configuration.

図９に示すように、従来型の半導体装置は、サポートリード１３によって支持されるダイパッド１に接着剤３を塗布して、その上に半導体素子２を固着している。ダイパッド１の中央付近はアップセットされている。サポートリード１３は曲げ加工することで、その中央部を封止樹脂体７に埋没している。半導体素子２には金属細線４が接続され、ダイパッド１の周辺にある複数の電極端子５とそれぞれ電気的に接続されている。   As shown in FIG. 9, in the conventional semiconductor device, the adhesive 3 is applied to the die pad 1 supported by the support leads 13, and the semiconductor element 2 is fixed thereon. The center of the die pad 1 is upset. The support lead 13 is bent to have its center portion buried in the sealing resin body 7. A thin metal wire 4 is connected to the semiconductor element 2 and electrically connected to a plurality of electrode terminals 5 around the die pad 1.

ダイパッド１、半導体素子２、接着剤３、金属細線４及び電極端子５は封止樹脂体７で封止されており、封止樹脂体７は四辺形の平板状に形成されている。電極端子５は金属細線４と接続されている面に対向する対向面が封止樹脂体７の底面より露出している。さらに電極端子５の一部は封止樹脂体７の底面に露出する電極端子５から連続的に封止樹脂体７の側面にも露出している。   The die pad 1, the semiconductor element 2, the adhesive 3, the fine metal wires 4 and the electrode terminals 5 are sealed with a sealing resin body 7, and the sealing resin body 7 is formed in a quadrangular flat plate shape. In the electrode terminal 5, the facing surface facing the surface connected to the fine metal wire 4 is exposed from the bottom surface of the sealing resin body 7. Further, a part of the electrode terminal 5 is continuously exposed on the side surface of the sealing resin body 7 from the electrode terminal 5 exposed on the bottom surface of the sealing resin body 7.

次に、他の従来の半導体装置で、組立コストを低減するために複数の半導体装置を一括して樹脂封止し、ダイシング加工によって個々の半導体装置に分割する工法を用いたものを図８を用いて説明する。   Next, FIG. 8 shows another conventional semiconductor device in which a plurality of semiconductor devices are collectively encapsulated with resin in order to reduce assembly costs and divided into individual semiconductor devices by dicing. It explains using.

図８は従来のＱＦＮ型樹脂封止型半導体装置を示す図であり、図８（ａ）は概略的な構成を示す平面図であり、図８（ｂ）は概略的な構成を示す断面図であり、図８（ｃ）は概略的な構成を示す背面図である。   FIG. 8 is a diagram showing a conventional QFN type resin-encapsulated semiconductor device, FIG. 8A is a plan view showing a schematic configuration, and FIG. 8B is a cross-sectional view showing the schematic configuration. FIG. 8C is a rear view showing a schematic configuration.

図８に示すように、従来型の半導体装置は、サポートリード１３によって支持されるダイパッド１に接着剤３を塗布して、その上に半導体素子２を固着している。ダイパッド１の中央付近はアップセットされている。サポートリード１３は、その裏面をハーフエッチングすることで封止樹脂体７に埋没している。半導体素子２には金属細線４が接続され、ダイパッド１の周辺にある複数の電極端子５とそれぞれ電気的に接続されている。   As shown in FIG. 8, in the conventional semiconductor device, the adhesive 3 is applied to the die pad 1 supported by the support leads 13, and the semiconductor element 2 is fixed thereon. The center of the die pad 1 is upset. The support lead 13 is buried in the sealing resin body 7 by half-etching the back surface thereof. A thin metal wire 4 is connected to the semiconductor element 2 and electrically connected to a plurality of electrode terminals 5 around the die pad 1.

ダイパッド１、半導体素子２、接着剤３、金属細線４及び電極端子５は封止樹脂体７で封止されており、封止樹脂体７は四辺形の平板状に形成されている。電極端子５は金属細線４と接続されている面に対向する対向面が封止樹脂体７の底面より露出している。さらに電極端子５の一部は、封止樹脂体７の底面に露出する電極端子５と不連続的に封止樹脂体７の側面にも露出している。   The die pad 1, the semiconductor element 2, the adhesive 3, the fine metal wires 4 and the electrode terminals 5 are sealed with a sealing resin body 7, and the sealing resin body 7 is formed in a quadrangular flat plate shape. In the electrode terminal 5, the facing surface facing the surface connected to the fine metal wire 4 is exposed from the bottom surface of the sealing resin body 7. Further, a part of the electrode terminal 5 is also exposed on the side surface of the sealing resin body 7 discontinuously with the electrode terminal 5 exposed on the bottom surface of the sealing resin body 7.

これらＱＦＮ型（ＳＯＮ型）の半導体装置は、樹脂封止体７の底面から電極端子５を露出させるよう片面封止することで小型、薄型化を可能としている。また、高放熱化を目的としてダイパッド１を封止樹脂体７より露出させつつ、ダイパッド１の中央付近を持ち上げることで、半導体素子２の大きさが周囲の電極端子５にオーバーラップしても接触しない構造を有する半導体装置である。
特開２０００―２４３８９１号公報 These QFN type (SON type) semiconductor devices can be reduced in size and thickness by sealing one side so that the electrode terminal 5 is exposed from the bottom surface of the resin sealing body 7. Further, the die pad 1 is exposed from the sealing resin body 7 for the purpose of increasing the heat dissipation, and the vicinity of the center of the die pad 1 is lifted so that the contact is made even if the size of the semiconductor element 2 overlaps the surrounding electrode terminals 5. This is a semiconductor device having a structure that does not.
JP 2000-243891 A

しかしながら、従来の半導体装置の構造では、半導体装置の底面と、封止樹脂体７から露出する電極端子部５とがほぼ平坦である。このため、図８（ｄ）および図９（ｄ）に示すように、基板１６上に接続ランド１５を形成し、電極端子５と接続ランド１５を接合剤１４で固着して半導体装置を基板１６に実装する際に、ごみや異物１７を半導体装置と基板１６との間に挟み込んだ場合には、基板１６と半導体装置との確実な接続ができず、電極端子５と接続ランド１５のコンタクト不良や実装強度低下などの実装不良の原因となる。   However, in the structure of the conventional semiconductor device, the bottom surface of the semiconductor device and the electrode terminal portion 5 exposed from the sealing resin body 7 are substantially flat. For this reason, as shown in FIGS. 8D and 9D, the connection lands 15 are formed on the substrate 16, and the electrode terminals 5 and the connection lands 15 are fixed by the bonding agent 14 to attach the semiconductor device to the substrate 16. When dust or foreign matter 17 is sandwiched between the semiconductor device and the substrate 16 during mounting, the substrate 16 and the semiconductor device cannot be reliably connected, and the contact between the electrode terminal 5 and the connection land 15 is poor. This may cause mounting defects such as mounting strength reduction.

本発明は従来の上記問題点を解決するもので、基板実装時にごみや異物を半導体装置と基板との間に挟み込んでも、基板と半導体装置との確実な接続ができる半導体装置を提供することを目的とする。   The present invention solves the above-described conventional problems, and provides a semiconductor device capable of reliably connecting a substrate and a semiconductor device even if dust or foreign matter is sandwiched between the semiconductor device and the substrate when the substrate is mounted. Objective.

上記した課題を解決するために、本発明の請求項１に係る半導体装置は、半導体素子と、半導体素子を搭載するダイパッドと、前記半導体素子と電気的に接続する複数の電極端子と、前記半導体素子と前記ダイパッドと前記電極端子とを樹脂封止する樹脂封止体とを有する半導体装置であって、前記電極端子の一部が外部端子として樹脂封止体から露出し、前記外部端子の実装対象の基板に対向する一部が凸型に突起して凸型突起部をなすものである。   In order to solve the above-described problem, a semiconductor device according to claim 1 of the present invention includes a semiconductor element, a die pad on which the semiconductor element is mounted, a plurality of electrode terminals electrically connected to the semiconductor element, and the semiconductor A semiconductor device having a resin sealing body for resin-sealing an element, the die pad, and the electrode terminal, wherein a part of the electrode terminal is exposed from the resin sealing body as an external terminal, and the external terminal is mounted A part facing the target substrate protrudes into a convex shape to form a convex protrusion.

上記した構成により、封止樹脂体は四辺形の平板状に形成されているとともに、外部端子が封止樹脂体の底面より露出しており、外部端子は半導体装置底面の周縁に配置される。外部端子の露出面に部分的に凸型の突起に形成された凸型突起部は半導体装置底面と段差を有している。これにより、半導体装置を基板実装する際に、ごみや異物を半導体装置と基板との間に挟み込んでも、基板との確実な接続ができる。   With the configuration described above, the sealing resin body is formed in a quadrangular flat plate shape, the external terminals are exposed from the bottom surface of the sealing resin body, and the external terminals are arranged on the periphery of the bottom surface of the semiconductor device. The convex protrusion part formed on the exposed surface of the external terminal partially on the convex protrusion has a step with the bottom surface of the semiconductor device. As a result, when the semiconductor device is mounted on the substrate, even if dust or foreign matter is sandwiched between the semiconductor device and the substrate, reliable connection with the substrate can be achieved.

本発明の請求項２に係る半導体装置は、外部端子の凸型突起部が平面視で円形に形成されているものである。
本発明の請求項３に係る半導体装置は、外部端子の凸型突起部が２段の階段状に形成されているものである。 According to a second aspect of the present invention, the convex protrusions of the external terminals are formed in a circle in plan view.
The semiconductor device according to claim 3 of the present invention is such that the convex projections of the external terminals are formed in two steps.

本発明の請求項４に係る半導体装置は、外部端子の凸型突起部が半球形に形成されているものである。
本発明の請求項５に係る半導体装置は、ダイパッドの半導体素子を搭載する搭載面に対向する対向面が樹脂封止体から露出する露出面をなし、前記ダイパッドの露出面の一部が凸型に突起して凸部突起部をなすものである。 According to a fourth aspect of the present invention, the convex protrusion of the external terminal is formed in a hemispherical shape.
According to a fifth aspect of the present invention, there is provided a semiconductor device in which a facing surface facing a mounting surface on which a semiconductor element of a die pad is mounted has an exposed surface exposed from a resin sealing body, and a part of the exposed surface of the die pad is a convex type. Projecting to form convex projections.

本発明の請求項６に係る半導体装置は、ダイパッドの凸部突起が２段の階段状に形成されているものである。   In a semiconductor device according to a sixth aspect of the present invention, the protrusions of the die pad are formed in two steps.

以上のように、本発明の半導体装置によれば、半導体装置底面の外部端子の露出面、ダイパッドの露出面に、半導体装置底面と段差を有する凸型の突起を形成することにより、半導体装置を基板実装する際に、ごみや異物を半導体装置と基板との間に挟み込んでも基板との確実な接続ができ、安定した組立実装が可能となり、高品質な半導体装置を提供することができる。   As described above, according to the semiconductor device of the present invention, by forming the convex protrusion having a step difference from the bottom surface of the semiconductor device on the exposed surface of the external terminal on the bottom surface of the semiconductor device and the exposed surface of the die pad. Even when dust or foreign matter is sandwiched between the semiconductor device and the substrate when the substrate is mounted, a reliable connection with the substrate can be achieved, stable assembly and mounting are possible, and a high-quality semiconductor device can be provided.

以下、本発明の半導体装置の実施形態について説明する。図１は本発明の第１の実施形態の半導体装置を示す図であり、図１（ａ）は概略的な構成を示す平面図であり、図１（ｂ）は概略的な構成を示す断面図であり、図１（ｃ）は概略的な構成を示す背面図であり、図１（ｄ）は半導体装置と基板実装時の概略的な構成を示す断面図である。   Hereinafter, embodiments of the semiconductor device of the present invention will be described. FIG. 1 is a view showing a semiconductor device according to a first embodiment of the present invention, FIG. 1 (a) is a plan view showing a schematic configuration, and FIG. 1 (b) is a cross section showing a schematic configuration. FIG. 1C is a rear view showing a schematic configuration, and FIG. 1D is a cross-sectional view showing a schematic configuration when the semiconductor device and the substrate are mounted.

図１（ａ）〜（ｄ）に示すように、第１の実施形態による半導体装置は、サポートリード１３で支持されるダイパッド１に接着剤３を塗布して、その上に半導体素子２を固着しており、ダイパッド１は中央部を周辺部よりもアップセットしている。半導体素子２は金属細線４を介してダイパッド１の周辺にある複数の電極端子５のそれぞれと電気的に接続されている。   As shown in FIGS. 1A to 1D, in the semiconductor device according to the first embodiment, the adhesive 3 is applied to the die pad 1 supported by the support leads 13, and the semiconductor element 2 is fixed thereon. Thus, the die pad 1 is set up in the center part more than the peripheral part. The semiconductor element 2 is electrically connected to each of a plurality of electrode terminals 5 around the die pad 1 through a fine metal wire 4.

ダイパッド１、半導体素子２、接着剤３、金属細線４及び電極端子５は封止樹脂体７で封止されており、封止樹脂体７は４辺形の平板状に形成されている。サポートリード１３は裏面にハーフエッチング加工を施して封止樹脂体７に埋没させている。   The die pad 1, the semiconductor element 2, the adhesive 3, the fine metal wire 4 and the electrode terminal 5 are sealed with a sealing resin body 7, and the sealing resin body 7 is formed in a quadrilateral flat plate shape. The support lead 13 is half-etched on the back surface and embedded in the sealing resin body 7.

電極端子５は金属細線４を接続している接続面（表面）６ａと対向する対向面（背面）６ｂにおいて封止樹脂体７の底面より外部端子として露出しており、電極端子５の一部は封止樹脂体７の底面に露出する部位とは不連続的に封止樹脂体７の側面にも露出している。   The electrode terminal 5 is exposed as an external terminal from the bottom surface of the sealing resin body 7 on the opposing surface (back surface) 6b facing the connection surface (front surface) 6a connecting the thin metal wires 4, and part of the electrode terminal 5 Is also exposed on the side surface of the sealing resin body 7 discontinuously from the portion exposed on the bottom surface of the sealing resin body 7.

封止樹脂体７の底面より外部端子として露出する電極端子５は、実装対象の基板１６に対向する一部が凸型に突起して凸型突起部６ｃに形成されている。ここでは、凸型突起部６ｃが平面視で円形に形成されて凸型丸形状で突起している。   The electrode terminal 5 exposed as an external terminal from the bottom surface of the sealing resin body 7 is formed in a convex protrusion 6c with a part protruding from the mounting target substrate 16 protruding in a convex shape. Here, the convex protrusion 6c is formed in a circular shape in plan view and protrudes in a convex circular shape.

図１（ｄ）に示すように、接続側の基板１６上には接続ランド１５を形成しており、半導体装置の電極端子５の凸型突起部６ｃと基板１６の接続ランド１５とを接合剤１４で接合して半導体装置を基板１６に実装している。   As shown in FIG. 1D, a connection land 15 is formed on the connection-side substrate 16, and the convex protrusion 6 c of the electrode terminal 5 of the semiconductor device and the connection land 15 of the substrate 16 are bonded to each other. The semiconductor device is mounted on the substrate 16 by bonding at 14.

この構成により、基板実装時に半導体装置の底面と基板１６との間に異物１７が挟み込んでも、電極端子５に半導体装置の底面よりも突出する凸型突起部６ｃが存在することで、基板１６の接続ランド１５と電極端子５および凸型突起部６ｃとを接合剤１４によって確実に接続できる。   With this configuration, even when the foreign matter 17 is sandwiched between the bottom surface of the semiconductor device and the substrate 16 when the substrate is mounted, the convex protrusion 6c that protrudes from the bottom surface of the semiconductor device exists in the electrode terminal 5, thereby The connection land 15 can be reliably connected to the electrode terminal 5 and the convex protrusion 6 c by the bonding agent 14.

図２は本発明の第２実施形態の半導体装置を示す図であり、図２（ａ）は概略的な構成を示す平面図であり、図２（ｂ）は概略的な構成を示す断面図であり、図２（ｃ）は概略的な構成を示す背面図である。   2A and 2B are diagrams showing a semiconductor device according to a second embodiment of the present invention. FIG. 2A is a plan view showing a schematic configuration, and FIG. 2B is a cross-sectional view showing the schematic configuration. FIG. 2C is a rear view showing a schematic configuration.

この第２実施形態による半導体装置において、先に図１において説明した半導体装置と異なる部分は、図２（ｂ）に示すように、電極端子５の凸型突起部６ｃが２段の階段状に形成されていることである。この構成により、接合剤１４と凸型突起部６ｃとの接合がより確実となる。   In the semiconductor device according to the second embodiment, as shown in FIG. 2B, the portion different from the semiconductor device described in FIG. 1 is that the convex protrusion 6c of the electrode terminal 5 has a two-step shape. It is formed. With this configuration, the bonding agent 14 and the convex protrusion 6c are more reliably bonded.

図３は本発明の第３実施形態の半導体装置を示す図であり、図３（ａ）は概略的な構成を示す平面図であり、図３（ｂ）は概略的な構成を示す断面図であり、図３（ｃ）は概略的な構成を示す背面図である。   FIG. 3 is a view showing a semiconductor device according to a third embodiment of the present invention, FIG. 3A is a plan view showing a schematic configuration, and FIG. 3B is a cross-sectional view showing the schematic configuration. FIG. 3C is a rear view showing a schematic configuration.

この第３実施形態による半導体装置において、先に図１において説明した半導体装置と異なる部分は、図３（ｂ）に示すように、ダイパッド１の半導体素子２を搭載する搭載面（表面）１ａと対向する対向面（背面）１ｂが封止樹脂体７から露出し、ダイパッド１の露出面の一部が凸型に突起して凸型突起部１ｃとして形成されている。この場合に、ダイパッド１の凸型突起部１ｃを２段の階段状に形成することも可能であり、ダイパッド１の凸型突起部１ｃによっても半導体装置と基板１６との接合力を高める機能を果たすことが可能である。   In the semiconductor device according to the third embodiment, the part different from the semiconductor device described above with reference to FIG. 1 is a mounting surface (front surface) 1a on which the semiconductor element 2 of the die pad 1 is mounted, as shown in FIG. Opposing opposing surface (back surface) 1b is exposed from the sealing resin body 7, and a part of the exposed surface of the die pad 1 protrudes into a convex shape to form a convex protruding portion 1c. In this case, the convex protrusion 1c of the die pad 1 can be formed in two steps, and the convex protrusion 1c of the die pad 1 also functions to increase the bonding force between the semiconductor device and the substrate 16. It is possible to fulfill.

図４は本発明の第４実施形態の半導体装置を示す図であり、図４（ａ）は概略的な構成を示す平面図であり、図４（ｂ）は概略的な構成を示す断面図であり、図４（ｃ）は概略的な構成を示す背面図である。   FIG. 4 is a view showing a semiconductor device according to a fourth embodiment of the present invention, FIG. 4A is a plan view showing a schematic configuration, and FIG. 4B is a cross-sectional view showing the schematic configuration. FIG. 4C is a rear view showing a schematic configuration.

この第４実施形態による半導体装置において、先に図１において説明した半導体装置と異なる部分は、図４（ｂ）に示すように、電極端子５の凸型突起部６ｃの形状が半球形をしていることである。このように、電極端子５の凸型突起部６ｃを半球形に形成することで、後述する半導体装置の製造時の樹脂封止工程で使用するテープと電極端子５との当接が良好となり、樹脂封止工程でパッケージ底面の電極端子５の露出面へ樹脂モレが発生することを低減できる。また、ダイパッド１の凸型突起部１ｃも半球形に形成することが可能である。   In the semiconductor device according to the fourth embodiment, the portion different from the semiconductor device described above with reference to FIG. 1 has a hemispherical shape of the convex protrusion 6c of the electrode terminal 5, as shown in FIG. 4B. It is that. Thus, by forming the convex protrusion 6c of the electrode terminal 5 in a hemispherical shape, the contact between the tape and the electrode terminal 5 used in the resin sealing process at the time of manufacturing a semiconductor device described later becomes good, It is possible to reduce the occurrence of resin leakage on the exposed surface of the electrode terminal 5 on the bottom surface of the package in the resin sealing step. The convex protrusion 1c of the die pad 1 can also be formed in a hemispherical shape.

次に、図５、６を用いて本発明の半導体装置に用いられるリードフレームとその製造方法について説明する。図５は本発明の半導体装置に用いられるリードフレームを示す平面図である。図６は本発明の半導体装置に用いられるリードフレームの製造方法を説明する工程断面図であり、図６（ａ）はリードフレーム素材を示す図であり、図６（ｂ）はリードフレームのエッチング、Ｐｄめっき工程を示す図であり、図６（ｃ）はリードフレームのダイパッド部アップセット工程を示す図であり、図（ｄ）はリードフレーム裏面にテープを貼り付ける工程を示す図である。   Next, a lead frame used in the semiconductor device of the present invention and a manufacturing method thereof will be described with reference to FIGS. FIG. 5 is a plan view showing a lead frame used in the semiconductor device of the present invention. FIG. 6 is a process cross-sectional view illustrating a method of manufacturing a lead frame used in the semiconductor device of the present invention, FIG. 6 (a) is a view showing a lead frame material, and FIG. 6 (b) is an etching of the lead frame. FIG. 6C is a view showing a die pad portion upset process of a lead frame, and FIG. 6D is a view showing a process of attaching a tape to the back surface of the lead frame.

まず、本発明に用いられるリードフレームの一実施形態について、図５を用いて説明する。図５に示すように、リードフレームは、ダイパッド１、電極端子５、外枠１０、内枠１１、穴１２及びサポートリード１３で構成され、１枚のリードフレームに複数個分の半導体装置が配置される。   First, an embodiment of a lead frame used in the present invention will be described with reference to FIG. As shown in FIG. 5, the lead frame includes a die pad 1, an electrode terminal 5, an outer frame 10, an inner frame 11, holes 12, and support leads 13, and a plurality of semiconductor devices are arranged on one lead frame. Is done.

また、図示しないがＰｄなどのめっきが施されており、リードフレーム裏面には樹脂封止する際に電極端子５の露出面への樹脂モレ防止用のテープが貼り付けられている。
次に、本発明に用いられるリードフレーム製造方法の一実施形態について、図６を用いて説明する。図６（ａ）に示すように、リードフレーム素材としては、０．１〜０．２ｍｍ程度の厚みで、比較的熱伝導の良好で、かつ強度の高いＣｕ合金を使用する。熱伝導の良好な素材を使用することによって高い放熱性を備えた半導体装置を提供できる。 Although not shown, Pd or the like is plated, and a tape for preventing resin leakage on the exposed surface of the electrode terminal 5 is attached to the back surface of the lead frame when the resin is sealed.
Next, an embodiment of a lead frame manufacturing method used in the present invention will be described with reference to FIG. As shown in FIG. 6 (a), as the lead frame material, a Cu alloy having a thickness of about 0.1 to 0.2 mm, relatively good heat conduction, and high strength is used. A semiconductor device having high heat dissipation can be provided by using a material having good heat conduction.

次に、図６（ｂ）に示すように、エッチング加工によってダイパッド１、電極端子５などを形成した後に、リードフレーム全体にＰｄめっき（図示せず）を施す。電極端子５の表面にはハーフエッチング加工による溝（図示せず）を形成することで、基板実時などに発生する応力により発生する電極端子５と封止樹脂体７との剥離を止めて、これによる断線を防止することができる。   Next, as shown in FIG. 6B, after forming the die pad 1, the electrode terminal 5, and the like by etching, Pd plating (not shown) is applied to the entire lead frame. By forming a groove (not shown) by a half-etching process on the surface of the electrode terminal 5, the peeling between the electrode terminal 5 and the sealing resin body 7 caused by the stress generated in the actual state of the substrate is stopped, Disconnection due to this can be prevented.

また、ＰｄめっきはＮｉ、Ｐｄ、Ａｕの３層で構成する。最外層にＡｕフラッシュを施すことで、樹脂封止体との良好な密着性を得ることができる。ここでは、Ｐｄめっきを１実施形態としたが、代わりに電極端子５の電気的に接続する部分へＡｇめっきを施しても良い。この場合、半導体装置の組立工程途中で、封止樹脂体７より露出するダイパッド１及び電極端子５に半田めっきなどを施す必要がある。   Pd plating is composed of three layers of Ni, Pd, and Au. By applying Au flash to the outermost layer, good adhesion with the resin sealing body can be obtained. Here, although Pd plating was made into 1 embodiment, you may give Ag plating to the part which the electrode terminal 5 electrically connects instead. In this case, it is necessary to perform solder plating or the like on the die pad 1 and the electrode terminal 5 exposed from the sealing resin body 7 during the assembly process of the semiconductor device.

次に、図６（ｃ）に示すように、プレス加工を途中で止める半切断加工によって、ダイパッド１の中央部を周辺部よりもアップセットし、電極端子５の下面に凸型突起部６ｃを形成して電極下面に段差を儲ける。   Next, as shown in FIG. 6 (c), the center portion of the die pad 1 is upset from the peripheral portion by semi-cutting that stops the pressing process halfway, and the convex protrusion 6 c is formed on the lower surface of the electrode terminal 5. Form a step on the lower surface of the electrode.

次に、図６（ｄ）に示すように、リードフレームの裏面に熱可塑性などの接着剤との２層構造をなすポリイミドテープ９を貼り付ける。このテープ９は樹脂封止する際に凸型突起部６ａを形成した電極端子５の裏面へ封止樹脂がモレないようにするためのものである。   Next, as shown in FIG. 6D, a polyimide tape 9 having a two-layer structure with an adhesive such as thermoplastic is attached to the back surface of the lead frame. This tape 9 is used to prevent the sealing resin from leaking to the back surface of the electrode terminal 5 on which the convex protrusions 6a are formed when the resin is sealed.

以上のようにして、本発明の半導体装置に用いるリードフレームを完成することができる。
次に、本発明半導体装置の製造方法の１実施形態について、図７を用いて説明する。図７は、本発明の半導体装置を製造する工程を説明する工程断面図であり、図７（ａ）は接着剤を塗布する工程を説明する図であり、図７（ｂ）は半導体素子を搭載する工程を説明する図であり、図７（ｃ）は金属細線の接続する工程を説明する図であり、図７（ｄ）は樹脂封止する工程を説明する図であり、図７（ｅ）はリードフレーム裏面のテープを剥離する工程を説明する図であり、図７（ｆ）は半導体装置を個別に分割する工程を説明する図である。 As described above, the lead frame used in the semiconductor device of the present invention can be completed.
Next, one embodiment of a method for manufacturing a semiconductor device of the present invention will be described with reference to FIG. FIG. 7 is a process cross-sectional view illustrating a process of manufacturing a semiconductor device of the present invention, FIG. 7 (a) is a diagram illustrating a process of applying an adhesive, and FIG. 7 (b) is a diagram illustrating a semiconductor element. FIG. 7C is a diagram for explaining a process for connecting a thin metal wire, FIG. 7D is a diagram for explaining a resin sealing process, and FIG. FIG. 7E is a diagram illustrating a process of peeling the tape on the back surface of the lead frame, and FIG. 7F is a diagram illustrating a process of dividing the semiconductor device individually.

まず、図７（ａ）に示すように、ダイパッド１の搭載面１ａの上にディスペンサ（図示せず）などを用いて接着剤３を塗布する。接着剤３は一例として熱硬化性のエポキシ樹脂にＡｇ粉を混合させた銀ペーストからなる。   First, as shown in FIG. 7A, the adhesive 3 is applied onto the mounting surface 1a of the die pad 1 using a dispenser (not shown) or the like. As an example, the adhesive 3 is made of a silver paste in which Ag powder is mixed with a thermosetting epoxy resin.

次に、図７（ｂ）に示すように、接着剤３を塗布したダイパッド１の搭載面１ａの上にコレット（図示せず）などを用いて半導体素子２を搭載した後に、ヒートステージ（図示せず）上で加熱して接着剤３を硬化させる。一例として、半導体素子２は０．１〜０．２ｍｍ程度の厚みのシリコン単結晶である。また、接着剤３の硬化条件は２００〜２５０℃、３０〜６０秒程度である。   Next, as shown in FIG. 7B, after mounting the semiconductor element 2 on the mounting surface 1a of the die pad 1 coated with the adhesive 3 using a collet (not shown), a heat stage (FIG. (Not shown) is heated to cure the adhesive 3. As an example, the semiconductor element 2 is a silicon single crystal having a thickness of about 0.1 to 0.2 mm. The curing conditions for the adhesive 3 are 200 to 250 ° C. and about 30 to 60 seconds.

次に、図７（ｃ）に示すように、ダイパッド１の搭載面１ａの上に固着された半導体素子２のボンディングパッドと電極端子５とを金属細線４を用いて電気的に接続する。
ワイヤーボンド装置のヒートステージ（図示せず）には真空孔が開いており、リードフレーム裏面のテープ９を吸引固定し、また、リードフレームの外周部を押さえ治具（図示せず）によりリードフレームのボンディングエリア外周部を固定した状態で、ワイヤーボンディングを実施する。一例として、金属細線は、直径２０〜２５μｍのＡｕワイヤーを用いる。 Next, as shown in FIG. 7C, the bonding pads of the semiconductor element 2 fixed on the mounting surface 1 a of the die pad 1 and the electrode terminals 5 are electrically connected using the metal thin wires 4.
A vacuum hole is opened in the heat stage (not shown) of the wire bonding apparatus, the tape 9 on the back surface of the lead frame is sucked and fixed, and the outer periphery of the lead frame is held by a holding jig (not shown). Wire bonding is carried out with the outer periphery of the bonding area fixed. As an example, an Au wire having a diameter of 20 to 25 μm is used as the metal thin wire.

次に、図７（ｄ）に示すように、シリンダにより型締めされる１８０℃程度に加熱した封止金型（図示せず）を搭載したトランスファー装置により、複数の半導体装置を一括して樹脂封止する。   Next, as shown in FIG. 7 (d), a plurality of semiconductor devices are collectively collected by a transfer device equipped with a sealing mold (not shown) heated to about 180 ° C. and clamped by a cylinder. Seal.

リードフレームの裏面には樹脂封止の際に電極端子５の裏面に封止樹脂がモレないようにテープ９が貼り付けてある。封止樹脂が硬化して樹脂封止体７が形成された後、型開きされると共にトランスファー装置より脱装される。そして、オモリなどで加圧しながら硬化炉などで封止樹脂の本硬化を実施する。一例として加圧力は１ｇ／ｍｍ２程度である。   A tape 9 is attached to the back surface of the lead frame so that the sealing resin does not leak onto the back surface of the electrode terminal 5 during resin sealing. After the sealing resin is cured and the resin sealing body 7 is formed, the mold is opened and detached from the transfer device. Then, main curing of the sealing resin is performed in a curing furnace or the like while pressing with a weight or the like. As an example, the applied pressure is about 1 g / mm 2.

次に、図７（ｅ）に示すように、封止成型体に２００℃程度の熱を加えながらテープ９を剥離する。テープ９を剥離する場合、封止成型体７に対してできるだけ小さな角度でテープを剥離することで、テープ剥離時の応力を抑制して半導体装置へのダメージを最小限にすることができる。   Next, as shown in FIG.7 (e), the tape 9 is peeled, applying a heat | fever about 200 degreeC to a sealing molding. When the tape 9 is peeled off, the tape is peeled off at the smallest possible angle with respect to the sealing molded body 7, thereby suppressing the stress at the time of tape peeling and minimizing damage to the semiconductor device.

次に、７（ｆ）に示すように、ダイシング装置（図示せず）により半導体装置を個々に分割する。封止成型体７はリングに貼り付けたＵＶシート（図示せず）上に貼り付け固定し、ブレードにより個々の半導体装置に分割する。一例としてブレードは電鋳製で０．２５〜０．３ｍｍ程度の厚みのものである。以上のようにして、本発明の半導体装置を完成することができる。   Next, as shown in 7 (f), the semiconductor device is individually divided by a dicing device (not shown). The sealing molded body 7 is attached and fixed on a UV sheet (not shown) attached to the ring, and is divided into individual semiconductor devices by a blade. As an example, the blade is made of electroforming and has a thickness of about 0.25 to 0.3 mm. As described above, the semiconductor device of the present invention can be completed.

本発明の半導体装置は、半導体装置底面の外部端子の露出面、ダイパッドの露出面に、半導体装置底面と段差を有する凸型の突起を形成することにより、半導体装置を基板実装する際に、ごみや異物を半導体装置と基板との間に挟み込んでも基板との確実な接続ができ、安定した組立実装が可能となり、高品質な半導体装置の提供が可能となる。   In the semiconductor device of the present invention, when the semiconductor device is mounted on the substrate by forming a convex protrusion having a step difference from the bottom surface of the semiconductor device on the exposed surface of the external terminal on the bottom surface of the semiconductor device and the exposed surface of the die pad. Even if a foreign object is sandwiched between the semiconductor device and the substrate, the substrate can be securely connected, stable assembly and mounting can be achieved, and a high-quality semiconductor device can be provided.

本発明の第１実施形態の半導体装置を示す図であり、（ａ）は半導体装置の概略的な構成を示す平面図、（ｂ）は半導体装置の概略的な構成を示す断面図、（ｃ）は半導体装置の概略的な構成を示す背面図、（ｄ）は半導体装置と基板実装時の概略的な構成を示す断面図BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the semiconductor device of 1st Embodiment of this invention, (a) is a top view which shows the schematic structure of a semiconductor device, (b) is sectional drawing which shows the schematic structure of a semiconductor device, (c) ) Is a rear view showing a schematic configuration of the semiconductor device, and (d) is a cross-sectional view showing a schematic configuration when the semiconductor device and the substrate are mounted. 本発明の第２実施形態の半導体装置を示す図であり、（ａ）は半導体装置の概略的な構成を示す平面図、（ｂ）は半導体装置の概略的な構成を示す断面図、（ｃ）は半導体装置の概略的な構成を示す背面図It is a figure which shows the semiconductor device of 2nd Embodiment of this invention, (a) is a top view which shows schematic structure of a semiconductor device, (b) is sectional drawing which shows schematic structure of a semiconductor device, (c) ) Is a rear view showing a schematic configuration of a semiconductor device. 本発明の第３実施形態の半導体装置を示す図であり、（ａ）は半導体装置の概略的な構成を示す平面図、（ｂ）は半導体装置の概略的な構成を示す断面図、（ｃ）は半導体装置の概略的な構成を示す背面図It is a figure which shows the semiconductor device of 3rd Embodiment of this invention, (a) is a top view which shows the schematic structure of a semiconductor device, (b) is sectional drawing which shows the schematic structure of a semiconductor device, (c) ) Is a rear view showing a schematic configuration of a semiconductor device. 本発明の第３実施形態の半導体装置を示す図であり、（ａ）は半導体装置の概略的な構成を示す平面図、（ｂ）は半導体装置の概略的な構成を示す断面図、（ｃ）は半導体装置の概略的な構成を示す背面図It is a figure which shows the semiconductor device of 3rd Embodiment of this invention, (a) is a top view which shows the schematic structure of a semiconductor device, (b) is sectional drawing which shows the schematic structure of a semiconductor device, (c) ) Is a rear view showing a schematic configuration of a semiconductor device. 本発明の半導体装置に用いるリードフレームを示す平面図The top view which shows the lead frame used for the semiconductor device of this invention 本発明の半導体装置に用いるリードフレームの製造方法を説明する工程断面図であり、（ａ）はリードフレーム素材を示す図、（ｂ）はリードフレームのエッチング、Ｐｄめっき工程を示す図、（ｃ）はリードフレームのダイパッド部アップセット工程を示す図、（ｄ）はリードフレーム裏面にテープを貼り付ける工程を示す図FIG. 5 is a process cross-sectional view illustrating a method of manufacturing a lead frame used in the semiconductor device of the present invention, where (a) shows a lead frame material, (b) shows a lead frame etching and Pd plating process, ) Is a diagram showing a die pad portion upset process of the lead frame, and (d) is a diagram showing a process of attaching a tape to the back surface of the lead frame. 本発明の半導体装置を製造する工程を説明する工程断面図であり、（ａ）は接着剤を塗布する工程を説明する図、（ｂ）は半導体素子を搭載する工程を説明する図、（ｃ）は金属細線の接続する工程を説明する図、（ｄ）は樹脂封止する工程を説明する図、（ｅ）はリードフレーム裏面のテープを剥離する工程を説明する図、（ｆ）は半導体装置を個別に分割する工程を説明する図It is process sectional drawing explaining the process of manufacturing the semiconductor device of this invention, (a) is a figure explaining the process of apply | coating an adhesive agent, (b) is a figure explaining the process of mounting a semiconductor element, (c) ) Is a diagram illustrating a process of connecting thin metal wires, (d) is a diagram illustrating a process of resin sealing, (e) is a diagram illustrating a process of peeling the tape on the back surface of the lead frame, and (f) is a semiconductor. The figure explaining the process of dividing an apparatus individually 複数の半導体装置を一括して樹脂封止し、ダイシング加工によって個々の半導体装置に分割する工法を用いた従来の半導体装置を示す図であり、（ａ）は半導体装置の概略的な構成を示す平面図、（ｂ）は半導体装置の概略的な構成を示す断面図、（ｃ）は半導体装置の概略的な構成を示す背面図、（ｄ）は半導体装置の概略的な構成を示す断面図It is a figure which shows the conventional semiconductor device using the construction method which seals several semiconductor devices collectively and divides | segments into each semiconductor device by a dicing process, (a) shows schematic structure of a semiconductor device. FIG. 2B is a cross-sectional view illustrating a schematic configuration of the semiconductor device, FIG. 3C is a rear view illustrating the schematic configuration of the semiconductor device, and FIG. 3D is a cross-sectional view illustrating the schematic configuration of the semiconductor device. 従来の半導体装置を示す図であり、（ａ）は半導体装置の概略的な構成を示す平面図、（ｂ）は半導体装置の概略的な構成を示す断面図、（ｃ）は半導体装置の概略的な構成を示す背面図、（ｄ）は半導体装置と基板実装時の概略的な構成を示す断面図It is a figure which shows the conventional semiconductor device, (a) is a top view which shows the schematic structure of a semiconductor device, (b) is sectional drawing which shows the schematic structure of a semiconductor device, (c) is the outline of a semiconductor device. The rear view which shows typical structure, (d) is sectional drawing which shows schematic structure at the time of a semiconductor device and board | substrate mounting

符号の説明Explanation of symbols

１ ダイパッド
１ｃ 凸型突起部
２ 半導体素子
３ 接着剤
４ 金属細線
５ 電極端子
６ｃ 凸型突起部
７ 樹脂封止体
８ リードフレーム素材
９ テープ
１０ 外枠
１１ 内枠
１２ 孔
１３ サポートリード
１４ 接合剤
１５ 接続ランド
１６ 基板
１７ 異物（ごみ） DESCRIPTION OF SYMBOLS 1 Die pad 1c Convex protrusion 2 Semiconductor element 3 Adhesive 4 Metal thin wire 5 Electrode terminal 6c Convex protrusion 7 Resin sealing body 8 Lead frame material 9 Tape 10 Outer frame 11 Inner frame 12 Hole 13 Support lead 14 Bonding agent 15 Connection land 16 Substrate 17 Foreign matter (garbage)

Claims (7)

半導体素子と、半導体素子を搭載するダイパッドと、前記半導体素子と電気的に接続する複数の電極端子と、前記半導体素子と前記ダイパッドと前記電極端子とを樹脂封止する樹脂封止体とを有する半導体装置であって、前記電極端子の一部が外部端子として樹脂封止体から露出し、前記外部端子の実装対象の基板に対向する一部が凸型に突起して凸型突起部をなすことを特徴とする半導体装置。 A semiconductor element; a die pad for mounting the semiconductor element; a plurality of electrode terminals electrically connected to the semiconductor element; and a resin sealing body for resin-sealing the semiconductor element, the die pad, and the electrode terminal. In the semiconductor device, a part of the electrode terminal is exposed as an external terminal from the resin sealing body, and a part of the external terminal facing the mounting target substrate protrudes in a convex shape to form a convex protrusion. A semiconductor device. 外部端子の凸型突起部が平面視で円形に形成されていることを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the convex protrusions of the external terminals are formed in a circular shape in plan view. 外部端子の凸型突起部が２段の階段状に形成されていることを特徴とする請求項１又は２記載の半導体装置。 The semiconductor device according to claim 1, wherein the convex protrusions of the external terminals are formed in a two-step staircase shape. 外部端子の凸型突起部が半球形に形成されていることを特徴とする請求項１記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the convex protrusion of the external terminal is formed in a hemispherical shape. ダイパッドの半導体素子を搭載する搭載面に対向する対向面が樹脂封止体から露出する露出面をなし、前記ダイパッドの露出面の一部が凸型に突起して凸部突起部をなすことを特徴とする請求項１記載の半導体装置。 A facing surface of the die pad facing the mounting surface on which the semiconductor element is mounted forms an exposed surface exposed from the resin sealing body, and a part of the exposed surface of the die pad protrudes into a convex shape to form a protruding protrusion. The semiconductor device according to claim 1. ダイパッドの凸部突起が２段の階段状に形成されていることを特徴とする請求項５記載の半導体装置。 6. The semiconductor device according to claim 5, wherein the protrusions of the die pad are formed in a two-step shape. ダイパッドの凸型突起部が半球形に形成されていることを特徴とする請求項５記載の半導体装置。 6. The semiconductor device according to claim 5, wherein the convex protrusions of the die pad are formed in a hemispherical shape.
JP2004145740A 2004-05-17 2004-05-17 Semiconductor device Pending JP2005327946A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10325825B2 (en) 2017-09-29 2019-06-18 Mitsubishi Electric Corporation Semiconductor apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10325825B2 (en) 2017-09-29 2019-06-18 Mitsubishi Electric Corporation Semiconductor apparatus

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