JP2005268568A

JP2005268568A - Production method of multilayer printed wiring board

Info

Publication number: JP2005268568A
Application number: JP2004079680A
Authority: JP
Inventors: Manabu Yamada; 学山田; Toru Matsumoto; 徹松本
Original assignee: Nippon CMK Corp; CMK Corp
Current assignee: Nippon CMK Corp; CMK Corp
Priority date: 2004-03-19
Filing date: 2004-03-19
Publication date: 2005-09-29

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a multilayer printed wiring board which can hold the roundness state of a circuit formation reference hole, and can improve position accuracy of interlayer connection and position accuracy of a circuit of an outer layer and an inner layer. <P>SOLUTION: The method is for manufacturing the multilayer printed wiring board with a via connecting at least a wiring layer. The outer layer of an insulating substrate is irradiated with laser and a non-through hole is shaped. After the circuit formation reference hole is shaped, the non-through hole is subjected to conducting processing without performing desmear and metal plating treatment for the circuit formation reference hole. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、層間接続の位置精度に加え、微細回路の位置精度に優れた多層プリント配線板の製造方法に関する。 The present invention relates to a method for manufacturing a multilayer printed wiring board that is excellent in positional accuracy of fine circuits in addition to positional accuracy of interlayer connections.

従来、多層プリント配線板の配線回路の位置決め方法としては、絶縁層にレーザ照射にて非貫通穴を穿孔すると共に、回路形成用基準穴を設け、次いで、デスミア処理、無電解・電解銅めっき処理を施し、写真法にて回路形成を行なっていた。従って、回路用基準穴にも、当然にデスミア処理、無電解・電解銅めっき処理が施されていた（例えば、特許文献１参照）。 Conventionally, as a wiring circuit positioning method for a multilayer printed wiring board, a non-through hole is drilled in the insulating layer by laser irradiation and a reference hole for circuit formation is provided, followed by desmear treatment, electroless / electrolytic copper plating treatment The circuit was formed by a photographic method. Therefore, naturally, the desmear process and the electroless / electrolytic copper plating process were also applied to the circuit reference hole (see, for example, Patent Document 1).

しかしながら、斯かる従来法では、次のような問題点が発生していた。すなわち、回路形成用基準穴にデスミア処理が施されるため、絶縁層が溶解されて非貫通穴が真円ではなくなってしまうと云う問題があった。さらに、無電解・電解銅めっき処理により回路形成用基準穴が当該銅めっきで埋められてしまう結果、非貫通穴を金属めっきで充填する必要がある場合に、基準穴を確認することができないこともあった。
特開２００３−２０９３６４号公報 However, such a conventional method has the following problems. That is, since the desmear process is performed on the reference hole for circuit formation, there is a problem that the insulating layer is dissolved and the non-through hole is not a perfect circle. Furthermore, as a result of the electroless / electrolytic copper plating process filling the circuit formation reference hole with the copper plating, the reference hole cannot be confirmed when it is necessary to fill the non-through hole with metal plating. There was also.
JP 2003-209364 A

本発明は、上記問題点を鑑み、回路形成用基準穴の真円状態を保ち、層間接続の位置精度及び外層と内層の回路の位置精度をより向上せしめることができる多層プリント配線板の製造方法を提供することを課題とする。 SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a multilayer printed wiring board manufacturing method capable of maintaining the perfect circular state of a circuit forming reference hole and further improving the positional accuracy of interlayer connection and the positional accuracy of circuits of an outer layer and an inner layer. It is an issue to provide.

本発明は、少なくとも配線層を接続するビアを備えた多層プリント配線板の製造方法であって、絶縁基板の外層にレーザを照射して非貫通穴を穿孔すると共に、回路形成用基準穴を穿孔した後、該回路形成用基準穴には、デスミア及び金属めっき処理を施すことなく非貫通穴を導通処理することにより上記課題を解決したものである。 The present invention relates to a method for manufacturing a multilayer printed wiring board having at least vias connecting wiring layers, and irradiates a laser on an outer layer of an insulating substrate to drill non-through holes and drill circuit forming reference holes. After that, the above-mentioned problem is solved by conducting non-through holes in the reference holes for circuit formation without conducting desmear and metal plating.

本発明によれば、回路形成用基準穴にデスミア処理及び金属めっき処理を施さないため、レーザ加工にて形成した真円（非貫通穴）を基準に回路形成を行なうことができる結果、従来に比し、多層プリント配線板の層間の位置精度及び外層回路の位置精度を格段に向上せしめることができる。 According to the present invention, since the desmear process and the metal plating process are not performed on the reference hole for circuit formation, the circuit can be formed based on a perfect circle (non-through hole) formed by laser processing. In comparison, the positional accuracy between the layers of the multilayer printed wiring board and the positional accuracy of the outer layer circuit can be remarkably improved.

図１を用いて、本発明の実施形態を詳細に説明する。図１（ａ）に示すように、絶縁基材１に銅箔２を備えたコア材３（多層構造でも構わない）を用意する。次いで、図１（ｂ）に示すように、サブトラクティブ法によりエッチングにて配線回路４及びアライメントマーク６を形成する。次いで、図１（ｃ）に示すように、ビルドアップ基材５を積層し、ビルドアップ配線層を形成する。ここでビルドアップ基材５は樹脂付銅箔（Resin Coated Copper foil（以下、ＲＣＣと呼ぶ））や、銅箔が無いフィルム状樹脂のラミネート、プリプレグ等の接着材料を介して銅箔を張り合わせたものを用いてもよい。 The embodiment of the present invention will be described in detail with reference to FIG. As shown in FIG. 1A, a core material 3 (which may be a multilayer structure) having a copper foil 2 on an insulating substrate 1 is prepared. Next, as shown in FIG. 1B, the wiring circuit 4 and the alignment mark 6 are formed by etching by a subtractive method. Subsequently, as shown in FIG.1 (c), the buildup base material 5 is laminated | stacked and a buildup wiring layer is formed. Here, the build-up base material 5 is obtained by bonding a copper foil with an adhesive material such as a resin-coated copper foil (hereinafter referred to as RCC), a film-like resin laminate without a copper foil, or a prepreg. A thing may be used.

次いで、図１（ｄ）に示すように、内層のレーザ用アライメントマーク６を基準レーザ加工にて非貫通穴７及び回路形成用基準穴８を形成する。ここでビルドアップ基材５にＲＣＣを使用した場合は、予めレーザ照射部とレーザ用アライメントマーク６上の銅箔をエッチングあるいはレーザにて除去する。レーザ照射部においては銅箔上から直接孔明けを行なう方法でもよい。 Next, as shown in FIG. 1 (d), the non-through hole 7 and the circuit forming reference hole 8 are formed on the inner layer laser alignment mark 6 by reference laser processing. Here, when RCC is used for the build-up base material 5, the copper foil on the laser irradiation part and the laser alignment mark 6 is previously removed by etching or laser. In a laser irradiation part, the method of drilling directly from on copper foil may be used.

次いで、図１（ｅ）に示すように、デスミア等のホールクリーニング処理及び無電解銅めっき等の導電化処理は、プリント配線板を支持する治具、あるいは当該処理で使用する薬液に耐えうるレジスト等により、回路基準孔８をマスクする工程と（図示せず）、電解銅めっき９の金属被膜を形成する工程とにより行なう。 Next, as shown in FIG. 1 (e), the hole cleaning process such as desmear and the conductive process such as electroless copper plating are performed using a jig that supports the printed wiring board or a resist that can withstand the chemical used in the process. For example, the step of masking the circuit reference hole 8 (not shown) and the step of forming a metal film of the electrolytic copper plating 9 are performed.

次いで、図１（ｆ）に示すように、写真法にて露光、現像、エッチングにて外層の配線回路１０を形成する。
この図１（ｃ）〜（ｆ）を繰り返すことによって多層化されることは言うまでもない。また、コア層に本発明の基準穴を設けて配線回路を形成しても構わない。 Next, as shown in FIG. 1 (f), an outer layer wiring circuit 10 is formed by exposure, development and etching by a photographic method.
It goes without saying that multilayering is performed by repeating FIGS. 1C to 1F. Moreover, the reference hole of the present invention may be provided in the core layer to form a wiring circuit.

本発明の実施例を図２と共に説明する。 An embodiment of the present invention will be described with reference to FIG.

実施例１
◎非貫通穴の電解銅めっきをフィルドビアめっきとした例
まず、図２（ａ）に示すように、絶縁基材２１に銅箔２２を積層したコア材２３を用意した。 Example 1
Example of Filled Via Plating as Electrolytic Copper Plating for Non-Through Hole First, as shown in FIG. 2A, a core material 23 in which a copper foil 22 was laminated on an insulating base material 21 was prepared.

次いで、図２（ｂ）に示すように、コア材２３に従来のサブトラクティブ法により配線回路２４、後のビルドアップ層と当該コア層を導電接続させるためのレーザ照射により形成される非貫通穴の底部ランド２５、レーザ照射の際の位置合わせに使用するレーザ用アライメントマーク２６、回路形成用基準穴の底部ランド２７を形成した。 Next, as shown in FIG. 2B, a non-through hole formed in the core material 23 by laser irradiation for electrically connecting the wiring circuit 24 and the subsequent buildup layer and the core layer to each other by a conventional subtractive method. , A laser alignment mark 26 used for alignment at the time of laser irradiation, and a bottom land 27 of a reference hole for circuit formation.

次いで、図２に示すように、コア材２３に銅箔の片面にエポキシ樹脂を塗布した樹脂付銅箔（日立化成製「MCF-6000E」）から成るビルドアップ基材２８を積層し、ビルドアップ配線層を形成した。 Next, as shown in FIG. 2, a build-up base material 28 made of resin-coated copper foil (“MCF-6000E” manufactured by Hitachi Chemical Co., Ltd.) in which an epoxy resin is applied to one side of the copper foil is laminated on the core material 23, and build-up is performed. A wiring layer was formed.

次いで、ビルドアップ基材２８の銅箔をエッチング除去し、全面にビルドアップ層樹脂を露出させた。 Next, the copper foil of the buildup base material 28 was removed by etching, and the buildup layer resin was exposed on the entire surface.

次いで、図２（ｄ）に示すように、内層に設けたレーザ用アライメントマーク２６をＣＣＤカメラ（図示せず）で認識させ、内層に形成したバイアホールの底部ランド２５及び回路形成用基準穴の底部ランド２７上のビルドアップ層樹脂にレーザ照射を行ない非貫通穴２９及び回路形成用基準穴３０を形成した。 Next, as shown in FIG. 2D, the laser alignment mark 26 provided in the inner layer is recognized by a CCD camera (not shown), and the bottom land 25 of the via hole formed in the inner layer and the reference hole for circuit formation are formed. The build-up layer resin on the bottom land 27 was irradiated with laser to form a non-through hole 29 and a circuit forming reference hole 30.

次いで、図２（ｅ）に示すように、過マンガン酸ナトリウムを含む溶液でデスミア処理を行ない、次いで無電解銅めっき処理により非貫通穴２９を電気的に導通させた。このデスミア処理及び無電解銅めっきの際に、プリント配線板を支持する治具に回路形成用基準穴３０をマスクする機構を持たせ、デスミア処理及び無電解銅めっき処理が回路形成用基準穴３０に施されないようにした。 Next, as shown in FIG. 2 (e), desmear treatment was performed with a solution containing sodium permanganate, and then the non-through hole 29 was made electrically conductive by electroless copper plating treatment. In the desmearing process and the electroless copper plating, a jig for supporting the printed wiring board is provided with a mechanism for masking the circuit forming reference hole 30, and the desmearing process and the electroless copper plating process are performed as the circuit forming reference hole 30. It was made not to be given to.

次いで、１５μｍの電解銅めっき処理を以下の条件で行ない、電解銅めっき３１の金属被膜を形成した。当該非貫通穴２９への電解銅めっき形態はフィルドビアめっきとした。
※フィルドビアめっき条件
硫酸５０ｇ／ｌ
硫酸銅(II)五水和物２００ｇ／ｌ
塩素イオン５０ｍｇ／ｌ
添加剤適量
水溶液温度２５±２℃
電流密度１．５Ａ／dm² Next, a 15 μm electrolytic copper plating process was performed under the following conditions to form a metal film of the electrolytic copper plating 31. The form of electrolytic copper plating on the non-through holes 29 was filled via plating.
* Filled via plating conditions Sulfuric acid 50g / l
Copper (II) sulfate pentahydrate 200g / l
Chloride ion 50mg / l
Additive Suitable amount Aqueous solution temperature 25 ± 2 ℃
Current density 1.5A / dm ²

次いで、図２（ｆ）に示すように、電解銅めっき３１被膜上にエッチングレジスト（図示せず）をラミネートした後、当該回路形成用基準穴３０とパターンマスクの基準マーク（図示せず）とを位置合わせし、露光、現像、エッチング、エッチングレジスト剥離を行なうことにより、外層の配線回路３２を形成し、多層プリント配線板を得た。尚、同様な工程を繰り返すことにより複数層のビルドアップ層が形成されることは言うまでもない。 Next, as shown in FIG. 2F, after laminating an etching resist (not shown) on the electrolytic copper plating 31 film, the circuit forming reference hole 30 and the reference mark (not shown) of the pattern mask Were aligned, and exposure, development, etching, and etching resist removal were performed to form an outer layer wiring circuit 32 to obtain a multilayer printed wiring board. Needless to say, a plurality of build-up layers are formed by repeating similar steps.

実施例２
◎非貫通穴の電解銅めっきをコンフォーマルめっきとした例
電解銅めっき３１処理工程を下記条件で行なった以外は実施例１と同様にして多層プリント配線板を得た。
※コンフォーマルめっき条件
硫酸１９０ｇ／ｌ
硫酸銅(II)五水和物７５ｇ／ｌ
塩素イオン５０ｍｇ／ｌ
添加剤適量
水溶液温度２５±２℃
電流密度１．５Ａ／dm² Example 2
Example in which electrolytic copper plating of non-through holes was conformal plating A multilayer printed wiring board was obtained in the same manner as in Example 1 except that the electrolytic copper plating 31 treatment step was performed under the following conditions.
* Conformal plating conditions Sulfuric acid 190g / l
Copper (II) sulfate pentahydrate 75g / l
Chloride ion 50mg / l
Additive Suitable amount Aqueous solution temperature 25 ± 2 ℃
Current density 1.5A / dm ²

次に、図３を用いて本発明方法における回路形成用基準穴の状態について説明する。
図３（ａ）は、回路形成用基準穴部を真上から見た拡大平面図で、ビルドアップ基材４３に、真円の回路形成用基準穴４６が形成されている。図３（ｂ）は、同回路形成用基準穴部の拡大断面説明図で、コア材４１に配線回路４２が形成されていると共に、ビルドアップ基材４３に回路形成用基準穴４６が形成されている。因に、この回路形成用基準穴４６は、銅箔エッチングにて開口部を設け、ビルドアップ基材４３に非貫通穴及び回路形成用基準穴をレーザ照射にて穿孔し、当該回路形成用基準穴をマスク治具で塞いだ後、デスミア処理及び無電解・電解銅めっき処理した後の回路形成用基準穴を示している。 Next, the state of the reference hole for circuit formation in the method of the present invention will be described with reference to FIG.
FIG. 3A is an enlarged plan view of the circuit formation reference hole portion as seen from directly above. A perfect circuit formation reference hole 46 is formed in the buildup base 43. FIG. 3B is an enlarged cross-sectional explanatory view of the reference hole portion for circuit formation, in which a wiring circuit 42 is formed in the core material 41 and a reference hole 46 for circuit formation is formed in the build-up base material 43. ing. The circuit forming reference hole 46 is provided with an opening by etching a copper foil, and a non-through hole and a circuit forming reference hole are formed in the build-up base 43 by laser irradiation. The reference hole for circuit formation after desmear processing and electroless / electrolytic copper plating processing is shown after the hole is closed with a mask jig.

比較例１
図４を用いて従来法における回路形成用基準穴の状態について説明する。
図４（ａ）は、回路形成用基準穴部を真上から見た拡大平面説明図で、電解銅めっき５５が施されたビルドアップ基材５３にひずんだ回路形成用基準穴５６が形成されている。図４（ｂ）は、同回路形成用基準穴部の拡大断面説明図で、コア材５１に配線回路５２が形成されていると共に、電解銅めっき５５が施されたビルドアップ基材５３に回路形成用基準穴５６が形成されている。因に、この回路形成用基準穴５６は、銅箔５４にエッチングにて開口部を設け、レーザ照射にてビルドアップ基材５３に非貫通穴及び回路形成用基準穴を穿孔し、デスミア処理及び無電解・電解銅めっき５５を処理した後の回路形成用基準穴を示している。 Comparative Example 1
The state of the circuit formation reference hole in the conventional method will be described with reference to FIG.
FIG. 4A is an enlarged plan view illustrating the circuit formation reference hole portion as viewed from directly above, and the circuit formation reference hole 56 is formed in the build-up base 53 to which the electrolytic copper plating 55 is applied. ing. FIG. 4B is an enlarged cross-sectional explanatory view of the reference hole portion for circuit formation, in which a wiring circuit 52 is formed on the core material 51 and a circuit is applied to the build-up base material 53 on which electrolytic copper plating 55 is applied. A formation reference hole 56 is formed. In this connection, the circuit forming reference hole 56 is provided with an opening in the copper foil 54 by etching, and a non-through hole and a circuit forming reference hole are drilled in the build-up base 53 by laser irradiation. The reference hole for circuit formation after processing the electroless / electrolytic copper plating 55 is shown.

比較例２
図５を用いて、他の従来法における回路形成用基準穴の状態について説明する。
図５（ａ）は、回路形成用基準穴部を真上から見た拡大平面説明図で、電解銅めっき６５が施されている。図５（ｂ）は、同回路形成用基準穴部の拡大断面説明図で、図４に示した従来法における回路形成用基準穴とは、電解銅めっき６５で回路形成用基準穴が埋められている点で相違している。すなわち、図５（ｂ）は、コア材６１に配線回路６２が形成した後、銅箔６４にエッチングにて開口部を設け、レーザ照射にてビルドアップ基材６３に非貫通穴及び回路形成用基準穴を穿孔し、デスミア処理後、ビアフィル用の無電解・電解銅めっき６５を施し、回路形成用基準穴が銅めっきで充填された状態を示している。 Comparative Example 2
The state of the reference hole for circuit formation in another conventional method will be described with reference to FIG.
FIG. 5A is an enlarged plan view illustrating the circuit formation reference hole portion as seen from directly above, and is provided with electrolytic copper plating 65. FIG. 5B is an enlarged cross-sectional explanatory view of the circuit forming reference hole portion. The circuit forming reference hole in the conventional method shown in FIG. Is different. That is, in FIG. 5B, after the wiring circuit 62 is formed in the core material 61, an opening is provided in the copper foil 64 by etching, and the non-through hole and circuit formation are formed in the build-up base 63 by laser irradiation. The reference hole is drilled, and after desmear treatment, electroless / electrolytic copper plating 65 for via fill is applied, and the circuit formation reference hole is filled with copper plating.

試験例
本発明方法と比較例における上記回路形成用基準穴を使用した位置あわせ精度について、比較試験を行なった。その結果は表１のとおりであった。 Test Example A comparative test was performed on the alignment accuracy using the circuit forming reference hole in the method of the present invention and the comparative example. The results are shown in Table 1.

上記表１から明らかな如く、本発明によれば、レーザによる非貫通穴である回路形成用基準穴に対し、デスミア処理が施されていないことにより、穴の真円が保たれ、外層回路基準穴の認識性および当該回路形成用基準穴とパターンマスクの基準マークとの合わせ精度が向上する。 As apparent from Table 1 above, according to the present invention, since the circuit forming reference hole which is a non-through hole by the laser is not subjected to desmear treatment, the perfect circle of the hole is maintained, and the outer layer circuit reference is maintained. The hole recognizability and the alignment accuracy between the circuit forming reference hole and the reference mark of the pattern mask are improved.

また、当該回路形成用基準穴に対し、電解銅めっきが施されていないため、回路形成用基準穴の認識性及び当該回路形成用基準穴とパターンマスクの基準マークとの合わせ精度が格段に向上する。 In addition, since electrolytic copper plating is not applied to the circuit formation reference hole, the recognizability of the circuit formation reference hole and the alignment accuracy between the circuit formation reference hole and the pattern mask reference mark are greatly improved. To do.

本発明の多層プリント配線板の製造工程例を示す断面説明図。Cross-sectional explanatory drawing which shows the example of a manufacturing process of the multilayer printed wiring board of this invention. 本発明の多層プリント配線板の製造工程例を示す斜視説明図。The perspective explanatory view showing the example of a manufacturing process of the multilayer printed wiring board of the present invention. （ａ）は本発明方法における回路形成用基準穴部の拡大平面説明図、（ｂ）は同回路形成用基準穴部の拡大断面説明図。(A) is an enlarged plane explanatory view of the circuit formation reference hole in the method of the present invention, (b) is an enlarged cross-sectional explanatory view of the circuit formation reference hole. （ａ）は従来法における回路形成用基準穴部の拡大平面説明図、（ｂ）は同回路形成用基準穴部の拡大断面説明図。(A) is an enlarged plan explanatory view of a reference hole portion for circuit formation in the conventional method, and (b) is an enlarged cross-sectional explanatory view of the reference hole portion for circuit formation. （ａ）は他の従来法における回路形成用基準穴部の拡大平面説明図、（ｂ）同回路形成用基準穴部の拡大断面説明図。(A) is an enlarged plan explanatory view of a circuit formation reference hole in another conventional method, (b) is an enlarged cross-sectional explanatory view of the circuit formation reference hole.

符号の説明Explanation of symbols

１、２１：絶縁基材
２、２２、５４、６４：銅箔
３、２３、４１、５１、６１：コア材
４、２４、４２、５２、６２：配線回路
５、２８、４３、５３、６３：ビルドアップ基材
６、２６：アライメントマーク
７、２９：非貫通穴
８、３０、４６、５６：回路形成用基準穴
９、３１、５５、６５：電解銅めっき
１０、３２：外層の配線回路
２５：バイアホール底部ランド
２７：回路形成用基準穴の底部ランド 1, 2: 1: Insulating base material 2, 22, 54, 64: Copper foil 3, 23, 41, 51, 61: Core material 4, 24, 42, 52, 62: Wiring circuit 5, 28, 43, 53, 63 : Build-up substrate 6, 26: Alignment mark 7, 29: Non-through hole 8, 30, 46, 56: Reference hole for circuit formation 9, 31, 55, 65: Electrolytic copper plating 10, 32: Wiring circuit of outer layer 25: Via hole bottom land 27: Bottom land of a reference hole for circuit formation

Claims

少なくとも配線層を接続するビアを備えた多層プリント配線板の製造方法であって、絶縁基板の外層にレーザを照射して非貫通穴を穿孔すると共に、回路形成用基準穴を穿孔した後、該回路形成用基準穴にはデスミア及び金属めっき処理を施すことなく非貫通穴を導通処理することを特徴とする多層プリント配線板の製造方法。 A method for manufacturing a multilayer printed wiring board having at least vias for connecting wiring layers, wherein the outer layer of an insulating substrate is irradiated with a laser to drill non-through holes, and after drilling circuit-forming reference holes, A method for producing a multilayer printed wiring board, wherein a non-through hole is subjected to conduction treatment without applying desmear and metal plating treatment to a circuit formation reference hole.