JP2005251780A - Semiconductor circuit component and its manufacturing method - Google Patents

Semiconductor circuit component and its manufacturing method Download PDF

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JP2005251780A
JP2005251780A JP2004055955A JP2004055955A JP2005251780A JP 2005251780 A JP2005251780 A JP 2005251780A JP 2004055955 A JP2004055955 A JP 2004055955A JP 2004055955 A JP2004055955 A JP 2004055955A JP 2005251780 A JP2005251780 A JP 2005251780A
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wiring board
multilayer wiring
circuit component
semiconductor circuit
semiconductor element
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Sadashi Nakamura
禎志 中村
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small and thin semiconductor circuit component with high density, in which a degree of freedom on arrangement of a mounting component such as a semiconductor device can be improved since a support by a rigid body becomes unnecessary as a completed semiconductor circuit component, by using a flexible thin multilayer wiring board to which all wiring layers are IVH-connected without easily being crushed even if it is treated as a multilayer wiring board single body. <P>SOLUTION: In the semiconductor circuit component, all upper and lower wiring layers in the multilayer wiring board 24 formed of flexible insulating substrates 21 are IVH-connected, and the semiconductor device 25 is loaded at least on one face. In the semiconductor circuit component, support by the rigid body becomes unnecessary. Thus, operation effect that the flexibility on arrangement of the mounting component such as the semiconductor device 25 can be obtained. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は多層配線基板上に半導体素子を搭載したフリップチップ型の半導体回路部品およびその製造方法に関するものである。   The present invention relates to a flip-chip type semiconductor circuit component in which a semiconductor element is mounted on a multilayer wiring board and a manufacturing method thereof.

従来の半導体回路部品の製造方法としては、図７に示すものがある。   A conventional method for manufacturing a semiconductor circuit component is shown in FIG.

図７（ａ）〜（ｅ）は従来の半導体回路部品の製造方法を示す断面図である。   7A to 7E are cross-sectional views showing a conventional method for manufacturing a semiconductor circuit component.

図７（ａ）において、金属板１の表面に感光性のソルダーレジスト２を全面に印刷し、パターンマスクを載置して入出力端子３の開口部を形成し、この開口部に電解銅めっき層を形成する。そしてソルダーレジスト２の表面に配線パターン３ａを形成し、このソルダーレジスト２の上に感光性の絶縁樹脂をスクリーン印刷やロールコーター等により塗布し、パターンマスクによりビアホール５を開口させ、第１の絶縁性樹脂層４を形成する。そして、ソルダーレジスト２の上に配線パターン３ａおよび入出力端子３を形成した方法を用いて上記の工程を繰り返し、第１の配線パターン６、ビア導体７、第２の絶縁樹脂層８、ビアホール５ａ、第２の配線パターン９、ビア導体７ａを形成する。   In FIG. 7A, a photosensitive solder resist 2 is printed on the entire surface of the metal plate 1, and a pattern mask is placed to form an opening of the input / output terminal 3, and electrolytic copper plating is applied to the opening. Form a layer. Then, a wiring pattern 3a is formed on the surface of the solder resist 2, and a photosensitive insulating resin is applied on the solder resist 2 by screen printing, a roll coater, or the like, and the via hole 5 is opened by the pattern mask to form the first insulating film. The conductive resin layer 4 is formed. Then, the above steps are repeated using a method in which the wiring pattern 3a and the input / output terminals 3 are formed on the solder resist 2, and the first wiring pattern 6, the via conductor 7, the second insulating resin layer 8, and the via hole 5a. Then, the second wiring pattern 9 and the via conductor 7a are formed.

次に、図７（ｂ）において、金属板１の表面に形成されているカバーフィルムを剥離し、感光性のドライフィルムを貼付し、パターンマスクを載置して露光および現像を行い、入出力端子３に対応する部分に開口部を形成する。そしてエッチングにより開口部の金属板１を除去する。この金属板１の除去により形成された孔１３にプローブ１４を挿入し、入出力端子３と半導体素子１１の接続端子との断線及び短絡を検査する。   Next, in FIG. 7B, the cover film formed on the surface of the metal plate 1 is peeled off, a photosensitive dry film is attached, a pattern mask is placed, and exposure and development are performed. An opening is formed in a portion corresponding to the terminal 3. Then, the metal plate 1 in the opening is removed by etching. A probe 14 is inserted into the hole 13 formed by removing the metal plate 1 to inspect the disconnection and short circuit between the input / output terminal 3 and the connection terminal of the semiconductor element 11.

次に、図７（ｃ）において、絶縁樹脂体上に接続部材１０ａを介して半導体素子１１を載置し、リフロー等により加熱して接続する。そして半導体素子１１を封止樹脂１２で樹脂封止する。   Next, in FIG.7 (c), the semiconductor element 11 is mounted on the insulating resin body via the connection member 10a, and it connects by heating by reflow etc. FIG. Then, the semiconductor element 11 is resin-sealed with a sealing resin 12.

次に、図７（ｄ）において、金属板１の全てをエッチングにより除去し、半導体回路部品１０が形成される。例えば多数個の場合にはダイシンソー等で個片化する。   Next, in FIG. 7D, the entire metal plate 1 is removed by etching, and the semiconductor circuit component 10 is formed. For example, in the case of a large number of pieces, it is separated into pieces by a die-sin saw or the like.

次に、図７（ｅ）において、個片化された半導体回路部品１０の入出力端子３に外部端子として半田ボール１５を形成する。   Next, in FIG. 7E, solder balls 15 are formed as external terminals on the input / output terminals 3 of the separated semiconductor circuit component 10.

なお、この出願の発明に関連する先行技術文献情報としては、例えば、特許文献１が知られている。
特開２００２−１５１６２２号公報 As prior art document information related to the invention of this application, for example, Patent Document 1 is known.
JP 2002-151622 A

しかしながら上記従来の構成では、金属板１の上に積層される配線パターン３ａ及びビア導体７、７ａで回路が形成された絶縁樹脂体の絶縁樹脂として、ビルドアップ基板に用いられるビルドアップ絶縁樹脂を使用しているため、非常に薄い多層配線基板を形成できるが、多層配線基板単体としては非常に機械的強度が弱く、また可撓性もないため脆く破砕しやすいという材料特性を有しているため、製造工程中はもちろん半導体回路部品１０として完成しても常に金属板１や半導体素子１１あるいは実装後の封止樹脂１２といった剛体による支持が必要であるという課題を有していた。   However, in the above conventional configuration, the build-up insulating resin used for the build-up substrate is used as the insulating resin of the insulating resin body in which the circuit is formed by the wiring pattern 3a and the via conductors 7 and 7a laminated on the metal plate 1. Because it is used, a very thin multilayer wiring board can be formed, but the multilayer wiring board itself has a material characteristic that it is very weak in mechanical strength and is not flexible so that it is brittle and easy to break. Therefore, even when the semiconductor circuit component 10 is completed during the manufacturing process, there is always a problem that it is necessary to support the metal plate 1, the semiconductor element 11, or the sealing resin 12 after mounting with a rigid body.

本発明は多層配線基板単体として扱っても簡単に破砕することなく、可撓性を有し、かつ全ての配線層がＩＶＨ接続された薄厚の多層配線基板を用いることによって、完成した半導体回路部品として剛体による支持が不要となるため、半導体素子をはじめとする実装部品の配置自由度を向上させることができ、高密度で小型薄厚の半導体回路部品を提供することを目的とするものである。   The present invention provides a completed semiconductor circuit component by using a thin multilayer wiring board that is flexible and does not easily break even when handled as a single multilayer wiring board, and all wiring layers are IVH-connected. Therefore, the object of the present invention is to provide a semiconductor circuit component having a high density, a small size, and a small thickness.

この目的を達成するために、以下の構成を有するものである。   In order to achieve this object, the present invention has the following configuration.

本発明の請求項１に記載の発明は、可撓性を有する絶縁性基材からなる多層配線基板の上下間の配線層を全てＩＶＨ接続し、少なくとも一面に半導体素子を搭載した半導体回路部品であり、半導体回路部品は剛体による支持が不要となり、半導体素子をはじめとする実装部品の配置自由度が向上するという作用効果が得られる。   The invention according to claim 1 of the present invention is a semiconductor circuit component in which all the wiring layers between the upper and lower layers of a multilayer wiring board made of an insulating base material having flexibility are IVH-connected, and a semiconductor element is mounted on at least one surface. In addition, since the semiconductor circuit component does not need to be supported by a rigid body, the operational effect that the degree of freedom of arrangement of mounting components such as semiconductor elements is improved can be obtained.

請求項２に記載の発明は、絶縁性基材を有機フィルムの両面に硬化しても可撓性を保つ接着剤を塗布する構成とした請求項１に記載の半導体回路部品であり、多層配線基板単体として扱っても簡単に破砕することなく、可撓性を保持するという作用効果が得られる。   The invention according to claim 2 is the semiconductor circuit component according to claim 1, wherein an adhesive that maintains flexibility even when the insulating substrate is cured on both sides of the organic film is applied. Even if it is handled as a single substrate, the effect of maintaining flexibility without being easily crushed can be obtained.

請求項３に記載の発明は、半導体素子をワイヤーボンディングまたはフリップチップボンディングにより実装した請求項１または２に記載の半導体回路部品であり、半導体回路部品の高密度化、小型薄厚化が向上するという作用効果が得られる。   The invention according to claim 3 is the semiconductor circuit component according to claim 1 or 2 in which the semiconductor element is mounted by wire bonding or flip chip bonding, and the densification and miniaturization and thinning of the semiconductor circuit component are improved. The effect is obtained.

請求項４に記載の発明は、多層配線基板の表面が平坦となるように表層配線を埋め込んだ請求項１〜３のいずれか１つに記載の半導体回路部品であり、これにより半導体素子のフリップチップ実装性が向上するという作用効果が得られる。   According to a fourth aspect of the present invention, there is provided the semiconductor circuit component according to any one of the first to third aspects, wherein the surface layer wiring is embedded so that the surface of the multilayer wiring board is flat. The effect of improving chip mountability can be obtained.

請求項５に記載の発明は、多層配線基板の少なくとも一面に少なくとも１つの半導体素子または受動部品デバイスを搭載した請求項１〜４のいずれか１つに記載の半導体回路部品であり、１つの半導体素子だけでは実現困難な回路システムを１つの半導体回路部品として製造可能とする作用効果が得られる。   The invention according to claim 5 is the semiconductor circuit component according to any one of claims 1 to 4, wherein at least one semiconductor element or passive component device is mounted on at least one surface of the multilayer wiring board. An effect is obtained that makes it possible to manufacture a circuit system that is difficult to realize with only elements as a single semiconductor circuit component.

請求項６に記載の発明は、両面に接着剤を塗布した有機フィルムから成る絶縁性基材に孔を形成する工程と、この孔の内部に導電性材料を充填する工程と、この導電性材料が充填された絶縁性基材の両面に配線層としての銅箔を貼り付ける工程と、この銅箔をパターニングする工程とを繰り返して多層配線基板を形成する工程とからなり、この多層配線基板上に形成した電極端子にプローブを接触させ電気検査をする工程と、この電気検査により所定の特性を得た前記多層配線基板に半導体素子を実装してこの半導体素子を封止樹脂で封止する工程とを含む半導体回路部品の製造方法であり、可撓性を有する多層配線基板の製造が可能となる作用効果が得られる。   The invention described in claim 6 includes a step of forming a hole in an insulating substrate made of an organic film having an adhesive applied on both sides, a step of filling a conductive material inside the hole, and the conductive material. A step of affixing a copper foil as a wiring layer on both surfaces of an insulating base material filled with a step of forming a multilayer wiring board by repeating a step of patterning the copper foil. A step of bringing a probe into contact with the electrode terminal formed on the substrate and conducting an electrical inspection, and a step of mounting the semiconductor element on the multilayer wiring board having predetermined characteristics obtained by the electrical inspection and sealing the semiconductor element with a sealing resin A method of manufacturing a semiconductor circuit component including the above-described effects can be obtained, which makes it possible to manufacture a flexible multilayer wiring board.

請求項７に記載の発明は、金属板の片面に配線パターンを形成する工程と、両面に接着剤を塗布した有機フィルムから成る絶縁性基材に孔を形成する工程と、この孔の内部に導電性材料を充填する工程と、この導電性材料が充填された絶縁性基材の両面に前記金属板の配線パターンを形成した面を貼り付けて両側の金属板を除去する工程とを繰り返して多層配線基板を形成する工程とからなり、この多層配線基板上に形成した電極端子にプローブを接触させ電気検査する工程と、この電気検査により所定の特性を得た前記多層配線基板に半導体素子を実装してこの半導体素子を封止樹脂で封止する工程とを含む半導体回路部品の製造方法であり、表層配線が埋め込まれた多層配線基板の製造が可能となる作用効果が得られる。   The invention according to claim 7 includes a step of forming a wiring pattern on one side of a metal plate, a step of forming a hole in an insulating base material made of an organic film coated with an adhesive on both sides, and an inside of the hole. Repeating the step of filling the conductive material and the step of removing the metal plates on both sides by pasting the surfaces on which the wiring patterns of the metal plate are formed on both sides of the insulating base material filled with the conductive material A step of forming a multilayer wiring board, a step of contacting a probe with an electrode terminal formed on the multilayer wiring board and conducting an electrical inspection, and a semiconductor element on the multilayer wiring board that has obtained predetermined characteristics by the electrical inspection. A method of manufacturing a semiconductor circuit component including a step of mounting and sealing the semiconductor element with a sealing resin, and an effect of enabling manufacture of a multilayer wiring board in which surface layer wiring is embedded is obtained.

請求項８に記載の発明は、金属板の片面に配線パターンを形成する工程と、両面に接着剤を塗布した有機フィルムから成る絶縁性基材に孔を形成する工程と、この孔の内部に導電性材料を充填する工程と、この導電性材料を充填した絶縁性基材の両面に前記金属板の配線パターンを形成した面を貼り付けて片面の金属板を除去する工程とを繰り返して多層配線基板を形成する工程とからなり、この多層配線基板に残した金属板に孔を形成し、この孔にプローブを挿入して電気検査する工程と、この電気検査により所定の特性を得た前記多層配線基板に半導体素子を実装してこの半導体素子を封止樹脂で封止する工程と、残った金属板の全てを除去する工程とを含む半導体回路部品の製造方法であり、金属板が支持体として機能するため、特にハンドリング面において半導体回路部品の製造を容易にする作用効果が得られる。   The invention described in claim 8 includes a step of forming a wiring pattern on one side of a metal plate, a step of forming a hole in an insulating substrate made of an organic film coated with an adhesive on both sides, and an inside of the hole. A process of filling a conductive material and a process of attaching a surface on which the wiring pattern of the metal plate is formed on both surfaces of an insulating base material filled with the conductive material and removing the metal plate on one side are repeated to form a multilayer Forming a wiring board, forming a hole in the metal plate left on the multilayer wiring board, inserting a probe into the hole, and performing an electrical inspection, and obtaining the predetermined characteristics by the electrical inspection. A method for manufacturing a semiconductor circuit component, comprising a step of mounting a semiconductor element on a multilayer wiring board and sealing the semiconductor element with a sealing resin, and a step of removing all of the remaining metal plate. To function as a body, especially Action and effect of facilitating the fabrication of semiconductor circuit components is obtained in Ndoringu surface.

以上のように本発明は、可撓性を有する絶縁性基材を有し、少なくとも２層以上の配線層を全てＩＶＨ接続してなる多層配線基板を用いて片面あるいは両面に少なくとも１つ以上の半導体素子が搭載されているという構成を備えることにより、薄い多層配線基板であるにもかかわらず、可撓性を有するため製造工程中はもちろん半導体回路部品として完成しても、脆く破砕するといったことが生じないため、金属板や半導体素子、あるいは実装後の封止樹脂といった剛体による支持が不要となり、半導体素子をはじめとする実装部品の配置自由度を向上させることができ、高密度で小型かつ薄厚の半導体回路部品を提供することができるという効果が得られる。   As described above, the present invention has a flexible insulating base material and uses at least one or both of one or both sides using a multilayer wiring board in which at least two wiring layers are all IVH-connected. Even though it is a thin multi-layer wiring board, it has a configuration in which a semiconductor element is mounted, so that it has flexibility, so even if it is completed as a semiconductor circuit component during the manufacturing process, it is fragile and crushed This eliminates the need for support by a rigid body such as a metal plate, a semiconductor element, or a sealing resin after mounting, and can improve the degree of freedom of placement of mounting components such as semiconductor elements. The effect that a thin semiconductor circuit component can be provided is obtained.

以下、本発明の実施の形態について図を用いて説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

（実施の形態１）
図１（ａ）〜（ｃ）は本発明の実施の形態１における半導体回路部品の構造を示す断面図である。 (Embodiment 1)
1A to 1C are cross-sectional views showing the structure of the semiconductor circuit component according to the first embodiment of the present invention.

図１（ｃ）に示す絶縁性基材２１は有機フィルム２１ａの両面に硬化後も可撓性を有する接着剤２１ｂが塗布された構造を有し、接着剤２１ｂの上には配線パターン２２ａが形成されている。また絶縁性基材２１の両面に形成された配線パターン２２ａを電気的に接続するためのビア２３が形成され、この両面基板を積層することにより図１（ａ）、（ｂ）に示す多層配線基板２４が形成され、隣り合う各層間の配線の接続が実現される。   The insulating substrate 21 shown in FIG. 1C has a structure in which an adhesive 21b having flexibility is applied to both surfaces of the organic film 21a even after curing, and a wiring pattern 22a is formed on the adhesive 21b. Is formed. Further, vias 23 for electrically connecting the wiring patterns 22a formed on both surfaces of the insulating base material 21 are formed, and the multilayer wiring shown in FIGS. 1A and 1B is formed by laminating the double-sided substrates. A substrate 24 is formed, and wiring connection between adjacent layers is realized.

なお、有機フィルム２１ａには製造工程や部品実装工程での耐熱性を考慮し、厚さ１２．５μｍのポリイミドフィルムを用いて密着性を向上させるために放電処理等による表面改質を施し、硬化しても可撓性を有するエポキシ変性ポリイミドからなる接着剤２１ｂを厚さ５〜１０μｍ程度塗布されている。また耐熱性を有する有機フィルム２１ａとしてアラミドフィルム、接着剤２１ｂにはエポキシ接着剤を用いても良い。   The organic film 21a is subjected to surface modification by discharge treatment or the like in order to improve adhesion using a polyimide film having a thickness of 12.5 μm in consideration of heat resistance in the manufacturing process and component mounting process, and cured. Even so, the adhesive 21b made of epoxy-modified polyimide having flexibility is applied to a thickness of about 5 to 10 μm. Further, an aramid film may be used as the organic film 21a having heat resistance, and an epoxy adhesive may be used as the adhesive 21b.

配線パターン２２ａは銅箔を接着剤２１ｂに貼り付けてフォトリソグラフィー工程とエッチング工程により形成される。このとき用いる銅箔は両面が粗化処理された電解銅箔であるが、配線パターン２２ａの線幅が２５μｍ程度実現するために厚みを９μｍ、粗化処理をＲａで２μｍ未満としている。ビア２３は直径約５０μｍのビアホールを形成して銅導電性ペーストを充填して形成している。このようにして形成される多層配線基板２４の上に半導体素子２５がフェイスアップでダイボンドされ、金ワイヤー２６によりワイヤーボンディングで実装され、封止樹脂２７によってモールドされ、多層配線基板２４の裏面に外部端子２８として半田ボールを形成することで図１（ａ）に示す本発明の実施の形態１における半導体回路部品が構成される。   The wiring pattern 22a is formed by attaching a copper foil to the adhesive 21b and performing a photolithography process and an etching process. The copper foil used at this time is an electrolytic copper foil whose both surfaces are roughened, but in order to realize the line width of the wiring pattern 22a of about 25 μm, the thickness is 9 μm, and the roughening treatment is Ra and less than 2 μm. The via 23 is formed by forming a via hole having a diameter of about 50 μm and filling with a copper conductive paste. The semiconductor element 25 is die-bonded face-up on the multilayer wiring board 24 thus formed, mounted by wire bonding with a gold wire 26, molded with a sealing resin 27, and externally attached to the back surface of the multilayer wiring board 24. By forming solder balls as the terminals 28, the semiconductor circuit component according to the first embodiment of the present invention shown in FIG.

図１（ａ）には多層配線基板２４として４層の配線基板を示したが、この層数に限定されるものでない。また多層配線基板２４として図１（ｃ）に示すような両面基板を用いても良い。また図１（ａ）には半導体素子２５として１素子のみを示したが複数の半導体素子２５やその他の部品デバイスが実装されていても良い。また外部端子２８として半田ボールを示したがＬＧＡのような単なる電極、ＰＧＡのようなピン端子など他の外部端子であっても良い。   Although FIG. 1A shows a four-layer wiring board as the multilayer wiring board 24, the number of layers is not limited to this. Further, as the multilayer wiring board 24, a double-sided board as shown in FIG. 1A shows only one element as the semiconductor element 25, a plurality of semiconductor elements 25 and other component devices may be mounted. Although the solder balls are shown as the external terminals 28, other external terminals such as a simple electrode such as LGA or a pin terminal such as PGA may be used.

また、本発明の実施の形態１に用いる多層配線基板２４は総厚が非常に薄い基板となりこの長所を活かす上でさらに半導体回路部品としての総厚を薄く仕上げるためには図１（ｂ）に示すように半導体素子２５が導電性バンプ２９を介してフリップチップ実装されている構造が好ましい。図１（ｂ）においても多層配線基板２４として４層の配線基板が示してあるがこの層数に限定されるわけではない。また多層配線基板２４として図１（ｃ）に示すような両面基板を用いても良い。   Further, the multilayer wiring board 24 used in the first embodiment of the present invention has a very thin total thickness, and in order to take advantage of this advantage, to further reduce the total thickness as a semiconductor circuit component, FIG. As shown, a structure in which the semiconductor element 25 is flip-chip mounted via conductive bumps 29 is preferable. Although FIG. 1B also shows a four-layer wiring board as the multilayer wiring board 24, the number of layers is not limited to this. Further, as the multilayer wiring board 24, a double-sided board as shown in FIG.

図２は本発明の実施の形態１における別の半導体回路部品の構造を示す断面図である。図２に示すように複数の半導体素子２５ａ、２５ｂやその他の部品デバイス３０が多層配線基板２４の両面に実装されていても良い。また外部端子２８として図１（ｂ）には半田ボールを示したがＬＧＡのような単なる電極、ＰＧＡのようなピン端子、図２のような基板端面を利用した電極など他の形状の外部端子２８であっても本発明の実施の形態１における半導体回路部品が構成できることはいうまでもない。   FIG. 2 is a cross-sectional view showing the structure of another semiconductor circuit component according to Embodiment 1 of the present invention. As shown in FIG. 2, a plurality of semiconductor elements 25 a and 25 b and other component devices 30 may be mounted on both surfaces of the multilayer wiring board 24. 1B shows solder balls as the external terminals 28, but external terminals of other shapes such as a simple electrode such as LGA, a pin terminal such as PGA, and an electrode using the substrate end face as shown in FIG. It goes without saying that the semiconductor circuit component according to the first embodiment of the present invention can be configured even with 28.

以下、本発明の実施の形態１における半導体回路部品の製造方法について図を用いて説明する。図３（ａ）〜（ｇ）は本発明の実施の形態１における半導体回路部品の製造方法を示す断面図である。   Hereinafter, a method for manufacturing a semiconductor circuit component according to the first embodiment of the present invention will be described with reference to the drawings. 3A to 3G are cross-sectional views showing a method for manufacturing a semiconductor circuit component in the first embodiment of the present invention.

図３（ａ）において、厚さ１２．５μｍのポリイミドフィルムからなる有機フィルムの両面に密着性を向上させるために放電処理等による表面改質を施し、硬化後も可撓性を有するエポキシ変性ポリイミドからなる接着剤を厚さ５〜１０μｍ塗布し、さらにその両面に保護フィルムとして厚さ９μｍのＰＥＮ（ポリエチレンナフタレート）フィルムをラミネートした絶縁性基材２１を準備する。   In FIG. 3 (a), an epoxy-modified polyimide that is flexible even after curing by subjecting both sides of an organic film made of a polyimide film with a thickness of 12.5 μm to surface adhesion by electrical discharge treatment to improve adhesion. An insulating substrate 21 is prepared by applying an adhesive composed of 5 to 10 μm in thickness and laminating a PEN (polyethylene naphthalate) film having a thickness of 9 μm on both sides as a protective film.

この絶縁性基材２１は総厚が４５〜５０μｍ程度と非常に薄いため、貫通孔の加工時の保持方法として絶縁性基材２１の弛みや皺を取り除く程度にテンションを絶縁性基材２１の四方からかけることによって保持を行った。貫通孔の加工は波長３５５ｎｍのＹＡＧレーザーを用いて行い、ＰＥＮフィルムの上面の孔径で６５〜７５μｍ、ＰＥＮフィルムの下面側からの穴一番小さい孔径が接着層で生じ約４０〜５０μｍの形状となるように加工を実施した。本実施の形態１ではＹＡＧレーザーを用いたが絶縁性基材２１の材質、厚さ、貫通孔の直径の大きさ等によっては炭酸ガスレーザーやパンチングなど他の加工方法でも適用は可能であり、ＹＡＧレーザー法に限定するものではない。そして加工後にＰＥＮフィルムの表面に付着する加工くずのクリーニングを実施した。   Since this insulating base material 21 is very thin with a total thickness of about 45 to 50 μm, tension is applied to the insulating base material 21 so as to remove slack and wrinkles of the insulating base material 21 as a holding method when processing the through-holes. Holding was done by calling from all sides. The through hole is processed using a YAG laser having a wavelength of 355 nm, the hole diameter on the upper surface of the PEN film is 65 to 75 μm, and the smallest hole diameter from the lower surface side of the PEN film is generated in the adhesive layer and has a shape of about 40 to 50 μm. Processing was carried out as follows. Although the YAG laser is used in the first embodiment, other processing methods such as a carbon dioxide laser and punching can be applied depending on the material, thickness, and diameter of the through hole of the insulating base material 21. It is not limited to the YAG laser method. And the processing waste adhering to the surface of a PEN film was processed after processing.

図３（ｂ）において、形成した貫通孔内に銅導電性ペーストをスキージング法で充填した。ここでスキージングする面と反対面から真空吸引を行いながら充填を行い、空気が銅導電性ペースト内に入り込む充填不良の発生を防止しながら銅導電性ペーストの充填性を確保している。本実施の形態１においては２往復のスキージングを繰り返し行い充填の確実性を向上させた。   In FIG.3 (b), the copper conductive paste was filled in the formed through-hole by the squeezing method. Here, filling is performed while performing vacuum suction from the surface opposite to the surface to be squeezed, and the filling property of the copper conductive paste is ensured while preventing the occurrence of filling failure in which air enters the copper conductive paste. In the first embodiment, two-way reciprocating squeezing is repeated to improve filling reliability.

充填する銅導電性ペーストは粒径約５μｍ程度の銅粉体とエポキシ樹脂およびアミン系硬化剤からなる混合材料からなり、銅粉の表面には酸化防止と電気的接合性を良好にするための表面処理を施している。また銅粉の充填密度を高めるため粒径約５μｍの銅粉の他に粒径１〜１．５μｍ程度の銅粉を混合した銅導電性ペーストを用いても良い。そして保護フィルムとしてラミネートしていたＰＥＮフィルムを剥離して絶縁性基材２１の表面に貫通孔以外に付着したペーストの除去を行い、ビア２３を形成した。   The copper conductive paste to be filled is composed of a mixed material composed of copper powder having a particle size of about 5 μm, an epoxy resin, and an amine curing agent. The surface of the copper powder is used for preventing oxidation and improving electrical bonding. Surface treatment is applied. Moreover, you may use the copper conductive paste which mixed copper powder with a particle size of about 1-1.5 micrometers other than copper powder with a particle size of about 5 micrometers in order to raise the filling density of copper powder. Then, the PEN film laminated as the protective film was peeled off, and the paste adhered to the surface of the insulating base material 21 other than the through holes was removed to form the vias 23.

図３（ｃ）において、配線パターン２２ａを形成するための銅箔２２をビア２３が形成された絶縁性基材２１の両面に配置する。このとき用いた銅箔２２は両面が粗化処理された電解銅箔で２５μｍ程度の幅の配線形成を実現するために厚みを約９μｍ、粗化処理をＲａで２μｍ未満としたものを使用した。そしてこの銅箔２２をビア２３に配置した状態でＳＵＳ板の間に挟み込み、真空熱プレス機を用いて温度を約２００℃、加圧を約２００ｋｇ／ｃｍ2で約１時間付加することにより銅箔２２と絶縁性基材２１を接着すると同時に銅箔２２とビア２３の電気的接続を行った。 In FIG. 3C, the copper foil 22 for forming the wiring pattern 22a is arranged on both surfaces of the insulating base material 21 in which the vias 23 are formed. The copper foil 22 used at this time was an electrolytic copper foil whose both surfaces were roughened and had a thickness of about 9 μm and a roughening treatment of Ra of less than 2 μm in order to realize wiring formation with a width of about 25 μm. . Then, the copper foil 22 is sandwiched between the SUS plates in a state where the copper foil 22 is disposed, and the copper foil 22 is applied by applying a temperature of about 200 ° C. and a pressure of about 200 kg / cm 2 for about 1 hour using a vacuum hot press. At the same time, the copper foil 22 and the via 23 were electrically connected.

また、ビア２３として充填された銅導電性ペースト中の銅粉体が圧縮されることにより、銅粉間あるいは銅粉と銅箔２２の間で接触点が増大すると同時に銅導電性ペーストの樹脂が硬化するため導通が発現し、常温に戻ってもビア２３にかけられた圧縮力がビア２３の周囲の銅箔２２と絶縁性基材２１の密着力により維持されるため、回路基板として実用上問題のないレベルの導通が確保される。   Further, by compressing the copper powder in the copper conductive paste filled as the via 23, the contact point increases between the copper powder or between the copper powder and the copper foil 22, and at the same time the resin of the copper conductive paste Since the resin is cured, conduction occurs, and the compressive force applied to the via 23 is maintained by the adhesion between the copper foil 22 and the insulating base material 21 around the via 23 even when the temperature returns to room temperature. A level of continuity is ensured.

図３（ｄ）において、この回路基板の両面に感光性ドライフィルムレジストをラミネートし、所定のパターンが形成された露光マスクを用いて露光を行い、レジストの現像、銅箔２２のエッチングおよび感光性ドライフィルムレジストを除去して配線パターン２２ａを形成する。ここで用いた感光性ドライフィルム、露光マスク、エッチング液等は特別な材料を使用することなく一般的に回路基板の製造に用いられているものを使用した。また装置についても平行光を発生する光源を使用した以外現像やエッチングなどシャワータイプの一般的に使用される装置を使用した。   In FIG. 3D, a photosensitive dry film resist is laminated on both sides of this circuit board, and exposure is performed using an exposure mask on which a predetermined pattern is formed, development of the resist, etching of the copper foil 22 and photosensitivity. The dry film resist is removed to form a wiring pattern 22a. The photosensitive dry film, the exposure mask, the etching solution, and the like used here were those generally used for manufacturing a circuit board without using a special material. Also for the apparatus, a shower type commonly used apparatus such as development and etching was used except that a light source that generates parallel light was used.

図３（ｅ）において、図３（ａ）〜（ｄ）に示す工程を繰り返し、図３（ｄ）に示す基板を積層することにより配線の多層化を実現した。そして表面に形成する配線用としての銅箔は片面を粗化、もう一方の面を光沢の電解銅箔とし、配線パターン２２ａを形成して必要に応じて配線パターン２２ａの表面にＮｉ−Ａｕ等のめっき処理を施したり、ソルダーレジストを形成したりしても良い。さらに部品の実装前に製造された多層配線基板２４の電気検査をプローブ端子やプローブカード等を用いて触針方法で全数検査を行い、高い歩留まりを実現している。また図３（ｄ）に示す基板の両面に積層することでより多層配線基板２４としての反りを抑制することができる。   In FIG. 3E, the steps shown in FIGS. 3A to 3D are repeated, and the substrate shown in FIG. The copper foil for wiring formed on the surface is roughened on one side, and the other side is made of glossy electrolytic copper foil. A wiring pattern 22a is formed, and Ni—Au or the like is formed on the surface of the wiring pattern 22a as necessary. The plating process may be performed or a solder resist may be formed. Further, the electrical inspection of the multilayer wiring board 24 manufactured before mounting the components is 100% inspected by a stylus method using a probe terminal, a probe card, or the like, thereby realizing a high yield. Further, the warpage as the multilayer wiring board 24 can be further suppressed by laminating the both sides of the board shown in FIG.

図３（ｆ）において、電気検査で良品となった多層配線基板２４の上に導電性バンプ２９を形成し、この導電性バンプ２９を介して半導体素子２５を載置し、赤外線リフロー炉やオーブン等で加熱したり、ほぼ半導体素子２５と同等の面積を有する加圧治具を用いて加圧したり、あるいは加圧しながら加熱する方法で接続する。接続方法としては導電性バンプ２９に半田を用いて赤外線リフロー炉やオーブン等で加熱するフリップチップボンディング法が最も好ましいが、導電性バンプ２９としてワイヤーボンディングを利用したＡｕボールバンプやＡｕめっきバンプ等を用いた他のフリップチップボンディング法でも良い。このようにして半導体素子２５の接続パッド上に形成された導電性バンプ２９を介して半導体素子２５と多層配線基板２４の配線パターン２２ａが接続される。そして半導体素子２５を封止樹脂２７で樹脂封止する。樹脂封止の方法は特に限定されるものではなく通常のポッティング法やトランスファーモールド法など用いて樹脂封止を行った。   In FIG. 3 (f), conductive bumps 29 are formed on the multilayer wiring board 24 that has become non-defective in the electrical inspection, and the semiconductor element 25 is placed through the conductive bumps 29, and an infrared reflow furnace or oven is placed. It connects by the method of heating with pressure etc., pressurizing using the pressurization jig | tool which has an area substantially equivalent to the semiconductor element 25, or heating while pressing. As a connection method, a flip chip bonding method in which solder is used for the conductive bumps 29 and heated in an infrared reflow furnace or an oven is the most preferable. However, as the conductive bumps 29, Au ball bumps or Au plating bumps using wire bonding are used. Other flip chip bonding methods used may be used. Thus, the semiconductor element 25 and the wiring pattern 22 a of the multilayer wiring board 24 are connected via the conductive bumps 29 formed on the connection pads of the semiconductor element 25. Then, the semiconductor element 25 is sealed with a sealing resin 27. The resin sealing method is not particularly limited, and the resin sealing is performed using a normal potting method, a transfer molding method, or the like.

図３（ｇ）において、多層配線基板２４に本発明の半導体回路部品用の回路を多数個並べて形成した場合には、ダイシングソーやトムソン歯、金型等を用いて切断し、半導体回路部品を個片化する。そして多層配線基板２４の半導体素子２５を実装した面の裏面側の配線パターン２２ａの上に外部端子２８としての半田ボールを形成した。この半田ボールはフラックスを使用した半田ボール転写法により半田ボールを所定の位置に配置し、赤外線リフロー炉やオーブン等による加熱処理によって形成した。本実施の形態１では外部端子２８として半田ボールを説明したがＬＧＡのような単なる電極、ＰＧＡのようなピン端子、図２に示す基板端面を利用した電極など他の形状の外部端子２８であっても良い。   In FIG. 3G, when a large number of circuits for the semiconductor circuit component of the present invention are formed side by side on the multilayer wiring board 24, the semiconductor circuit component is cut by using a dicing saw, Thomson teeth, a mold or the like. Divide into pieces. Then, solder balls as external terminals 28 were formed on the wiring pattern 22a on the back side of the surface on which the semiconductor element 25 of the multilayer wiring board 24 was mounted. The solder balls were formed by heat treatment using an infrared reflow oven, oven, or the like by placing the solder balls at predetermined positions by a solder ball transfer method using flux. In the first embodiment, the solder ball is described as the external terminal 28. However, the external terminal 28 may have other shapes such as a simple electrode such as LGA, a pin terminal such as PGA, and an electrode using the substrate end face shown in FIG. May be.

（実施の形態２）
図４は本発明の実施の形態２における別の半導体回路部品の構造を示す断面図である。 (Embodiment 2)
FIG. 4 is a cross-sectional view showing the structure of another semiconductor circuit component according to Embodiment 2 of the present invention.

実施の形態１と異なる点は半導体回路部品の構造において、使用する多層配線基板２４の配線パターン２２ａが少なくとも表層の絶縁性基材２１に埋設されている構造である。この配線パターン２２ａが埋設されることにより多層配線基板２４の表面平滑性が向上し、封止樹脂２７の注入がスムーズになり半導体素子２５の実装時に導電性バンプ２９が配線パターン２２ａの上から滑り落ちたり位置ずれが防止でき、フリップチップボンディング法において高い実装歩留まりが実現できる。   The difference from the first embodiment is the structure of the semiconductor circuit component in which the wiring pattern 22a of the multilayer wiring board 24 to be used is embedded in the insulating base material 21 at least on the surface layer. By embedding the wiring pattern 22a, the surface smoothness of the multilayer wiring board 24 is improved, the injection of the sealing resin 27 becomes smooth, and the conductive bumps 29 slip from the wiring pattern 22a when the semiconductor element 25 is mounted. Dropping and positional displacement can be prevented, and a high mounting yield can be realized in the flip chip bonding method.

本実施の形態２における半導体回路部品に使用した材料や多層配線基板１０の構造、実装する半導体素子１１やその他の部品デバイスの種類、外部端子１４の種類などの適用については、実施の形態１での説明と同様で、特に図４の構造に限定されるものではない。   The application of the materials used for the semiconductor circuit components in the second embodiment, the structure of the multilayer wiring board 10, the types of the semiconductor elements 11 and other component devices to be mounted, the types of the external terminals 14 and the like are described in the first embodiment. 4 is not particularly limited to the structure shown in FIG.

以下、本発明の実施の形態２における半導体回路部品の製造方法について図を用いて説明する。図５は本発明の実施の形態２における半導体回路部品の構造を示す断面図である。   Hereinafter, a method for manufacturing a semiconductor circuit component according to Embodiment 2 of the present invention will be described with reference to the drawings. FIG. 5 is a sectional view showing the structure of the semiconductor circuit component according to the second embodiment of the present invention.

図５（ａ）において、金属板３１の上の片面全面に電解銅めっきされた２層の金属板３１を用いて配線パターン２２ａの形成を行った。ここで金属板３１には厚さ約５０μｍのＡｌ合金を用いて製造工程のハンドリングに必要な剛性を付与した。このＡｌ合金の金属板３１の上に直接銅を電解めっきできないため、Ｆｅ、Ｍｎ、Ｚｎ等によるシード層をめっき形成し、銅を厚み約９μｍ電解めっきした。銅の表面は粗化処理されているが、Ｒａで２μｍ未満とした。そして感光性ドライフィルムレジストをラミネートし、所定のパターンが形成された露光マスクを用いて露光を行い、レジストの現像、銅箔のエッチングおよび感光性ドライフィルムレジストの除去を行い、配線パターン２２ａを形成した。   In FIG. 5A, the wiring pattern 22a was formed using a two-layer metal plate 31 that was electrolytically plated with copper on the entire surface of one surface of the metal plate 31. Here, the metal plate 31 was provided with rigidity necessary for handling the manufacturing process using an Al alloy having a thickness of about 50 μm. Since copper could not be electroplated directly on the Al alloy metal plate 31, a seed layer of Fe, Mn, Zn or the like was formed by plating, and the copper was electroplated with a thickness of about 9 μm. The surface of the copper was roughened, but Ra was less than 2 μm. Then, a photosensitive dry film resist is laminated, and exposure is performed using an exposure mask on which a predetermined pattern is formed. The resist is developed, the copper foil is etched, and the photosensitive dry film resist is removed to form a wiring pattern 22a. did.

ここで用いたエッチング液はＡｌと銅のうち銅のみが選択的にエッチングされる必要があり、硫酸過水溶液を使用した。その他は一般的な回路基板の製造に用いられているものを使用し、また装置についても平行光を発生する光源を使用した以外、現像やエッチングなどシャワータイプの一般的に使用される装置を使用した。   As the etching solution used here, only copper of Al and copper needs to be selectively etched, and an aqueous sulfuric acid solution was used. Others are the same as those used for general circuit board manufacturing, and the equipment used is a shower type commonly used equipment such as development and etching, except that a light source that generates parallel light is used. did.

図５（ｂ）において、厚さ１２．５μｍのポリイミドフィルムからなる有機フィルムの両面に密着性を向上させるために放電処理等による表面改質を施し、硬化後も可撓性を有するエポキシ変性ポリイミドからなる接着剤を厚さ５〜１０μｍ塗布し、さらにその両面に保護フィルムとして厚さ９μｍのＰＥＮ（ポリエチレンナフタレート）フィルムをラミネートした絶縁性基材２１を準備する。   In FIG. 5 (b), an epoxy-modified polyimide that is flexible even after curing by applying surface modification to the both sides of an organic film made of a polyimide film having a thickness of 12.5 μm to improve adhesion, such as discharge treatment. An insulating substrate 21 is prepared by applying an adhesive composed of 5 to 10 μm in thickness and laminating a PEN (polyethylene naphthalate) film having a thickness of 9 μm on both sides as a protective film.

この絶縁性基材２１は総厚が４５〜５０μｍ程度と非常に薄いため、貫通孔の加工時の保持方法として絶縁性基材２１の弛みや皺を取り除く程度にテンションを絶縁性基材２１の四方からかけることによって保持を行った。貫通孔の加工は波長３５５ｎｍのＹＡＧレーザーを用いて行い、ＰＥＮフィルムの上面の孔径で６５〜７５μｍ、ＰＥＮフィルムの下面側からの穴一番小さい孔径が接着層で生じ約４０〜５０μｍの形状となるように加工を実施した。本実施の形態２ではＹＡＧレーザーを用いたが絶縁性基材２１の材質、厚さ、貫通孔の直径の大きさ等によっては炭酸ガスレーザーやパンチングなど他の加工方法でも適用は可能であり、ＹＡＧレーザー法に限定するものではない。そして加工後にＰＥＮフィルムの表面に付着する加工くずのクリーニングを実施した。   Since this insulating base material 21 is very thin with a total thickness of about 45 to 50 μm, tension is applied to the insulating base material 21 so as to remove slack and wrinkles of the insulating base material 21 as a holding method when processing the through-holes. Holding was done by calling from all sides. The through hole is processed using a YAG laser having a wavelength of 355 nm, the hole diameter on the upper surface of the PEN film is 65 to 75 μm, and the smallest hole diameter from the lower surface side of the PEN film is generated in the adhesive layer and has a shape of about 40 to 50 μm. Processing was carried out as follows. Although the YAG laser is used in the second embodiment, other processing methods such as a carbon dioxide laser and punching can be applied depending on the material, thickness, and diameter of the through hole of the insulating base material 21. It is not limited to the YAG laser method. And the processing waste adhering to the surface of a PEN film was processed after processing.

図５（ｃ）において、形成した貫通孔内に銅導電性ペーストをスキージング法で充填した。ここでスキージングする面と反対面から真空吸引を行いながら充填を行い、空気が銅導電性ペースト内に入り込む充填不良の発生を防止しながら銅導電性ペーストの充填性を確保している。本実施の形態２においては２往復のスキージングを繰り返し行い充填の確実性を向上させた。   In FIG.5 (c), the copper conductive paste was filled in the formed through-hole by the squeezing method. Here, filling is performed while performing vacuum suction from the surface opposite to the surface to be squeezed, and the filling property of the copper conductive paste is ensured while preventing the occurrence of filling failure in which air enters the copper conductive paste. In the second embodiment, two-way reciprocating squeezing is repeated to improve filling reliability.

ここで、充填する銅導電性ペーストは粒径約５μｍ程度の銅粉体とエポキシ樹脂およびアミン系硬化剤からなる混合材料からなり、銅粉の表面には酸化防止と電気的接合性を良好にするための表面処理を施している。また銅粉の充填密度を高めるため粒径約５μｍの銅粉の他に粒径１〜１．５μｍ程度の銅粉を混合した銅導電性ペーストを用いても良い。そして保護フィルムとしてラミネートしていたＰＥＮフィルムを剥離して絶縁性基材２１の表面に貫通孔以外に付着したペーストの除去を行い、ビア２３を形成した。   Here, the copper conductive paste to be filled is made of a mixed material composed of a copper powder having a particle size of about 5 μm, an epoxy resin, and an amine curing agent, and the surface of the copper powder has good anti-oxidation and electrical bondability. The surface treatment is performed. Moreover, you may use the copper conductive paste which mixed copper powder with a particle size of about 1-1.5 micrometers other than copper powder with a particle size of about 5 micrometers in order to raise the filling density of copper powder. Then, the PEN film laminated as the protective film was peeled off, and the paste adhered to the surface of the insulating base material 21 other than the through holes was removed to form the vias 23.

図５（ｄ）において、配線パターン２２ａを形成した金属板３１をビア２３が形成された絶縁性基材２１の両面の所定位置にアライメントして配置する。そしてこのアライメントされた状態でＳＵＳ板の間に挟み込み、真空熱プレス機を用いて温度を約２００℃、加圧を約２００ｋｇ／ｃｍ2で約１時間付加することにより配線パターン２２ａが形成された金属板３１を絶縁性基材２１に接着すると同時に銅箔とビア２３の電気的接続を行った。またビア２３として充填された銅導電性ペースト中の銅粉体が圧縮されることにより、銅粉間あるいは銅粉と銅箔間で接触点が増大すると同時に銅導電性ペーストの樹脂が硬化するため導通が発現し、常温に戻ってもビア２３にかけられた圧縮力がビア２３の周囲の銅箔と絶縁性基材２１の密着力により維持されるため、回路基板としての実用上問題のないレベルの導通が確保される。 In FIG.5 (d), the metal plate 31 in which the wiring pattern 22a was formed is arrange | positioned in alignment with the predetermined position of both surfaces of the insulating base material 21 in which the via | veer 23 was formed. The metal plate on which the wiring pattern 22a is formed is sandwiched between the SUS plates in this aligned state and is applied for about 1 hour at a temperature of about 200 ° C. and a pressure of about 200 kg / cm 2 using a vacuum hot press. At the same time as 31 was bonded to the insulating substrate 21, the copper foil and the via 23 were electrically connected. Moreover, since the copper powder in the copper conductive paste filled as the via 23 is compressed, the contact point increases between the copper powder or between the copper powder and the copper foil, and at the same time, the resin of the copper conductive paste is cured. Even when the electrical conductivity is developed and the temperature returns to room temperature, the compressive force applied to the via 23 is maintained by the adhesion between the copper foil around the via 23 and the insulating base material 21, so that there is no practical problem as a circuit board. Is ensured.

図５（ｅ）において、Ａｌ合金からなる金属板３１の全てをエッチングにより除去し、Ａｌと銅のうちＡｌのみが選択的にエッチング可能なエッチング液に浸漬して金属板３１の除去を行う。ここで使用したエッチング液は希塩酸や水酸化ナトリウム水溶液を用いた。金属板３１をエッチング除去し、水洗してＦｅ、Ｍｎ、Ｚｎ等によるシード層を水中でふき取り除去することにより、銅の配線パターン２２ａが多層配線基板２４の表面に現れる。なおＦｅ、Ｍｎ、Ｚｎ等によるシード層は専用のエッチング液で溶解させて除去しても良い。   In FIG. 5 (e), the entire metal plate 31 made of an Al alloy is removed by etching, and the metal plate 31 is removed by immersing in an etching solution in which only Al of copper and Al can be selectively etched. The etching solution used here was diluted hydrochloric acid or aqueous sodium hydroxide. The metal plate 31 is removed by etching, washed with water, and the seed layer made of Fe, Mn, Zn or the like is wiped away in water, whereby a copper wiring pattern 22 a appears on the surface of the multilayer wiring board 24. Note that the seed layer made of Fe, Mn, Zn or the like may be removed by dissolving with a dedicated etching solution.

図５（ｆ）において、図５（ａ）〜（ｅ）に示す工程を繰り返し、図５（ｅ）に示す両面基板の両面に積層することにより、配線の多層化を実現した。そして表面に形成する配線用として、必要に応じて配線の表面にＮｉ−Ａｕ等のめっき処理やソルダーレジストを形成したりしても良い。さらに部品の実装前に製造された多層配線基板２４の電気検査をプローブ端子やプローブカード等を用いて触針方法で全数検査を行い、高い歩留まりを実現している。また両面基板の両面に積層することにより多層配線基板２４の反りを防止することができる。   In FIG. 5 (f), the steps shown in FIGS. 5 (a) to 5 (e) were repeated and laminated on both sides of the double-sided substrate shown in FIG. 5 (e), thereby realizing multilayer wiring. For wiring to be formed on the surface, if necessary, a plating process such as Ni—Au or a solder resist may be formed on the surface of the wiring. Further, the electrical inspection of the multilayer wiring board 24 manufactured before mounting the components is 100% inspected by a stylus method using a probe terminal, a probe card, or the like, thereby realizing a high yield. Further, the multilayer wiring board 24 can be prevented from warping by being laminated on both sides of the double-sided board.

図５（ｇ）において、電気検査で良品となった多層配線基板２４の上に導電性バンプ２９を形成し、この導電性バンプ２９を介して半導体素子２５を載置し、赤外線リフロー炉やオーブン等で加熱したり、ほぼ半導体素子２５と同等の面積を有する加圧治具を用いて加圧したり、あるいは加圧しながら加熱する方法で接続する。接続方法としては導電性バンプ２９に半田を用いて赤外線リフロー炉やオーブン等で加熱するフリップチップボンディング法が最も好ましいが、導電性バンプ２９としてワイヤーボンディングを利用したＡｕボールバンプやＡｕめっきバンプ等を用いた他のフリップチップボンディング法でも良い。このようにして半導体素子２５の接続パッド上に形成された導電性バンプ２９を介して半導体素子２５と多層配線基板２４の配線パターン２２ａが接続される。そして半導体素子２５を封止樹脂２７で樹脂封止する。樹脂封止の方法は特に限定されるものではなく通常のポッティング法やトランスファーモールド法など用いて樹脂封止を行った。   In FIG. 5 (g), conductive bumps 29 are formed on the multilayer wiring board 24 that has become non-defective in the electrical inspection, and the semiconductor element 25 is placed through the conductive bumps 29, and an infrared reflow furnace or oven is placed. It connects by the method of heating with pressure etc., pressurizing using the pressurization jig | tool which has an area substantially equivalent to the semiconductor element 25, or heating while pressing. As a connection method, a flip chip bonding method in which solder is used for the conductive bump 29 and heated in an infrared reflow furnace or an oven is the most preferable. Other flip chip bonding methods used may be used. Thus, the semiconductor element 25 and the wiring pattern 22 a of the multilayer wiring board 24 are connected via the conductive bumps 29 formed on the connection pads of the semiconductor element 25. Then, the semiconductor element 25 is sealed with a sealing resin 27. The resin sealing method is not particularly limited, and the resin sealing is performed using a normal potting method, a transfer molding method, or the like.

図５（ｈ）において、多層配線基板２４に本発明の半導体回路部品用の回路を多数個並べて形成した場合には、ダイシングソーやトムソン歯、金型等を用いて切断し、半導体回路部品を個片化する。そして多層配線基板２４の半導体素子２５を実装した面の裏面側の配線パターン２２ａの上に外部端子２８としての半田ボールを形成した。この半田ボールはフラックスを使用した半田ボール転写法により半田ボールを所定の位置に配置し、赤外線リフロー炉やオーブン等による加熱処理によって形成した。本実施の形態２では外部端子２８として半田ボールを説明したがＬＧＡのような単なる電極、ＰＧＡのようなピン端子、図２に示す基板端面を利用した電極など他の形状の外部端子２８であっても良い。   In FIG. 5 (h), when a large number of circuits for the semiconductor circuit component of the present invention are formed side by side on the multilayer wiring board 24, the semiconductor circuit component is cut by using a dicing saw, a Thomson tooth, a mold, or the like. Divide into pieces. Then, solder balls as external terminals 28 were formed on the wiring pattern 22a on the back side of the surface on which the semiconductor element 25 of the multilayer wiring board 24 was mounted. The solder balls were formed by heat treatment using an infrared reflow oven, oven, or the like by placing the solder balls at predetermined positions by a solder ball transfer method using flux. In the second embodiment, the solder ball is described as the external terminal 28. However, the external terminal 28 may have other shapes such as a simple electrode such as LGA, a pin terminal such as PGA, and an electrode using the substrate end face shown in FIG. May be.

（実施の形態３）
以下、本発明の実施の形態３における半導体回路部品の製造方法について、図を用いて説明する。図６は本発明の実施の形態３における半導体回路部品の製造方法を示す断面図である。 (Embodiment 3)
Hereinafter, a method for manufacturing a semiconductor circuit component according to Embodiment 3 of the present invention will be described with reference to the drawings. FIG. 6 is a cross-sectional view showing a method of manufacturing a semiconductor circuit component according to Embodiment 3 of the present invention.

図６（ａ）において、金属板３１の上の片面全面に電解銅めっきされた２層の金属板３１を用いて配線パターン２２ａの形成を行った。ここで金属板３１には厚さ約５０μｍのＡｌ合金を用いて製造工程のハンドリングに必要な剛性を付与した。このＡｌ合金の金属板３１の上に直接銅を電解めっきできないため、Ｆｅ、Ｍｎ、Ｚｎ等によるシード層をめっき形成し、銅を厚み約９μｍ電解めっきした。銅の表面は粗化処理されているが、Ｒａで２μｍ未満とした。そして感光性ドライフィルムレジストをラミネートし、所定のパターンが形成された露光マスクを用いて露光を行い、レジストの現像、銅箔のエッチングおよび感光性ドライフィルムレジストの除去を行い、配線パターン２２ａを形成した。   In FIG. 6A, the wiring pattern 22a was formed by using a two-layer metal plate 31 plated with electrolytic copper on the entire surface of one surface of the metal plate 31. Here, the metal plate 31 was provided with rigidity necessary for handling the manufacturing process using an Al alloy having a thickness of about 50 μm. Since copper could not be electroplated directly on the Al alloy metal plate 31, a seed layer of Fe, Mn, Zn or the like was formed by plating, and the copper was electroplated with a thickness of about 9 μm. The surface of the copper was roughened, but Ra was less than 2 μm. Then, a photosensitive dry film resist is laminated, and exposure is performed using an exposure mask on which a predetermined pattern is formed. The resist is developed, the copper foil is etched, and the photosensitive dry film resist is removed to form a wiring pattern 22a. did.

ここで用いたエッチング液はＡｌと銅のうち銅のみが選択的にエッチングされる必要があり、硫酸過水溶液を使用した。その他は一般的な回路基板の製造に用いられているものを使用し、また装置についても平行光を発生する光源を使用した以外、現像やエッチングなどシャワータイプの一般的に使用される装置を使用した。   As the etching solution used here, only copper of Al and copper needs to be selectively etched, and an aqueous sulfuric acid solution was used. Others are the same as those used for general circuit board manufacturing, and the equipment used is a shower type commonly used equipment such as development and etching, except that a light source that generates parallel light is used. did.

図６（ｂ）において、厚さ１２．５μｍのポリイミドフィルムからなる有機フィルムの両面に密着性を向上させるために放電処理等による表面改質を施し、硬化後も可撓性を有するエポキシ変性ポリイミドからなる接着剤を厚さ５〜１０μｍ塗布し、さらにその両面に保護フィルムとして厚さ９μｍのＰＥＮ（ポリエチレンナフタレート）フィルムをラミネートした絶縁性基材２１を準備する。   In FIG. 6 (b), an epoxy-modified polyimide that is flexible even after curing by subjecting both sides of an organic film made of a polyimide film having a thickness of 12.5 μm to surface adhesion by electrical discharge treatment to improve adhesion. An insulating substrate 21 is prepared by applying an adhesive composed of 5 to 10 μm in thickness and laminating a PEN (polyethylene naphthalate) film having a thickness of 9 μm on both sides as a protective film.

この絶縁性基材２１は総厚が４５〜５０μｍ程度と非常に薄いため、貫通孔の加工時の保持方法として絶縁性基材２１の弛みや皺を取り除く程度にテンションを絶縁性基材２１の四方からかけることによって保持を行った。貫通孔の加工は波長３５５ｎｍのＹＡＧレーザーを用いて行い、ＰＥＮフィルムの上面の孔径で６５〜７５μｍ、ＰＥＮフィルムの下面側からの穴一番小さい孔径が接着層で生じ約４０〜５０μｍの形状となるように加工を実施した。本実施の形態３ではＹＡＧレーザーを用いたが絶縁性基材２１の材質、厚さ、貫通孔の直径の大きさ等によっては炭酸ガスレーザーやパンチングなど他の加工方法でも適用は可能であり、ＹＡＧレーザー法に限定するものではない。そして加工後にＰＥＮフィルムの表面に付着する加工くずのクリーニングを実施した。   Since this insulating base material 21 is very thin with a total thickness of about 45 to 50 μm, tension is applied to the insulating base material 21 so as to remove slack and wrinkles of the insulating base material 21 as a holding method when processing the through-holes. Holding was done by calling from all sides. The through hole is processed using a YAG laser having a wavelength of 355 nm, the hole diameter on the upper surface of the PEN film is 65 to 75 μm, and the smallest hole diameter from the lower surface side of the PEN film is generated in the adhesive layer and has a shape of about 40 to 50 μm. Processing was carried out as follows. Although the YAG laser is used in the third embodiment, other processing methods such as a carbon dioxide laser and punching can be applied depending on the material, thickness, and diameter of the through hole of the insulating base material 21. It is not limited to the YAG laser method. And the processing waste adhering to the surface of a PEN film was processed after processing.

図６（ｃ）において、形成した貫通孔内に銅導電性ペーストをスキージング法で充填した。ここでスキージングする面と反対面から真空吸引を行いながら充填を行い、空気が銅導電性ペースト内に入り込む充填不良の発生を防止しながら銅導電性ペーストの充填性を確保している。本実施の形態３においては２往復のスキージングを繰り返し行い充填の確実性を向上させた。   In FIG.6 (c), the copper conductive paste was filled in the formed through-hole by the squeezing method. Here, filling is performed while performing vacuum suction from the surface opposite to the surface to be squeezed, and the filling property of the copper conductive paste is ensured while preventing the occurrence of filling failure in which air enters the copper conductive paste. In the third embodiment, two-way reciprocating squeezing is repeated to improve filling reliability.

ここで、充填する銅導電性ペーストは粒径約５μｍ程度の銅粉体とエポキシ樹脂およびアミン系硬化剤からなる混合材料からなり、銅粉の表面には酸化防止と電気的接合性を良好にするための表面処理を施している。また銅粉の充填密度を高めるため粒径約５μｍの銅粉の他に粒径１〜１．５μｍ程度の銅粉を混合した銅導電性ペーストを用いても良い。そして保護フィルムとしてラミネートしていたＰＥＮフィルムを剥離して絶縁性基材２１の表面に貫通孔以外に付着したペーストの除去を行い、ビア２３を形成した。   Here, the copper conductive paste to be filled is made of a mixed material composed of a copper powder having a particle size of about 5 μm, an epoxy resin, and an amine curing agent, and the surface of the copper powder has good anti-oxidation and electrical bondability. The surface treatment is performed. Moreover, you may use the copper conductive paste which mixed copper powder with a particle size of about 1-1.5 micrometers other than copper powder with a particle size of about 5 micrometers in order to raise the filling density of copper powder. Then, the PEN film laminated as the protective film was peeled off, and the paste adhered to the surface of the insulating base material 21 other than the through holes was removed to form the vias 23.

図６（ｄ）において、配線パターン２２ａを形成した金属板３１をビア２３が形成された絶縁性基材２１の両面の所定位置にアライメントして配置する。そしてこのアライメントされた状態でＳＵＳ板の間に挟み込み、真空熱プレス機を用いて温度を約２００℃、加圧を約２００ｋｇ／ｃｍ2で約１時間付加することにより配線パターン２２ａが形成された金属板３１を絶縁性基材２１に接着すると同時に銅箔とビア２３の電気的接続を行った。またビア２３として充填された銅導電性ペースト中の銅粉体が圧縮されることにより、銅粉間あるいは銅粉と銅箔間で接触点が増大すると同時に銅導電性ペーストの樹脂が硬化するため導通が発現し、常温に戻ってもビア２３にかけられた圧縮力がビア２３の周囲の銅箔と絶縁性基材２１の密着力により維持されるため、回路基板としての実用上問題のないレベルの導通が確保される。 In FIG. 6D, the metal plate 31 on which the wiring pattern 22a is formed is arranged in alignment with predetermined positions on both surfaces of the insulating base material 21 on which the vias 23 are formed. The metal plate on which the wiring pattern 22a is formed is sandwiched between the SUS plates in this aligned state and is applied for about 1 hour at a temperature of about 200 ° C. and a pressure of about 200 kg / cm 2 using a vacuum hot press. At the same time as 31 was bonded to the insulating substrate 21, the copper foil and the via 23 were electrically connected. Moreover, since the copper powder in the copper conductive paste filled as the via 23 is compressed, the contact point increases between the copper powder or between the copper powder and the copper foil, and at the same time, the resin of the copper conductive paste is cured. Even when the electrical conductivity is developed and the temperature returns to room temperature, the compressive force applied to the via 23 is maintained by the adhesion between the copper foil around the via 23 and the insulating base material 21, so that there is no practical problem as a circuit board. Is ensured.

図６（ｅ）において、Ａｌ合金からなる金属板３１の片面全てをエッチング除去するため、残す側の金属板３１に発泡剥離フィルムやドライフィルムなどをラミネートしてエッチング液に触れないように保護する。次にＡｌと銅のうちＡｌのみが選択的にエッチング可能なエッチング液に浸漬して金属板３１の除去を行う。ここで使用したエッチング液は、希塩酸や水酸化ナトリウム水溶液を用いた。金属板３１をエッチング除去し、水洗した後、Ｆｅ、Ｍｎ、Ｚｎ等によるシード層を水中でふき取り除去することにより、銅の配線パターン２２ａが多層配線基板２４の表面に現れる。なおＦｅ、Ｍｎ、Ｚｎ等によるシード層は専用のエッチング液で溶解除去してもかまわない。最後に、発泡剥離フィルムの場合ならオーブンによる加熱処理、ドライフィルムなら炭酸ナトリウム水溶液による剥離処理することにより除去して片面の金属板３１を残した。   In FIG. 6 (e), in order to etch and remove all one side of the metal plate 31 made of an Al alloy, a foam release film or a dry film is laminated on the remaining metal plate 31 to protect it from contact with the etching solution. . Next, the metal plate 31 is removed by dipping in an etching solution in which only Al of copper and Al can be selectively etched. As the etching solution used here, dilute hydrochloric acid or sodium hydroxide aqueous solution was used. After the metal plate 31 is removed by etching and washed with water, the copper wiring pattern 22a appears on the surface of the multilayer wiring board 24 by wiping and removing the seed layer of Fe, Mn, Zn or the like in water. Note that the seed layer made of Fe, Mn, Zn or the like may be dissolved and removed with a dedicated etching solution. Finally, in the case of a foam release film, it was removed by heat treatment in an oven, and in the case of a dry film, it was removed by a release treatment with an aqueous sodium carbonate solution, leaving a metal plate 31 on one side.

図６（ｆ）において、図６（ａ）〜（ｅ）に示す工程を繰り返し、図６（ｅ）に示す両面基板の片面に積層することにより、配線の多層化を実現した。表面に形成する配線用として必要に応じて配線の表面にＮｉ−Ａｕ等のめっき処理やソルダーレジストを形成しても良い。   6 (f), the steps shown in FIGS. 6 (a) to 6 (e) were repeated and laminated on one side of the double-sided substrate shown in FIG. 6 (e), thereby realizing multilayer wiring. For wiring to be formed on the surface, a plating treatment such as Ni—Au or a solder resist may be formed on the surface of the wiring as necessary.

図６（ｇ）において、金属板３１の上に多層配線基板２４が形成された構造になっているため、通常実施するべき電気検査を行うことができない。そこでこの電気検査を可能にする方法がこの工程である。まず金属板３１の裏面に感光性のドライフィルムをラミネートし、パターンマスクを使って露光および現像を行って、入出力端子３２を露出させる程度の大きさの開口部を形成する。そしてドライフィルムをエッチングレジストとしてドライフィルムの開口部の金属板３１を例えば希塩酸等のエッチング液を使用して除去する。電気検査は金属板３１の開口された孔にプローブ３３を挿入し、半導体素子２５の実装面の配線パターン２２ａにもう一対のプローブ３３を触針することにより電気検査が可能となる。   In FIG. 6G, since the multilayer wiring substrate 24 is formed on the metal plate 31, the electrical inspection that should be normally performed cannot be performed. Therefore, this process is a method that enables this electrical inspection. First, a photosensitive dry film is laminated on the back surface of the metal plate 31, and exposure and development are performed using a pattern mask to form an opening that is large enough to expose the input / output terminal 32. Then, using the dry film as an etching resist, the metal plate 31 at the opening of the dry film is removed using an etchant such as dilute hydrochloric acid. The electrical inspection can be performed by inserting the probe 33 into the opened hole of the metal plate 31 and bringing another pair of probes 33 into contact with the wiring pattern 22a on the mounting surface of the semiconductor element 25.

図６（ｈ）において、電気検査で良品となった多層配線基板２４の上に導電性バンプ２９を形成し、この導電性バンプ２９を介して半導体素子２５を載置し、赤外線リフロー炉やオーブン等で加熱したり、ほぼ半導体素子２５と同等の面積を有する加圧治具を用いて加圧したり、あるいは加圧しながら加熱する方法で接続する。接続方法としては導電性バンプ２９に半田を用いて赤外線リフロー炉やオーブン等で加熱するフリップチップボンディング法が最も好ましいが、導電性バンプ２９としてワイヤーボンディングを利用したＡｕボールバンプやＡｕめっきバンプ等を用いた他のフリップチップボンディング法でも良い。このようにして半導体素子２５の接続パッド上に形成された導電性バンプ２９を介して半導体素子２５と多層配線基板２４の配線パターン２２ａが接続される。そして半導体素子２５を封止樹脂２７で樹脂封止する。樹脂封止の方法は特に限定されるものではなく通常のポッティング法やトランスファーモールド法などを用いて樹脂封止を行った。ここで金属板３１が片面に残っているため、多層配線基板２４に剛性が付加され、ハンドリング性や実装性、実装歩留まりが向上できる。   In FIG. 6 (h), conductive bumps 29 are formed on the multilayer wiring board 24 that has become non-defective in the electrical inspection, and the semiconductor element 25 is placed through the conductive bumps 29, and an infrared reflow furnace or oven is placed. It connects by the method of heating with pressure etc., pressurizing using the pressurization jig | tool which has an area substantially equivalent to the semiconductor element 25, or heating while pressing. As a connection method, a flip chip bonding method in which solder is used for the conductive bump 29 and heated in an infrared reflow furnace or an oven is the most preferable. Other flip chip bonding methods used may be used. Thus, the semiconductor element 25 and the wiring pattern 22 a of the multilayer wiring board 24 are connected via the conductive bumps 29 formed on the connection pads of the semiconductor element 25. Then, the semiconductor element 25 is sealed with a sealing resin 27. The resin sealing method is not particularly limited, and resin sealing was performed using a normal potting method, a transfer mold method, or the like. Here, since the metal plate 31 remains on one side, rigidity is added to the multilayer wiring board 24, and handling properties, mountability, and mounting yield can be improved.

図６（ｉ）において、金属板３１の残りの部分全てをエッチングにより除去するため、Ａｌと銅のうちＡｌのみが選択的にエッチング可能なエッチング液に浸漬して金属板３１の除去を行う。   In FIG. 6I, in order to remove all the remaining portions of the metal plate 31 by etching, the metal plate 31 is removed by immersing in an etchant in which only Al of copper and Al can be selectively etched.

図６（ｊ）において、多層配線基板２４に本発明の半導体回路部品用の回路を多数個並べて形成した場合には、ダイシングソーやトムソン歯、金型等を用いて切断し、半導体回路部品を個片化する。そして多層配線基板２４の半導体素子２５を実装した面の裏面側の配線パターン２２ａの上に外部端子２８としての半田ボールを形成した。この半田ボールはフラックスを使用した半田ボール転写法により半田ボールを所定の位置に配置し、赤外線リフロー炉やオーブン等による加熱処理によって形成した。本実施の形態３では外部端子２８として半田ボールを説明したがＬＧＡのような単なる電極、ＰＧＡのようなピン端子、図２に示す基板端面を利用した電極など他の形状の外部端子２８であっても良い。   In FIG. 6 (j), when a large number of circuits for semiconductor circuit components of the present invention are formed side by side on the multilayer wiring board 24, the semiconductor circuit components are cut by using a dicing saw, Thomson teeth, a mold or the like. Divide into pieces. Then, solder balls as external terminals 28 were formed on the wiring pattern 22a on the back side of the surface on which the semiconductor element 25 of the multilayer wiring board 24 was mounted. The solder balls were formed by heat treatment using an infrared reflow oven, oven, or the like by placing the solder balls at predetermined positions by a solder ball transfer method using flux. In the third embodiment, the solder ball is described as the external terminal 28. However, the external terminal 28 may have other shapes such as a simple electrode such as LGA, a pin terminal such as PGA, and an electrode using the substrate end face shown in FIG. May be.

本発明にかかる半導体回路部品は、部品を実装する多層配線基板が単体で扱っても簡単に破砕することなく、可撓性を有し、かつ全ての配線層がＩＶＨ接続された薄厚の多層配線基板を用いることによって、完成した半導体回路部品として剛体による支持が不要となるため、半導体素子をはじめとする実装部品の配置自由度を向上させることができ、高密度で小型薄厚の半導体回路部品が提供でき、携帯電話をはじめとする小型軽量のモバイル機器に使用する半導体回路部品として有用である。   The semiconductor circuit component according to the present invention is a thin multilayer wiring that is flexible and has all the wiring layers IVH-connected without being easily crushed even if the multilayer wiring substrate on which the component is mounted is handled alone. By using a substrate, it is not necessary to support a rigid semiconductor body as a completed semiconductor circuit component, so it is possible to improve the degree of freedom of placement of mounting components such as semiconductor elements. It can be provided and is useful as a semiconductor circuit component used for small and light mobile devices such as mobile phones.

（ａ）〜（ｃ）本発明の実施の形態１における半導体回路部品の構造を示す断面図(A)-(c) Sectional drawing which shows the structure of the semiconductor circuit component in Embodiment 1 of this invention. 本発明の実施の形態１における別の半導体回路部品の構造を示す断面図Sectional drawing which shows the structure of another semiconductor circuit component in Embodiment 1 of this invention （ａ）〜（ｇ）本発明の実施の形態１における半導体回路部品の製造方法を示す断面図(A)-(g) Sectional drawing which shows the manufacturing method of the semiconductor circuit component in Embodiment 1 of this invention. 本発明の実施の形態２における半導体回路部品の構造を示す断面図Sectional drawing which shows the structure of the semiconductor circuit component in Embodiment 2 of this invention （ａ）〜（ｈ）本発明の実施の形態２における半導体回路部品の製造方法を示す断面図(A)-(h) Sectional drawing which shows the manufacturing method of the semiconductor circuit component in Embodiment 2 of this invention. （ａ）〜（ｊ）本発明の実施の形態３における半導体回路部品の製造方法を示す断面図(A)-(j) Sectional drawing which shows the manufacturing method of the semiconductor circuit component in Embodiment 3 of this invention. （ａ）〜（ｅ）従来の半導体回路部品の製造方法を示す断面図(A)-(e) Sectional drawing which shows the manufacturing method of the conventional semiconductor circuit component

符号の説明Explanation of symbols

２１ 絶縁性基材
２１ａ 有機フィルム
２１ｂ 接着剤
２２ 銅箔
２２ａ 配線パターン
２３ ビア
２４ 多層配線基板
２５ 半導体素子
２５ａ 半導体素子
２５ｂ 半導体素子
２６ 金ワイヤー
２７ 封止樹脂
２８ 外部端子
２９ 導電性バンプ
３０ その他の部品デバイス
３１ 金属板
３２ 入出力端子
３３ プローブ DESCRIPTION OF SYMBOLS 21 Insulating base material 21a Organic film 21b Adhesive agent 22 Copper foil 22a Wiring pattern 23 Via 24 Multilayer wiring board 25 Semiconductor element 25a Semiconductor element 25b Semiconductor element 26 Gold wire 27 Sealing resin 28 External terminal 29 Conductive bump 30 Other components Device 31 Metal plate 32 Input / output terminal 33 Probe

Claims (8)

可撓性を有する絶縁性基材からなる多層配線基板の上下間の配線層を全てＩＶＨ接続し、少なくとも一面に半導体素子を搭載した半導体回路部品。 A semiconductor circuit component in which all wiring layers between upper and lower layers of a multilayer wiring board made of an insulating base material having flexibility are IVH-connected and a semiconductor element is mounted on at least one surface. 絶縁性基材を有機フィルムの両面に硬化しても可撓性を保つ接着剤を塗布する構成とした請求項１に記載の半導体回路部品。 The semiconductor circuit component according to claim 1, wherein an adhesive that maintains flexibility even when the insulating substrate is cured on both surfaces of the organic film is applied. 半導体素子をワイヤーボンディングまたはフリップチップボンディングにより実装した請求項１または２に記載の半導体回路部品。 3. The semiconductor circuit component according to claim 1, wherein the semiconductor element is mounted by wire bonding or flip chip bonding. 多層配線基板の表面が平坦となるように表層配線を埋め込んだ請求項１〜３のいずれか１つに記載の半導体回路部品。 The semiconductor circuit component according to claim 1, wherein the surface layer wiring is embedded so that the surface of the multilayer wiring board is flat. 多層配線基板の少なくとも一面に少なくとも１つの半導体素子または受動部品デバイスを搭載した請求項１〜４のいずれか１つに記載の半導体回路部品。 The semiconductor circuit component according to claim 1, wherein at least one semiconductor element or passive component device is mounted on at least one surface of the multilayer wiring board. 両面に接着剤を塗布した有機フィルムから成る絶縁性基材に孔を形成する工程と、この孔の内部に導電性材料を充填する工程と、この導電性材料が充填された絶縁性基材の両面に配線層としての銅箔を貼り付ける工程と、この銅箔をパターニングする工程とを繰り返して多層配線基板を形成する工程とからなり、この多層配線基板上に形成した電極端子にプローブを接触させ電気検査をする工程と、この電気検査により所定の特性を得た前記多層配線基板に半導体素子を実装してこの半導体素子を封止樹脂で封止する工程とを含む半導体回路部品の製造方法。 A step of forming a hole in an insulating substrate made of an organic film coated with an adhesive on both sides, a step of filling a conductive material into the hole, and an insulating substrate filled with the conductive material. It consists of the process of affixing copper foil as a wiring layer on both sides and the process of patterning this copper foil to form a multilayer wiring board. The probe is brought into contact with the electrode terminals formed on this multilayer wiring board. A method of manufacturing a semiconductor circuit component, comprising: a step of performing an electrical inspection; and a step of mounting a semiconductor element on the multilayer wiring board that has obtained predetermined characteristics by the electrical inspection and sealing the semiconductor element with a sealing resin. . 金属板の片面に配線パターンを形成する工程と、両面に接着剤を塗布した有機フィルムから成る絶縁性基材に孔を形成する工程と、この孔の内部に導電性材料を充填する工程と、この導電性材料が充填された絶縁性基材の両面に前記金属板の配線パターンを形成した面を貼り付けて両側の金属板を除去する工程とを繰り返して多層配線基板を形成する工程とからなり、この多層配線基板上に形成した電極端子にプローブを接触させ電気検査する工程と、この電気検査により所定の特性を得た前記多層配線基板に半導体素子を実装してこの半導体素子を封止樹脂で封止する工程とを含む半導体回路部品の製造方法。 A step of forming a wiring pattern on one side of the metal plate, a step of forming a hole in an insulating substrate made of an organic film coated with an adhesive on both sides, a step of filling a conductive material into the hole, From the step of forming a multilayer wiring board by repeating the steps of pasting the surfaces of the insulating base material filled with the conductive material on both surfaces of the metal plate and removing the metal plates on both sides A step of performing electrical inspection by bringing a probe into contact with an electrode terminal formed on the multilayer wiring board, and mounting the semiconductor element on the multilayer wiring board that has obtained predetermined characteristics by the electrical inspection, and sealing the semiconductor element A method of manufacturing a semiconductor circuit component including a step of sealing with resin. 金属板の片面に配線パターンを形成する工程と、両面に接着剤を塗布した有機フィルムから成る絶縁性基材に孔を形成する工程と、この孔の内部に導電性材料を充填する工程と、この導電性材料を充填した絶縁性基材の両面に前記金属板の配線パターンを形成した面を貼り付けて片面の金属板を除去する工程とを繰り返して多層配線基板を形成する工程とからなり、この多層配線基板に残した金属板に孔を形成し、この孔にプローブを挿入して電気検査する工程と、この電気検査により所定の特性を得た前記多層配線基板に半導体素子を実装してこの半導体素子を封止樹脂で封止する工程と、残った金属板の全てを除去する工程とを含む半導体回路部品の製造方法。 A step of forming a wiring pattern on one side of the metal plate, a step of forming a hole in an insulating substrate made of an organic film coated with an adhesive on both sides, a step of filling a conductive material into the hole, A step of forming a multilayer wiring board by repeating a step of attaching a surface on which the wiring pattern of the metal plate is formed on both surfaces of the insulating base material filled with the conductive material and removing the metal plate on one side. Forming a hole in the metal plate left on the multilayer wiring board, inserting a probe into the hole and conducting an electrical inspection, and mounting a semiconductor element on the multilayer wiring board that has obtained predetermined characteristics by the electrical inspection. A method for manufacturing a semiconductor circuit component, comprising: a step of sealing a semiconductor element with a sealing resin; and a step of removing all remaining metal plates.
JP2004055955A 2004-03-01 2004-03-01 Semiconductor circuit component and its manufacturing method Pending JP2005251780A (en)

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JP2011210930A (en) * 2010-03-30 2011-10-20 Murata Mfg Co Ltd Flexible board, and circuit module including the same
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JP2007227933A (en) * 2006-02-23 2007-09-06 Agere Systems Inc Flexible circuit board for flip-chip-on-flex applications
JP2011210930A (en) * 2010-03-30 2011-10-20 Murata Mfg Co Ltd Flexible board, and circuit module including the same
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