JP2005243944A - Ceramic electronic component - Google Patents

Ceramic electronic component Download PDF

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JP2005243944A
JP2005243944A JP2004052152A JP2004052152A JP2005243944A JP 2005243944 A JP2005243944 A JP 2005243944A JP 2004052152 A JP2004052152 A JP 2004052152A JP 2004052152 A JP2004052152 A JP 2004052152A JP 2005243944 A JP2005243944 A JP 2005243944A
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multilayer body
layers
conductive resin
ceramic electronic
electronic component
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Kazutaka Uchi
一隆 内
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Kyocera Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a ceramic electronic component which is excellent in impact resistance, better in dimensional accuracy and is downsized. <P>SOLUTION: In the ceramic electronic component 10, a laminated element material 1 of a rectangular solid shape is formed by laminating a plurality of ceramic layers 2 through internal conductors 3, 4 with the layers placed therebetween, and terminal electrodes 5, 6 are electrically connected to the internal conductors 3, 4 from a side face to a main surface of the laminated element material 1. The terminal electrode 5, 6 are formed by metal plating layers 5a, 6a adhered to the side face of the laminated element material 1, and by conductive resin layers 5b, 6b adhered to from the main surface of the laminated element material 1 to upper portions of ends of the metal plating layers 5a, 6a. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、セラミック電子部品に関し、特に直方体の一方の端面に複数の端子電極を有するセラミック電子部品の端子電極の構造に関するものである。   The present invention relates to a ceramic electronic component, and more particularly to a structure of a terminal electrode of a ceramic electronic component having a plurality of terminal electrodes on one end face of a rectangular parallelepiped.

代表的なセラミック電子部品として、多連型コンデンサを例にとって説明する。   As a typical ceramic electronic component, a description will be given taking a multiple capacitor as an example.

図４は、従来の多連型コンデンサを示す図であり、（ａ）は外観斜視図、（ｂ）はＸ−Ｘ線断面図である。   4A and 4B are diagrams showing a conventional multiple capacitor, where FIG. 4A is an external perspective view, and FIG. 4B is a cross-sectional view taken along line XX.

図に示すように、多連型コンデンサ３０の積層素体３１は、誘電体層３２を複数積層して形成されている。   As shown in the figure, the multilayer body 31 of the multiple capacitor 30 is formed by laminating a plurality of dielectric layers 32.

また、積層素体３１の各誘電体層（セラミック層）３２間に、例えば複数の第１及び第２の容量形成電極（内部導体）３３、３４が対向形成され、第１の容量形成電極３３は積層素体３１の一端面に、第２の容量形成電極３４は積層素体３１の他端面に延出している。   In addition, a plurality of first and second capacitance forming electrodes (internal conductors) 33 and 34 are formed to face each other between the dielectric layers (ceramic layers) 32 of the multilayer body 31, and the first capacitance forming electrode 33 is formed. Is extended to one end surface of the multilayer body 31 and the second capacitance forming electrode 34 is extended to the other end surface of the multilayer body 31.

さらに、複数の端子電極３５、３６は、積層素体３１の端面及びこの端面に接する主面にまたがって形成されている。これにより、端子電極３５、３６の端面部分で、第１及び第２の容量形成電極３３、３４と接続している。また、端子電極３５、３６の主面部分（実装面）は、配線基板との実装が確実のものとしている。   Further, the plurality of terminal electrodes 35 and 36 are formed across the end surface of the multilayer body 31 and the main surface in contact with the end surface. Thus, the end surfaces of the terminal electrodes 35 and 36 are connected to the first and second capacitance forming electrodes 33 and 34. Further, the main surface portions (mounting surfaces) of the terminal electrodes 35 and 36 are surely mounted on the wiring board.

また、端子電極３５、３６の表面には、必要に応じて、表面メッキ層（図示せず）が形成されている。   Further, a surface plating layer (not shown) is formed on the surfaces of the terminal electrodes 35 and 36 as necessary.

このような多連型コンデンサ３０は、一方の主面（実装面）を下にして配線基板１１上の配線パターン１２に半田１３などの接合材により表面実装される。   Such a multiple capacitor 30 is surface-mounted on the wiring pattern 12 on the wiring board 11 with a bonding material such as solder 13 with one main surface (mounting surface) facing down.

ここで、近年、多連型コンデンサ３０は、携帯型電話機や携帯型コンピュータなどの携帯型電子機器への需要が増えてきている。   Here, in recent years, demand for portable electronic devices such as portable telephones and portable computers has been increasing.

しかしながら、携帯型電子機器は、使用時や携帯時において、落下などによる衝撃が、機器内部の配線基板に実装されている多連型コンデンサ３０に加わり、図４に示すように、多連型コンデンサ３０にクラック３８が発生するという問題点があった。   However, when the portable electronic device is used or carried, impact due to dropping or the like is applied to the multiple capacitor 30 mounted on the wiring board inside the device, and as shown in FIG. There was a problem that cracks 38 occurred in 30.

そこで、図５に示すように、複数積層された誘電体層４２間に容量形成電極（内部導体）４３、４４が形成された直方体の積層素体４１と、積層素体４１の端面から主面にまたがるように形成されるとともに、容量形成電極４３、４４に接続し、且つ金属成分及びガラス成分を含む導電性ペーストを焼き付けた下地導体層４５ａ、４６ａと、下地導体層４５ａ、４６ａの主面部及び積層素体４１主面にまたがるように形成された導電性樹脂層４５ｂ、４６ｂとからなる端子電極４５、４６とを備えた多連型コンデンサ４０が特開２００３−７５６７号公報に開示されている（特許文献1参照）。
特開２００３−７５６７号公報 （３−５頁、図１−１３） Therefore, as shown in FIG. 5, a rectangular parallelepiped laminated body 41 in which capacitance forming electrodes (internal conductors) 43 and 44 are formed between a plurality of laminated dielectric layers 42, and from the end face of the laminated body 41 to the main surface The base conductor layers 45a and 46a connected to the capacitor forming electrodes 43 and 44 and baked with a conductive paste containing a metal component and a glass component, and main surface portions of the base conductor layers 45a and 46a. Japanese Unexamined Patent Application Publication No. 2003-7567 discloses a multiple capacitor 40 including terminal electrodes 45 and 46 including conductive resin layers 45b and 46b formed so as to straddle the main surface of the multilayer body 41. (See Patent Document 1).
JP 2003-7567 A (page 3-5, FIG. 1-13)

しかしながら、近年、発明者の調査によれば、積層素体４１の端面と主面との面取り部、端子電極４５、４６及び接合材１３が接している部分を起点としてクラック３８が発生し、積層素体４１の側面に進行することがわかってきている。すなわち、図５に示す多連型コンデンサ４０では、積層素体４１の端面と主面との面取り部には下地導体層４５ａ、４６ａのみが形成されているため、積層素体４１の端面と主面との面取り部に生じる応力を緩和するには限界があり、落下などによる衝撃が厳しくなった場合、クラック３８の発生を防止するには限界があった。   However, recently, according to the inventor's investigation, the crack 38 is generated starting from the chamfered portion between the end surface and the main surface of the multilayer body 41, the portion where the terminal electrodes 45 and 46, and the bonding material 13 are in contact with each other. It has been found that it proceeds to the side surface of the element body 41. That is, in the multiple capacitor 40 shown in FIG. 5, only the base conductor layers 45a and 46a are formed at the chamfered portion between the end surface and the main surface of the multilayer body 41. There is a limit to alleviate the stress generated in the chamfered portion with the surface, and there is a limit to prevent the generation of the crack 38 when the impact due to dropping or the like becomes severe.

また、下地導体層４５ａ、４６ａは、ガラス成分を含むため、このガラス成分を起点としてクラック３８が発生しやすくなっていた。   In addition, since the underlying conductor layers 45a and 46a include a glass component, the cracks 38 are likely to be generated starting from the glass component.

さらに、下地導体層４５ａ、４６ａは、導電性ペーストを焼き付けて形成されるため、積層素体４１の主面に形成される下地導体層４５ａ、４６ａの厚みを精度良く制御することが困難であり、多連型コンデンサ４０のＴ方向の寸法バラツキの原因となっていた。また、導電性樹脂層４５ｂ、４６ｂは、積層素体４１の主面において下地導体層４５ａ、４６ａにのり上げるように形成されるため、多連型コンデンサ４０のＴ方向の寸法が大きくなり、小型化が困難であるという問題点があった。   Furthermore, since the underlying conductor layers 45a and 46a are formed by baking conductive paste, it is difficult to accurately control the thickness of the underlying conductor layers 45a and 46a formed on the main surface of the multilayer body 41. This is a cause of dimensional variation in the T direction of the multiple capacitor 40. In addition, since the conductive resin layers 45b and 46b are formed on the main surface of the multilayer body 41 so as to be lifted up to the underlying conductor layers 45a and 46a, the size of the multiple capacitor 40 in the T direction is increased and the size is reduced. There was a problem that it was difficult to make it.

本発明は、上述の問題点に鑑みて案出されたものであり、その目的は、耐衝撃性に優れているとともに、寸法精度が良好であり、小型化が可能であるセラミック電子部品を提供することにある。   The present invention has been devised in view of the above-mentioned problems, and an object thereof is to provide a ceramic electronic component that has excellent impact resistance, good dimensional accuracy, and can be miniaturized. There is to do.

本発明は、複数のセラミック層を間に内部導体を介して積層することにより直方体状の積層素体を形成するとともに、該積層素体の側面より主面にかけて前記内部導体に電気的に接続される端子電極を形成してなるセラミック電子部品において、前記端子電極が、前記積層素体の側面に被着される金属メッキ層と、前記積層素体の主面より前記金属メッキ層の端部上にかけて被着される導電性樹脂層とで形成されていることを特徴とするものである。   The present invention forms a rectangular parallelepiped multilayer body by laminating a plurality of ceramic layers with an internal conductor interposed therebetween, and is electrically connected to the internal conductor from the side surface to the main surface of the multilayer body. In the ceramic electronic component formed by forming the terminal electrode, the terminal electrode is attached to a side surface of the multilayer body, and the end of the metal plating layer is above the main surface of the multilayer body. It is characterized by being formed with a conductive resin layer to be applied over.

また、前記積層素体の側面と主面との間の角部に曲面状の面取りが施されており、該面取り部上で前記金属メッキ層と導電性樹脂層とが重畳されていることを特徴とするものである。   Further, a curved chamfer is applied to a corner portion between the side surface and the main surface of the multilayer body, and the metal plating layer and the conductive resin layer are superimposed on the chamfered portion. It is a feature.

さらに、前記導電性樹脂層が内方より外方に向かって漸次厚く形成されていることを特徴とするものである。   Furthermore, the conductive resin layer is formed so as to be gradually thicker from the inside toward the outside.

そして、前記導電性樹脂層のヤング率が０．１〜１５ＧＰａであることを特徴とするものである。   And the Young's modulus of the said conductive resin layer is 0.1-15GPa, It is characterized by the above-mentioned.

本発明によれば、端子電極が、積層素体の側面に被着される金属メッキ層と、積層素体の主面より金属メッキ層の端部上にかけて被着される導電性樹脂層とで形成されている。すなわち、ヤング率が小さい導電性樹脂層の存在により、応力を吸収できるとともに、金属メッキ層はガラス成分を含まないため、落下などによる衝撃が厳しくなった場合も、クラックをより効果的に低減できる。   According to the present invention, the terminal electrode includes the metal plating layer that is deposited on the side surface of the multilayer body, and the conductive resin layer that is deposited from the main surface of the multilayer body to the end of the metal plating layer. Is formed. That is, the presence of the conductive resin layer having a low Young's modulus can absorb stress, and the metal plating layer does not contain a glass component, so that even when the impact due to dropping becomes severe, cracks can be reduced more effectively. .

また、積層素体の側面と主面との間の角部に曲面状の面取りが施されており、面取り部上で金属メッキ層と導電性樹脂層とが重畳されている。すなわち、積層素体の面取り部に形成される端子電極の内、ヤング率が小さい導電性樹脂層の体積が占める割合を大きくすることができることから、このことによっても、落下などの衝撃によるクラックをより効果的に低減できる。   In addition, a curved chamfer is applied to the corner between the side surface and the main surface of the multilayer body, and the metal plating layer and the conductive resin layer are superimposed on the chamfer. That is, the proportion of the volume of the conductive resin layer having a small Young's modulus among the terminal electrodes formed on the chamfered portion of the multilayer body can be increased. It can reduce more effectively.

さらに、金属メッキ層は、積層素体の主面に形成されないことから、Ｔ方向の寸法バラツキを低減できるため、寸法精度が良好になる。また、Ｔ方向の寸法を小さくできることにより、小型化が可能である。   Furthermore, since the metal plating layer is not formed on the main surface of the multilayer body, the dimensional variation in the T direction can be reduced, so that the dimensional accuracy is improved. Further, since the dimension in the T direction can be reduced, the size can be reduced.

さらに、導電性樹脂層が内方より外方に向かって漸次厚く形成されているため、Ｔ方向の寸法を増大させることなく、積層素体の面取り部に形成される端子電極の内、ヤング率が小さい導電性樹脂層の体積が占める割合を大きくすることができることから、このことによっても、落下などの衝撃によるクラックをより効果的に低減できるとともに、寸法精度が良好であり、且つ小型化が可能である。   Furthermore, since the conductive resin layer is formed to be gradually thicker from the inside to the outside, the Young's modulus among the terminal electrodes formed on the chamfered portion of the multilayer body without increasing the dimension in the T direction. Since the proportion of the volume of the small conductive resin layer can be increased, this can also reduce cracks due to impacts such as dropping more effectively, with good dimensional accuracy, and miniaturization. Is possible.

そして、導電性樹脂層のヤング率が０．１〜１５ＧＰａである。すなわち、導電性樹脂層のヤング率が１５ＧＰａより大きい場合、落下などの衝撃によるクラックを低減できなくなる。一方、導電性樹脂層のヤング率が０．１ＧＰａ未満である場合、外部応力により変形しやすくなる。   And the Young's modulus of a conductive resin layer is 0.1-15GPa. That is, when the Young's modulus of the conductive resin layer is greater than 15 GPa, cracks due to impact such as dropping cannot be reduced. On the other hand, when the Young's modulus of the conductive resin layer is less than 0.1 GPa, the conductive resin layer is easily deformed by external stress.

以下、本発明のセラミック電子部品を図面に基づいて説明する。   The ceramic electronic component of the present invention will be described below with reference to the drawings.

代表的なセラミック電子部品として、多連型コンデンサを例にとって説明する。   As a typical ceramic electronic component, a description will be given taking a multiple capacitor as an example.

図１は、本発明の多連型コンデンサを示す断面図である。図２は、図１の多連型コンデンサを配線基板上に表面実装した状態を示す断面図である。   FIG. 1 is a cross-sectional view showing a multiple capacitor of the present invention. FIG. 2 is a cross-sectional view showing a state where the multiple capacitor of FIG. 1 is surface-mounted on a wiring board.

図において、１０は多連型コンデンサ（セラミック電子部品）、１は積層素体、２は誘電体層（セラミック層）、３、４は内部導体、５、６は端子電極である。また、１１は配線基板、１２は配線パターン、１３は半田（接合材）である。   In the figure, 10 is a multiple capacitor (ceramic electronic component), 1 is a multilayer body, 2 is a dielectric layer (ceramic layer), 3 and 4 are internal conductors, and 5 and 6 are terminal electrodes. Further, 11 is a wiring board, 12 is a wiring pattern, and 13 is solder (bonding material).

図１に示すように、多連型コンデンサ１０の積層素体１は、誘電体層２を複数積層して形成されている。   As shown in FIG. 1, the multilayer body 1 of the multiple capacitor 10 is formed by laminating a plurality of dielectric layers 2.

誘電体層２は、チタン酸バリウム（ＢａＴｉＯ３）を主成分とする非還元性誘電体材料、及びガラス成分を含む誘電体材料からなり、その形状は、２．０ｍｍ×１．２ｍｍなどであり、その厚みは高容量化のために１〜５μｍとしている。この誘電体層２が図上、上方向に積層して積層素体１が構成される。なお、誘電体層２の形状、厚み、積層数は容量値によって任意に変更することができる。 The dielectric layer 2 is made of a non-reducing dielectric material mainly composed of barium titanate (BaTiO 3 ) and a dielectric material containing a glass component, and its shape is 2.0 mm × 1.2 mm or the like. The thickness is set to 1 to 5 μm for increasing the capacity. This dielectric layer 2 is laminated in the upward direction in the figure to form a multilayer body 1. The shape, thickness, and number of layers of the dielectric layer 2 can be arbitrarily changed depending on the capacitance value.

積層素体１の各誘電体層２間に、例えばＮｉを主成分とする内部導体３、４が形成され、その厚みは１〜２μｍであり、内部導体３、４の端部が積層素体１の両端面あるいは端面と主面の面取り部に夫々延出している。また、内部導体３、４は、誘電体層２を挟んで対向形成される容量形成電極３ａ、４ａと、積層素体１の積層方向の上下側且つ端面付近に形成されるとともに、互いに対向しないダミー電極３ｂ、４ｂとからなる。ここで、図中では、積層素体１の端面に容量形成電極３ａ、４ａの端部が延出するとともに、積層素体１の端面と主面の面取り部にダミー電極３ｂｂ、４ｂの端部が延出しているが、積層素体１の端面にダミー電極３ｂ、４の一部の端部が延出するようにしても良く、また積層素体１の端面と主面の面取り部に容量形成電極３ａ、４ａの一部の端部が延出するようにしても良い。   Between each dielectric layer 2 of the multilayer body 1, for example, inner conductors 3 and 4 mainly composed of Ni are formed, the thickness thereof is 1 to 2 μm, and the ends of the inner conductors 3 and 4 are the multilayer body. 1 is extended to both end surfaces or chamfered portions of the end surface and the main surface. Further, the inner conductors 3 and 4 are formed on the upper and lower sides in the stacking direction of the multilayer body 1 and in the vicinity of the end surfaces of the capacitor forming electrodes 3a and 4a formed to face each other with the dielectric layer 2 interposed therebetween, and do not face each other It consists of dummy electrodes 3b and 4b. Here, in the drawing, the end portions of the capacitance forming electrodes 3a and 4a extend to the end face of the multilayer body 1, and the end portions of the dummy electrodes 3bb and 4b are chamfered between the end face and the main surface of the multilayer body 1. However, some end portions of the dummy electrodes 3b and 4 may extend to the end surface of the multilayer body 1, and the end surfaces of the multilayer body 1 and the chamfered portion of the main surface may have capacitance. You may make it the one part edge part of the formation electrodes 3a and 4a extend.

端子電極５、６は、積層素体１の一対の長辺側端面に被着形成され、且つ内部導体３、４にそれぞれ接続されている。   The terminal electrodes 5 and 6 are formed on the pair of long side end surfaces of the multilayer body 1 and are connected to the internal conductors 3 and 4, respectively.

本発明の特徴的なことは、端子電極５、６が、積層素体１の側面に被着される金属メッキ層５ａ、６ａと、積層素体１の主面より金属メッキ層５ａ、６ａの端部上にかけて被着される導電性樹脂層５ｂ、６ｂとで形成されていることである。   The characteristic feature of the present invention is that the terminal electrodes 5 and 6 are metal plating layers 5 a and 6 a that are deposited on the side surfaces of the multilayer body 1, and the metal plating layers 5 a and 6 a from the main surface of the multilayer body 1. That is, the conductive resin layers 5b and 6b are formed on the end portions.

また、積層素体１の側面と主面との間の角部に曲面状の面取りが施されており、面取り部上で金属メッキ層５ａ、６ａと導電性樹脂層５ｂ、６ｂとが重畳されている。   Further, a curved chamfer is applied to the corner between the side surface and the main surface of the multilayer body 1, and the metal plating layers 5a and 6a and the conductive resin layers 5b and 6b are superimposed on the chamfered portion. ing.

さらに、導電性樹脂層５ｂ、６ｂが内方より外方に向かって漸次厚く形成されている。   Further, the conductive resin layers 5b and 6b are formed so as to be gradually thicker from the inside toward the outside.

そして、導電性樹脂層５ｂ、６ｂのヤング率が０．１〜１５ＧＰａである。   The Young's modulus of the conductive resin layers 5b and 6b is 0.1 to 15 GPa.

導電性樹脂層５ｂ、６ｂは、エポキシ樹脂、フェノール樹脂、アクリル樹脂などの熱硬化性樹脂に、Ｃｕ、Ｎｉ、Ａｇなどの導電性粉末が含有させて構成されている。   The conductive resin layers 5b and 6b are configured by adding a conductive powder such as Cu, Ni, or Ag to a thermosetting resin such as an epoxy resin, a phenol resin, or an acrylic resin.

金属メッキ層５ａ、６ａは、Ｎｉメッキ層の他、Ａｇ、Ａｕ、Ｐｄ、Ｐｔなどの酸化しにくい金属メッキ層が挙げられる。   Examples of the metal plating layers 5a and 6a include Ni plating layers and metal plating layers such as Ag, Au, Pd, and Pt that are difficult to oxidize.

また、金属メッキ層５ａ、６ａの厚みをｔ１、内部導体３、４（容量形成電極３ａ、４ａ及び／またはダミー電極３ｂ、４ｂ）の端部が積層素体１の端面に露出する間隔の最大値をｔ２とした場合、ｔ１／ｔ２≧１．５の範囲にあることが望ましい。このことにより、メッキ工程において、金属メッキ層５ａ、６ａが複数の内部導体３、４間に存在する誘電体層２を越えて、複数の内部導体（容量形成電極３ａ、４ａ及び／またはダミー電極３ｂ、４ｂ）の端部にまたがるように、十分に成長させることができる。 Further, the thickness of the metal plating layers 5 a and 6 a is t 1 , and the interval at which the end portions of the inner conductors 3 and 4 (capacitance forming electrodes 3 a and 4 a and / or dummy electrodes 3 b and 4 b) are exposed on the end surface of the multilayer body 1 is obtained. When the maximum value is t 2 , it is desirable that t 1 / t 2 ≧ 1.5. Thus, in the plating process, the metal plating layers 5a and 6a go beyond the dielectric layer 2 existing between the plurality of inner conductors 3 and 4, so that the plurality of inner conductors (capacitance forming electrodes 3a and 4a and / or dummy electrodes). It can be grown sufficiently to span the ends of 3b, 4b).

さらに、多連型コンデンサ１０のＴ方向の寸法をＴ、積層素体１の端面及び端面と主面との面取り部の曲率半径をＲとした場合、０．０２≦Ｒ／Ｔ≦０．２、好ましくは０．０５≦Ｒ／Ｔ≦０．１の範囲にあることが望ましい。すなわち、Ｒ／Ｔ＜０．０２の範囲にある場合、積層素体１の端面と主面との面取り部において、金属メッキ層及び導電性樹脂層（５ａ−５ｂ、６ａ−６ｂ）が十分接続するための面積を確保できない。一方、Ｒ／Ｔ＞０．２の範囲にある場合、異なる極の容量形成電極と金属メッキ層（３ａ−６ａ、３ｂ−５ａ）間の導通が発生しないようにするために、エンドマージンを大きくしたり、容量形成電極３ａ、４ａの積層数を小さくする必要があるため、多連型コンデンサ１０の大容量化が困難になる。   Further, when the dimension in the T direction of the multiple capacitor 10 is T and the radius of curvature of the chamfered portion between the end surface and the end surface of the multilayer body 1 is R, 0.02 ≦ R / T ≦ 0.2 Preferably, it is desirable that the range is 0.05 ≦ R / T ≦ 0.1. That is, when R / T <0.02, the metal plating layer and the conductive resin layer (5a-5b, 6a-6b) are sufficiently connected at the chamfered portion between the end surface and the main surface of the multilayer body 1. The area for doing this cannot be secured. On the other hand, when R / T> 0.2, the end margin is increased in order to prevent conduction between the capacitance forming electrodes of different poles and the metal plating layers (3a-6a, 3b-5a). In addition, since it is necessary to reduce the number of stacked capacitance forming electrodes 3a and 4a, it is difficult to increase the capacity of the multiple capacitor 10.

以下、本発明の多連型コンデンサ１０の製造方法について説明する。なお、各符号は焼成の前後で区別しないものとする。   Hereinafter, a method for manufacturing the multiple capacitor 10 of the present invention will be described. In addition, each code | symbol shall not distinguish before and after baking.

まず、誘電体層となるセラミックグリーンシート２上に、導電ペーストをスクリーン印刷で形成し、容量形成電極３ａ、４ａ及びダミー導体３ｂ、４ｂを形成する。   First, a conductive paste is formed by screen printing on the ceramic green sheet 2 serving as a dielectric layer to form the capacitance forming electrodes 3a and 4a and the dummy conductors 3b and 4b.

次に、このようなセラミックグリーンシート２を、容量形成電極３ａ、４ａが互いに対向し、且つ容量形成電極３ａ、４ａが互いに異なる端面に延出するとともに、ダミー導体３ｂ、４ｂが互いに異なる端面に延出するように所定の積層枚数重ねた後、切断して各コンデンサユニットＮを含む未焼成状態の積層素体１とし、所定の雰囲気、温度、時間を加えて焼成する。これにより、積層素体１の一対の端面には、各コンデンサユニットＮ毎に容量形成電極３ａ、４ａ及びダミー導体３ｂ、４ｂが露出している。   Next, such a ceramic green sheet 2 is formed so that the capacitance forming electrodes 3a and 4a face each other, the capacitance forming electrodes 3a and 4a extend to different end faces, and the dummy conductors 3b and 4b are different end faces. After a predetermined number of laminated layers are stacked so as to extend, the laminated body 1 is cut and formed into an unfired laminated body 1 including each capacitor unit N, and fired by adding a predetermined atmosphere, temperature, and time. As a result, the capacitance forming electrodes 3 a and 4 a and the dummy conductors 3 b and 4 b are exposed for each capacitor unit N on the pair of end faces of the multilayer body 1.

次に、上記容量形成電極３ａ、４ａ及びダミー導体３ｂ、４ｂの延出領域を被覆するように、通常の無電解メッキ法を用いて金属メッキ層５ａ、６ａを形成する。   Next, metal plating layers 5a and 6a are formed using a normal electroless plating method so as to cover the extension regions of the capacitance forming electrodes 3a and 4a and the dummy conductors 3b and 4b.

まず、容量形成電極３ａ、４ａ及びダミー導体３ｂ、４ｂの延出している部分にメッキ被膜が形成される。そして、メッキ処理の時間の経過とともにメッキ被膜が成長し、隣接しあう容量形成電極３ａ、４ａ及びダミー導体３ｂ、４ｂ同士間のメッキ被膜が互いに架橋して結果として、延出領域の複数の容量形成電極３ａ−３ａ間、ダミー導体３ｂ−３ｂ間の電気的な接続、及び別の延出領域の複数の容量形成電極４ａ−４ａ間、ダミー導体４ｂ−４ｂ間の電気的な接続が達成され、延出領域全面にわたって金属メッキ層５ａ、６ａが形成される。なおこのとき、例えば金属メッキ層５ａ、６ａがＮｉメッキ層、Ｓｎメッキ層の２層構造である場合、通常の電気メッキ法あるいは無電解メッキ法を用いて、まずＮｉメッキ層を形成した後、Ｓｎメッキ層を形成する。   First, a plating film is formed on the extended portions of the capacitance forming electrodes 3a and 4a and the dummy conductors 3b and 4b. Then, the plating film grows with the elapse of time of the plating process, and the plating film between the adjacent capacitance forming electrodes 3a, 4a and the dummy conductors 3b, 4b crosses each other, resulting in a plurality of capacitances in the extension region. The electrical connection between the formation electrodes 3a-3a and between the dummy conductors 3b-3b, and the electrical connection between the plurality of capacitance formation electrodes 4a-4a in the different extension regions and between the dummy conductors 4b-4b are achieved. The metal plating layers 5a and 6a are formed over the entire extended region. At this time, for example, when the metal plating layers 5a and 6a have a two-layer structure of a Ni plating layer and a Sn plating layer, first, after forming a Ni plating layer using a normal electroplating method or electroless plating method, An Sn plating layer is formed.

その後、金属メッキ層５ａ、６ａに接続するとともに、積層素体１の主面から端面と主面との面取り部にまたがるように、夫々導電性のエポキシ系熱硬化性導電性樹脂層５ｂ、６ｂを塗布、乾燥、硬化の各工程を順次経て形成する。塗布方法としては、スクリーン印刷法、ディスペンサからの滴下法などが用いられる。このとき、実装面側（あるいは反対側）の一対の導電性樹脂層５ｂ、６ｂを形成した後、実装面と反対側（あるいは実装面側）の一対の導電性樹脂層５ｂ、６ｂを形成する方法により、平坦な面に導電性樹脂層５ｂ、６ｂを形成することになるため、精度良く形成することができる。   After that, the conductive epoxy thermosetting conductive resin layers 5b and 6b are connected to the metal plating layers 5a and 6a and extend from the main surface of the multilayer body 1 to the chamfered portion between the end surface and the main surface. Are formed through the respective steps of coating, drying and curing. As a coating method, a screen printing method, a dropping method from a dispenser, or the like is used. At this time, after forming the pair of conductive resin layers 5b and 6b on the mounting surface side (or opposite side), the pair of conductive resin layers 5b and 6b on the opposite side (or mounting surface side) is formed. Since the conductive resin layers 5b and 6b are formed on a flat surface by the method, the conductive resin layers 5b and 6b can be formed with high accuracy.

このようにして、金属メッキ層５ａ、６ａ及び導電性樹脂層５ｂ、６ｂとからなる端子電極５、６が形成される。必要に応じて、導電性樹脂層５ｂ、６ｂを被覆するように、Ｎｉメッキ層、Ｓｎメッキ層などの表面メッキ層（図示せず）を形成するようにしても良い。   Thus, the terminal electrodes 5 and 6 which consist of the metal plating layers 5a and 6a and the conductive resin layers 5b and 6b are formed. If necessary, a surface plating layer (not shown) such as a Ni plating layer or a Sn plating layer may be formed so as to cover the conductive resin layers 5b and 6b.

このようにして、本発明の多連型コンデンサ１０が得られる。   In this way, the multiple capacitor 10 of the present invention is obtained.

なお、本発明は上記の実施の形態例に限定されるものではなく、本発明の要旨を逸脱しない範囲内での種々の変更や改良などは何ら差し支えない。   It should be noted that the present invention is not limited to the above-described embodiment, and various modifications and improvements can be made without departing from the scope of the present invention.

例えば、上記実施の形態ではセラミック電子部品として多連型コンデンサ１０を用いて説明したが、本発明は、端子電極５、６が積層素体１の端面からそれに隣接する３面または４面にまたがるように形成された通常の積層セラミックコンデンサにも適用できる。また、端子電極５、６が、積層素体１の端面からそれに隣接する１面にのみまたがるように形成されたセラミック電子部品にも適用できる。さらに、本発明は、他の電子部品や、半導体部品などの他のセラミック電子部品にも適用できる。   For example, although the above embodiment has been described using the multiple capacitor 10 as the ceramic electronic component, in the present invention, the terminal electrodes 5 and 6 extend from the end face of the multilayer body 1 to three or four faces adjacent thereto. The present invention can also be applied to an ordinary multilayer ceramic capacitor formed as described above. Further, the present invention can also be applied to a ceramic electronic component in which the terminal electrodes 5 and 6 are formed so as to extend from the end face of the multilayer body 1 to only one face adjacent thereto. Furthermore, the present invention can be applied to other electronic components and other ceramic electronic components such as semiconductor components.

図３は、本発明の多連型コンデンサの他の実施の形態を示す断面図である。同図によれば、積層素体１の積層方向の上下側且つ端面付近に形成されるダミー電極３ｂ、４ｂの他、容量形成電極３ａ、４ａと略同一平面に配置されるとともに、金属メッキ層５ａ、６ａに夫々接続されるダミー電極３ｂ、４ｂが形成されている。このことにより、隣接する内部導体（３ａ−３ｃ、４ａ−４ｃ）の端部が積層素体１の端面に露出する間隔をさらに小さくでき、これらの内部導体（３ａ−３ｃ、４ａ−４ｃ）にまたがるように金属メッキ層５ａ、６ａを形成しやすくなる。   FIG. 3 is a cross-sectional view showing another embodiment of the multiple capacitor of the present invention. According to the figure, in addition to the dummy electrodes 3b and 4b formed on the upper and lower sides in the laminating direction of the multilayer body 1 and in the vicinity of the end surface, the capacitor element electrodes 3a and 4a are disposed on substantially the same plane, and the metal plating layer Dummy electrodes 3b and 4b connected to 5a and 6a, respectively, are formed. As a result, the interval at which the end portions of the adjacent inner conductors (3a-3c, 4a-4c) are exposed on the end face of the multilayer body 1 can be further reduced, and these inner conductors (3a-3c, 4a-4c) As a result, the metal plating layers 5a and 6a can be easily formed.

本発明の多連型コンデンサを示す断面図である。It is sectional drawing which shows the multiple capacitor | condenser of this invention. 本発明の多連型コンデンサを配線基板上に表面実装した状態を示す断面図である。It is sectional drawing which shows the state which surface mounted the multiple capacitor | condenser of this invention on the wiring board. 本発明の多連型コンデンサの他の実施の形態を示す断面図である。It is sectional drawing which shows other embodiment of the multiple capacitor | condenser of this invention. 従来の多連型コンデンサを示す図であり、（ａ）は外観斜視図、（ｂ）はＸ−Ｘ線断面図である。It is a figure which shows the conventional multiple capacitor | condenser, (a) is an external appearance perspective view, (b) is XX sectional drawing. 従来の他の多連型コンデンサを示す図であり、（ａ）は外観斜視図、（ｂ）はＸ−Ｘ線断面図である。It is a figure which shows the other conventional multiple capacitor | condenser, (a) is an external appearance perspective view, (b) is XX sectional drawing.

符号の説明Explanation of symbols

１０・・・・多連型コンデンサ（セラミック電子部品）
１・・・・・積層素体
２・・・・・誘電体層
３、４・・・内部導体
３ａ、４ａ・容量形成電極
３ｂ、４ｂ・ダミー導体
５、６・・・端子電極
５ａ、６ａ・金属メッキ層
５ｂ、６ｂ・導電性樹脂層
１１・・・・配線基板
１２・・・・配線パターン
１３・・・・半田 10 ... Multiple capacitors (ceramic electronic parts)
DESCRIPTION OF SYMBOLS 1 ... Laminated body 2 ... Dielectric layer 3, 4 ... Internal conductor 3a, 4a * Capacity forming electrode 3b, 4b * Dummy conductor 5, 6 ... Terminal electrode 5a, 6a・ Metal plating layers 5b and 6b ・ Conductive resin layer 11... Wiring substrate 12.

Claims (4)

複数のセラミック層を間に内部導体を介して積層することにより直方体状の積層素体を形成するとともに、該積層素体の側面より主面にかけて前記内部導体に電気的に接続される端子電極を形成してなるセラミック電子部品において、
前記端子電極が、前記積層素体の側面に被着される金属メッキ層と、前記積層素体の主面より前記金属メッキ層の端部上にかけて被着される導電性樹脂層とで形成されていることを特徴とするセラミック電子部品。 A rectangular parallelepiped multilayer body is formed by laminating a plurality of ceramic layers with an internal conductor interposed therebetween, and a terminal electrode electrically connected to the internal conductor from the side surface to the main surface of the multilayer body is provided. In the formed ceramic electronic component,
The terminal electrode is formed of a metal plating layer deposited on the side surface of the multilayer body and a conductive resin layer deposited from the main surface of the multilayer body to the end of the metal plating layer. Ceramic electronic parts characterized by 前記積層素体の側面と主面との間の角部に曲面状の面取りが施されており、該面取り部上で前記金属メッキ層と導電性樹脂層とが重畳されていることを特徴とする請求項１に記載のセラミック電子部品。 A curved chamfer is applied to a corner between a side surface and a main surface of the multilayer body, and the metal plating layer and a conductive resin layer are superimposed on the chamfer. The ceramic electronic component according to claim 1. 前記導電性樹脂層が内方より外方に向かって漸次厚く形成されていることを特徴とする請求項２に記載のセラミック電子部品。 The ceramic electronic component according to claim 2, wherein the conductive resin layer is formed so as to be gradually thicker from the inside toward the outside. 前記導電性樹脂層のヤング率が０．１〜１５ＧＰａであることを特徴とする請求項１乃至請求項３のいずれかに記載のセラミック電子部品。 The ceramic electronic component according to any one of claims 1 to 3, wherein the conductive resin layer has a Young's modulus of 0.1 to 15 GPa.
JP2004052152A 2004-02-26 2004-02-26 Ceramic electronic component Pending JP2005243944A (en)

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JP2008041786A (en) * 2006-08-03 2008-02-21 Murata Mfg Co Ltd Laminated ceramic electronic part
JP2008283170A (en) * 2007-03-28 2008-11-20 Murata Mfg Co Ltd Multilayer electronic component and method for manufacturing the same
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US8547682B2 (en) 2009-04-24 2013-10-01 Murata Manufacturing Co., Ltd. Multilayer ceramic electronic component including directly plated external electrodes
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Publication number Priority date Publication date Assignee Title
JP2008041786A (en) * 2006-08-03 2008-02-21 Murata Mfg Co Ltd Laminated ceramic electronic part
JP2008283170A (en) * 2007-03-28 2008-11-20 Murata Mfg Co Ltd Multilayer electronic component and method for manufacturing the same
US7933113B2 (en) 2007-03-28 2011-04-26 Murata Manufacturing Co., Ltd. Multilayer electronic component and method for manufacturing multilayer electronic component
US8631549B2 (en) 2007-03-28 2014-01-21 Murata Manufacturing Co., Ltd. Method for manufacturing multilayer electronic component
JP2009170875A (en) * 2007-12-21 2009-07-30 Murata Mfg Co Ltd Multilayer ceramic electronic component and method for manufacturing the same
US9418790B2 (en) 2007-12-21 2016-08-16 Murata Manufacturing Co., Ltd. Method for manufacturing a multilayer ceramic electronic component
US7764484B2 (en) 2008-03-04 2010-07-27 Murata Manufacturing Co., Ltd. Multilayer electronic component and method for manufacturing the same
US8547682B2 (en) 2009-04-24 2013-10-01 Murata Manufacturing Co., Ltd. Multilayer ceramic electronic component including directly plated external electrodes
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US9439301B2 (en) 2012-10-26 2016-09-06 Samsung Electro-Mechanics Co., Ltd. Multilayered chip electronic component and board for mounting the same
US9214278B2 (en) 2012-11-07 2015-12-15 Samsung Electro-Mechanics Co., Ltd. Multilayered ceramic electronic component and board for mounting the same
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