JP2005235809A - Ic chip - Google Patents

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JP2005235809A
JP2005235809A JP2004039342A JP2004039342A JP2005235809A JP 2005235809 A JP2005235809 A JP 2005235809A JP 2004039342 A JP2004039342 A JP 2004039342A JP 2004039342 A JP2004039342 A JP 2004039342A JP 2005235809 A JP2005235809 A JP 2005235809A
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wiring
layer wiring
lower layer
pad
line width
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Chizuru Ishita
ちづる 井下
Kazuo Aoki
青木　　一夫
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Renesas Technology Corp
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To further narrow the pitch of pads arranged in a staggered layout while solving EM and IRdrop problems to reduce a chip size, in a super multi-pin IC whose chip size is restricted by the number of IOs (the number of pads). <P>SOLUTION: The pads 2 and 3 connected by leader lines from an internal circuit 10 are arranged in a staggered layout. Each of the leader lines connected to the farther pads 3 in the staggered layout is composed of surface layer wiring 4a located in the same layer as the pads arranged in the staggered layout, and at least one lower layer wiring which is located below the surface layer wiring 4a and has a line width wider than that of the surface layer wiring. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

この発明は、パッドと内部回路とを接続する引出配線のエレクトロマイグレーション（以下ＥＭと称す）、およびこの引出配線による電圧降下、すなわちＩＲdropとを抑止するための引出配線構造を有するＩＣチップに関するものである。   The present invention relates to an IC chip having a lead-out wiring structure for suppressing electromigration (hereinafter referred to as EM) of a lead-out wiring that connects a pad and an internal circuit, and a voltage drop due to the lead-out wiring, that is, IRdrop. is there.

先端技術の進歩を取り込み、微細で高集積かつ大規模な高速ＩＣチップの製造ができるようになると、１つのＩＣチップで大容量の情報を取扱うことが可能となる。それに伴いＩＣチップ外部との情報交換量も増え、１チップにおけるＩＯ（Input-Output)ピン数も増加してくる。こうした超多ピンのＩＣチップで、ワイヤボンディングを用いてパッケージするような場合、非常に多くのパッドをより小さいピッチで配列するために、パッド配列を千鳥配列の構造にする手法が用いられる。このとき、パッドピッチが狭いと、チップ内部回路の入出力回路セルや電源セルからより遠くに位置するパッド、すなわち千鳥配列の外側のパッドとその入出力回路セルや電源セルとを接続する引出配線が細くなり、ＥＭやＩＲdropが問題となる可能性がある。このため、パッドに複数の配線を接続して電流密度の低下を実現する構造などが提案されている（たとえば特許文献１参照）。また、上記問題を解決するために、引出配線を複数層で構成する手法が知られている。   When the advancement of advanced technology is taken in and the manufacture of fine, high-integrated and large-scale high-speed IC chips becomes possible, it becomes possible to handle a large amount of information with one IC chip. Accordingly, the amount of information exchange with the outside of the IC chip increases, and the number of IO (Input-Output) pins in one chip also increases. When such an ultra-multi-pin IC chip is packaged using wire bonding, in order to arrange a very large number of pads at a smaller pitch, a technique of making the pad arrangement into a staggered arrangement is used. At this time, if the pad pitch is narrow, the lead wiring that connects the pad located farther from the input / output circuit cell and power cell of the internal circuit of the chip, that is, the pad outside the zigzag array and the input / output circuit cell and power cell. There is a possibility that EM and IRdrop become a problem. For this reason, a structure that realizes a reduction in current density by connecting a plurality of wirings to a pad has been proposed (see, for example, Patent Document 1). Further, in order to solve the above problem, a technique of configuring the lead wiring in a plurality of layers is known.

千鳥配列のパッド構造では、内部回路を囲むように並べられた入出力回路セルの周囲に、各パッドを、入出力回路セルに近い内側と、それより遠い側の外側とに、交互（千鳥）に二重に配置する。入出力回路セルや電源セルと、上記内側および外側のパッドとを接続する構成とすることにより、より多くのパッドが配置できるようなる。このような構造をとる場合、入出力回路セルや電源セルから千鳥配列の外側のパッドへ接続するためには、引出配線は内側のパッドの間を通る。   In the pad structure of the staggered arrangement, the pads are alternately arranged around the input / output circuit cells arranged so as to surround the internal circuit, on the inner side near the input / output circuit cell and on the outer side on the far side (staggered). Doubly arranged. More pads can be arranged by connecting the input / output circuit cells and power supply cells to the inner and outer pads. In the case of such a structure, in order to connect the input / output circuit cell and the power supply cell to the pad outside the staggered arrangement, the lead-out wiring passes between the pads inside.

上記のように千鳥配列の遠方パッドに対する引出配線は、上述のように多層配線とする場合が多い。すなわち、隣り合う近接パッドの間の狭い間隙を通る遠方パッドへの引出配線を、その間隙に合わせてその幅を狭くして、かつ一定の断面積を確保するためにその下層に、さらに同じ幅の引出配線を層が異なるようにして配置する。これら外側のパッドへの各層の引出配線は、スルーホールによって全層が結合される。
特開２００２−１６０６５号公報 As described above, the lead-out wiring for the distant pads in the staggered arrangement is often a multilayer wiring as described above. That is, the lead-out wiring to the far pad passing through the narrow gap between the adjacent neighboring pads is narrowed to the width in accordance with the gap, and the same width is further provided in the lower layer in order to ensure a constant cross-sectional area. The lead-out wirings are arranged in different layers. All layers of the lead-out wiring of each layer to these outer pads are coupled by through holes.
JP 2002-16065 A

微細で高集積かつ大規模な高速ＩＣにおいて、どれだけチップサイズを小さくできるかが商品価値およびコストの面において、非常に重要になってくる。内部回路の規模ではなくＩＯ数（パッド数）によりチップサイズが決定される超多ピンＩＣチップでは、千鳥配列パッド構造にするだけでは小サイズ化は不十分である。千鳥配列パッドのピッチをいかに狭くできるかが、チップサイズに大きく影響し、ひいてはコストに影響する。パッドピッチをいかに狭くできるかは、高集積になるほど、また超多ピンになればなるほどチップサイズを小さくするために重要になってくる。   In a high-speed IC that is fine, highly integrated, and large-scale, how much the chip size can be reduced is very important in terms of product value and cost. In an ultra-multi-pin IC chip whose chip size is determined not by the scale of the internal circuit but by the number of IOs (the number of pads), the size reduction is insufficient only by the staggered pad structure. How narrow the pitch of the staggered pad can greatly affect the chip size, which in turn affects the cost. How narrow the pad pitch is becomes more important in order to reduce the chip size the higher the integration and the greater the number of pins.

このパッドピッチをより一層狭めるために、千鳥配列パッドの外側に配置されるパッドに接続される引出配線の線幅をできるだけ狭くすることが必要となる。しかし、回路の規模が大きく微細で、高集積になればなるほど、流れる電流量も増加し、ＥＭやＩＲdropへの影響も非常に大きくなるため、上記引出配線の複数層のすべてを合わせて、これらに耐え得るだけの断面積を確保しなければならない。しかし、従来の引出配線の構造では、複数層の引出配線の線幅が同一であるため、引出配線の線幅は、千鳥配列パッドの近接パッド間を通る最上層の表層配線の線幅で決定されていた。とくに、配置できる層数が少ない場合には、ＥＭやＩＲdropを考慮すると線幅を十分狭くできず、パッドピッチを狭くできないという問題があった。   In order to further reduce the pad pitch, it is necessary to make the line width of the lead wiring connected to the pads arranged outside the staggered arrangement pad as narrow as possible. However, the larger the circuit scale, the higher the integration, the greater the amount of current that flows, and the greater the impact on EM and IRdrop. Must have enough cross-sectional area to withstand. However, in the conventional lead wire structure, the line width of the lead wires in the multiple layers is the same, so the line width of the lead wire is determined by the line width of the uppermost surface layer wire passing between the adjacent pads of the staggered pad. It had been. In particular, when the number of layers that can be arranged is small, there is a problem that the line width cannot be sufficiently narrowed and the pad pitch cannot be narrowed in consideration of EM and IRdrop.

本発明は、上記のような問題点を解決するためになされたもので、ＩＯ数（パッド数）によってチップサイズが決定されてしまうような超多ピンのＩＣチップにおいて、ＥＭやＩＲdropの問題を解決しながら、千鳥配列パッドのパッドピッチをさらに狭くし、チップサイズをより小さくすることができるＩＣチップを提供することを目的とする。   The present invention has been made to solve the above-described problems. In an ultra-multi-pin IC chip whose chip size is determined by the number of IOs (pads), the problem of EM and IRdrop is solved. An object of the present invention is to provide an IC chip capable of further reducing the pad pitch of the staggered pad and further reducing the chip size.

本発明のＩＣチップは、内部回路からの引出配線が接続されたパッドが千鳥配列されるＩＣチップである。このＩＣチップでは、その千鳥配列の前記内部回路から遠い方の遠方パッドに接続される引出配線が、千鳥配列のパッドが形成される層と同じ層に位置する表層配線と、それより下層に位置し、線幅が表層配線の線幅より広い少なくとも１つの下層配線とを有する。   The IC chip of the present invention is an IC chip in which pads to which lead wires from internal circuits are connected are staggered. In this IC chip, the lead-out wiring connected to the far pad farther from the internal circuit in the staggered arrangement is located on the same layer as the layer on which the staggered pad is formed, and on the lower layer. And at least one lower layer wiring having a line width wider than that of the surface layer wiring.

この構成により、ＥＭによる断線や電気抵抗の増大をきたすことなく、パッドピッチを狭くしてＩＣチップを小型化することができる。なお、多層に配置された外方パッドへの引出配線はすべて１つの外方パッドに、たとえばスルーホールなどを設け導電材料を充填することにより電気的に接続される。   With this configuration, it is possible to reduce the size of the IC chip by narrowing the pad pitch without causing disconnection by EM or increasing electrical resistance. Note that all the lead wires to the outer pads arranged in multiple layers are electrically connected by providing, for example, a through hole in one outer pad and filling with a conductive material.

本発明の別のＩＣチップは、内部回路からの引出配線が接続されたパッドが、千鳥配列されるＩＣチップである。このＩＣチップのその千鳥配列のパッドにおいて、その千鳥配列の内部回路から遠い側の遠方パッドに接続される引出配線が、千鳥配列のパッドが形成される層と同じ層に位置する配線層を含まず、千鳥配列のパッドが形成される層より下層に位置する、少なくとも１つの下層配線を有する。   Another IC chip of the present invention is an IC chip in which pads to which lead-out lines from internal circuits are connected are staggered. In this IC chip pad of the IC chip, the lead wiring connected to the far pad far from the internal circuit of the IC chip array includes a wiring layer located in the same layer as the layer on which the pad of the staggered array is formed. First, it has at least one lower layer wiring located below the layer where the staggered pad is formed.

上記のように、表層配線が設けられず、下層配線のみで引出配線を構成することによっても、ＥＭによる断線や電気抵抗の増大をきたすことなく、パッドピッチを狭くしてＩＣチップの小型化を実現することができる。   As described above, even if the lead wiring is formed only by the lower layer wiring without providing the surface layer wiring, the pad pitch is reduced and the IC chip can be reduced in size without causing disconnection by EM or increase in electric resistance. Can be realized.

次に本発明の実施の形態について図面を用いて説明する。   Next, embodiments of the present invention will be described with reference to the drawings.

（実施の形態１）
（１） 構成
本発明の実施の形態１の詳細な構成を図１〜３により説明する。図１は本実施の形態におけるＩＣチップ１５をアセンブリした半導体装置２０の概要を示す図であり、本実施の形態における特徴部分である遠方パッドへの引出配線等は省略されている。このＩＣチップ１５は、内部回路１０の辺に沿って、千鳥状に近接パッド２と遠方パッド３とに配置されたパッドを有している。このパッドは内部回路から引き出される、図示していない引出配線によって内部回路と電気的に接続されている。パッド２，３は外部リード１２と金線１１によりワイヤボンディングされている。 (Embodiment 1)
(1) Configuration A detailed configuration of the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a diagram showing an outline of a semiconductor device 20 in which an IC chip 15 is assembled in the present embodiment, and lead-out wiring and the like to a distant pad, which is a characteristic part in the present embodiment, are omitted. The IC chip 15 has pads arranged on the proximity pad 2 and the far pad 3 in a staggered manner along the side of the internal circuit 10. This pad is electrically connected to the internal circuit by a lead wiring (not shown) drawn from the internal circuit. The pads 2 and 3 are wire bonded by external leads 12 and gold wires 11.

図２は、千鳥配列パッドで構成された本発明に係るパッド周辺を示したものであり、図３は、図２のＩＩＩ−ＩＩＩ線に沿う断面図である。図２において、内部回路に含まれる入出力回路セル１の辺に沿って、千鳥状に近接パッド２と、遠方パッド３とが配列され、その入出力回路セル１と千鳥配列されたパッドとは引出配線により電気的に接続されている。とくに遠方パッドは、表層部では、隣り合う近接パッド２の間の間隙を通る細い引出配線４ａによって接続される。図２に示す引出配線４ａは、各パッドと同じ層に形成された表層配線であり、図３に示すように、その下により線幅の広い下層配線４ｂが設けられている。   FIG. 2 shows the periphery of the pad according to the present invention composed of staggered pads, and FIG. 3 is a cross-sectional view taken along the line III-III of FIG. In FIG. 2, adjacent pads 2 and distant pads 3 are arranged in a zigzag pattern along the side of the input / output circuit cell 1 included in the internal circuit, and the input / output circuit cells 1 and the staggered pads are They are electrically connected by lead wires. In particular, the distant pads are connected by a thin lead wire 4a passing through a gap between adjacent adjacent pads 2 in the surface layer portion. The lead-out wiring 4a shown in FIG. 2 is a surface layer wiring formed in the same layer as each pad, and as shown in FIG. 3, a lower layer wiring 4b having a wider line width is provided below it.

図３において、遠方パッドへの引出配線は、表層配線４ａと、それより下に位置し、層間絶縁膜７の中に設けられた複数の下層配線４ｂとで構成される。本実施の形態では、下層配線４ｂのすべてにおいてその線幅が同じであり、かつ表層配線４ａの線幅より広い点に特徴がある。ここで、各層の引出配線４ａ、４ｂは、各々スルーホールによって全層が結合され遠方パッドに電気的に接続されるが、図面が複雑になるため省略されている。   In FIG. 3, the lead-out wiring to the far pad is composed of the surface layer wiring 4 a and a plurality of lower layer wirings 4 b provided in the interlayer insulating film 7 located below the surface wiring 4 a. The present embodiment is characterized in that the line width of all the lower layer wirings 4b is the same and wider than that of the surface layer wiring 4a. Here, the lead-out wirings 4a and 4b of each layer are all connected by a through hole and are electrically connected to a distant pad, but are omitted because the drawing becomes complicated.

上記遠方パッドに接続される引出配線が従来と異なるところは、入出力回路セル１と遠方パッドとを接続する引出配線４における表層配線４ａと、下層配線４ｂとの線幅が異なり、下層配線４ｂの線幅が表層配線４ａの線幅より広いことにある。すなわち、従来の遠方パッドへの引出配線では、表層配線４ａと下層配線４ｂとが同じ線幅であるのに対し、本実施の形態では、下層配線４ｂは、表層配線４ａより同じ線幅で広くしたことを特徴とする。   The lead wire connected to the far pad differs from the conventional one in that the line width of the surface layer wire 4a and the lower layer wire 4b in the lead wire 4 connecting the input / output circuit cell 1 and the far pad is different. Is wider than the line width of the surface wiring 4a. That is, in the conventional lead-out wiring to the far pad, the surface layer wiring 4a and the lower layer wiring 4b have the same line width, whereas in the present embodiment, the lower layer wiring 4b is wider than the surface layer wiring 4a with the same line width. It is characterized by that.

従来の構成においては、表層配線と下層配線との線幅を同一としていたために、表層配線４ａの幅を狭くすることは、その下に位置するすべての下層配線の全線幅を狭くすることになる。このため、ＥＭによる断線や電圧降下によるＩＣの誤動作を防止するのに必要なトータルの線幅、ひいては断面積を確保することができなくなる。この結果、表層配線４ａの線幅の縮小には限界があった。しかし、本実施の形態においては、下層配線４ｂの線幅を揃えて、表層配線４ａの線幅より広くすることにより、必要なトータルの線幅、または断面積を確保することが可能である。   In the conventional configuration, since the line widths of the surface layer wiring and the lower layer wiring are made the same, reducing the width of the surface layer wiring 4a reduces the total line width of all the lower layer wirings located therebelow. Become. For this reason, it is impossible to ensure the total line width and thus the cross-sectional area necessary for preventing the malfunction of the IC due to the disconnection by EM or the voltage drop. As a result, there is a limit to the reduction in the line width of the surface layer wiring 4a. However, in the present embodiment, it is possible to ensure the necessary total line width or cross-sectional area by making the line width of the lower layer wiring 4b uniform and wider than the line width of the surface layer wiring 4a.

また、上記実施の形態の変形例であるが、図３において、表層配線４ａが設けられず、下層配線４ｂのみが配置される構成であってもよい。この場合、隣り合う２つの近接パッド２の間の隙間Ｌより広い線幅の下層配線４ｂを含んでもよい。本変形例のように表層配線４ａが配置されず、下層配線のみで引出配線を構成してもよい。上記変形例は、以後の実施の形態２〜実施の形態６において図示するＩＣチップの遠方パッドへの引出配線のすべてに共通して存在する。実施の形態２〜実施の形態６における変形例については、その作用効果はそれぞれの実施の形態における作用効果が変形例にもそのまま当て嵌まるので説明を省略する。しかし、以後のすべての実施の形態の図４〜図８において、変形例として表層配線４ａが設けられず、下層配線４ｂのみで遠方パッドへの引出配線が形成される変形例があるものとする。その場合、下層配線のなかに隣り合う２つの近接パッド２の間の隙間Ｌより広い線幅の下層配線４ｂが含まれている。   Moreover, although it is a modification of the said embodiment, in FIG. 3, the structure by which only the lower layer wiring 4b is arrange | positioned without providing the surface layer wiring 4a may be sufficient. In this case, the lower layer wiring 4b having a line width wider than the gap L between the two adjacent pads 2 may be included. As in the present modification, the surface wiring 4a may not be arranged, and the extraction wiring may be configured with only the lower wiring. The above-described modification is common to all the lead wires to the far pads of the IC chip illustrated in the following second to sixth embodiments. About the modification in Embodiment 2-Embodiment 6, since the effect in each embodiment applies also to a modification as it is, description is abbreviate | omitted. However, in FIG. 4 to FIG. 8 of all subsequent embodiments, there is a modification in which the surface wiring 4a is not provided as a modification, and a lead-out wiring to a far pad is formed only by the lower wiring 4b. . In that case, the lower layer wiring 4b having a line width wider than the gap L between two adjacent pads 2 adjacent to each other is included in the lower layer wiring.

（２） 作用効果
本実施の形態では、入出力回路セルや電源セルから、千鳥配列の遠方パッドに接続される引出配線の表層配線４ａの線幅をより狭くし、下層配線４ｂの線幅をすべて表層配線４ａの線幅より広くする。このため、ＥＭによる断線やＩＲdropによるＩＣの誤動作を防止できるだけのトータルの配線幅を確保しつつ、千鳥配列パッド構造のパッドピッチをより狭くすることが可能になる。この結果、チップサイズをより小さくでき、コストの削減をすることが可能となる。特に、本実施の形態の構成は、内部回路の規模ではなく、ＩＯ数（パッド数）によってチップサイズが決定される超多ピンのＩＣや、配線層数の少ない仕様のＩＣのパッドピッチを狭くする場合に有効である。 (2) Effects In the present embodiment, the line width of the surface layer wiring 4a of the lead wiring connected to the distant pad in the staggered arrangement is narrowed from the input / output circuit cell and the power cell, and the line width of the lower layer wiring 4b is reduced. All are made wider than the line width of the surface layer wiring 4a. Therefore, it is possible to further reduce the pad pitch of the staggered pad structure while ensuring a total wiring width that can prevent disconnection due to EM and IC malfunction due to IRdrop. As a result, the chip size can be further reduced, and the cost can be reduced. In particular, the configuration of this embodiment narrows the pad pitch of an ultra-multi-pin IC whose chip size is determined by the number of IOs (the number of pads) rather than the scale of the internal circuit or an IC with a specification with a small number of wiring layers. It is effective when

表層配線を設けないで下層配線のみで引出配線を構成する変形例の場合、ＥＭによる断線やＩＲdropによるＩＣの誤動作を防止できるだけのトータルの配線幅を確保しつつ、千鳥配列パッド構造のパッドピッチをより狭くすることが可能になる。この結果、チップサイズをより小さくでき、コストの削減をすることが可能となる。特に、本実施の形態の構成は、内部回路の規模ではなく、ＩＯ数（パッド数）によってチップサイズが決定される超多ピンのＩＣや、配線層数の少ない仕様のＩＣのパッドピッチを狭くする場合に有効である。   In the case of a modification in which the lead-out wiring is configured by only the lower-layer wiring without providing the surface layer wiring, the pad pitch of the staggered pad structure is secured while ensuring the total wiring width that can prevent the disconnection by EM and the malfunction of the IC by IRdrop. It becomes possible to make it narrower. As a result, the chip size can be further reduced, and the cost can be reduced. In particular, the configuration of this embodiment narrows the pad pitch of an ultra-multi-pin IC whose chip size is determined by the number of IOs (the number of pads) rather than the scale of the internal circuit or an IC with a specification with a small number of wiring layers. It is effective when

ここで、配線はどのような金属を用いても構わない。また、実装に際して、ＴＡＢ等のワイヤボンディング以外の方法で上記のＩＣチップをパッケージングしてもよい。   Here, any metal may be used for the wiring. In mounting, the IC chip may be packaged by a method other than wire bonding such as TAB.

（実施の形態２）
（１） 構成
図４は、本発明の実施の形態２における遠方パッドへの引出配線の断面図である。図４は、図２におけるＩＩＩ−ＩＩＩ線と同じ位置の断面図である。図４において、千鳥配列されたパッドの隣り合う近接パッド２の間の間隙に、入出力回路セル１と遠方パッド３とを接続する引出配線４の表層配線４ａが配置される。この引出配線４は、表層配線４ａと、複数層からなる下層配線４ｂとで構成されており、下層配線４ｂは、最下層を第１層として、上に順に積層番号をカウントする。（ｎ−１）、ｎ、（ｎ＋１）は、それぞれ最下層から数えて、（ｎ−１）番目、ｎ番目、（ｎ＋１）番目の引出配線の層を示している。 (Embodiment 2)
(1) Configuration FIG. 4 is a cross-sectional view of the lead-out wiring to the far pad in Embodiment 2 of the present invention. 4 is a cross-sectional view taken along the line III-III in FIG. In FIG. 4, the surface layer wiring 4 a of the lead wiring 4 that connects the input / output circuit cell 1 and the far pad 3 is arranged in the gap between adjacent pads 2 adjacent to the pads arranged in a staggered pattern. The lead-out wiring 4 is composed of a surface layer wiring 4a and a lower layer wiring 4b composed of a plurality of layers. The lower layer wiring 4b counts the stacking numbers in order from the bottom layer to the first layer. (N−1), n, and (n + 1) respectively indicate the (n−1) th, nth, and (n + 1) th lead wiring layers, counted from the lowest layer.

上記実施の形態１では、下層配線４ｂの太さを表層配線４ａに対し太くすることで、表層配線４ａの線幅を狭くして、パッドピッチを狭くしても、ＥＭによる断線やＩＲdropによるＩＣの誤動作を防止できるだけのトータルの線幅を確保した。しかし、本実施の形態における引出配線の構造は、下層配線の線幅の広げ方によってはパッドへのワイヤボンディング時の応力等の影響が懸念される場合に対処可能である点に特徴がある。   In the first embodiment, the thickness of the lower layer wiring 4b is made thicker than that of the surface layer wiring 4a, so that even if the line width of the surface layer wiring 4a is reduced and the pad pitch is reduced, EM disconnection or IRdrop IC The total line width was secured to prevent malfunctions. However, the structure of the lead-out wiring in the present embodiment is characterized in that it can cope with the case where the influence of stress or the like at the time of wire bonding to the pad is concerned depending on how the line width of the lower layer wiring is increased.

図４に示す本実施の形態における引出配線の構造では、入出力回路セルや電源セルと、千鳥配列の遠方パッドとを接続する引出配線４の下層配線４ｂにおいて、ｎ番目から下の層の配線の線幅を、表層配線４ａの線幅より広くしている。つまり、（ｎ＋１）番目以上（（ｎ＋１）番目の層を含む）の層の引出配線の線幅は、表層配線４ａの線幅と同じにし、ｎ番目以下（ｎ番目の層を含む）の引出配線の線幅を表層配線４ａの線幅より広くしたことに特徴がある。   In the structure of the lead wiring in the present embodiment shown in FIG. 4, in the lower layer wiring 4b of the lead wiring 4 that connects the input / output circuit cells and the power supply cells to the distant pads in the staggered arrangement, the wiring from the nth to the lower layer Is made wider than the line width of the surface layer wiring 4a. That is, the line width of the lead wirings of the (n + 1) th and higher layers (including the (n + 1) th layer) is the same as the line width of the surface wiring 4a, and the wirings of the nth and lower (including the nth layer) are drawn. It is characterized in that the line width of the wiring is made wider than that of the surface layer wiring 4a.

表層配線のエッジとその隣の近接パッド２のエッジとの距離ｇとし、（ｎ＋１）番目の配線層のエッジと隣の近接パッド２のエッジとの距離Ｓn+1とし、ｄnは、パッドの底面と、ｎ番目の配線層の上面との間の距離を示す。各層の引出配線４ａ、４ｂは、各々スルーホールによって全層が結合され遠方パッドに電気的に接続されるが、図面が複雑になるため省略されている。   The distance g between the edge of the surface layer wiring and the edge of the adjacent pad 2 adjacent thereto is defined as the distance Sn + 1 between the edge of the (n + 1) th wiring layer and the edge of the adjacent pad 2 adjacent thereto, and dn is the bottom surface of the pad. And the distance between the upper surface of the nth wiring layer. The lead wires 4a and 4b of each layer are all connected by a through hole and are electrically connected to a distant pad, but are omitted because the drawing becomes complicated.

上記の引出配線は、近接パッドにワイヤボンディングで金線を接続する際にワイヤボンディングの応力の影響を受ける。しかし、図２に示す構成のように、近接パッド２からワイヤボンディングの応力の影響を受けやすい（ｎ＋１）番目以上の層の引出配線を、表層配線の線幅と同じにし、かつ線幅を広くする配線層をｎ番目以下の層とするため、近接パッドからの距離Ｓn+1およびｄnが増すためワイヤボンディングにおける応力の影響を避けることができる。表層配線４ａと近接パッド２との距離ｇは、上記距離Ｓn+1およびｄnに比較して小さいが、表層配線方向のワイヤボンディングによる応力は小さいため問題ない。   The above lead wiring is affected by the stress of wire bonding when a gold wire is connected to the adjacent pad by wire bonding. However, as in the configuration shown in FIG. 2, the (n + 1) th or higher layer lead wiring that is easily affected by the stress of wire bonding from the adjacent pad 2 is made the same as the line width of the surface layer wiring and the line width is increased. Since the wiring layer to be formed is the nth layer or less, the distances Sn + 1 and dn from the adjacent pads are increased, so that the influence of stress in wire bonding can be avoided. Although the distance g between the surface layer wiring 4a and the adjacent pad 2 is smaller than the distances Sn + 1 and dn, there is no problem because the stress due to wire bonding in the surface layer wiring direction is small.

（２） 作用効果
本実施の形態では、入出力回路セルや電源セルから千鳥配列の遠方パッドに接続される引出配線４のうち、下層配線４ｂにおいて、（ｎ＋１）番目以上の層の配線を表層配線４ａの線幅と同様にし、ｎ番目以下の層における引出配線の線幅を表層配線４ａの線幅より広くする。このため、入出力回路セルや電源セルから千鳥配列の遠方パッドに接続される引出配線において、表層配線４ａとその表層配線４ａに隣り合う近接パッド２との距離ｇをできるだけ狭めた場合でも、ＥＭによる断線やＩＲdropによるＩＣの誤動作を防止できるだけのトータルの線幅、または断面積を確保できる。このため、千鳥配列パッド構造のパッドピッチをより狭くすることが可能になり、チップサイズをより小さくでき、コストの削減が可能となる。 (2) Operational Effect In the present embodiment, (n + 1) th and higher layers of the lead wirings 4b connected to the distant pads in the staggered arrangement from the input / output circuit cells and the power supply cells are connected to the surface layer. Similarly to the line width of the wiring 4a, the line width of the lead-out wiring in the nth and lower layers is made wider than the line width of the surface layer wiring 4a. For this reason, even when the distance g between the surface layer wiring 4a and the adjacent pad 2 adjacent to the surface layer wiring 4a is reduced as much as possible in the lead wiring connected from the input / output circuit cell or the power cell to the distant pad in the staggered arrangement, the EM It is possible to secure a total line width or cross-sectional area sufficient to prevent disconnection due to IR and IC malfunction due to IRdrop. For this reason, the pad pitch of the staggered pad structure can be made narrower, the chip size can be made smaller, and the cost can be reduced.

また、上記の下層配線４ｂのエッジと両側に位置する近接パッド２のエッジとが近接することを避け、すなわちＳn+1などを大きくとり、線幅を広くする下層配線においても、近接パッド２の底面からのｄnを十分大きく確保した。このため、近接パッドへのワイヤボンディングの際、近接パッドにかかる圧力によって発生する下方向への応力の影響を軽減でき、製造時のトラブルを防ぐことができる。   Further, avoiding the proximity of the edge of the lower layer wiring 4b and the edge of the adjacent pad 2 located on both sides, that is, in the lower layer wiring in which Sn + 1 is increased and the line width is widened, Dn from the bottom surface was secured sufficiently large. For this reason, the influence of the downward stress generated by the pressure applied to the proximity pad at the time of wire bonding to the proximity pad can be reduced, and trouble during manufacturing can be prevented.

（実施の形態３）
（１） 構成
図５は本発明の実施の形態３における引出配線の構成を示す図である。図５において、２は千鳥配列の近接パッドを示し、４は入出力回路セルや電源セルと遠方パッドを接続する引出配線を示す。遠方パッドへの引出配線４は、表層配線４ａと、下層配線４ｂとで構成されている。下層配線（ｎ−１）、ｎ、（ｎ＋１）、（ｎ＋２）は、それぞれ最下層から数えて、（ｎ−１）、ｎ、（ｎ＋１）、（ｎ＋２）番目の下層配線の層を示している。 (Embodiment 3)
(1) Configuration FIG. 5 is a diagram showing a configuration of the lead wiring in the third embodiment of the present invention. In FIG. 5, reference numeral 2 denotes a staggered proximity pad, and 4 denotes an extraction wiring for connecting an input / output circuit cell or power cell to a remote pad. The lead-out wiring 4 to the distant pad is composed of a surface layer wiring 4a and a lower layer wiring 4b. Lower layer wirings (n−1), n, (n + 1), and (n + 2) indicate the layers of the (n−1), n, (n + 1), and (n + 2) th lower layer wirings counted from the lowest layer, respectively. Yes.

図５において、入出力回路セルや電源セルと千鳥配列の遠方パッドとを接続する引出配線４のうち、複数の下層配線４ｂにおいて、（ｎ＋１）番目以上（（ｎ＋１）番目を含む）の層における引出配線の線幅を、表層配線４ａの線幅よりも所定の大きさだけ広くし、さらにｎ番目以下（ｎ番目を含む）の層における引出配線の線幅を、上記（ｎ＋１）番目以上の層における配線の線幅より広くしたものである。要約すると、下層配線４ｂを上部と下部とに分けて、上部の下層配線の線幅を表層配線４ａよりも所定値分だけ広くし、下部の下層配線の線幅をさらに上記上部の下層配線の線幅よりも広くした構成を有する。   In FIG. 5, among the lead-out wirings 4 that connect the input / output circuit cells and the power supply cells and the distant pads in the staggered arrangement, in the plurality of lower layer wirings 4 b, in the (n + 1) th and higher (including (n + 1) th) layers. The line width of the lead-out wiring is made wider than the line width of the surface layer wiring 4a by a predetermined size, and the line width of the lead-out wiring in the n-th layer (including the n-th) layer is set to the (n + 1) -th or more. This is wider than the line width of the wiring in the layer. In summary, the lower layer wiring 4b is divided into an upper part and a lower part, the line width of the upper lower layer wiring is made wider than the surface layer wiring 4a by a predetermined value, and the line width of the lower lower layer wiring is further increased. The configuration is wider than the line width.

ｇは、表層配線４ａのエッジと隣り合う近接パッド２のエッジとの距離であり、Ｓn+2は、上記上部の下層配線のうちワイヤボンディングの応力の影響を受けやすいと予測される（たとえば後で説明するワイヤボンディングの影響が及ぶ範囲Ｆに最も近いエッジを有する下層配線）下層線層のエッジ、図５の構造では（ｎ＋２）番目の下層配線のエッジ、と近接パッド２のエッジとの距離である。またｄnは、近接パッドの底面とｎ番目の下層配線の重なり部分までの距離を示す。各層の引出配線は、々スルーホールによって全層が結合されているが、図面を明確に示すために記載を省略している。   g is the distance between the edge of the surface wiring 4a and the edge of the adjacent pad 2 and Sn + 2 is predicted to be susceptible to the stress of wire bonding in the upper lower wiring (for example, The lower layer wiring having an edge closest to the range F affected by the wire bonding described in FIG. 5) The distance between the edge of the lower layer line layer, the edge of the (n + 2) th lower layer wiring in the structure of FIG. It is. Dn represents the distance from the bottom surface of the proximity pad to the overlapping portion of the nth lower layer wiring. All layers of the lead-out wiring of each layer are coupled by through holes, but the description is omitted for the sake of clarity.

ここで、（ｎ＋１）番目以上の引出配線の線幅は、（ｎ＋１）番目以上の層における引出配線のエッジと、近接パッド２のエッジとが近接することによって近接パッドへのワイヤボンディングによるダメージや応力の影響を受けない範囲内で広くする。また、（ｎ＋１）番目以上の引出配線の線幅よりさらに広くする下部の下層配線を、ｎ番目以下の層にすることで、ｎ番目以下の層における配線が、両側のパッド領域に重なるほど広く配線幅になった場合においても、近接パッド２の底面と下層配線との距離ｄn+1は、パッドへワイヤをボンディングする際のダメージや応力の影響を受けるおそれの少ない距離だけ離れる。   Here, the line width of the (n + 1) th or more lead-out wiring is such that the edge of the lead-out wiring in the (n + 1) th or more layer and the edge of the proximity pad 2 are close to each other due to damage due to wire bonding to the proximity pad. Widen within the range not affected by stress. Further, by making the lower lower layer wiring wider than the line width of the (n + 1) th or more extraction wirings to be the nth or lower layer, the wiring in the nth or lower layer becomes wider as it overlaps the pad regions on both sides. Even when the wiring width is reached, the distance dn + 1 between the bottom surface of the adjacent pad 2 and the lower layer wiring is separated by a distance that is less likely to be affected by damage or stress when bonding the wire to the pad.

（２） 作用効果
本実施の形態では、入出力回路セルや電源セルから千鳥配列の遠方パッドに接続される引出配線４のうち、下層配線４ｂにおいて、（ｎ＋１）番目以上の引出配線の線幅を表層配線４ａの線幅より広くし、ｎ番目以下の層の引出配線幅を（ｎ＋１）番目以上の引出配線幅よりさらに広くする。この構成により、表層配線４ａの線幅を狭くし、表層配線４ａに隣接する近接パッド２との距離ｇをできるだけ狭めても、ＥＭによる断線やＩＲdropによるＩＣの誤動作を防止できるだけのトータルの線幅を確保することができる。これにより、千鳥配列パッド構造のパッドピッチをより狭くすることが可能になり、チップサイズをより小さくすることにより、コストの削減が可能となる。 (2) Operational effect In the present embodiment, the line width of the (n + 1) th or more extraction wirings in the lower layer wiring 4b among the extraction wirings 4 connected from the input / output circuit cells and the power supply cells to the distant pads in the staggered arrangement. Is made wider than the line width of the surface layer wiring 4a, and the leading wiring width of the nth and lower layers is made wider than the (n + 1) th leading wiring width. With this configuration, even if the line width of the surface layer wiring 4a is reduced and the distance g between the adjacent pads 2 adjacent to the surface layer wiring 4a is reduced as much as possible, the total line width is sufficient to prevent disconnection due to EM and IC malfunction due to IRdrop. Can be secured. As a result, the pad pitch of the staggered pad structure can be made narrower, and the cost can be reduced by reducing the chip size.

また、（ｎ＋１）番目以上の層の引出配線幅は、（ｎ＋１）番目以上の層の引出配線のエッジと近接パッド２のエッジとが近接しても、近接パッドへワイヤをボンディングする際のダメージや応力の影響を受けない距離までを限度として広くしてある。このため、ｎ番目以下の層の引出配線は、その線幅を広くした領域が近接パッドの領域に重なるような配線幅になった場合においても、近接パッド底面と上記引出配線までの距離ｄnがパッドへワイヤをボンディングする際のダメージや応力の影響を受けるおそれの少ない距離だけ離れているので、製造時のトラブルを防ぐことができる。   The lead wiring width of the (n + 1) th and higher layers is the damage caused when bonding the wire to the neighboring pad even if the edge of the leading wiring of the (n + 1) th and higher layers and the edge of the neighboring pad 2 are close to each other. It is widened up to a distance that is not affected by stress. For this reason, the lead wiring of the nth and lower layers has a distance dn between the bottom surface of the proximity pad and the lead wiring even when the wiring width is such that the widened region overlaps the proximity pad region. Since they are separated by a distance that is less likely to be affected by damage or stress when bonding a wire to a pad, troubles during manufacturing can be prevented.

（実施の形態４）
（１） 構成
図６は、本発明の実施の形態４における引出配線の構造を示す断面図である。図６において、２は千鳥配列の近接パッドを示し、４は入出力回路セルや電源セルと千鳥配列の遠方パッドとを接続する引出配線を示す。引出配線４は、表層配線４ａと、その下に位置する複数の下層配線４ｂで構成されている。複数の下層配線４ｂにおいて、（ｎ−１）、ｎ、（ｎ＋１）は、それぞれ最下層から数えて、（ｎ−１）、ｎ、（ｎ＋１）番目の配線層を示している。 (Embodiment 4)
(1) Configuration FIG. 6 is a cross-sectional view showing the structure of the lead wiring in the fourth embodiment of the present invention. In FIG. 6, reference numeral 2 denotes a staggered proximity pad, and 4 denotes an extraction wiring for connecting an input / output circuit cell or power cell to a staggered remote pad. The lead-out wiring 4 is composed of a surface layer wiring 4a and a plurality of lower layer wirings 4b located therebelow. In the plurality of lower layer wirings 4b, (n−1), n, and (n + 1) indicate the (n−1), n, and (n + 1) th wiring layers, counting from the lowest layer, respectively.

図６に示す引出配線では、入出力回路セルや電源セルと遠方パッドとを接続する引出配線４の下層配線４ｂにおいて、その線幅を表層配線４ａの線幅より広くして下の位置になるにつれて、徐々に太くしていく。すなわち、（ｎ＋１）番目よりｎ番目、ｎ番目より（ｎ−１）番目の層というように、下に位置する層にしたがって線幅を広くしていくことを特徴とする。   In the lead-out wiring shown in FIG. 6, in the lower layer wiring 4b of the lead-out wiring 4 that connects the input / output circuit cell or the power supply cell and the remote pad, the line width is made wider than the line width of the surface layer wiring 4a and is located at the lower position. As it gets thicker, it gradually gets thicker. That is, it is characterized in that the line width is increased according to the layer located below, such as nth from the (n + 1) th and (n-1) th from the nth.

ｇは、表層配線４ａのエッジと隣接する近接パッド２のエッジとの距離、Ｓn+2は、上記上部の下層配線のうちワイヤボンディングの応力の影響を受けやすいと予測される（すぐ後に説明するワイヤボンディングの影響が及ぶ範囲Ｆに近い）下層配線のエッジ、図５の構造と同様に（ｎ＋２）番目の配線層のエッジ、と近接パッド２のエッジとの距離である。ｄnは、パッドの底面とｎ番目の配線層の重なり部分までの距離を示す。またＦは、ワイヤボンディングにおいてパッドにかかる圧力、ダメージ等の影響が伝播される範囲を示す。   g is the distance between the edge of the surface layer wiring 4a and the edge of the adjacent pad 2 and Sn + 2 is predicted to be susceptible to the stress of wire bonding among the upper lower layer wirings (described immediately below). The distance between the edge of the lower layer wiring (close to the range F affected by the wire bonding), the edge of the (n + 2) th wiring layer, and the edge of the adjacent pad 2 as in the structure of FIG. dn represents the distance to the overlapping portion of the bottom surface of the pad and the nth wiring layer. F denotes a range in which the influence of pressure, damage, etc. applied to the pad is propagated in wire bonding.

ここで、線幅を徐々に広くしていく際、近接パッドへワイヤボンディングする際のダメージや応力の影響を受けないよう、近接パッドのエッジと下層配線のエッジとの距離Ｓn+2や、下層配線と近接パッドの底面までの距離ｄnを十分大きく確保する。   Here, when the line width is gradually increased, the distance Sn + 2 between the edge of the adjacent pad and the edge of the lower layer wiring, and the lower layer so as not to be affected by damage and stress when wire bonding to the adjacent pad is performed. A sufficiently large distance dn between the wiring and the bottom surface of the proximity pad is secured.

また、通常、パッドへのワイヤリングは、近接パッド領域全体にワイヤボンディングされるのではなく、近接パッドの中心を標的にしてボンディングされる。したがって、図６に示す範囲Ｆのように、近接パッドへワイヤをボンディングする際のダメージや応力の影響する範囲は、近接パッドの中心から一定距離の範囲内と考えられる。近接パッド２の中心から下層配線までの距離が常に範囲Ｆに入らないように、下層配線の線幅を徐々に広くしている。   Also, normally, the wiring to the pad is not performed by wire bonding to the entire adjacent pad region, but is performed by targeting the center of the adjacent pad. Therefore, as in the range F shown in FIG. 6, the range affected by the damage and stress when the wire is bonded to the proximity pad is considered to be within a certain distance from the center of the proximity pad. The line width of the lower layer wiring is gradually increased so that the distance from the center of the proximity pad 2 to the lower layer wiring does not always fall within the range F.

上記引出配線は、本来は各々スルーホールによって全層が結合されているが、ここでは記載を省略している
（２） 作用効果
本実施の形態では、入出力回路セルや電源セルから千鳥配列の遠方パッドに接続される引出配線のうち、下層配線においてその線幅を下層になるにつれ、徐々に広くしていく。このため、表層配線４ａと表層配線４ａに隣り合う近接パッド２との距離ｇをできるだけ狭めても、ＥＭによる断線やＩＲdropによるＩＣの誤動作を防止できるだけのトータルの配線幅を確保することができる。そして、千鳥配列パッド構造のパッドピッチをより狭くすることが可能になり、チップサイズをより小さくすることにより、コストの削減を得ることができる。また、近接パッドへのワイヤボンディングの際にかかる圧力によって発生し得る応力による影響が少なくなるよう、下層配線の線幅を下に位置するにしたがって徐々に広くしていくことで、製造時のトラブルを防ぐことができる。 Although all the layers of the lead wiring are originally connected by through holes, the description is omitted here. (2) Operational effect In this embodiment, the input and output circuit cells and the power supply cells are arranged in a staggered arrangement. Of the lead wires connected to the far pad, the line width of the lower layer wire is gradually increased as the layer becomes lower. For this reason, even if the distance g between the surface layer wiring 4a and the adjacent pad 2 adjacent to the surface layer wiring 4a is reduced as much as possible, it is possible to secure a total wiring width that can prevent disconnection due to EM and malfunction of the IC due to IRdrop. Further, the pad pitch of the staggered pad structure can be made narrower, and the cost can be reduced by reducing the chip size. Also, in order to reduce the influence of the stress that can be generated by the pressure applied during wire bonding to the proximity pad, the line width of the lower layer wiring is gradually increased as it is positioned below, thereby preventing problems during manufacturing. Can be prevented.

（実施の形態５）
（１） 構成
図７は、本発明の実施の形態５における引出配線の構成を示す図である。図７において、２は、千鳥配列の近接パッドを示し、４は入出力回路セルや電源セルと遠方パッドとを接続する引出配線を示す。引出配線４は、最上層の表層配線４ａと、その下に位置する複数の下層配線４ｂで構成されており、８は保護膜であり、９はワイヤボンディングのために保護膜が設けられない開口領域である。 (Embodiment 5)
(1) Configuration FIG. 7 is a diagram showing the configuration of the lead wiring in the fifth embodiment of the present invention. In FIG. 7, 2 indicates a staggered proximity pad, and 4 indicates an extraction wiring for connecting an input / output circuit cell or power cell to a remote pad. The lead-out wiring 4 is composed of a top layer wiring 4a and a plurality of lower layer wirings 4b located thereunder, 8 is a protective film, and 9 is an opening in which no protective film is provided for wire bonding. It is an area.

各層の引出配線は、すべて本来は各々スルーホールによって全層が結合されているが、ここでは構造を明確にするために記載を省略している。   All the lead wires in each layer are originally connected to each other by through holes, but the description is omitted here for clarity.

通常、半導体集積回路の全表面は、保護膜８によって保護されており、近接パッドの中央部分のみワイヤリング接続等のため保護膜が形成されず、開口領域９が開けられている。近接パッドへのワイヤボンディングは近接パッドの中心を標的にその保護膜より内側の開口領域９にボンディングされる。したがって、保護膜で被覆されている領域の下部では、近接パッドへのワイヤボンディングの直接の影響は小さいと考えられる。   Normally, the entire surface of the semiconductor integrated circuit is protected by the protective film 8, and the protective film is not formed only for the central portion of the proximity pad due to wiring connection or the like, and the opening region 9 is opened. Wire bonding to the proximity pad is performed by bonding to the opening region 9 inside the protective film with the center of the proximity pad as a target. Therefore, it is considered that the direct influence of the wire bonding on the proximity pad is small in the lower part of the region covered with the protective film.

本実施の形態では、表層配線４ａを細くし、下層配線４ｂの線幅を表層配線より広くした場合に、下層配線の線幅の拡張範囲を、隣り合う近接パッドにおける開口領域９にはみ出さないようにしたことを特徴とする。   In the present embodiment, when the surface layer wiring 4a is made thinner and the line width of the lower layer wiring 4b is made wider than that of the surface layer wiring, the expanded range of the line width of the lower layer wiring does not protrude into the opening region 9 in the adjacent adjacent pad. It is characterized by doing so.

（２） 作用効果
本発明は、入出力回路セルや電源セルから外側の千鳥配列パッドに接続される引出配線の下層配線において、その線幅を広くすることで、表層配線４ａと表層配線４ａに隣り合う近接パッド２との距離ｇをできるだけ狭めても、ＥＭによる断線やＩＲdropによるＩＣの誤動作を防止できるだけのトータルの配線幅を確保することができる。そして千鳥配列パッド構造のパッドピッチを狭く、チップサイズをより小さくして、コストの削減をする場合、下層配線の線幅の拡張を隣接する近接パッド上の開口領域にはみ出さない範囲とする。このことにより、トータルの線幅（断面積）を十分大きく確保し、ＥＭによる断線やＩＲdropによるＩＣの誤動作を防止したＩＣの動作を提供することができる。また、近接パッドへのワイヤボンディングの際にかかる圧力によって発生し得る下方向への応力による影響を軽減でき、製造時のトラブルを防ぐことができる。 (2) Operational Effect The present invention provides a surface wiring 4a and a surface wiring 4a by increasing the line width of the lower wiring of the lead wiring connected to the outer staggered array pad from the input / output circuit cell and the power cell. Even if the distance g between adjacent adjacent pads 2 is reduced as much as possible, it is possible to ensure a total wiring width sufficient to prevent disconnection due to EM and malfunction of the IC due to IRdrop. When the pad pitch of the staggered pad structure is narrowed and the chip size is further reduced to reduce the cost, the extension of the line width of the lower layer wiring is set so as not to protrude into the opening area on the adjacent pad. As a result, it is possible to provide an IC operation that ensures a sufficiently large total line width (cross-sectional area) and prevents disconnection due to EM and IC malfunction due to IRdrop. Further, it is possible to reduce the influence of downward stress that can be generated by the pressure applied during wire bonding to the proximity pad, and to prevent troubles during manufacturing.

（実施の形態６）
（１） 構成
図８は、本発明の実施の形態６における引出配線の構造を示す図である。図８において、２は千鳥配列パッドの近接パッドを示し、４は入出力回路セルや電源セルと遠方パッドとを接続する引出配線を示す。引出配線４は、最上層の表層配線４ａと、その下に位置する複数の下層配線４ｂとで構成されている。複数の下層配線４ｂにおいて、（ｎ−１）、ｎ、（ｎ＋１）は、それぞれ最下層から数えて（ｎ−１）、ｎ、（ｎ＋１）番目の配線層を示している。８は保護膜であり、９はワイヤボンディングのために保護膜が配置されない開口領域である。 (Embodiment 6)
(1) Configuration FIG. 8 is a diagram showing the structure of the lead wiring in the sixth embodiment of the present invention. In FIG. 8, reference numeral 2 denotes a proximity pad of a staggered arrangement pad, and 4 denotes an extraction wiring for connecting an input / output circuit cell or a power supply cell to a remote pad. The lead-out wiring 4 is composed of a top layer wiring 4a and a plurality of lower layer wirings 4b positioned therebelow. In the plurality of lower layer wirings 4b, (n−1), n, and (n + 1) indicate the (n−1), n, and (n + 1) th wiring layers counted from the lowest layer, respectively. Reference numeral 8 denotes a protective film, and 9 denotes an opening region where the protective film is not disposed for wire bonding.

従来と同様に、各層の引出配線は、すべて本来は各々スルーホールによって全層が結合されているが、ここでは今回の発明を明確にするために記載を省略している。   As in the prior art, all of the lead-out wirings of each layer are originally connected to each other by through holes, but the description is omitted here for the sake of clarity of the present invention.

図８において、入出力回路セルや電源セルと千鳥配列の遠方パッドとを接続する引出配線４のうち、下層配線４ｂにおいて、その線幅を表層配線４ａの線幅から下に位置するにつれて徐々に広くしていく場合に、ｎ番目以上の層の引出配線の線幅を表層配線４ａの線幅より広く広げる場合は、その線幅を表層配線に隣り合う近接パッド上の開口領域にはみ出さない範囲とする。そして、ｎ番目以下の層において引出配線の線幅を広く広げる場合は、その線幅を、平面的に見て表層配線に隣り合う近接パッド上の開口領域９にはみ出すように拡張する。   In FIG. 8, among the extraction wirings 4 that connect the input / output circuit cells and the power supply cells and the distant pads in the staggered arrangement, the line width of the lower layer wiring 4b gradually increases as it is positioned below the line width of the surface layer wiring 4a. In the case of increasing the width, if the line width of the extraction wiring of the nth or higher layer is made wider than the line width of the surface layer wiring 4a, the line width does not protrude into the opening region on the adjacent pad adjacent to the surface layer wiring. Range. When the line width of the lead-out wiring is widened in the nth and lower layers, the line width is expanded so as to protrude into the opening region 9 on the adjacent pad adjacent to the surface layer wiring in a plan view.

（２） 作用効果
本実施の形態では、入出力回路セルや電源セルから千鳥配列の遠方パッドに接続される引出配線の表層配線４ａと、表層配線４ａに隣り合う近接パッド２との距離ｇをできるだけ狭めて、下層配線において、平面的に見て保護膜の範囲を越える程度にまで線幅を広くすることで、ＥＭによる断線やＩＲdropによるＩＣの誤動作を防止できるだけのトータルの配線幅を確保することができる。そして、千鳥配列パッド構造のパッドピッチをより狭くし、チップサイズをより小さくしてコストの削減を行なう場合において、（ｎ＋１）番目以上の下層配線の線幅を広くする場合は、表層配線に隣り合う近接パッド上の保護膜の端までとすることで、近接パッドへのワイヤボンディングの際にかかる圧力によって発生し得る下方向への応力による影響を少なくできる。さらに、近接パッドからの応力による影響の少ないｎ番目以下の配線層は、近接パッドの保護膜上の端を超えて広げることで、トータルの配線幅をより多く確保し、ＥＭによる断線やＩＲdropによるＩＣの誤動作を防止したＩＣの動作を提供できる。また、近接パッドへのワイヤボンディングの際にかかる圧力によって発生し得る下方向への応力による影響を軽減でき、製造時のトラブルを防ぐことができる。 (2) Operational Effect In the present embodiment, the distance g between the surface layer wiring 4a of the lead wiring connected to the distant pad in the staggered arrangement from the input / output circuit cell and the power cell and the adjacent pad 2 adjacent to the surface layer wiring 4a is set as follows. By narrowing as much as possible and widening the lower layer wiring so that it exceeds the range of the protective film in plan view, the total wiring width is secured to prevent disconnection due to EM and IC malfunction due to IRdrop. be able to. When the pad pitch of the staggered pad structure is made narrower and the chip size is made smaller to reduce the cost, when the line width of the (n + 1) th or lower layer wiring is widened, it is adjacent to the surface layer wiring. By extending to the end of the protective film on the matching proximity pad, it is possible to reduce the influence of the downward stress that can be generated by the pressure applied during wire bonding to the proximity pad. Furthermore, the nth or lower wiring layer, which is less affected by stress from the proximity pad, is expanded beyond the edge of the proximity pad on the protective film, thereby securing a larger total wiring width, and by EM disconnection or IRdrop. It is possible to provide an IC operation that prevents an IC malfunction. Further, it is possible to reduce the influence of downward stress that can be generated by the pressure applied during wire bonding to the proximity pad, and to prevent troubles during manufacturing.

次に、上記の実施の形態を含めて、本発明の他の実施の形態を羅列的に紹介する。   Next, other embodiments of the present invention including the above-described embodiments will be introduced in a list.

上記の下層配線は複数の層から構成され、その下層配線のすべての線幅を、表層配線の線幅より広くすることができる。   The lower layer wiring is composed of a plurality of layers, and all the line widths of the lower layer wiring can be made wider than the line width of the surface layer wiring.

この構成により、遠方パッドへの引出配線の断面積合計を大きくして、電気抵抗を小さくでき、したがって引出配線における電圧降下やＥＭを最小限に抑えることができる。   With this configuration, the total cross-sectional area of the lead-out wiring to the far pad can be increased, and the electrical resistance can be reduced. Therefore, voltage drop and EM in the lead-out wiring can be minimized.

また、上記の下層配線は複数の層から構成され、その下層配線のうち、所定の層以下に位置する下層配線の線幅が、表層配線の線幅よりも広く、上記所定の層より上に位置する下層配線の線幅が表層配線の線幅と同じであるようにできる。   In addition, the lower layer wiring is composed of a plurality of layers, and among the lower layer wirings, the line width of the lower layer wiring located below a predetermined layer is wider than the line width of the surface layer wiring and is above the predetermined layer. The line width of the lower layer wiring positioned can be the same as the line width of the surface layer wiring.

下層配線の線幅を自由に変えられない場合、所定の層より上では表層配線と同じ線幅とし、所定の層以下に位置する下層配線の線幅を表層配線より広くすることにより、上記電圧降下やＥＭを抑制することができる。   When the line width of the lower layer wiring cannot be changed freely, the above-mentioned voltage is obtained by setting the line width equal to that of the surface layer wiring above the predetermined layer and making the line width of the lower layer wiring located below the predetermined layer wider than the surface layer wiring. Descent and EM can be suppressed.

上記の下層配線は複数の層から構成され、その下層配線のうち、所定の層以上に位置する下層配線の線幅が、表層配線の線幅よりも広く、所定の層より下に位置する下層配線の線幅が、所定の層以上に位置し、表層配線の線幅より広い線幅を有する下層配線の線幅よりも広いようにできる。   The lower layer wiring is composed of a plurality of layers, and among the lower layer wirings, the lower layer wiring located above a predetermined layer has a line width wider than that of the surface layer wiring and located below the predetermined layer. The line width of the wiring can be made larger than the line width of the lower layer wiring which is located in a predetermined layer or more and has a line width wider than that of the surface layer wiring.

また、下層配線は複数の層から構成され、千鳥配列の内部回路に近い方の近接パッドが２つ隣り合う間隔よりも広い線幅の下層配線を少なくとも１つ含むようにできる。   The lower layer wiring is composed of a plurality of layers, and can include at least one lower layer wiring having a line width wider than the interval between two adjacent pads closer to the internal circuit in the staggered arrangement.

上記のように、少なくとも１つの下層配線の線幅を近接パッド間隔より広くすることにより、上記電圧降下やＥＭを抑制することができる。   As described above, the voltage drop and EM can be suppressed by making the line width of at least one lower layer wiring wider than the adjacent pad interval.

また、上記の下層配線は複数の層から構成され、その下層配線は、下に位置するにしたがい徐々にその線幅が広くなっているようにできる。   Further, the lower layer wiring is composed of a plurality of layers, and the lower layer wiring can be gradually widened as it is positioned below.

上記の態様によっても、遠方パッドへの引出配線の断面積合計を大きくすることができる。   Also according to the above aspect, the total cross-sectional area of the lead-out wiring to the far pad can be increased.

上記のＩＣチップにおいて、千鳥配列のパッドは開口領域が設けられた保護膜で被覆され、下層配線は、平面的に見て、その下層配線が接続する遠方パッドに隣り合う近接パッドにおける開口領域にはみ出さない線幅を有するようにできる。   In the above IC chip, the staggered pads are covered with a protective film provided with an opening region, and the lower layer wiring is seen in a plan view in the opening region in the adjacent pad adjacent to the far pad to which the lower layer wiring is connected. It can have a line width that does not protrude.

この構成により、下層配線は平面的に見てとくに保護膜の範囲内に限定される。このため、保護膜を形成後に近接パッド上の保護膜開口領域にワイヤボンディングする際に、その応力の影響を軽減することができる。   With this configuration, the lower layer wiring is particularly limited within the range of the protective film in plan view. For this reason, the influence of the stress can be reduced when wire bonding is performed on the protective film opening region on the proximity pad after the protective film is formed.

上記のＩＣチップにおいて、千鳥配列のパッドは開口領域が設けられた保護膜で被覆され、上記の下層配線は複数の層から構成され、所定の層より下に位置する下層配線は、平面的に見てその下層配線が接続する遠方パッドに隣り合う近接パッドにおける開口領域にはみ出す線幅を有するようにできる。   In the above IC chip, the staggered pads are covered with a protective film provided with an opening region, the lower layer wiring is composed of a plurality of layers, and the lower layer wiring located below a predetermined layer is planar. As can be seen, the line width of the adjacent pad adjacent to the distant pad to which the lower layer wiring is connected protrudes from the opening region.

この構成により、ワイヤボンディングの応力の影響が及ばない下の領域の下層配線の線幅を非常に広くでき、より確実にＥＭによる断線やＩＲdropを防止することが可能になる。   With this configuration, the line width of the lower layer wiring in the lower region that is not affected by the stress of wire bonding can be made very wide, and disconnection due to EM and IRdrop can be more reliably prevented.

上記において、本発明の実施の形態について説明を行ったが、上記に開示された本発明の実施の形態は、あくまで例示であって、本発明の範囲はこれら発明の実施の形態に限定されない。本発明の範囲は、特許請求の範囲の記載によって示され、さらに特許請求の範囲の記載と均等の意味および範囲内でのすべての変更を含むものである。   Although the embodiments of the present invention have been described above, the embodiments of the present invention disclosed above are merely examples, and the scope of the present invention is not limited to these embodiments. The scope of the present invention is indicated by the description of the scope of claims, and further includes meanings equivalent to the description of the scope of claims and all modifications within the scope.

本発明は、ＩＯ数（パッド数）によってチップサイズが決められてしまうような超多ピンのＩＣチップにおいて、千鳥配列の遠方パッドへの引出配線を多層にして、表層配線の線幅を狭く、下層配線の線幅をそれより広くすることにより、ＥＭやＩＲdropの問題を解決しながら、千鳥配列パッドのパッドピッチをさらに狭くし、チップサイズをより小さくすることができる。今後ますます半導体装置の微細化の傾向が強まるので、上記本発明のＩＣチップは、すべてのエレクトロニクス分野に広範に利用されることが期待される。   In the present invention, in an ultra-multi-pin IC chip whose chip size is determined by the number of IOs (number of pads), the lead-out wiring to the distant pads in a zigzag array is multilayered, and the line width of the surface layer wiring is narrowed. By making the line width of the lower layer wiring wider than that, the pad pitch of the staggered pad can be further narrowed and the chip size can be further reduced while solving the problems of EM and IRdrop. Since the trend of miniaturization of semiconductor devices will increase in the future, the IC chip of the present invention is expected to be widely used in all electronics fields.

本発明の実施の形態１におけるＩＣチップを含む半導体装置の概要を示す図である。It is a figure which shows the outline | summary of the semiconductor device containing the IC chip in Embodiment 1 of this invention. 図１のＩＣチップにおける千鳥配列のパッドを示す図である。It is a figure which shows the pad of the staggered arrangement | sequence in the IC chip of FIG. 図２におけるＩＩＩ−ＩＩＩ線に沿う断面図である。It is sectional drawing which follows the III-III line in FIG. 本発明の実施の形態２におけるＩＣチップの遠方パッドへの引出配線を示す断面図である。It is sectional drawing which shows the extraction | drawer wiring to the far pad of IC chip in Embodiment 2 of this invention. 本発明の実施の形態３におけるＩＣチップの遠方パッドへの引出配線を示す断面図である。It is sectional drawing which shows the lead-out wiring to the far pad of the IC chip in Embodiment 3 of this invention. 本発明の実施の形態４におけるＩＣチップの遠方パッドへの引出配線を示す断面図である。It is sectional drawing which shows the extraction | drawer wiring to the far pad of the IC chip in Embodiment 4 of this invention. 本発明の実施の形態５におけるＩＣチップの遠方パッドへの引出配線を示す断面図である。It is sectional drawing which shows the extraction | drawer wiring to the far pad of IC chip in Embodiment 5 of this invention. 本発明の実施の形態６におけるＩＣチップの遠方パッドへの引出配線を示す断面図である。It is sectional drawing which shows the extraction | drawer wiring to the far pad of the IC chip in Embodiment 6 of this invention.

符号の説明Explanation of symbols

１ 入出力回路セル、２ 近接パッド、３ 遠方パッド、４ 遠方パッドへの引出配線、４ａ 表層配線、４ｂ 下層配線、７ 層間絶縁膜、８ 保護膜、９ 保護膜の開口領域、１０ 半導体チップの内部回路、１１ 金線、１２ 外部リード、１５ ＩＣチップ、２０ 半導体装置、ｇ 表層配線のエッジと隣の近接パッドのエッジとの距離、ｄn 隣の近接パッドと線幅が重複する下層配線との最小距離、Ｓn+1，Ｓn+2 隣の内側エッジと、その近接パッドの線幅が重複しない下層配線のエッジとの距離、Ｆ ワイヤボンディングの影響が及ぶ範囲、Ｌ 隣り合う２つの近接パッド２の間の隙間。   DESCRIPTION OF SYMBOLS 1 Input / output circuit cell, 2 Proximity pad, 3 Far pad, 4 Leading wiring to far pad, 4a Surface wiring, 4b Lower wiring, 7 Interlayer insulating film, 8 Protective film, 9 Open area of protective film, 10 Semiconductor chip Internal circuit, 11 gold wire, 12 external lead, 15 IC chip, 20 semiconductor device, g distance between the edge of the surface layer wiring and the edge of the adjacent neighboring pad, dn with the lower layer wiring whose line width overlaps with the adjacent neighboring pad Minimum distance, Sn + 1, Sn + 2 The distance between the adjacent inner edge and the edge of the lower layer wiring where the adjacent pad width does not overlap, the range affected by F-wire bonding, L Two adjacent pads 2 Gap between.

Claims (9)

内部回路からの引出配線が接続されたパッドが、千鳥配列されるＩＣ(Integrated Circuit)チップにおいて、
その千鳥配列の前記内部回路から遠い方の遠方パッドに接続される前記引出配線が、前記千鳥配列のパッドが形成される層と同じ層に位置する表層配線と、その表層配線と電気的に接続され、その表層配線より下層に位置し、線幅が前記表層配線の線幅より広い少なくとも１つの下層配線とを有する、ＩＣチップ。 In an IC (Integrated Circuit) chip in which pads connected to lead-out wiring from the internal circuit are arranged in a staggered manner,
The lead-out wiring connected to the far pad far from the internal circuit of the staggered arrangement is a surface layer wiring located in the same layer as the layer where the staggered pad is formed, and is electrically connected to the surface wiring. And an at least one lower layer wiring which is positioned below the surface layer wiring and whose line width is wider than the line width of the surface layer wiring. 前記下層配線は複数の層から構成され、その下層配線のすべての線幅が、前記表層配線の線幅より広い、請求項１に記載のＩＣチップ。   2. The IC chip according to claim 1, wherein the lower layer wiring is composed of a plurality of layers, and all line widths of the lower layer wiring are wider than the line width of the surface layer wiring. 前記下層配線は複数の層から構成され、その下層配線のうち、所定の層以下に位置する下層配線の線幅が、前記表層配線の線幅よりも広く、前記所定の層より上に位置する下層配線の線幅が前記表層配線の線幅と同じである、請求項１に記載のＩＣチップ。   The lower layer wiring is composed of a plurality of layers, and of the lower layer wirings, the lower layer wiring located below a predetermined layer has a line width wider than the surface layer wiring and above the predetermined layer. 2. The IC chip according to claim 1, wherein the line width of the lower layer wiring is the same as the line width of the surface layer wiring. 前記下層配線は複数の層から構成され、その下層配線のうち、所定の層以上に位置する下層配線の線幅が、前記表層配線の線幅よりも広く、前記所定の層より下に位置する下層配線の線幅が、前記所定の層以上に位置し、前記表層配線の線幅より広い線幅を有する下層配線の線幅よりも広い、請求項１に記載のＩＣチップ。   The lower layer wiring is composed of a plurality of layers, and among the lower layer wirings, the line width of the lower layer wiring located above a predetermined layer is wider than the line width of the surface layer wiring and positioned below the predetermined layer. 2. The IC chip according to claim 1, wherein a line width of a lower layer wiring is wider than a line width of a lower layer wiring that is located above the predetermined layer and has a line width wider than that of the surface layer wiring. 内部回路からの引出配線が接続されたパッドが、千鳥配列されるＩＣ(Integrated Circuit)チップにおいて、
その千鳥配列のパッドにおいて、その千鳥配列の前記内部回路から遠い側の遠方パッドに接続される前記引出配線が、前記千鳥配列のパッドが形成される層と同じ層に位置する配線層を含まず、前記千鳥配列のパッドが形成される層より下層に位置する、少なくとも１つの下層配線を有する、ＩＣチップ。 In an IC (Integrated Circuit) chip in which pads connected to lead-out wiring from the internal circuit are arranged in a staggered manner,
In the staggered pad, the lead-out wiring connected to the far pad far from the internal circuit of the staggered array does not include a wiring layer located in the same layer as the layer on which the staggered pad is formed. An IC chip having at least one lower layer wiring located below the layer on which the staggered pads are formed. 前記下層配線は複数の層から構成され、前記千鳥配列の内部回路に近い方の近接パッドが２つ隣り合う間隔よりも広い線幅の下層配線を少なくとも１つ含む、請求項５に記載のＩＣチップ。   6. The IC according to claim 5, wherein the lower layer wiring is composed of a plurality of layers, and includes at least one lower layer wiring having a line width wider than an interval between two adjacent pads closer to the internal circuit of the staggered arrangement. Chip. 前記下層配線は複数の層から構成され、その下層配線が、下に位置するにしたがいその線幅が広くなっている、請求項１、５、６のいずれかに記載のＩＣチップ。   The IC chip according to claim 1, wherein the lower layer wiring is composed of a plurality of layers, and the line width of the lower layer wiring becomes wider as the lower layer wiring is positioned below. 前記ＩＣチップにおいて、前記千鳥配列のパッドは開口領域が設けられた保護膜で被覆され、前記下層配線は、平面的に見て、その下層配線が接続する前記遠方パッドに隣り合う、前記千鳥配列の前記内部回路に近い方の近接パッドにおける前記開口領域にはみ出さない線幅を有する、請求項１〜７のいずれかに記載のＩＣチップ。   In the IC chip, the staggered pads are covered with a protective film having an opening region, and the lower layer wiring is adjacent to the distant pad to which the lower layer wiring is connected in a plan view. The IC chip according to claim 1, wherein the IC chip has a line width that does not protrude into the opening region in a proximity pad closer to the internal circuit. 前記ＩＣチップにおいて、前記千鳥配列のパッドが開口領域が設けられた保護膜で被覆され、前記下層配線は複数の層から構成され、所定の層より下に位置する下層配線は、平面的に見てその下層配線が接続する前記遠方パッドに隣り合う、前記千鳥配列の前記内部回路に近いほうの２つの近接パッドにおける開口領域にはみ出す線幅を有する、請求項１〜７のいずれかに記載のＩＣチップ。   In the IC chip, the staggered pads are covered with a protective film provided with an opening region, the lower layer wiring is composed of a plurality of layers, and the lower layer wiring located below a predetermined layer is seen in plan view. 8. The line width according to claim 1, which has a line width that protrudes into an opening region in two adjacent pads that are adjacent to the far pad to which the lower layer wiring is connected and that is closer to the internal circuit in the staggered arrangement. IC chip.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7911063B2 (en) 2007-12-05 2011-03-22 Renesas Electronics Corporation Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7911063B2 (en) 2007-12-05 2011-03-22 Renesas Electronics Corporation Semiconductor device

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