JP2005166822A - 不揮発性メモリを含む半導体装置及びその製造方法 - Google Patents
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- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- Manufacturing & Machinery (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
【解決手段】 論理回路領域において、第3のゲート電極膜40と第1のゲート電極膜37を積層し、N型トランジスタ及びP型トランジスタ共に表面チャネル領域を持つような相補型MOS論理回路を構成する。
【選択図】 図11
Description
11 メモリセルアレイ
11a、11b、11c メモリセル
12 カラムデコーダ
13 センスアンプ
14,15 ロウデコーダ
14a、14b ワード線
15a、15b セレクトゲート線
16 ソース線ドライバ
20、30 シリコン基板
21素子領域
21a 素子分離領域
22 コンタクトプラグ
31 素子分離領域
32 P型ウェル領域
33 N型ウェル領域
34 トンネル絶縁膜
35 第1のゲート絶縁膜
35a 高電圧トランジスタ
36 第2のゲート絶縁膜
36a 低電圧トランジスタ
37 第1のゲート電極膜
38 第2のゲート電極膜
39 インターゲート絶縁膜
40 第3のゲート電極膜
41 側壁絶縁膜
42 ソース及びドレイン領域
43 サリサイド電極膜
23 制御ゲートコンタクト
50 システムLSI
51 CPU
52 第1の不揮発性メモリ
53 第2の不揮発性メモリ
54 第3の不揮発性メモリ
Claims (5)
- 半導体基体と、
前記半導体基体上に積層された、トンネル絶縁膜、第1のゲート電極膜、第2のゲート電極膜、インターゲート絶縁膜、及び第3のゲート電極膜からなる第1のゲートと、前記トンネル絶縁膜に接する前記半導体基体を挟むように、前記半導体基体の表面領域に形成されたソース及びドレイン領域とを備えた第1のMOSトランジスタを少なくとも一つ有する不揮発性メモリセルと、
前記不揮発性メモリセルから離れて前記半導体基体上に積層された、ゲート絶縁膜、前記第1のゲート電極膜及び前記第3のゲート電極膜からなる第2のゲートと、前記ゲート絶縁膜に接する前記半導体基体を挟むように、前記半導体基体の表面領域に形成されたソース及びドレイン領域とを備えた第2のMOSトランジスタを有する相補型MOS論理回路とを
具備したことを特徴とする不揮発性メモリを含む半導体装置。 - 前記インターゲート絶縁膜の一部に開口部があり、前記開口部を介して前記第3のゲート電極膜と前記第2のゲート電極膜とが接続されていることを特徴とする請求項1に記載の不揮発性メモリを含む半導体装置。
- 前記メモリセルが、メモリセルトランジスタと、電流経路が前記メモリセルトランジスタの一端に接続された選択トランジスタとの、2つの第1のMOSトランジスタによって構成されていることを特徴とする請求項1又は請求項2に記載の不揮発性メモリを含む半導体装置。
- 半導体基体の素子形成領域を囲むように素子分離領域を形成する工程と、
前記素子形成領域にトンネル絶縁膜を形成する工程と、
前記素子形成領域のうち、相補型MOS論理回路を形成する論理回路領域における前記トンネル絶縁膜を剥離する工程と、
前記論理回路領域における前記半導体基体上に、ゲート絶縁膜を形成する工程と、
前記トンネル絶縁膜及び前記ゲート絶縁膜上に第1のゲート電極膜を形成する工程と、
前記素子形成領域のうち、不揮発性メモリセルを形成するメモリセル領域における前記第1のゲート電極膜上に第2のゲート電極膜を形成する工程と、
前記メモリセル領域における前記トンネル絶縁膜、前記第1のゲート電極膜及び第2のゲート電極膜を選択的にパターニングする工程と、
前記メモリセル領域における前記第2のゲート電極膜上にインターゲート絶縁膜を形成する工程と、
前記メモリセル領域における前記インターゲート絶縁膜上、及び前記論理回路領域における前記第1のゲート電極膜上に第3のゲート電極膜を形成する工程と、
前記第3のゲート電極膜に不純物を導入する工程と、
前記メモリセル領域における前記第3のゲート電極膜、前記インターゲート絶縁膜、前記第2のゲート電極膜、及び前記第1のゲート電極膜と、前記論理回路領域における前記第3のゲート電極膜及び前記第1のゲート電極膜とを選択的にパターニングする工程と、
パターニングされた前記第3のゲート電極膜をマスクにして、前記半導体基体表面に不純物を導入してソース及びドレイン領域を形成する工程とを
有することを特徴とする不揮発性メモリを含む半導体装置の製造方法。 - 前記インターゲート絶縁膜を形成する工程と、前記第3のゲート電極膜を形成する工程との間に、前記メモリセル領域における前記インターゲート絶縁膜の一部に開口部を形成する工程を有することを特徴とする請求項1に記載の不揮発性メモリを含む半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2003401854A JP2005166822A (ja) | 2003-12-01 | 2003-12-01 | 不揮発性メモリを含む半導体装置及びその製造方法 |
US10/999,135 US20050157536A1 (en) | 2003-12-01 | 2004-11-30 | Semiconductor device including nonvolatile memory and method of fabricating the same |
US12/246,135 US20090039412A1 (en) | 2003-12-01 | 2008-10-06 | Semiconductor device including nonvolatile memory and method of fabricating the same |
Applications Claiming Priority (1)
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JP2003401854A JP2005166822A (ja) | 2003-12-01 | 2003-12-01 | 不揮発性メモリを含む半導体装置及びその製造方法 |
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JP2005166822A true JP2005166822A (ja) | 2005-06-23 |
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US (2) | US20050157536A1 (ja) |
JP (1) | JP2005166822A (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008205191A (ja) * | 2007-02-20 | 2008-09-04 | Toshiba Corp | 不揮発性半導体メモリ素子および不揮発性半導体メモリ装置 |
JP2008244009A (ja) * | 2007-03-26 | 2008-10-09 | Fujitsu Ltd | 半導体装置およびその製造方法 |
JP2009010381A (ja) * | 2007-06-26 | 2009-01-15 | Dongbu Hitek Co Ltd | フラッシュメモリー素子の製造方法 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006108310A (ja) * | 2004-10-04 | 2006-04-20 | Toshiba Corp | 不揮発性半導体記憶装置とその製造方法 |
JP2009272565A (ja) * | 2008-05-09 | 2009-11-19 | Toshiba Corp | 半導体記憶装置、及びその製造方法 |
US20150287706A1 (en) * | 2012-10-24 | 2015-10-08 | Mitsunari Sukekawa | Semiconductor device and method for manufacturing the same |
JP2021150600A (ja) * | 2020-03-23 | 2021-09-27 | キオクシア株式会社 | 半導体記憶装置 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6278165B1 (en) * | 1998-06-29 | 2001-08-21 | Kabushiki Kaisha Toshiba | MIS transistor having a large driving current and method for producing the same |
US20030030123A1 (en) * | 2001-08-10 | 2003-02-13 | Masayuki Ichige | Semiconductor memory device equipped with memory transistor and peripheral transistor and method of manufacturing the same |
US6925008B2 (en) * | 2001-09-29 | 2005-08-02 | Kabushiki Kaisha Toshiba | Non-volatile semiconductor memory device with a memory unit including not more than two memory cell transistors |
-
2003
- 2003-12-01 JP JP2003401854A patent/JP2005166822A/ja active Pending
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2004
- 2004-11-30 US US10/999,135 patent/US20050157536A1/en not_active Abandoned
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2008
- 2008-10-06 US US12/246,135 patent/US20090039412A1/en not_active Abandoned
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008205191A (ja) * | 2007-02-20 | 2008-09-04 | Toshiba Corp | 不揮発性半導体メモリ素子および不揮発性半導体メモリ装置 |
JP2008244009A (ja) * | 2007-03-26 | 2008-10-09 | Fujitsu Ltd | 半導体装置およびその製造方法 |
JP2009010381A (ja) * | 2007-06-26 | 2009-01-15 | Dongbu Hitek Co Ltd | フラッシュメモリー素子の製造方法 |
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