JP2005124120A - Driving circuit, processing circuit, and differential class ab amplifier - Google Patents

Driving circuit, processing circuit, and differential class ab amplifier Download PDF

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JP2005124120A
JP2005124120A JP2004039296A JP2004039296A JP2005124120A JP 2005124120 A JP2005124120 A JP 2005124120A JP 2004039296 A JP2004039296 A JP 2004039296A JP 2004039296 A JP2004039296 A JP 2004039296A JP 2005124120 A JP2005124120 A JP 2005124120A
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JP4408715B2 (en
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Atsushi Shimatani
淳 嶋谷
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NEC Electronics Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To make a driving circuit and a processing circuit which are equipped with two or more differential class AB amplifiers to be higher integration and lower consumption power. <P>SOLUTION: At the time of a test mode, a common bias circuit 2 switches: a pair of N and P channel differential bias voltage to a ground level or a power source level; a pair of N and P channel constant current bias voltage to a ground level or a power source level; a pair of N and P channel shift bias voltage to a ground level or a power source level. These switching outputs respectively control constant current MOS transistors 111, 121 of a pair of N and P receiving differential amplifiers 11, 12, a pair of P and N channel constant current MOS transistors 133, 134, and a pair of P and N channel shift MOS transistors 135, 136 in the differential class AB amplifier. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、駆動回路および処理回路に関し、特に、複数の差動ＡＢ級増幅回路を備える駆動回路および処理回路に関する。   The present invention relates to a drive circuit and a processing circuit, and more particularly to a drive circuit and a processing circuit including a plurality of differential class AB amplifier circuits.

従来、この種の駆動回路または処理回路は、複数の差動ＡＢ級増幅回路を備え、複数のアナログデータ線の並列駆動または複数のアナログ信号の並列増幅を低消費電力で行うために用いられてきた。なお、本発明の駆動回路および処理回路は、同等の特徴部を備えるため、以下、本明細書では、これら駆動回路および処理回路を代表して、例えば、表示装置の駆動回路について説明する。   Conventionally, this type of driving circuit or processing circuit includes a plurality of differential class AB amplifier circuits, and has been used to perform parallel driving of a plurality of analog data lines or parallel amplification of a plurality of analog signals with low power consumption. It was. In addition, since the drive circuit and processing circuit of this invention are provided with an equivalent characteristic part, hereafter, the drive circuit of a display apparatus is demonstrated in this specification on behalf of these drive circuits and processing circuits, for example.

この従来の表示装置の駆動回路は、例えばＬＣＤパネルの各列のデータ線などの容量性負荷を並列に電圧駆動し表示データに応じた各列のアナログ信号を並列出力するため、電源ライン間の全電源電圧範囲で入出力可能な、いわゆるＲａｉｌ−Ｔｏ−Ｒａｉｌ入出力可能な複数の差動ＡＢ級増幅器をそれぞれボルテージフォロア接続して用いてきた。   The driving circuit of this conventional display device, for example, drives a capacitive load such as a data line of each column of an LCD panel in parallel and outputs an analog signal of each column according to display data in parallel. A plurality of differential class AB amplifiers capable of inputting and outputting in the entire power supply voltage range and capable of inputting and outputting Rail-To-Rail have been used in voltage follower connection.

例えば、図５は、この従来の表示装置の駆動回路の構成例および表示パネルを示すブロック図である。   For example, FIG. 5 is a block diagram illustrating a configuration example of a driving circuit of the conventional display device and a display panel.

この従来の表示装置の駆動回路は、制御回路４，階調電源５，走査線駆動回路６およびデータ線駆動回路７を備え、表示パネル８を駆動する。   The driving circuit of this conventional display device includes a control circuit 4, a gradation power source 5, a scanning line driving circuit 6, and a data line driving circuit 7, and drives the display panel 8.

ここで、表示パネル８は、薄膜ＭＯＳトランジスタ（ＴＦＴ）をスイッチ素子に用いたアクティブマトリクス駆動方式のカラー液晶パネルであり、行方向および列方向にそれぞれ所定間隔で設けられた走査線およびデータ線の交点に画素を行列配置し、各画素は、等価的に容量性負荷である液晶容量と、走査線にゲートを接続したＴＦＴとをデータ線および共通電極線の間に直列接続して備える。   Here, the display panel 8 is an active matrix driving type color liquid crystal panel using thin film MOS transistors (TFTs) as switching elements, and includes scanning lines and data lines provided at predetermined intervals in the row direction and the column direction, respectively. Pixels are arranged in a matrix at intersections, and each pixel includes a liquid crystal capacitor, which is equivalently a capacitive load, and a TFT having a gate connected to a scanning line connected in series between a data line and a common electrode line.

この表示パネル８の各行の走査線には、水平同期信号および垂直同期信号などに基づいて走査線駆動回路７により生成された走査パルスが印加され、表示パネル８の各列のデータ線には、共通電極線に共通電位Ｖｃｏｍを印加している状態において、デジタル表示データに基づいてデータ線駆動回路７により色ごとに生成されたアナログデータ信号が印加される。これにより、表示パネル８には、カラーの文字や画像などが表示される。   A scanning pulse generated by the scanning line driving circuit 7 based on a horizontal synchronizing signal and a vertical synchronizing signal is applied to the scanning line of each row of the display panel 8, and the data line of each column of the display panel 8 is In a state where the common potential Vcom is applied to the common electrode line, an analog data signal generated for each color by the data line driving circuit 7 based on the digital display data is applied. As a result, color characters, images, and the like are displayed on the display panel 8.

次に、本発明に関連しているデータ線駆動回路７について、主に説明する。このデータ線駆動回路７は、各列の表示データを階調電圧の択一によりそれぞれＤ／Ａ変換するＤ／Ａ変換回路７１と、インピーダンス変換し各列のデータ線を駆動しアナログ表示データ信号を出力する出力回路７２を備え、この出力回路７２は、それぞれボルテージフォロア接続されＲａｉｌ−Ｔｏ−Ｒａｉｌ入出力可能な複数の差動ＡＢ級増幅回路１と、これら複数の差動ＡＢ級増幅回路１へ共通のバイアス電圧を供給する共通バイアス回路２とを備える。   Next, the data line driving circuit 7 related to the present invention will be mainly described. The data line driving circuit 7 includes a D / A conversion circuit 71 that D / A converts display data of each column by selecting a gradation voltage, and impedance conversion to drive a data line of each column to generate an analog display data signal. The output circuit 72 includes a plurality of differential class AB amplifier circuits 1 that are voltage follower-connected and can input and output Rail-To-Rail, and the plurality of differential class AB amplifier circuits 1. And a common bias circuit 2 for supplying a common bias voltage.

この従来のデータ線駆動回路７の出力回路７２は、消費電力の少ない差動ＡＢ級増幅回路１を用い、且つ、共通バイアス回路２との組み合わせにより、差動ＡＢ級増幅回路１の複数配列による回路規模増大を抑制して複数のデータ線を並列に駆動でき、回路面積が節減され、低消費電力化される。   The output circuit 72 of the conventional data line driving circuit 7 uses a differential class AB amplifier circuit 1 with low power consumption and a combination of the common bias circuit 2 and a plurality of arrangements of the differential class AB amplifier circuit 1. A plurality of data lines can be driven in parallel while suppressing an increase in circuit scale, and the circuit area is reduced and the power consumption is reduced.

図６は、上述の差動ＡＢ級増幅回路１の従来例１を示す回路図である。この差動ＡＢ級増幅回路１は、差動増幅器１７およびＡＢ級出力回路１８を備え、例えば、特許文献１の第１図記載のＡＢ級出力回路におけるドライバとして、Ｒａｉｌ−Ｔｏ−Ｒａｉｌ入力可能な、一般的な差動増幅器１７を用いることにより得られ、Ｒａｉｌ−Ｔｏ−Ｒａｉｌ入出力可能となる。   FIG. 6 is a circuit diagram showing a conventional example 1 of the differential class AB amplifier circuit 1 described above. The differential class AB amplifier circuit 1 includes a differential amplifier 17 and a class AB output circuit 18. For example, Rail-To-Rail input is possible as a driver in the class AB output circuit described in FIG. This is obtained by using a general differential amplifier 17 and enables Rail-To-Rail input / output.

差動増幅器１７は、Ｎ受け差動増幅ミラー出力部１７１およびＰ受け差動増幅部１７２を備える。   The differential amplifier 17 includes an N receiving differential amplification mirror output unit 171 and a P receiving differential amplification unit 172.

Ｎ受け差動増幅ミラー出力部１７１は、正転入力端子Ｖｉｎ（＋）および反転入力端子Ｖｉｎ（−）をゲートに接続した１対のＮチャネル差動ＭＯＳトランジスタ１１２，１１３と、これら１対のＮチャネル差動ＭＯＳトランジスタ１１２，１１３の負荷として接続された１対のＰチャネル負荷ＭＯＳトランジスタ１１４，１１５と、これら１対のＰチャネル負荷ＭＯＳトランジスタ１１４，１１５の差動電流のミラー電流Ｉ４，Ｉ５をＰ受け差動増幅部１７２の１対のＮチャネル負荷ＭＯＳトランジスタ１２４，１２５へ加算出力する１対のＰチャネルミラー出力ＭＯＳトランジスタ１１７，１１８と、１対のＮチャネル差動ＭＯＳトランジスタ２１，２２のソースに定電流Ｉ１を供給する定電流源１１６とを備える。   The N receiving differential amplification mirror output unit 171 includes a pair of N-channel differential MOS transistors 112 and 113 having a normal input terminal Vin (+) and an inverting input terminal Vin (−) connected to the gate, and a pair of these. A pair of P-channel load MOS transistors 114 and 115 connected as loads of N-channel differential MOS transistors 112 and 113, and mirror currents I4 and I5 of the differential current of the pair of P-channel load MOS transistors 114 and 115 A pair of P channel mirror output MOS transistors 117 and 118 and a pair of N channel differential MOS transistors 21 and 22 for adding and outputting to the pair of N channel load MOS transistors 124 and 125 of the P receiving differential amplifier 172 And a constant current source 116 for supplying a constant current I1 to the source.

また、Ｐ受け差動増幅部１７２は、反転入力端子Ｖｉｎ（−）および正転入力端子Ｖｉｎ（＋）をゲートに接続した１対のＰチャネル差動ＭＯＳトランジスタ１２２，１２３と、これら１対のＰチャネル差動ＭＯＳトランジスタ１２２，１２３の電流ミラー型負荷として接続された１対のＮチャネル負荷ＭＯＳトランジスタ１２４，１２５と、１対のＰチャネル差動ＭＯＳトランジスタ１２２，１２３のソースに定電流Ｉ２を供給する定電流源１２６とを備え、Ｐチャネル差動ＭＯＳトランジスタ１２３のドレインからＡＢ級出力回路１８のＮチャネル出力段ＭＯＳトランジスタ１３２のゲートへ出力する。   The P receiving differential amplification unit 172 includes a pair of P channel differential MOS transistors 122 and 123 having the inverting input terminal Vin (−) and the non-inverting input terminal Vin (+) connected to the gate, and a pair of these. A constant current I2 is applied to the sources of a pair of N-channel load MOS transistors 124 and 125 connected as a current mirror type load of the P-channel differential MOS transistors 122 and 123 and a pair of P-channel differential MOS transistors 122 and 123. A constant current source 126 is provided, and outputs from the drain of the P-channel differential MOS transistor 123 to the gate of the N-channel output stage MOS transistor 132 of the class AB output circuit 18.

ＡＢ級出力回路１８は、出力端子−電源端子間および出力端子−接地端子間にそれぞれ接続された１対のＰおよびＮチャネル出力段ＭＯＳトランジスタ１３１，１３２と、これら１対のＰおよびＮチャネル出力段ＭＯＳトランジスタ１３１，１３２のゲート−電源端子間およびゲート−接地端子間にそれぞれ接続された１対の定電流源１３７，１３８と、これら１対の定電流源１３７，１３８の間に並列接続され１対の定電圧源１３９，１４０にゲートをそれぞれ接続しレベルシフタとして機能する１対のＰおよびＮチャネルシフトＭＯＳトランジスタ１３５，１３６と、電源端子，接地端子よりダイオード接続Ｐ，ＮチャネルＭＯＳトランジスタの直列２段分の閾値だけ低い，高い電圧を供給する１対の定電圧源１３９，１４０とを備える。   The class AB output circuit 18 includes a pair of P and N channel output stage MOS transistors 131 and 132 connected between the output terminal and the power supply terminal and between the output terminal and the ground terminal, and the pair of P and N channel outputs. A pair of constant current sources 137 and 138 connected between the gate and power supply terminals and between the gate and ground terminals of the stage MOS transistors 131 and 132 are connected in parallel between the pair of constant current sources 137 and 138, respectively. A pair of P and N channel shift MOS transistors 135 and 136 which function as a level shifter by connecting their gates to a pair of constant voltage sources 139 and 140, respectively, and a diode connected P and N channel MOS transistor in series from a power supply terminal and a ground terminal A pair of constant voltage sources 139 and 140 that supply a high voltage that is lower by a threshold of two stages.

なお、この従来例の複数の差動ＡＢ級増幅回路１のバイアス部を共通化する場合、差動ＡＢ級増幅回路の定電流源１１６，１２６，１３７および１３８をそれぞれ電流ミラー回路構成とし、それらのミラー出力である定電流ＭＯＳトランジスタおよびミラー入力ＭＯＳトランジスタを分離し、共通バイアス回路２は、差動ＡＢ級増幅回路１の定電流ＭＯＳトランジスタのゲートにバイアス電圧を供給するミラー入力ＭＯＳトランジスタと、定電圧源１３９，１４０とを備える構成になる。   When the bias portions of the plurality of differential class AB amplifier circuits 1 of the conventional example are shared, the constant current sources 116, 126, 137 and 138 of the differential class AB amplifier circuit are configured as current mirror circuits, respectively. The common bias circuit 2 separates the constant current MOS transistor and the mirror input MOS transistor that are mirror outputs of the mirror output, and the mirror input MOS transistor supplies a bias voltage to the gate of the constant current MOS transistor of the differential class AB amplifier circuit 1; The constant voltage sources 139 and 140 are provided.

この従来の差動ＡＢ級増幅回路において、差動増幅器１７の２つの定電流源１１６，１２６は、通常、それぞれＮ，ＰチャネルＭＯＳトランジスタの電流ミラー回路で構成される。定電流源１２６のＰチャネルＭＯＳトランジスタが正常動作する入力電圧範囲は、ＶＳＳ以上、ＶＤＤ−［Ｖｇｓ＋Ｖｄｓ（ｓａｔ）］以下である。ＶＤＤ−［Ｖｇｓ＋Ｖｄｓ（ｓａｔ）］以上の入力電圧範囲では、定電流源１１６を構成するＮチャネルＭＯＳトランジスタの電流ミラー回路が正常動作しており、それぞれ電流ミラー回路を構成する２組のＰチャネルＭＯＳトランジスタ１１４，１１７と１１５，１１８とにより、バイアス電流Ｉ１による差動電流のミラー電流Ｉ４，Ｉ５が折り返され、Ｎチャネル負荷ＭＯＳトランジスタ１２４，１２５に供給される。そのため、差動増幅部分が、接地端子から電源端子までの入力電圧範囲で動作し、Ｒａｉｌ−ｔｏ−ｒａｉｌ入力可能となり、差動ＡＢ級増幅回路がＲａｉｌ−ｔｏ−ｒａｉｌ入出力可能となる。   In this conventional differential class AB amplifier circuit, the two constant current sources 116 and 126 of the differential amplifier 17 are usually constituted by current mirror circuits of N and P channel MOS transistors, respectively. The input voltage range in which the P-channel MOS transistor of the constant current source 126 normally operates is VSS or more and VDD− [Vgs + Vds (sat)] or less. In the input voltage range of VDD− [Vgs + Vds (sat)] or more, the current mirror circuit of the N-channel MOS transistor constituting the constant current source 116 is operating normally, and two sets of P-channel MOSs each constituting the current mirror circuit. Transistors 114, 117 and 115, 118 fold mirror currents I4, I5, which are differential currents based on bias current I1, and supply them to N-channel load MOS transistors 124, 125. Therefore, the differential amplification section operates in the input voltage range from the ground terminal to the power supply terminal, and Rail-to-rail input is possible, and the differential class AB amplifier circuit is capable of Rail-to-rail input / output.

図７は、上述の差動ＡＢ級増幅回路の従来例２を示す回路図である（特許文献２参照）。この従来の差動ＡＢ級増幅回路１は、Ｎ受け差動増幅器１１，Ｐ受け差動増幅器１２およびＡＢ級出力回路１３を備え、Ｒａｉｌ−Ｔｏ−Ｒａｉｌ入出力が可能である。   FIG. 7 is a circuit diagram showing Conventional Example 2 of the above-described differential class AB amplifier circuit (see Patent Document 2). This conventional differential class AB amplifier circuit 1 includes an N receiving differential amplifier 11, a P receiving differential amplifier 12, and a class AB output circuit 13, and is capable of Rail-To-Rail input / output.

Ｎ受け差動増幅器１１は、反転入力端子Ｖｉｎ（−）および正転入力端子Ｖｉｎ（＋）をゲートに接続した１対のＮチャネル差動ＭＯＳトランジスタ１１２，１１３と、これら１対のＮチャネル差動ＭＯＳトランジスタ１１２，１１３に接続された電流ミラー型の１対のＰチャネル負荷ＭＯＳトランジスタ１１４，１１５と、バイアス電圧ＢＮをゲートに入力し１対のＮチャネル差動ＭＯＳトランジスタ１１２，１１３のソースに定電流Ｉ１を供給するＮチャネル定電流源ＭＯＳトランジスタ１１１とを備え、Ｎチャネル差動ＭＯＳトランジスタ１１３のドレインからＡＢ級出力回路のＰチャネル出力段ＭＯＳトランジスタ１３１のゲートへ出力する。   The N receiving differential amplifier 11 includes a pair of N channel differential MOS transistors 112 and 113 in which the inverting input terminal Vin (−) and the normal input terminal Vin (+) are connected to the gate, and the pair of N channel differentials. A pair of current mirror type P-channel load MOS transistors 114 and 115 connected to the dynamic MOS transistors 112 and 113, and a bias voltage BN are inputted to the gates to be sources of the pair of N-channel differential MOS transistors 112 and 113. An N-channel constant current source MOS transistor 111 for supplying a constant current I1 is provided, and output from the drain of the N-channel differential MOS transistor 113 to the gate of the P-channel output stage MOS transistor 131 of the class AB output circuit.

Ｐ受け差動増幅器１２は、反転入力端子Ｖｉｎ（−）および正転入力端子Ｖｉｎ（＋）をゲートに接続した１対のＰチャネル差動ＭＯＳトランジスタ１２２，１２３と、これら１対のＰチャネル差動ＭＯＳトランジスタ１２２，１２３に接続された電流ミラー型の１対のＮチャネル負荷ＭＯＳトランジスタ１２４，１２５と、バイアス電圧ＢＰをゲートに入力し１対のＰチャネル差動ＭＯＳトランジスタ１２２，１２３のソースに定電流Ｉ２を供給するＮチャネル定電流源ＭＯＳトランジスタ１２１とを備え、Ｐチャネル差動ＭＯＳトランジスタ１２３のドレインからＡＢ級出力回路１３のＮチャネル出力段ＭＯＳトランジスタ１３２のゲートへ出力する。   The P receiving differential amplifier 12 includes a pair of P channel differential MOS transistors 122 and 123 having a inverting input terminal Vin (−) and a normal input terminal Vin (+) connected to the gate, and a difference between the pair of P channel differential MOS transistors 122 and 123. A pair of N-channel load MOS transistors 124 and 125 of a current mirror type connected to the dynamic MOS transistors 122 and 123, and a bias voltage BP are input to the gates and the sources of the pair of P-channel differential MOS transistors 122 and 123 are input. An N-channel constant current source MOS transistor 121 for supplying a constant current I2 is provided, and output from the drain of the P-channel differential MOS transistor 123 to the gate of the N-channel output stage MOS transistor 132 of the class AB output circuit 13.

ＡＢ級出力回路１３は、出力端子−電源端子間および出力端子−接地端子間にそれぞれ接続され１対のＮおよびＰ受け差動増幅器１１，１２の出力線をそれぞれゲートに接続した１対のＰおよびＮチャネル出力段ＭＯＳトランジスタ１３１，１３２と、Ｎ受け差動増幅器１１の出力線−電源端子間およびＰ受け差動増幅器１２の出力線−接地端子間にそれぞれ接続され１対のＰおよびＮチャネル定電流バイアス電圧ＢＰ，ＢＮをそれぞれゲートに入力した１対のＰおよびＮチャネル定電流ＭＯＳトランジスタ１３３，１３４と、１対のＮおよびＰ受け差動増幅器１１，１２の出力線間に並列接続されレベルシフタとして機能する１対のＰおよびＮチャネルシフトＭＯＳトランジスタ１３５，１３６とを備える。   The class AB output circuit 13 is connected between the output terminal and the power supply terminal and between the output terminal and the ground terminal, respectively, and is connected to the gates of the output lines of the pair of N and P receiving differential amplifiers 11 and 12, respectively. N-channel output stage MOS transistors 131 and 132 and a pair of P and N channels connected between the output line of the N receiving differential amplifier 11 and the power supply terminal and between the output line of the P receiving differential amplifier 12 and the ground terminal, respectively. A pair of P and N channel constant current MOS transistors 133 and 134 having constant current bias voltages BP and BN input to their gates are connected in parallel between the output lines of a pair of N and P receiving differential amplifiers 11 and 12, respectively. A pair of P and N channel shift MOS transistors 135 and 136 functioning as level shifters are provided.

また、このＡＢ級出力回路１３は、１対のＰおよびＮチャネルシフトＭＯＳトランジスタ１３５，１３６のゲート−電源端子間およびゲート−接地端子間にそれぞれ接続されバイアス電圧ＢＰ，ＢＮをゲートに入力した１対のＰおよびＮチャネルミラー出力ＭＯＳトランジスタ１４１，１４２と、１対のＰおよびＮチャネルシフトＭＯＳトランジスタ１３５，１３６のゲート−電源端子間およびゲート−接地端子間にそれぞれ接続され１対のＰおよびＮチャネル出力段ＭＯＳトランジスタ１３１，１３２のミラー電流Ｉ７，Ｉ６を流す１対のＰおよびＮチャネルミラー出力ＭＯＳトランジスタ１４３，１４４とを備える。   The class AB output circuit 13 is connected to the gates of the pair of P and N channel shift MOS transistors 135 and 136 between the power source terminal and between the gate and the ground terminal, respectively, and inputs bias voltages BP and BN to the gate. A pair of P and N channel mirror output MOS transistors 141 and 142 and a pair of P and N channels connected between the gate and power supply terminals and between the gate and ground terminals of P and N channel shift MOS transistors 135 and 136, respectively. It includes a pair of P and N channel mirror output MOS transistors 143 and 144 through which mirror currents I7 and I6 of channel output stage MOS transistors 131 and 132 flow.

更に、この従来例のＡＢ級出力回路では、１対のＰおよびＮチャネル出力段ＭＯＳトランジスタ１３１，１３２のゲートおよび出力端子Ｖｏｕｔの間に位相補償用の１対のミラー容量１４５，１４６が追加接続され、差動ＡＢ級増幅回路が良好な周波数特性を有している。   Further, in this conventional class AB output circuit, a pair of mirror capacitors 145 and 146 for phase compensation are additionally connected between the gates of the pair of P and N channel output stage MOS transistors 131 and 132 and the output terminal Vout. Thus, the differential class AB amplifier circuit has good frequency characteristics.

なお、この従来例の複数の差動ＡＢ級増幅回路へバイアス電圧ＢＰ，ＢＮを供給する共通バイアス回路２は、電流ミラー回路のＰおよびＮチャネルミラー入力ＭＯＳトランジスタを備える構成になる。   Note that the common bias circuit 2 for supplying the bias voltages BP and BN to the plurality of differential class AB amplifier circuits of the conventional example includes a P and N channel mirror input MOS transistors of a current mirror circuit.

この従来の差動ＡＢ級増幅回路１において、１対のＮおよびＰチャネルミラー出力ＭＯＳトランジスタ１４２，１４１は、バイアス電圧ＢＮ，ＢＰをゲートに入力して電流ミラー制御され、１対のＰおよびＮチャネルミラー出力ＭＯＳトランジスタ１４３，１４４は、１対のＰおよびＮチャネル出力段ＭＯＳトランジスタ１３１，１３２と同じく電流ミラー制御され、それらの接続点が１対のＰおよびＮチャネルシフトＭＯＳトランジスタ１３５，１３６のゲートに接続されている。従って、１対のＰおよびＮチャネルシフトＭＯＳトランジスタ１３５，１３６のゲート電圧が、従来例１と異なり定電圧でなく、差動ＡＢ級増幅回路１の出力状態によりダイナミックに変動し、１対のＰおよびＮチャネル出力段ＭＯＳトランジスタ１３１，１３２の一方のみを電流ミラー動作状態とし、アイドリング電流を小さい値に制御し、クロスオーバ歪を低減している。   In this conventional differential class AB amplifier circuit 1, a pair of N and P channel mirror output MOS transistors 142 and 141 are current mirror controlled by inputting bias voltages BN and BP to their gates, and a pair of P and N Channel mirror output MOS transistors 143 and 144 are current mirror controlled in the same manner as a pair of P and N channel output stage MOS transistors 131 and 132, and their connection points are a pair of P and N channel shift MOS transistors 135 and 136. Connected to the gate. Therefore, the gate voltage of the pair of P and N channel shift MOS transistors 135 and 136 is not a constant voltage unlike the conventional example 1, but dynamically varies depending on the output state of the differential class AB amplifier circuit 1, and the pair of P and N channel shift MOS transistors 135 and 136 Only one of the N-channel output stage MOS transistors 131 and 132 is set in a current mirror operation state, the idling current is controlled to a small value, and the crossover distortion is reduced.

また、上述した、図６，図７の複数の差動ＡＢ級増幅回路および共通バイアス回路において、図示されていないが、テストモード時に、定電流源または定電流ＭＯＳトランジスタおよびシフトＭＯＳトランジスタがオフするように制御され、且つ、テストモード時にオンする１対のＰおよびＮチャネルテストＭＯＳトランジスタが、ＡＢ級出力回路の１対のＰおよびＮチャネル出力段ＭＯＳトランジスタのゲート−電源端子間およびゲート−接地端子間にそれぞれ追加接続され、テストモード時に、１対のＰおよびＮチャネル出力段ＭＯＳトランジスタをそれぞれオフさせ、これら出力ＭＯＳトランジスタのアイドリング電流をゼロにしている。これにより、テストモード時に、全ての回路電流パスがオフされ、データ線駆動回路としてのチップリーク電流を測定することができる。   In the above-described differential class AB amplifier circuit and common bias circuit of FIGS. 6 and 7, although not shown, the constant current source or the constant current MOS transistor and the shift MOS transistor are turned off in the test mode. And a pair of P and N channel test MOS transistors controlled in the test mode and turned on in the test mode are connected between the gate and power supply terminals of the pair of P and N channel output stage MOS transistors of the class AB output circuit and between the gate and the ground. The terminals are additionally connected to each other, and in the test mode, the pair of P and N channel output stage MOS transistors are respectively turned off, and the idling current of these output MOS transistors is made zero. Thereby, in the test mode, all circuit current paths are turned off, and the chip leakage current as the data line driving circuit can be measured.

特開昭６１−３５００４号公報（第１図）JP-A-61-35004 (FIG. 1) 特開２００１−１７７３５２号公報（図４）Japanese Patent Laying-Open No. 2001-177352 (FIG. 4)

しかしながら、上述した従来の駆動回路における差動ＡＢ級増幅回路には、いくつかの問題がある。   However, the differential class AB amplifier circuit in the conventional drive circuit described above has several problems.

図６に示した従来例１の差動ＡＢ級増幅回路の問題点は、Ｒａｉｌ−ｔｏ−ｒａｉｌ入出力可能であるが、ＶＤＤ−［Ｖｇｓ＋Ｖｄｓ（ｓａｔ）］以上の入力電圧範囲では、バイアス電流Ｉ１による差動電流のミラー電流Ｉ４，Ｉ５の折り返しが必要となっているため、折返しミラー回路により素子数も増加するだけでなく、折返しミラー電流Ｉ４，Ｉ５の分、消費電流が増大し、高集積化および低消費電力化の妨げにもなることである。   The problem of the differential class AB amplifier circuit of the conventional example 1 shown in FIG. 6 is that Rail-to-rail input / output is possible, but in the input voltage range of VDD− [Vgs + Vds (sat)] or more, the bias current I1 Since the mirror currents I4 and I5 of the differential current due to the current need to be folded, not only the number of elements is increased by the folding mirror circuit, but also the current consumption increases by the folding mirror currents I4 and I5, and high integration is achieved. This also hinders the reduction of power consumption and power consumption.

また、図７に示した従来例２の差動ＡＢ級増幅回路の問題点は、この差動ＡＢ級増幅回路をデータ線駆動回路の出力回路として複数個用いた場合、１対のＰおよびＮチャネルシフトＭＯＳトランジスタ１３５，１３６のゲート電圧は、差動ＡＢ級増幅回路１の出力状態により変動するため、複数の差動ＡＢ級増幅回路１の１対のＰおよびＮチャネルＭＯＳトランジスタ１３５，１３６のゲートを共通接続できず、差動ＡＢ級増幅回路ごとに電流ミラー回路を構成する４つのミラー出力ＭＯＳトランジスタ１４１〜１４４が必要となり、高集積化の妨げとなることである。   Further, the problem with the differential class AB amplifier circuit of the conventional example 2 shown in FIG. 7 is that when a plurality of differential class AB amplifier circuits are used as output circuits of the data line driving circuit, a pair of P and N Since the gate voltages of the channel shift MOS transistors 135 and 136 vary depending on the output state of the differential class AB amplifier circuit 1, a pair of P and N channel MOS transistors 135 and 136 of the plurality of differential class AB amplifier circuits 1 are used. The gates cannot be connected in common, and four mirror output MOS transistors 141 to 144 constituting a current mirror circuit are required for each differential class AB amplifier circuit, which hinders high integration.

また、差動ＡＢ級増幅回路の出力段ＭＯＳトランジスタのアイドリング電流を電流ミラーで制御しているため、図７に示した４つのミラー出力ＭＯＳトランジスタ１４１〜１４４による電流ミラー電流Ｉ６，Ｉ７の分、消費電流が増大することである。   Since the idling current of the output stage MOS transistor of the differential class AB amplifier circuit is controlled by the current mirror, the current mirror currents I6 and I7 by the four mirror output MOS transistors 141 to 144 shown in FIG. The current consumption increases.

また、これら差動ＡＢ級増幅回路１をデータ線駆動回路７の出力回路７２として用いた場合、テストモード時に、全ての回路電流パスをオフさせるために、１対のＰおよびＮチャネル出力段ＭＯＳトランジスタのゲート−電源端子間およびゲート−接地端子間に１対のＰおよびＮチャネルテストＭＯＳトランジスタを追加し、１対のＰおよびＮチャネル出力段ＭＯＳトランジスタのゲート電圧を電源レベルおよび接地レベルに固定している。表示装置の駆動回路には、差動ＡＢ級増幅回路１が１チップにつき３００〜５００個使われ、ＰまたはＮチャネルテストＭＯＳトランジスタが６００〜１０００個必要となり、高集積化の妨げとなることである。   When these differential class AB amplifier circuit 1 is used as output circuit 72 of data line drive circuit 7, a pair of P and N channel output stage MOSs are used to turn off all circuit current paths in the test mode. A pair of P and N channel test MOS transistors are added between the gate and power supply terminals of the transistor and between the gate and ground terminals, and the gate voltages of the pair of P and N channel output stage MOS transistors are fixed at the power supply level and the ground level. doing. In the display circuit drive circuit, 300 to 500 differential class AB amplifier circuits 1 are used per chip, and 600 to 1000 P or N channel test MOS transistors are required, which hinders high integration. is there.

従って、本発明の目的は、複数の差動ＡＢ級増幅回路を備える駆動回路および処理回路を更に高集積化および低消費電力化することにある。   Accordingly, an object of the present invention is to further increase the integration and power consumption of a drive circuit and a processing circuit including a plurality of differential class AB amplifier circuits.

そのため、本発明は、それぞれボルテージフォロア接続され複数のアナログ信号を並列入力し複数のデータ線を並列駆動する複数の差動ＡＢ級増幅回路と、これら複数の差動ＡＢ級増幅回路へ共通にバイアス電圧を供給する共通バイアス回路とを備える駆動回路において、
前記差動ＡＢ級増幅回路が、１対の正転および反転入力端子をそれぞれ入力接続し１対のＮおよびＰチャネル差動バイアス電圧によりそれぞれ定電流制御された１対のＮおよびＰ受け差動増幅器と、
出力端子−電源端子間および出力端子−接地端子間にそれぞれ接続され前記１対のＮおよびＰ受け差動増幅器の出力線をそれぞれゲートに接続した１対のＰおよびＮチャネル出力段ＭＯＳトランジスタと、
前記Ｎ受け差動増幅器の出力線−電源端子間および前記Ｐ受け差動増幅器の出力線−接地端子間にそれぞれ接続され１対のＰおよびＮチャネル定電流バイアス電圧をそれぞれゲートに入力した１対のＰおよびＮチャネル定電流ＭＯＳトランジスタと、
前記１対のＮおよびＰ受け差動増幅器の出力線間に並列接続され１対のＰおよびＮチャネルシフトバイアス電圧をそれぞれゲートに入力しレベルシフタとして機能する１対のＰおよびＮチャネルシフトＭＯＳトランジスタとを備え、
前記共通バイアス回路が、テストモード時に、前記１対のＮおよびＰチャネル差動バイアス電圧を接地レベルおよび電源レベルへそれぞれ切り換え前記１対のＰおよびＮチャネル定電流バイアス電圧を接地レベルおよび電源レベルへそれぞれ切り換え前記１対のＰおよびＮチャネルシフトバイアス電圧を電源レベルおよび接地レベルへそれぞれ切り換えている。 Therefore, the present invention provides a common bias to a plurality of differential class AB amplifier circuits that are voltage follower connected to each other and input a plurality of analog signals in parallel and drive a plurality of data lines in parallel. In a drive circuit comprising a common bias circuit for supplying a voltage,
The differential class AB amplifier circuit is connected to a pair of normal and inverting input terminals, respectively, and a pair of N and P receiving differentials each controlled at a constant current by a pair of N and P channel differential bias voltages. An amplifier;
A pair of P and N channel output stage MOS transistors connected between the output terminal and the power supply terminal and between the output terminal and the ground terminal, respectively, and connected to the gates of the output lines of the pair of N and P receiving differential amplifiers;
A pair of P and N channel constant current bias voltages connected to each other between the output line and the power supply terminal of the N receiving differential amplifier and between the output line and the ground terminal of the P receiving differential amplifier, respectively. P and N channel constant current MOS transistors,
A pair of P and N channel shift MOS transistors which are connected in parallel between the output lines of the pair of N and P receiving differential amplifiers and which respectively input a pair of P and N channel shift bias voltages to the gates and function as level shifters; With
In the test mode, the common bias circuit switches the pair of N and P channel differential bias voltages to a ground level and a power supply level, respectively, and the pair of P and N channel constant current bias voltages to a ground level and a power supply level. Switching Each of the pair of P and N channel shift bias voltages is switched to a power supply level and a ground level.

また、本発明は、複数のアナログ信号を並列入力し並列増幅する複数の差動ＡＢ級増幅回路と、これら複数の差動ＡＢ級増幅回路へ共通にバイアス電圧を供給する共通バイアス回路とを備える処理回路において、
前記差動ＡＢ級増幅回路が、１対の正転および反転入力端子をそれぞれ入力接続し１対のＮおよびＰチャネル差動バイアス電圧によりそれぞれ定電流制御された１対のＮおよびＰ受け差動増幅器と、
出力端子−電源端子間および出力端子−接地端子間にそれぞれ接続され前記１対のＮおよびＰ受け差動増幅器の出力線をそれぞれゲートに接続した１対のＰおよびＮチャネル出力段ＭＯＳトランジスタと、
前記Ｎ受け差動増幅器の出力線−電源端子間および前記Ｐ受け差動増幅器の出力線−接地端子間にそれぞれ接続され１対のＰおよびＮチャネル定電流バイアス電圧をそれぞれゲートに入力した１対のＰおよびＮチャネル定電流ＭＯＳトランジスタと、
前記１対のＮおよびＰ受け差動増幅器の出力線間に並列接続され１対のＰおよびＮチャネルシフトバイアス電圧をそれぞれゲートに入力しレベルシフタとして機能する１対のＰおよびＮチャネルシフトＭＯＳトランジスタとを備え、
前記共通バイアス回路が、テストモード時に、前記１対のＮおよびＰチャネル差動バイアス電圧を接地レベルおよび電源レベルへそれぞれ切り換え出力し前記１対のＰおよびＮチャネル定電流バイアス電圧を接地レベルおよび電源レベルへそれぞれ切り換え出力し前記１対のＰおよびＮチャネルシフトバイアス電圧を電源レベルおよび接地レベルへそれぞれ切り換え出力している。 The present invention also includes a plurality of differential class AB amplifier circuits that input a plurality of analog signals in parallel and amplify them in parallel, and a common bias circuit that supplies a bias voltage to the plurality of differential class AB amplifier circuits in common. In the processing circuit,
The differential class AB amplifier circuit is connected to a pair of normal and inverting input terminals, respectively, and a pair of N and P receiving differentials each controlled at a constant current by a pair of N and P channel differential bias voltages. An amplifier;
A pair of P and N channel output stage MOS transistors connected between the output terminal and the power supply terminal and between the output terminal and the ground terminal, respectively, and connected to the gates of the output lines of the pair of N and P receiving differential amplifiers;
A pair of P and N channel constant current bias voltages connected to each other between the output line and the power supply terminal of the N receiving differential amplifier and between the output line and the ground terminal of the P receiving differential amplifier, respectively. P and N channel constant current MOS transistors,
A pair of P and N channel shift MOS transistors which are connected in parallel between the output lines of the pair of N and P receiving differential amplifiers and which respectively input a pair of P and N channel shift bias voltages to the gates and function as level shifters; With
In the test mode, the common bias circuit switches and outputs the pair of N and P channel differential bias voltages to the ground level and the power supply level, respectively, and outputs the pair of P and N channel constant current bias voltages to the ground level and the power supply. The pair of P and N channel shift bias voltages are switched and output to the power supply level and the ground level, respectively.

また、前記共通バイアス回路が、定電流源と、
テストモード時にオフするスイッチと、
これら定電流源およびスイッチを直列接続した直列回路の回路電流に対応してチャネル別に複数のミラー電流を複数の出力端からそれぞれ出力する１対のＰおよびＮチャネル電流ミラー回路と、
これら１対のＰおよびＮチャネル電流ミラー回路の入力端−電源端子間および入力端−接地端子間にチャネル別に接続されテストモード時にそれぞれオンする１対のスイッチと、
前記Ｎチャネル電流ミラー回路の１出力端−電源端子間および前記Ｐチャネル電流ミラー回路の１出力端−接地端子間にチャネル別に接続されゲートおよびドレインをそれぞれ共通接続した１対のＰおよびＮチャネルＭＯＳトランジスタと、
テストモード時にそれぞれオフする１対のスイッチと、
これら１対のＰおよびＮチャネルＭＯＳトランジスタおよび１対のスイッチをチャネル別に直列接続した１対の直列回路の一端にチャネル別に一端を接続して前記１対のＰおよびＮチャネル定電流バイアス電圧の出力ノードとしチャネル別に他端を接地端子および電源端子に接続しテストモード時にそれぞれオンする１対のスイッチとを備えている。 The common bias circuit includes a constant current source,
A switch that turns off in test mode;
A pair of P and N channel current mirror circuits for outputting a plurality of mirror currents from a plurality of output terminals for each channel corresponding to the circuit current of a series circuit in which the constant current source and the switch are connected in series;
A pair of switches connected to each channel between the input terminal and the power supply terminal and between the input terminal and the ground terminal of the pair of P and N channel current mirror circuits and turned on in the test mode;
A pair of P and N channel MOSs connected to each channel between the one output terminal of the N channel current mirror circuit and the power supply terminal and between the one output terminal of the P channel current mirror circuit and the ground terminal, with the gate and drain connected in common. A transistor,
A pair of switches each turned off in test mode;
One pair of P and N channel MOS transistors and one pair of switches are connected in series to each channel, and one end of each pair is connected to one end of each series circuit to output the pair of P and N channel constant current bias voltages. Each node is provided with a pair of switches that are turned on in the test mode by connecting the other end to a ground terminal and a power terminal for each channel.

また、ゲートおよびドレインをそれぞれ共通接続した２つのＰチャネルＭＯＳトランジスタおよび２つのＮチャネルＭＯＳトランジスタを前記Ｎチャネル電流ミラー回路の１出力端−電源端子間および前記Ｐチャネル電流ミラー回路の１出力端−接地端子間にチャネル別に直列接続した１対のＰおよびＮチャネル直列回路と、
これら１対のＰおよびＮチャネル直列回路の一端にチャネル別に一端を接続して前記１対のＰおよびＮチャネルシフトバイアス電圧の出力ノードとしチャネル別に他端を電源端子および接地端子に接続しテストモード時にそれぞれオンする１対のスイッチとを備えている。 Further, two P-channel MOS transistors and two N-channel MOS transistors each having a gate and a drain connected in common are connected between one output terminal of the N-channel current mirror circuit and a power supply terminal and one output terminal of the P-channel current mirror circuit. A pair of P and N channel series circuits connected in series by channel between ground terminals;
One end of each pair of P and N channel series circuits is connected to each channel to serve as an output node for the pair of P and N channel shift bias voltages, and the other end is connected to the power supply terminal and the ground terminal for each channel. And a pair of switches that each turn on at times.

また、前記Ｎチャネル電流ミラー回路の１出力端−電源端子間および前記Ｐチャネル電流ミラー回路の１出力端−接地端子間にチャネル別に接続されゲートおよびドレインをそれぞれ共通接続した１対のＰおよびＮチャネルＭＯＳトランジスタと、
これら１対のＰおよびＮチャネルＭＯＳトランジスタのドレインにチャネル別に一端を接続して前記１対のＰおよびＮチャネル差動バイアス電圧の出力ノードとしチャネル別に他端を電源端子および接地端子に接続しテストモード時にそれぞれオンする１対のスイッチとを備えている。 In addition, a pair of P and N is connected to each channel between one output end of the N-channel current mirror circuit and the power supply terminal and between one output end of the P-channel current mirror circuit and the ground terminal, and the gate and drain are commonly connected. A channel MOS transistor;
One end of each pair of P and N channel MOS transistors is connected to the drain for each channel to output the pair of P and N channel differential bias voltage, and the other end is connected to the power supply terminal and the ground terminal for each channel. And a pair of switches that are turned on in each mode.

また、前記１対のＰおよびＮチャネル電流ミラー回路の入力端が、前記１対のＰおよびＮチャネル差動バイアス電圧の出力ノードであってもよい。   The input terminals of the pair of P and N channel current mirror circuits may be output nodes of the pair of P and N channel differential bias voltages.

また、本発明の差動ＡＢ級増幅回路は、１対の正転および反転入力端子をそれぞれ入力接続し１対のＮおよびＰチャネル差動バイアス電圧によりそれぞれ定電流制御された１対のＮおよびＰ受け差動増幅器と、
前記Ｎ受け差動増幅器の出力線−電源端子間および前記Ｐ受け差動増幅器の出力線−接地端子間にそれぞれ接続され１対のＰおよびＮチャネル定電流バイアス電圧をそれぞれゲートに入力した１対のＰおよびＮチャネル定電流ＭＯＳトランジスタと、
前記１対のＮおよびＰ受け差動増幅器の出力線間に並列接続され１対のＰおよびＮチャネルシフトバイアス電圧にゲートを接続しレベルシフタとして機能する１対のＰおよびＮチャネルシフトＭＯＳトランジスタと、
出力端子−電源端子間および出力端子−接地端子間にそれぞれ接続され前記１対のＮおよびＰ受け差動増幅器の出力線をそれぞれゲートに接続した１対のＰおよびＮチャネル出力段ＭＯＳトランジスタとを備えている。 In addition, the differential class AB amplifier circuit of the present invention has a pair of normal and inverted input terminals connected to each other, and a pair of N and P-channel differential bias voltages that are constant current controlled by a pair of N and P channel differential bias voltages, respectively. A P receiving differential amplifier;
A pair of P and N channel constant current bias voltages connected to each other between the output line and the power supply terminal of the N receiving differential amplifier and between the output line and the ground terminal of the P receiving differential amplifier, respectively. P and N channel constant current MOS transistors,
A pair of P and N channel shift MOS transistors connected in parallel between the output lines of the pair of N and P receiving differential amplifiers and connected to a pair of P and N channel shift bias voltages with their gates functioning as level shifters;
A pair of P and N channel output stage MOS transistors connected between the output terminal and the power supply terminal and between the output terminal and the ground terminal and respectively connected to the gates of the output lines of the pair of N and P receiving differential amplifiers. I have.

本発明の駆動回路および処理回路において、複数備えられるＲａｉｌ−ｔｏ−ｒａｉｌ入出力可能な差動ＡＢ級増幅回路の素子数および回路電流パスが減少し、回路面積および消費電力が削減され、駆動回路および処理回路が高集積化および低消費電力化される。   In the drive circuit and the processing circuit of the present invention, the number of elements and circuit current paths of a plurality of Rail-to-rail input / output differential class AB amplifier circuits that are provided are reduced, the circuit area and power consumption are reduced, and the drive circuit In addition, the processing circuit is highly integrated and has low power consumption.

すなわち、本発明の駆動回路における差動ＡＢ級増幅回路において、例えば、図６の従来例１の差動ＡＢ級増幅回路の差動増幅部で必要であった折返しミラー回路が本発明では不要となり、また、図７の従来例２の差動ＡＢ級増幅回路のＡＢ級出力回路で１対のＰおよびＮチャネルシフトＭＯＳトランジスタのゲート電圧を制御するため必要であった４つのミラー出力ＭＯＳトランジスタが本発明では不要となり、差動ＡＢ級増幅回路の素子数が減少し、図６，図７示した電流Ｉ４〜Ｉ７の電流パスを有せず、回路面積および消費電力が削減され、駆動回路が高集積化および低消費電力化される。   That is, in the differential class AB amplifier circuit in the drive circuit of the present invention, for example, the folding mirror circuit required in the differential amplifier section of the differential class AB amplifier circuit of Conventional Example 1 in FIG. In addition, the four mirror output MOS transistors necessary for controlling the gate voltages of the pair of P and N channel shift MOS transistors in the class AB output circuit of the differential class AB amplifier circuit of the conventional example 2 of FIG. This is unnecessary in the present invention, the number of elements of the differential class AB amplifier circuit is reduced, the current paths of the currents I4 to I7 shown in FIGS. 6 and 7 are not provided, the circuit area and power consumption are reduced, and the drive circuit is reduced. High integration and low power consumption are achieved.

また、従来、差動ＡＢ級増幅回路をデータ線駆動回路の出力回路として用いた場合、テストモード時に、全ての回路電流パスをオフさせるために、１対のＰおよびＮチャネル出力段ＭＯＳトランジスタのゲート−電源端子間およびゲート−接地端子間に１対のＰおよびＮチャネルテストＭＯＳトランジスタを追加し１対のＰおよびＮチャネル出力段ＭＯＳトランジスタのゲート電圧を電源レベルおよび接地レベルに固定していたが、本発明における差動ＡＢ級増幅回路では、従来の１対のＰおよびＮチャネルテストＭＯＳトランジスタの追加が不要となり、差動ＡＢ級増幅回路の素子数が２個減少し、回路面積が削減される。   Conventionally, when a differential class AB amplifier circuit is used as an output circuit of a data line driving circuit, a pair of P and N channel output stage MOS transistors are used to turn off all circuit current paths in the test mode. A pair of P and N channel test MOS transistors were added between the gate and power supply terminals and between the gate and ground terminals, and the gate voltages of the pair of P and N channel output stage MOS transistors were fixed at the power supply level and the ground level. However, in the differential class AB amplifier circuit of the present invention, the addition of the conventional pair of P and N channel test MOS transistors becomes unnecessary, the number of elements of the differential class AB amplifier circuit is reduced by two, and the circuit area is reduced. Is done.

特に、表示装置の駆動回路のデータ線駆動回路などにおいて、差動ＡＢ級増幅回路が、１チップにつき、３００〜５００個使われ、表示装置の駆動回路の回路面積および消費電力が著しく削減されるなどの効果がある。   Particularly, in the data line driving circuit of the driving circuit of the display device, 300 to 500 differential class AB amplifier circuits are used per chip, and the circuit area and power consumption of the driving circuit of the display device are significantly reduced. There are effects such as.

本発明の駆動回路は、差動ＡＢ級増幅回路のＲａｉｌ−ｔｏ−ｒａｉｌ入出力特性を損なわずに、回路面積および消費電力を更に削減し、駆動回路を高集積化および低消費電力化した。   The drive circuit of the present invention further reduces the circuit area and power consumption without impairing the Rail-to-rail input / output characteristics of the differential class AB amplifier circuit, and the drive circuit is highly integrated and has low power consumption.

本発明の駆動回路は、図５に示した、従来の表示装置の駆動回路のデータ線駆動回路７における出力回路７２と同じく、複数の差動ＡＢ級増幅回路１および共通バイアス回路２を備え、差動ＡＢ級増幅回路１は、Ｒａｉｌ−ｔｏ−ｒａｉｌ入出力可能であり、差動ＡＢ級増幅回路１および共通バイアス回路２の内部構成がそれぞれ異なる。これら差動ＡＢ級増幅回路１および共通バイアス回路２の構成および動作について、次の実施例で、図面を参照して説明する。   Like the output circuit 72 in the data line drive circuit 7 of the drive circuit of the conventional display device shown in FIG. 5, the drive circuit of the present invention includes a plurality of differential class AB amplifier circuits 1 and a common bias circuit 2. The differential class AB amplifier circuit 1 is capable of rail-to-rail input / output, and the differential class AB amplifier circuit 1 and the common bias circuit 2 have different internal configurations. The configurations and operations of the differential class AB amplifier circuit 1 and the common bias circuit 2 will be described in the following embodiment with reference to the drawings.

図１は、本発明の駆動回路の実施例１における差動ＡＢ級増幅回路１および共通バイアス回路２の構成例を示す回路図であり、図１（Ａ）は、差動ＡＢ級増幅回路１を示し、図１（Ｂ）は、共通バイアス回路２を示す。   FIG. 1 is a circuit diagram showing a configuration example of a differential class AB amplifier circuit 1 and a common bias circuit 2 in Embodiment 1 of the drive circuit of the present invention. FIG. 1 (A) shows a differential class AB amplifier circuit 1. FIG. 1B shows the common bias circuit 2.

図１（Ａ）を参照すると、本実施例の駆動回路における差動ＡＢ級増幅回路１は、Ｎ受け差動増幅器１１，Ｐ受け差動増幅器１２およびＡＢ級出力回路１３を備える。   Referring to FIG. 1A, the differential class AB amplifier circuit 1 in the drive circuit of this embodiment includes an N receiving differential amplifier 11, a P receiving differential amplifier 12, and a class AB output circuit 13.

Ｎ受け差動増幅器１１は、反転入力端子Ｖｉｎ（−）および正転入力端子Ｖｉｎ（＋）をゲートに接続した１対のＮチャネル差動ＭＯＳトランジスタ１１２，１１３と、これら１対のＮチャネル差動ＭＯＳトランジスタ１１２，１１３に接続された電流ミラー型の１対のＰチャネル負荷ＭＯＳトランジスタ１１４，１１５と、Ｎチャネル差動バイアス電圧ＢＮ１をゲートに入力し１対のＮチャネル差動ＭＯＳトランジスタ１１２，１１３のソースに定電流Ｉ１を供給するＮチャネル定電流源ＭＯＳトランジスタ１１１とを備え、Ｎチャネル差動ＭＯＳトランジスタ１１３のドレインからＡＢ級出力回路のＰチャネル出力段ＭＯＳトランジスタ１３１のゲートへ出力する。   The N receiving differential amplifier 11 includes a pair of N channel differential MOS transistors 112 and 113 in which the inverting input terminal Vin (−) and the normal input terminal Vin (+) are connected to the gate, and the pair of N channel differentials. A pair of current mirror type P-channel load MOS transistors 114, 115 connected to the dynamic MOS transistors 112, 113, and a pair of N-channel differential MOS transistors 112, 115 having an N-channel differential bias voltage BN1 input to the gate. An N-channel constant current source MOS transistor 111 that supplies a constant current I1 to the source of 113 is output from the drain of the N-channel differential MOS transistor 113 to the gate of the P-channel output stage MOS transistor 131 of the class AB output circuit.

Ｐ受け差動増幅器１２は、反転入力端子Ｖｉｎ（−）および正転入力端子Ｖｉｎ（＋）をゲートに接続した１対のＰチャネル差動ＭＯＳトランジスタ１２２，１２３と、これら１対のＰチャネル差動ＭＯＳトランジスタ１２２，１２３に接続された電流ミラー型の１対のＮチャネル負荷ＭＯＳトランジスタ１２４，１２５と、Ｐチャネル差動バイアス電圧ＢＰ１をゲートに入力し１対のＰチャネル差動ＭＯＳトランジスタ１２２，１２３のソースに定電流Ｉ２を供給するＮチャネル定電流源ＭＯＳトランジスタ１２１とを備え、Ｐチャネル差動ＭＯＳトランジスタ１２３のドレインからＡＢ級出力回路１３のＮチャネル出力段ＭＯＳトランジスタ１３２のゲートへ出力する。   The P receiving differential amplifier 12 includes a pair of P channel differential MOS transistors 122 and 123 having a inverting input terminal Vin (−) and a normal input terminal Vin (+) connected to the gate, and a difference between the pair of P channel differential MOS transistors 122 and 123. A pair of current mirror type N-channel load MOS transistors 124, 125 connected to the dynamic MOS transistors 122, 123, and a pair of P-channel differential MOS transistors 122, N-channel constant current source MOS transistor 121 that supplies constant current I2 to the source of 123, and outputs from the drain of P-channel differential MOS transistor 123 to the gate of N-channel output stage MOS transistor 132 of class AB output circuit 13 .

ＡＢ級出力回路１３は、出力端子−電源端子間および出力端子−接地端子間にそれぞれ接続され１対のＮおよびＰ受け差動増幅器１１，１２の出力線をそれぞれゲートに接続した１対のＰおよびＮチャネル出力段ＭＯＳトランジスタ１３１，１３２と、Ｎ受け差動増幅器１１の出力線−電源端子間およびＰ受け差動増幅器１２の出力線−接地端子間にそれぞれ接続され１対のＰおよびＮチャネル定電流バイアス電圧ＢＰ２，ＢＮ２をそれぞれゲートに入力した１対のＰおよびＮチャネル定電流ＭＯＳトランジスタ１３３，１３４と、１対のＮおよびＰ受け差動増幅器１１，１２の出力線間に並列接続され１対のＰおよびＮチャネル定電流バイアス電圧ＢＰ３，ＢＮ３をそれぞれゲートに入力しレベルシフタとして機能する１対のＰおよびＮチャネルシフトＭＯＳトランジスタ１３５，１３６とを備える。   The class AB output circuit 13 is connected between the output terminal and the power supply terminal and between the output terminal and the ground terminal, respectively, and is connected to the gates of the output lines of the pair of N and P receiving differential amplifiers 11 and 12, respectively. N-channel output stage MOS transistors 131 and 132 and a pair of P and N channels connected between the output line of the N receiving differential amplifier 11 and the power supply terminal and between the output line of the P receiving differential amplifier 12 and the ground terminal, respectively. A pair of P and N channel constant current MOS transistors 133 and 134 having constant current bias voltages BP2 and BN2 input to their gates, respectively, and a pair of N and P receiving differential amplifiers 11 and 12 are connected in parallel. A pair of P and N channel constant current bias voltages BP3 and BN3 are respectively input to the gates, and a pair of P and N channels functioning as level shifters. And a Nerushifuto MOS transistor 135 and 136.

また、本実施例におけるＡＢ級出力回路１３では、従来と同じく、１対のＰおよびＮチャネル出力段ＭＯＳトランジスタ１３１，１３２のゲートおよび出力端子Ｖｏｕｔの間に位相補償用の１対のミラー容量１４５，１４６が追加接続され、差動ＡＢ級増幅回路１が良好な周波数特性を有している。   In the class AB output circuit 13 in this embodiment, a pair of mirror capacitors 145 for phase compensation is provided between the gates of the pair of P and N channel output stage MOS transistors 131 and 132 and the output terminal Vout, as in the conventional case. , 146 are additionally connected, and the differential class AB amplifier circuit 1 has good frequency characteristics.

図１（Ｂ）を参照すると、本発明の駆動回路における共通バイアス回路２は、定電流源２１と、テストモード時にオフするスイッチ２２と、これら定電流源２１およびスイッチ２２を直列接続した直列回路の回路電流に対応してチャネル別に複数のミラー電流を複数の出力端からそれぞれ出力する１対のＰおよびＮチャネル電流ミラー回路２３，２４と、これら１対のＰおよびＮチャネル電流ミラー回路２３，２４の入力端−電源端子間および入力端−接地端子間にチャネル別に接続されテストモード時にそれぞれオンする１対のスイッチ２５，２６とを備える。   Referring to FIG. 1B, the common bias circuit 2 in the drive circuit of the present invention includes a constant current source 21, a switch 22 that is turned off in the test mode, and a series circuit in which the constant current source 21 and the switch 22 are connected in series. A pair of P and N channel current mirror circuits 23 and 24 for outputting a plurality of mirror currents for each channel from a plurality of output terminals, respectively, and a pair of P and N channel current mirror circuits 23, And a pair of switches 25 and 26 that are connected to each other between the input terminal and the power supply terminal and between the input terminal and the ground terminal and are turned on in the test mode.

また、共通バイアス回路２は、Ｎチャネル電流ミラー回路２４の１出力端−電源端子間およびＰチャネル電流ミラー回路２３の１出力端−接地端子間にチャネル別に接続されゲートおよびドレインをそれぞれ共通接続した１対のＰおよびＮチャネルＭＯＳトランジスタ２７，２８と、これら１対のＰおよびＮチャネルＭＯＳトランジスタ２７，２８のドレインにチャネル別に一端を接続して１対のＰおよびＮチャネル差動バイアス電圧ＢＰ１，ＢＮ１の出力ノードとしチャネル別に他端を電源端子および接地端子に接続しテストモード時にそれぞれオンする１対のスイッチ２９，３０とを備え、テストモード時に、１対のＮおよびＰチャネル差動バイアス電圧ＢＰ１，ＢＮ１を接地レベルおよび電源レベルへそれぞれ切り換え出力する。   The common bias circuit 2 is connected to each channel between one output terminal of the N-channel current mirror circuit 24 and the power supply terminal and between one output terminal of the P-channel current mirror circuit 23 and the ground terminal, and has a gate and a drain connected in common. One pair of P and N channel MOS transistors 27 and 28, and one pair of P and N channel MOS transistors 27 and 28 connected to the drains of the drains of the pair of P and N channel MOS transistors 27 and 28 for each channel A pair of switches 29 and 30 which are connected to the power supply terminal and the ground terminal as the output node of BN1 and connected to the power supply terminal and the ground terminal and are turned on in the test mode, respectively, and a pair of N and P channel differential bias voltages in the test mode BP1 and BN1 are switched and output to the ground level and the power supply level, respectively.

また、共通バイアス回路２は、Ｎチャネル電流ミラー回路２４の１出力端−電源端子間およびＰチャネル電流ミラー回路２３の１出力端−接地端子間にチャネル別に接続されゲートおよびドレインをそれぞれ共通接続した１対のＰおよびＮチャネルＭＯＳトランジスタ３１，３２と、テストモード時にそれぞれオフする１対のスイッチ３３，３４と、これら１対のＰおよびＮチャネルＭＯＳトランジスタ３１，３２および１対のスイッチ３３，３４をチャネル別に直列接続した１対の直列回路の一端にチャネル別に一端を接続して１対のＰおよびＮチャネル定電流バイアス電圧ＢＰ２，ＢＮ２の出力ノードとしチャネル別に他端を接地端子および電源端子に接続しテストモード時にそれぞれオンする１対のスイッチ３５，３６とを備え、テストモード時に、１対のＰおよびＮチャネル定電流バイアス電圧ＢＰ２，ＢＮ２を接地レベルおよび電源レベルへそれぞれ切り換え出力する。   The common bias circuit 2 is connected to each channel between one output terminal of the N-channel current mirror circuit 24 and the power supply terminal and between one output terminal of the P-channel current mirror circuit 23 and the ground terminal, and has a gate and a drain connected in common. A pair of P and N channel MOS transistors 31 and 32, a pair of switches 33 and 34 which are turned off in the test mode, respectively, and the pair of P and N channel MOS transistors 31 and 32 and the pair of switches 33 and 34 One end of each pair of series circuits connected in series for each channel is connected to one end of each channel to serve as an output node for a pair of P and N channel constant current bias voltages BP2 and BN2, and the other end of each channel is connected to a ground terminal and a power supply terminal. A pair of switches 35 and 36 that are connected and turned on in the test mode, respectively. The mode, each switching output a pair of P and N-channel constant current bias voltage BP2, the BN2 to ground level and the power level.

また、共通バイアス回路２は、ゲートおよびドレインをそれぞれ共通接続した２つのＰチャネルＭＯＳトランジスタ３７，３８および２つのＮチャネルＭＯＳトランジスタ３９，４０をＮチャネル電流ミラー回路２４の１出力端−電源端子間およびＰチャネル電流ミラー回路２３の１出力端−接地端子間にチャネル別に直列接続した１対のＰおよびＮチャネル直列回路と、これら１対のＰおよびＮチャネル直列回路の一端にチャネル別に一端を接続して１対のＰおよびＮチャネルシフトバイアス電圧ＢＰ３，ＢＮ３の出力ノードとしチャネル別に他端を電源端子および接地端子に接続しテストモード時にそれぞれオンする１対のスイッチ４１，４２とを備え、テストモード時に、１対のＰおよびＮチャネルシフトバイアス電圧ＢＰ３，ＢＮ３を電源レベルおよび接地レベルへそれぞれ切り換え出力する。   Further, the common bias circuit 2 includes two P-channel MOS transistors 37 and 38 and two N-channel MOS transistors 39 and 40 each having a gate and a drain connected in common, between one output terminal of the N-channel current mirror circuit 24 and the power supply terminal. And a pair of P and N channel series circuits connected in series between one output terminal and the ground terminal of the P channel current mirror circuit 23, and one end of each pair of P and N channel series circuits connected to one end of the pair of P and N channel series circuits. And a pair of switches 41 and 42 which serve as output nodes of a pair of P and N channel shift bias voltages BP3 and BN3 and which are connected to the power supply terminal and the ground terminal for each channel and turned on in the test mode, respectively. During mode, a pair of P and N channel shift bias voltages BP3, BN3 Respectively switching outputs to the power supply level and the ground level.

なお、共通バイアス回路２における各スイッチは、ＰまたはＮチャネルＭＯＳトランジスタから構成される。   Each switch in the common bias circuit 2 is composed of a P or N channel MOS transistor.

次に、本実施例の駆動回路における差動ＡＢ級増幅回路１の動作について説明する。本実施例の差動ＡＢ級増幅回路１におけるＮ受け差動増幅器１１は、差動段の定電流源をＮチャネル定電流ＭＯＳトランジスタ１１１で構成しているため、電源端子ＶＤＤから［Ｖｇｓ１＋Ｖｄｓ１（ｓａｔ）］までの入力信号を増幅し、ＡＢ級出力回路１３へ伝達できる。ここで、Ｖｄｓ１（ｓａｔ）は、定電流源を構成するＮチャネル定電流ＭＯＳトランジスタ１１１の飽和領域動作時のソース−ドレイン間電圧であり、Ｖｇｓ１は、Ｎチャネル差動ＭＯＳトランジスタ１１２もしくは１１３にバイアス電流Ｉ２が流れた時の、Ｎチャネル差動ＭＯＳトランジスタ１１２もしくは１１３のソース−ゲート間電圧である。   Next, the operation of the differential class AB amplifier circuit 1 in the drive circuit of this embodiment will be described. The N receiving differential amplifier 11 in the differential class AB amplifier circuit 1 of the present embodiment is configured such that the constant current source of the differential stage is composed of the N channel constant current MOS transistor 111, and therefore [Vgs1 + Vds1 (sat) from the power supply terminal VDD. )] Can be amplified and transmitted to the class AB output circuit 13. Here, Vds1 (sat) is a source-drain voltage when the N-channel constant current MOS transistor 111 constituting the constant current source operates in the saturation region, and Vgs1 is biased to the N-channel differential MOS transistor 112 or 113. This is the source-gate voltage of the N-channel differential MOS transistor 112 or 113 when the current I2 flows.

また、Ｐ受け差動増幅器１２は、差動段の定電流源をＰチャネル定電流ＭＯＳトランジスタ１２１で構成しているため、ＶＤＤ−［Ｖｇｓ２＋Ｖｄｓ２（ｓａｔ）］から接地電位ＶＳＳまでの入力信号を増幅し、ＡＢ級出力回路１３へ伝達できる。ここで、Ｖｄｓ２（ｓａｔ）は、定電流源を構成するＰチャネル定電流ＭＯＳトランジスタ１２１の飽和領域動作時のソース−ドレイン間電圧であり、Ｖｇｓ２は、Ｐチャネル差動ＭＯＳトランジスタ１２２もしくは１２３にバイアス電流Ｉ３が流れた時の、Ｐチャネル差動ＭＯＳトランジスタ１２２もしくは１２３のソース−ゲート間電圧である。   Further, the P receiving differential amplifier 12 amplifies an input signal from VDD− [Vgs2 + Vds2 (sat)] to the ground potential VSS because the constant current source of the differential stage is composed of the P channel constant current MOS transistor 121. And can be transmitted to the class AB output circuit 13. Here, Vds2 (sat) is a source-drain voltage when the P channel constant current MOS transistor 121 constituting the constant current source operates in the saturation region, and Vgs2 is biased to the P channel differential MOS transistor 122 or 123. This is the source-gate voltage of the P-channel differential MOS transistor 122 or 123 when the current I3 flows.

図２は、本実施例の差動ＡＢ級増幅回路１の動作モードを説明するための説明図であり、差動ＡＢ級増幅回路１の入力信号Ｖｉｎ（＋），Ｖｉｎ（−）の入力電圧範囲を縦軸方向に示す。   FIG. 2 is an explanatory diagram for explaining the operation mode of the differential class AB amplifier circuit 1 of the present embodiment, and the input voltages Vin (+) and Vin (−) of the differential class AB amplifier circuit 1. The range is shown in the vertical axis direction.

本実施例の差動ＡＢ級増幅回路１は、入力信号Ｖｉｎ（＋），Ｖｉｎ（−）の入力電圧範囲に対応して３つの動作モード（１）〜（３）を有する。   The differential class AB amplifier circuit 1 of this embodiment has three operation modes (1) to (3) corresponding to the input voltage ranges of the input signals Vin (+) and Vin (−).

動作モード（１）は、入力信号Ｖｉｎ（＋，Ｖｉｎ（−）がＶＤＤ−［Ｖｇｓ２＋Ｖｄｓ２（ｓａｔ）］以上、ＶＤＤ以下の入力電圧範囲に対応し、この入力電圧範囲では、Ｐ受け差動増幅器１２のＰチャネル定電流ＭＯＳトランジスタ１２１は許容入力電圧範囲外であるため正常動作が不可能となっている。しかし、このとき、Ｎ受け差動増幅器１１のＮチャネル定電流ＭＯＳトランジスタ１１１は許容入力範囲内であるため、Ｎ受け差動増幅器１１からＡＢ級出力回路１３へ信号伝達され、差動ＡＢ級増幅回路としても正常動作する。   The operation mode (1) corresponds to an input voltage range in which the input signal Vin (+, Vin (−) is greater than or equal to VDD− [Vgs2 + Vds2 (sat)] and less than or equal to VDD. In this input voltage range, the P receiving differential amplifier 12 Since the P-channel constant current MOS transistor 121 is out of the allowable input voltage range, it cannot operate normally, but at this time, the N-channel constant current MOS transistor 111 of the N receiving differential amplifier 11 is in the allowable input range. Therefore, a signal is transmitted from the N receiving differential amplifier 11 to the class AB output circuit 13, and the differential class AB amplifier circuit operates normally.

動作モード（２）は、入力信号Ｖｉｎ（＋），Ｖｉｎ（−）が［Ｖｇｓ１＋Ｖｄｓ１（ｓａｔ）］以上ＶＤＤ−［Ｖｇｓ２＋Ｖｄｓ２（ｓａｔ）］以下の入力電圧範囲に対応し、この入力電圧範囲では、ＮおよびＰ受け差動増幅器１１，１２のＮおよびＰチャネル定電流ＭＯＳトランジスタ１１１，１２１が共に許容入力電圧範囲内であるため、ＮおよびＰ受け差動増幅器１１，１２は共に正常動作し、ＮおよびＰ受け差動増幅器１１，１２からＡＢ級出力回路１３へ信号伝達され、差動ＡＢ級増幅回路として正常動作する。   The operation mode (2) corresponds to an input voltage range in which the input signals Vin (+) and Vin (−) are not less than [Vgs1 + Vds1 (sat)] and not more than VDD− [Vgs2 + Vds2 (sat)], and in this input voltage range, N Since both the N and P channel constant current MOS transistors 111 and 121 of the P receiving differential amplifiers 11 and 12 are within the allowable input voltage range, both the N and P receiving differential amplifiers 11 and 12 operate normally. A signal is transmitted from the P receiving differential amplifiers 11 and 12 to the class AB output circuit 13 and operates normally as a differential class AB amplifier circuit.

動作モード（３）は、入力信号Ｖｉｎ（＋），Ｖｉｎ（−）が接地電圧ＶＳＳ以上［Ｖｇｓ１＋Ｖｄｓ１（ｓａｔ）］以下の入力電圧範囲に対応し、この入力電圧範囲では、Ｎ受け差動増幅器１１のＮチャネル定電流ＭＯＳトランジスタ１１１は、許容入力電圧範囲外であるため正常動作が不可能となっている。しかし、このとき、Ｐ受け差動増幅器１２のＰチャネル定電流ＭＯＳトランジスタ１２１は許容入力電圧範囲内であるため、入力信号は差動増幅器１２によってＡＢ級出力回路１３へ伝達され、差動ＡＢ級増幅回路としても正常動作する。   The operation mode (3) corresponds to an input voltage range in which the input signals Vin (+) and Vin (−) are not less than the ground voltage VSS and not more than [Vgs1 + Vds1 (sat)], and in this input voltage range, the N receiving differential amplifier 11 Since the N-channel constant current MOS transistor 111 is outside the allowable input voltage range, it cannot operate normally. However, at this time, since the P channel constant current MOS transistor 121 of the P receiving differential amplifier 12 is within the allowable input voltage range, the input signal is transmitted to the class AB output circuit 13 by the differential amplifier 12, and the differential class AB It operates normally as an amplifier circuit.

このように、本実施例における差動ＡＢ級増幅回路は、ＮおよびＰ受け差動増幅器１１，１２のうち、どちらか一方が正常動作しない範囲でも、他方の差動増幅器が正常動作しているため、従来と同じく、電源端子ＶＤＤから接地端子ＶＳＳまで、どの入力電圧範囲でも、ＡＢ級出力回路１３へ信号伝達可能、つまり、Ｒａｉｌ−ｔｏ−ｒａｉｌ入力可能ということになる。   As described above, in the differential class AB amplifier circuit in this embodiment, the other differential amplifier operates normally even in a range where either one of the N and P receiving differential amplifiers 11 and 12 does not operate normally. Therefore, as in the prior art, signals can be transmitted to the AB class output circuit 13 in any input voltage range from the power supply terminal VDD to the ground terminal VSS, that is, Rail-to-rail input is possible.

また、例えば、図６の従来例１の差動ＡＢ級増幅回路の差動増幅部で必要であった折返しミラー回路を不要となり、図７の従来例２の差動ＡＢ級増幅回路のＡＢ級出力回路で１対のＰおよびＮチャネルシフトＭＯＳトランジスタのゲート電圧を制御するため必要であった４つのミラー出力ＭＯＳトランジスタが本発明では不要となり、差動ＡＢ級増幅回路の素子数が減少し、図６，図７に示した電流Ｉ４〜Ｉ７の電流パスを有せず、回路面積および消費電力が削減され、駆動回路が高集積化および低消費電力化される。   Further, for example, the folding mirror circuit required in the differential amplifier section of the differential class AB amplifier circuit of the conventional example 1 in FIG. 6 becomes unnecessary, and the class AB amplifier circuit of the differential class AB amplifier circuit of the conventional example 2 in FIG. The four mirror output MOS transistors required for controlling the gate voltages of the pair of P and N channel shift MOS transistors in the output circuit are unnecessary in the present invention, and the number of elements of the differential class AB amplifier circuit is reduced. The current paths of the currents I4 to I7 shown in FIGS. 6 and 7 are not provided, the circuit area and power consumption are reduced, and the drive circuit is highly integrated and has low power consumption.

特に、表示装置の駆動回路のデータ線駆動回路などにおいて、差動ＡＢ級増幅回路が、１チップにつき、３００〜５００個使われ、表示装置の駆動回路の回路面積および消費電力が著しく削減される。   Particularly, in the data line driving circuit of the driving circuit of the display device, 300 to 500 differential class AB amplifier circuits are used per chip, and the circuit area and power consumption of the driving circuit of the display device are significantly reduced. .

次に、本実施例の駆動回路における共通バイアス回路２の動作について説明する。本実施例の駆動回路における共通バイアス回路２は、テストモード時に、１対のＮおよびＰチャネル差動バイアス電圧、１対のＰおよびＮチャネル定電流バイアス電圧、および、１対のＰおよびＮチャネルシフトバイアス電圧を電源レベルまたは接地レベルへそれぞれ切り換えて出力するスイッチ制御を行う。   Next, the operation of the common bias circuit 2 in the drive circuit of this embodiment will be described. The common bias circuit 2 in the driving circuit of the present embodiment includes a pair of N and P channel differential bias voltages, a pair of P and N channel constant current bias voltages, and a pair of P and N channels in the test mode. Switch control is performed to switch and output the shift bias voltage to the power supply level or the ground level.

図３は、本実施例の駆動回路における共通バイアス回路２のスイッチ制御を説明するための説明図であり、通常時およびテストモード時のスイッチのオン／オフ状態を示す。なお、図１（Ｂ）の共通バイアス回路２における各スイッチのオン／オフ状態は、通常時のオン／オフ状態を示したものである。   FIG. 3 is an explanatory diagram for explaining the switch control of the common bias circuit 2 in the drive circuit of the present embodiment, and shows the on / off states of the switches in the normal time and the test mode. Note that the on / off state of each switch in the common bias circuit 2 of FIG. 1B indicates the normal on / off state.

図１（Ｂ）の共通バイアス回路２において、通常時には、３つのスイッチ２２，３３，３４がオンし、その他のスイッチがオフし、１対のＰおよびＮチャネル電流ミラー回路２３，２４は、定電流源２１に対応して複数のミラー電流を複数の出力端からそれぞれ出力する。   In the common bias circuit 2 of FIG. 1B, in normal times, the three switches 22, 33, 34 are turned on, the other switches are turned off, and the pair of P and N channel current mirror circuits 23, 24 are fixed. A plurality of mirror currents are output from a plurality of output terminals corresponding to the current source 21, respectively.

１対のＰおよびＮチャネルＭＯＳトランジスタ２７，２８は、１対のＰおよびＮ受け差動増幅器１２，１１の１対のＰおよびＮチャネル定電流ＭＯＳトランジスタ１２１，１１１と共に、チャネル別に電流ミラー回路を構成し、ダイオード接続ＭＯＳトランジスタの１段分の閾値電圧である１対のＰおよびＮチャネル差動バイアス電圧ＢＰ１，ＢＮ１を生成し、１対のＰおよびＮチャネル定電流ＭＯＳトランジスタ１２１，１１１へ出力し、これら１対のＰおよびＮチャネル定電流ＭＯＳトランジスタ１２１，１１１は、バイアス電流Ｉ２，Ｉ１を流す。   A pair of P and N channel MOS transistors 27 and 28, together with a pair of P and N channel constant current MOS transistors 121 and 111 of a pair of P and N receiving differential amplifiers 12 and 11, provide a current mirror circuit for each channel. A pair of P and N channel differential bias voltages BP1 and BN1 which are threshold voltages for one stage of the diode-connected MOS transistor are generated and output to the pair of P and N channel constant current MOS transistors 121 and 111. The pair of P and N channel constant current MOS transistors 121 and 111 pass bias currents I2 and I1.

１対のＰおよびＮチャネルＭＯＳトランジスタ３１，３２は、ＡＢ級出力回路１３の１対のＰおよびＮチャネル定電流ＭＯＳトランジスタ１３３，１３４と共に、チャネル別に電流ミラー回路を構成し、ダイオード接続ＭＯＳトランジスタの１段分の閾値電圧である１対のＰおよびＮチャネル定電流バイアス電圧ＢＰ２，ＢＮ２を生成し、１対のＰおよびＮチャネル定電流ＭＯＳトランジスタ１３３，１３４へ出力し、これら１対のＰおよびＮチャネル定電流ＭＯＳトランジスタ１３３，１３４は、バイアス電流Ｉ３を流す。   A pair of P and N channel MOS transistors 31 and 32 together with a pair of P and N channel constant current MOS transistors 133 and 134 of class AB output circuit 13 constitute a current mirror circuit for each channel, A pair of P and N channel constant current bias voltages BP2 and BN2 which are threshold voltages for one stage are generated and output to a pair of P and N channel constant current MOS transistors 133 and 134. N-channel constant current MOS transistors 133 and 134 pass a bias current I3.

１対の２つのＰチャネルＭＯＳトランジスタ３７，３８および２つのＮチャネルＭＯＳトランジスタ３９，４０は、ダイオード接続ＭＯＳトランジスタの直列２段分の閾値電圧である１対のＰおよびＮチャネルシフトバイアス電圧ＢＰ３，ＢＮ３を生成し、ＡＢ級出力回路１３の１対のＰおよびＮチャネルシフトＭＯＳトランジスタ１３５，１３６へ出力し、これら１対のＰおよびＮチャネルシフトＭＯＳトランジスタ１３５，１３６は、レベルシフタとして機能する。   A pair of two P-channel MOS transistors 37 and 38 and two N-channel MOS transistors 39 and 40 are a pair of P and N-channel shift bias voltages BP3, which are threshold voltages corresponding to two stages of diode-connected MOS transistors in series. BN3 is generated and output to a pair of P and N channel shift MOS transistors 135 and 136 of the class AB output circuit 13, and the pair of P and N channel shift MOS transistors 135 and 136 function as a level shifter.

また、図１（Ｂ）の共通バイアス回路２において、テストモード時には、３つのスイッチ２２，３３，３４がオフし、その他のスイッチがオンする。これにより、共通バイアス回路２の全ての回路電流パスが遮断され、且つ、１対のＮおよびＰチャネル差動バイアス電圧ＢＮ１，ＢＰ１が接地レベルおよび電源レベルへそれぞれ切り換え出力され、１対のＰおよびＮチャネル定電流バイアス電圧ＢＰ２，ＢＮ２が接地レベルおよび電源レベルへそれぞれ切り換え出力され、１対のＰおよびＮチャネルシフトバイアス電圧ＢＰ３，ＢＮ３が電源レベルおよび接地レベルへそれぞれ切り換え出力される。   In the common bias circuit 2 of FIG. 1B, in the test mode, the three switches 22, 33, and 34 are turned off, and the other switches are turned on. As a result, all circuit current paths of the common bias circuit 2 are cut off, and a pair of N and P channel differential bias voltages BN1 and BP1 are switched and output to the ground level and the power supply level, respectively. N-channel constant current bias voltages BP2 and BN2 are switched and output to the ground level and the power supply level, respectively, and a pair of P and N-channel shift bias voltages BP3 and BN3 are switched and output to the power supply level and the ground level, respectively.

このため、差動ＡＢ級増幅回路１において、１対のＰおよびＮ受け差動増幅器１２，１１の１対のＰおよびＮチャネル定電流ＭＯＳトランジスタ１２１，１１１がそれぞれオフする。また、ＡＢ級出力回路１３の１対のＰおよびＮチャネル定電流ＭＯＳトランジスタ１３３，１３４がそれぞれオンし、ＡＢ級出力回路１３の１対のＰおよびＮチャネルシフトＭＯＳトランジスタ１３５，１３６がそれぞれオフし、１対のＰおよびＮチャネル出力段ＭＯＳトランジスタ１３１，１３２のゲートが電源レベル，接地レベルに固定され、１対のＰおよびＮチャネル出力段ＭＯＳトランジスタ１３１，１３２は完全にオフし、差動ＡＢ級増幅回路１の全ての回路電流パスがオフする。   For this reason, in the differential class AB amplifier circuit 1, the pair of P and N channel constant current MOS transistors 121 and 111 of the pair of P and N receiving differential amplifiers 12 and 11 are turned off, respectively. Also, the pair of P and N channel constant current MOS transistors 133 and 134 of the class AB output circuit 13 are turned on, and the pair of P and N channel shift MOS transistors 135 and 136 of the class AB output circuit 13 are turned off. The gates of the pair of P and N channel output stage MOS transistors 131 and 132 are fixed at the power supply level and the ground level, and the pair of P and N channel output stage MOS transistors 131 and 132 are completely turned off. All the circuit current paths of the class amplifier circuit 1 are turned off.

このため、テストモードにおいて、駆動回路の回路電流がゼロとなり、駆動回路のリーク電流測定が可能となる。   For this reason, in the test mode, the circuit current of the drive circuit becomes zero, and the leakage current of the drive circuit can be measured.

従来、差動ＡＢ級増幅回路をデータ線駆動回路の出力回路として用いた場合、テストモード時に、全ての回路電流パスをオフさせるために、１対のＰおよびＮチャネル出力段ＭＯＳトランジスタ１３１，１３２のゲート−電源端子間およびゲート−接地端子間に１対のＰおよびＮチャネルテストＭＯＳトランジスタを追加し１対のＰおよびＮチャネル出力段ＭＯＳトランジスタ１３１，１３２のゲート電圧を電源レベルおよび接地レベルに固定していたが、本発明における差動ＡＢ級増幅回路では、１対のＰおよびＮチャネルシフトＭＯＳトランジスタ１３５，１３６がオフし１対のＰおよびＮチャネル定電流ＭＯＳトランジスタ１３３，１３４がオンして、１対のＰおよびＮチャネル出力段ＭＯＳトランジスタ１３１，１３２のゲート電圧を電源レベルおよび接地レベルに固定でき、従来の１対のＰおよびＮチャネルテストＭＯＳトランジスタの追加が不要となり、差動ＡＢ級増幅回路の素子数が２個減少し、回路面積が削減される。   Conventionally, when a differential class AB amplifier circuit is used as an output circuit of a data line driving circuit, a pair of P and N channel output stage MOS transistors 131 and 132 are turned off in order to turn off all circuit current paths in the test mode. A pair of P and N channel test MOS transistors are added between the gate and power supply terminals and between the gate and ground terminals, and the gate voltages of the pair of P and N channel output stage MOS transistors 131 and 132 are set to the power supply level and the ground level. In the differential class AB amplifier circuit of the present invention, the pair of P and N channel shift MOS transistors 135 and 136 are turned off, and the pair of P and N channel constant current MOS transistors 133 and 134 are turned on. The gate voltages of a pair of P and N channel output stage MOS transistors 131 and 132 Power levels and can be fixed to the ground level, additional P and N-channel testing MOS transistor of a conventional pair is not required, the number of elements of the differential class AB amplifier circuit is reduced two, which reduces the circuit area.

特に、表示装置の駆動回路などは、差動ＡＢ級増幅回路を１チップにつき３００〜５００個使用するため、表示装置の駆動回路の回路面積が著しく削減され、表示装置の駆動回路が高集積化される。   In particular, since the display device drive circuit uses 300 to 500 differential class AB amplifier circuits per chip, the circuit area of the display device drive circuit is significantly reduced, and the display device drive circuit is highly integrated. Is done.

なお、図１（Ｂ）に示した、本実施例における共通バイアス回路は、多数のスイッチを用いた制御回路であり、様々な変形例が考えられる。   Note that the common bias circuit in this embodiment shown in FIG. 1B is a control circuit using a large number of switches, and various modifications can be considered.

例えば、図４は、本発明の駆動回路における共通バイアス回路２の変形例を示す回路図である。本変形例の共通バイアス回路２は、図１（Ｂ）に示した共通バイアス回路と比較すると、１対のＰおよびＮチャネルＭＯＳトランジスタ２７，２８と、１対のスイッチ２９，３０と、１対のＰおよびＮチャネル電流ミラー回路のミラー出力ＭＯＳトランジスタ２個とが削除され、１対のＰおよびＮチャネル電流ミラー回路の入力端が、１対のＰおよびＮチャネル差動バイアス電圧ＢＰ１，ＢＮ１の出力ノードになっている。   For example, FIG. 4 is a circuit diagram showing a modification of the common bias circuit 2 in the drive circuit of the present invention. Compared with the common bias circuit shown in FIG. 1B, the common bias circuit 2 of the present modification has a pair of P and N channel MOS transistors 27 and 28, a pair of switches 29 and 30, and a pair. The two mirror output MOS transistors of the P and N channel current mirror circuits are deleted, and the input terminals of the pair of P and N channel current mirror circuits are connected to the pair of P and N channel differential bias voltages BP1 and BN1. It is an output node.

本変形例の共通バイアス回路２は、１対のＰおよびＮチャネル差動バイアス電圧ＢＰ１，ＢＮ１と、１対のＰおよびＮチャネル定電流バイアス電圧ＢＰ２，ＢＮ２および１対のＰおよびＮチャネルシフトバイアス電圧ＢＰ３，ＢＮ３とを順に設計する必要があるが、その回路面積は、図１（Ｂ）に示した共通バイアス回路より更に縮小される。   The common bias circuit 2 of this modification includes a pair of P and N channel differential bias voltages BP1 and BN1, a pair of P and N channel constant current bias voltages BP2 and BN2, and a pair of P and N channel shift biases. Although it is necessary to design the voltages BP3 and BN3 in order, the circuit area is further reduced as compared with the common bias circuit shown in FIG.

また、上述した実施例では、複数の差動ＡＢ級増幅回路および共通バイアス回路を備える駆動回路について説明した。しかし、この説明に限定されず、例えば、複数のアナログ信号を並列入力し並列増幅する複数の差動ＡＢ級増幅回路と、これら複数の差動ＡＢ級増幅回路へ共通にバイアス電圧を供給する共通バイアス回路とを備える処理回路においても、駆動回路と同様の効果が奏せられることは、明らかであろう。   In the above-described embodiments, the drive circuit including a plurality of differential class AB amplifier circuits and a common bias circuit has been described. However, the present invention is not limited to this description. For example, a plurality of differential class AB amplifier circuits that input and amplify a plurality of analog signals in parallel, and a common supply of a bias voltage to the plurality of differential class AB amplifier circuits. It will be apparent that the processing circuit including the bias circuit can achieve the same effect as the driving circuit.

また、上述した実施例では、複数の差動ＡＢ級増幅回路を備える駆動回路として説明した。しかし、この説明に限定されず、差動ＡＢ級増幅回路が、各対のＰおよびＮチャネルバイアス電圧により制御され、様々な回路に単体で使用できることも、明らかであろう。   In the above-described embodiments, the driving circuit having a plurality of differential class AB amplifier circuits has been described. However, without being limited to this description, it will be apparent that the differential class AB amplifier circuit is controlled by each pair of P and N channel bias voltages and can be used alone in a variety of circuits.

本発明の駆動回路の実施例１における差動ＡＢ級増幅回路１および共通バイアス回路２の構成例を示す回路図である。FIG. 3 is a circuit diagram showing a configuration example of a differential class AB amplifier circuit 1 and a common bias circuit 2 in Embodiment 1 of the drive circuit of the present invention. 図１（Ａ）の差動ＡＢ級増幅回路１の動作モードを説明するための説明図である。FIG. 2 is an explanatory diagram for explaining an operation mode of the differential class AB amplifier circuit 1 of FIG. 図１（Ｂ）の共通バイアス回路２のスイッチ制御を説明するための説明図である。FIG. 3 is an explanatory diagram for explaining switch control of the common bias circuit 2 of FIG. 図１（Ｂ）の共通バイアス回路２の変形例を示す回路図である。FIG. 6 is a circuit diagram illustrating a modification of the common bias circuit 2 of FIG. 従来の表示装置の駆動回路の構成例および表示パネルを示すブロック図である。It is a block diagram which shows the structural example of the drive circuit of the conventional display apparatus, and a display panel. 差動ＡＢ級増幅回路１の従来例１を示す回路図である。FIG. 6 is a circuit diagram showing a conventional example 1 of a differential class AB amplifier circuit 1; 差動ＡＢ級増幅回路１の従来例２を示す回路図である。It is a circuit diagram which shows the prior art example 2 of the differential class AB amplifier circuit 1.

符号の説明Explanation of symbols

１ 差動ＡＢ級増幅回路
２ 共通バイアス回路
４ 制御回路
５ 階調電源
６ 走査線駆動回路
７ データ線駆動回路
８ 表示パネル
１１ Ｎ受け差動増幅器
１２ Ｐ受け差動増幅器
１３ ＡＢ級出力回路
１７ 差動増幅器
２１，１１６，１２６，１３７〜１３８ 定電流源
２２，２５〜２６，２９〜３０，３３〜３６，４１〜４２ スイッチ
２３ Ｐチャネル電流ミラー回路
２４ Ｎチャネル電流ミラー回路
２７〜２８，３１〜３２，３７〜４０，１１１〜１３６，１４１〜１４４ ＭＯＳトランジスタ
７１ Ｄ／Ａ変換回路
７２ 出力回路
１３９〜１４０ 定電圧源
１４５〜１４６ ミラー容量
１７１ Ｎ受け差動増幅ミラー出力部
１７２ Ｐ受け差動増幅部 DESCRIPTION OF SYMBOLS 1 Differential class AB amplifier circuit 2 Common bias circuit 4 Control circuit 5 Gradation power supply 6 Scan line drive circuit 7 Data line drive circuit 8 Display panel 11 N receiving differential amplifier 12 P receiving differential amplifier 13 AB class output circuit 17 Difference Dynamic amplifier 21, 116, 126, 137 to 138 Constant current source 22, 25 to 26, 29 to 30, 33 to 36, 41 to 42 Switch 23 P channel current mirror circuit 24 N channel current mirror circuit 27 to 28, 31 to 32, 37 to 40, 111 to 136, 141 to 144 MOS transistor 71 D / A conversion circuit 72 Output circuit 139 to 140 Constant voltage source 145 to 146 Miller capacitance 171 N receiving differential amplification mirror output unit 172 P receiving differential amplification Part

Claims (11)

それぞれボルテージフォロア接続され複数のアナログ信号を並列入力し複数のデータ線を並列駆動する複数の差動ＡＢ級増幅回路と、これら複数の差動ＡＢ級増幅回路へ共通にバイアス電圧を供給する共通バイアス回路とを備える駆動回路において、
前記差動ＡＢ級増幅回路が、１対の正転および反転入力端子をそれぞれ入力接続し１対のＮおよびＰチャネル差動バイアス電圧によりそれぞれ定電流制御された１対のＮおよびＰ受け差動増幅器と、
出力端子−電源端子間および出力端子−接地端子間にそれぞれ接続され前記１対のＮおよびＰ受け差動増幅器の出力線をそれぞれゲートに接続した１対のＰおよびＮチャネル出力段ＭＯＳトランジスタと、
前記Ｎ受け差動増幅器の出力線−電源端子間および前記Ｐ受け差動増幅器の出力線−接地端子間にそれぞれ接続され１対のＰおよびＮチャネル定電流バイアス電圧をそれぞれゲートに入力した１対のＰおよびＮチャネル定電流ＭＯＳトランジスタと、
前記１対のＮおよびＰ受け差動増幅器の出力線間に並列接続され１対のＰおよびＮチャネルシフトバイアス電圧をそれぞれゲートに入力しレベルシフタとして機能する１対のＰおよびＮチャネルシフトＭＯＳトランジスタとを備え、
前記共通バイアス回路が、テストモード時に、前記１対のＮおよびＰチャネル差動バイアス電圧を接地レベルおよび電源レベルへそれぞれ切り換え出力し前記１対のＰおよびＮチャネル定電流バイアス電圧を接地レベルおよび電源レベルへそれぞれ切り換え出力し前記１対のＰおよびＮチャネルシフトバイアス電圧を電源レベルおよび接地レベルへそれぞれ切り換え出力することを特徴とする駆動回路。 A plurality of differential class AB amplifier circuits that are each connected to a voltage follower and input a plurality of analog signals in parallel and drive a plurality of data lines in parallel, and a common bias that supplies a common bias voltage to the plurality of differential class AB amplifier circuits In a drive circuit comprising a circuit,
The differential class AB amplifier circuit is connected to a pair of normal and inverting input terminals, respectively, and a pair of N and P receiving differentials each controlled at a constant current by a pair of N and P channel differential bias voltages. An amplifier;
A pair of P and N channel output stage MOS transistors connected between the output terminal and the power supply terminal and between the output terminal and the ground terminal, respectively, and connected to the gates of the output lines of the pair of N and P receiving differential amplifiers;
A pair of P and N channel constant current bias voltages connected to each other between the output line and the power supply terminal of the N receiving differential amplifier and between the output line and the ground terminal of the P receiving differential amplifier, respectively. P and N channel constant current MOS transistors,
A pair of P and N channel shift MOS transistors which are connected in parallel between the output lines of the pair of N and P receiving differential amplifiers and which respectively input a pair of P and N channel shift bias voltages to the gates and function as level shifters; With
In the test mode, the common bias circuit switches and outputs the pair of N and P channel differential bias voltages to the ground level and the power supply level, respectively, and outputs the pair of P and N channel constant current bias voltages to the ground level and the power supply. A drive circuit characterized by switching to a level and switching and outputting the pair of P and N channel shift bias voltages to a power supply level and a ground level, respectively. 前記共通バイアス回路が、定電流源と、
テストモード時にオフするスイッチと、
これら定電流源およびスイッチを直列接続した直列回路の回路電流に対応してチャネル別に複数のミラー電流を複数の出力端からそれぞれ出力する１対のＰおよびＮチャネル電流ミラー回路と、
これら１対のＰおよびＮチャネル電流ミラー回路の入力端−電源端子間および入力端−接地端子間にチャネル別に接続されテストモード時にそれぞれオンする１対のスイッチと、
前記Ｎチャネル電流ミラー回路の１出力端−電源端子間および前記Ｐチャネル電流ミラー回路の１出力端−接地端子間にチャネル別に接続されゲートおよびドレインをそれぞれ共通接続した１対のＰおよびＮチャネルＭＯＳトランジスタと、
テストモード時にそれぞれオフする１対のスイッチと、
これら１対のＰおよびＮチャネルＭＯＳトランジスタおよび１対のスイッチをチャネル別に直列接続した１対の直列回路の一端にチャネル別に一端を接続して前記１対のＰおよびＮチャネル定電流バイアス電圧の出力ノードとしチャネル別に他端を接地端子および電源端子に接続しテストモード時にそれぞれオンする１対のスイッチとを備える、請求項１記載の駆動回路。 The common bias circuit includes a constant current source;
A switch that turns off in test mode;
A pair of P and N channel current mirror circuits for outputting a plurality of mirror currents from a plurality of output terminals for each channel corresponding to the circuit current of a series circuit in which the constant current source and the switch are connected in series;
A pair of switches connected to each channel between the input terminal and the power supply terminal and between the input terminal and the ground terminal of the pair of P and N channel current mirror circuits and turned on in the test mode;
A pair of P and N channel MOSs connected to each channel between the one output terminal of the N channel current mirror circuit and the power supply terminal and between the one output terminal of the P channel current mirror circuit and the ground terminal, with the gate and drain connected in common. A transistor,
A pair of switches each turned off in test mode;
One pair of P and N channel MOS transistors and one pair of switches are connected in series to each channel, and one end of each pair is connected to one end of each series circuit to output the pair of P and N channel constant current bias voltages. The drive circuit according to claim 1, further comprising: a pair of switches that are connected to the ground terminal and the power supply terminal for each channel as a node and are turned on in the test mode. ゲートおよびドレインをそれぞれ共通接続した２つのＰチャネルＭＯＳトランジスタおよび２つのＮチャネルＭＯＳトランジスタを前記Ｎチャネル電流ミラー回路の１出力端−電源端子間および前記Ｐチャネル電流ミラー回路の１出力端−接地端子間にチャネル別に直列接続した１対のＰおよびＮチャネル直列回路と、
これら１対のＰおよびＮチャネル直列回路の一端にチャネル別に一端を接続して前記１対のＰおよびＮチャネルシフトバイアス電圧の出力ノードとしチャネル別に他端を電源端子および接地端子に接続しテストモード時にそれぞれオンする１対のスイッチとを備える、請求項２記載の駆動回路。 Two P-channel MOS transistors and two N-channel MOS transistors having gates and drains connected in common are connected between one output terminal of the N-channel current mirror circuit and the power supply terminal and one output terminal of the P-channel current mirror circuit-ground terminal. A pair of P and N channel series circuits connected in series between the channels,
One end of each pair of P and N channel series circuits is connected to each channel to serve as an output node for the pair of P and N channel shift bias voltages, and the other end is connected to the power supply terminal and the ground terminal for each channel. The drive circuit according to claim 2, further comprising a pair of switches that are sometimes turned on. 前記Ｎチャネル電流ミラー回路の１出力端−電源端子間および前記Ｐチャネル電流ミラー回路の１出力端−接地端子間にチャネル別に接続されゲートおよびドレインをそれぞれ共通接続した１対のＰおよびＮチャネルＭＯＳトランジスタと、
これら１対のＰおよびＮチャネルＭＯＳトランジスタのドレインにチャネル別に一端を接続して前記１対のＰおよびＮチャネル差動バイアス電圧の出力ノードとしチャネル別に他端を電源端子および接地端子に接続しテストモード時にそれぞれオンする１対のスイッチとを備える、請求項２または３記載の駆動回路。 A pair of P and N channel MOSs connected to each channel between the one output terminal of the N channel current mirror circuit and the power supply terminal and between the one output terminal of the P channel current mirror circuit and the ground terminal, with the gate and drain connected in common. A transistor,
One end of each pair of P and N channel MOS transistors is connected to the drain for each channel to output the pair of P and N channel differential bias voltage, and the other end is connected to the power supply terminal and the ground terminal for each channel. The drive circuit according to claim 2, further comprising a pair of switches that are turned on in each mode. 前記１対のＰおよびＮチャネル電流ミラー回路の入力端が、前記１対のＰおよびＮチャネル差動バイアス電圧の出力ノードである、請求項２または３記載の駆動回路。   4. The drive circuit according to claim 2, wherein an input terminal of the pair of P and N channel current mirror circuits is an output node of the pair of P and N channel differential bias voltages. 複数のアナログ信号を並列入力し並列増幅する複数の差動ＡＢ級増幅回路と、これら複数の差動ＡＢ級増幅回路へ共通にバイアス電圧を供給する共通バイアス回路とを備える処理回路において、
前記差動ＡＢ級増幅回路が、
１対の正転および反転入力端子をそれぞれ入力接続し１対のＮおよびＰチャネル差動バイアス電圧によりそれぞれ定電流制御された１対のＮおよびＰ受け差動増幅器と、
出力端子−電源端子間および出力端子−接地端子間にそれぞれ接続され前記１対のＮおよびＰ受け差動増幅器の出力線をそれぞれゲートに接続した１対のＰおよびＮチャネル出力段ＭＯＳトランジスタと、
前記Ｎ受け差動増幅器の出力線−電源端子間および前記Ｐ受け差動増幅器の出力線−接地端子間にそれぞれ接続され１対のＰおよびＮチャネル定電流バイアス電圧をそれぞれゲートに入力した１対のＰおよびＮチャネル定電流ＭＯＳトランジスタと、
前記１対のＮおよびＰ受け差動増幅器の出力線間に並列接続され１対のＰおよびＮチャネルシフトバイアス電圧をそれぞれゲートに入力しレベルシフタとして機能する１対のＰおよびＮチャネルシフトＭＯＳトランジスタとを備え、
前記共通バイアス回路が、テストモード時に、前記１対のＮおよびＰチャネル差動バイアス電圧を接地レベルおよび電源レベルへそれぞれ切り換え出力し前記１対のＰおよびＮチャネル定電流バイアス電圧を接地レベルおよび電源レベルへそれぞれ切り換え出力し前記１対のＰおよびＮチャネルシフトバイアス電圧を電源レベルおよび接地レベルへそれぞれ切り換え出力することを特徴とする処理回路。 In a processing circuit comprising a plurality of differential class AB amplifier circuits that input a plurality of analog signals in parallel and amplify the analog signals in common, and a common bias circuit that supplies a common bias voltage to the plurality of differential class AB amplifier circuits,
The differential class AB amplifier circuit comprises:
A pair of N and P receiving differential amplifiers, each of which is connected to a pair of normal and inverting input terminals and is controlled in constant current by a pair of N and P channel differential bias voltages;
A pair of P and N channel output stage MOS transistors connected between the output terminal and the power supply terminal and between the output terminal and the ground terminal, respectively, and connected to the gates of the output lines of the pair of N and P receiving differential amplifiers;
A pair of P and N channel constant current bias voltages connected to each other between the output line and the power supply terminal of the N receiving differential amplifier and between the output line and the ground terminal of the P receiving differential amplifier, respectively. P and N channel constant current MOS transistors,
A pair of P and N channel shift MOS transistors which are connected in parallel between the output lines of the pair of N and P receiving differential amplifiers and which respectively input a pair of P and N channel shift bias voltages to the gates and function as level shifters; With
In the test mode, the common bias circuit switches and outputs the pair of N and P channel differential bias voltages to the ground level and the power supply level, respectively, and outputs the pair of P and N channel constant current bias voltages to the ground level and the power supply. A processing circuit for switching to a level and switching and outputting the pair of P and N channel shift bias voltages to a power supply level and a ground level, respectively. 前記共通バイアス回路が、定電流源と、
テストモード時にオフするスイッチと、
これら定電流源およびスイッチを直列接続した直列回路の回路電流に対応してチャネル別に複数のミラー電流を複数の出力端からそれぞれ出力する１対のＰおよびＮチャネル電流ミラー回路と、
これら１対のＰおよびＮチャネル電流ミラー回路の入力端−電源端子間および入力端−接地端子間にチャネル別に接続されテストモード時にそれぞれオンする１対のスイッチと、
前記Ｎチャネル電流ミラー回路の１出力端−電源端子間および前記Ｐチャネル電流ミラー回路の１出力端−接地端子間にチャネル別に接続されゲートおよびドレインをそれぞれ共通接続した１対のＰおよびＮチャネルＭＯＳトランジスタと、
テストモード時にそれぞれオフする１対のスイッチと、
これら１対のＰおよびＮチャネルＭＯＳトランジスタおよび１対のスイッチをチャネル別に直列接続した１対の直列回路の一端にチャネル別に一端を接続して前記１対のＰおよびＮチャネル定電流バイアス電圧の出力ノードとしチャネル別に他端を接地端子および電源端子に接続しテストモード時にそれぞれオンする１対のスイッチとを備える、請求項６記載の処理回路。 The common bias circuit includes a constant current source;
A switch that turns off in test mode;
A pair of P and N channel current mirror circuits for outputting a plurality of mirror currents for each channel from a plurality of output terminals corresponding to the circuit current of a series circuit in which the constant current source and the switch are connected in series;
A pair of switches connected to each channel between the input terminal and the power supply terminal and between the input terminal and the ground terminal of the pair of P and N channel current mirror circuits and turned on in the test mode;
A pair of P and N channel MOSs connected to each channel between the one output terminal of the N channel current mirror circuit and the power supply terminal and between the one output terminal of the P channel current mirror circuit and the ground terminal and having a gate and a drain connected in common, respectively. A transistor,
A pair of switches each turned off in test mode;
One pair of P and N channel MOS transistors and one pair of switches are connected in series to each channel and one end of each pair is connected to one end of each series circuit to output the pair of P and N channel constant current bias voltages. The processing circuit according to claim 6, further comprising: a pair of switches that are connected to the ground terminal and the power supply terminal for each channel as a node and are turned on in the test mode. ゲートおよびドレインをそれぞれ共通接続した２つのＰチャネルＭＯＳトランジスタおよび２つのＮチャネルＭＯＳトランジスタを前記Ｎチャネル電流ミラー回路の１出力端−電源端子間および前記Ｐチャネル電流ミラー回路の１出力端−接地端子間にチャネル別に直列接続した１対のＰおよびＮチャネル直列回路と、
これら１対のＰおよびＮチャネル直列回路の一端にチャネル別に一端を接続して前記１対のＰおよびＮチャネルシフトバイアス電圧の出力ノードとしチャネル別に他端を電源端子および接地端子に接続しテストモード時にそれぞれオンする１対のスイッチとを備える、請求項７記載の処理回路。 Two P-channel MOS transistors and two N-channel MOS transistors having gates and drains connected in common are connected between one output terminal of the N-channel current mirror circuit and the power supply terminal and one output terminal of the P-channel current mirror circuit-ground terminal. A pair of P and N channel series circuits connected in series between the channels,
One end of each pair of P and N channel series circuits is connected to each channel to serve as an output node for the pair of P and N channel shift bias voltages, and the other end is connected to the power supply terminal and the ground terminal for each channel. The processing circuit of claim 7, comprising a pair of switches that are each turned on at times. 前記Ｎチャネル電流ミラー回路の１出力端−電源端子間および前記Ｐチャネル電流ミラー回路の１出力端−接地端子間にチャネル別に接続されたゲートおよびドレインをそれぞれ共通接続し１対のＰおよびＮチャネルＭＯＳトランジスタと、
これら１対のＰおよびＮチャネルＭＯＳトランジスタのドレインにチャネル別に一端を接続して前記１対のＰおよびＮチャネル差動バイアス電圧の出力ノードとしチャネル別に他端を電源端子および接地端子に接続しテストモード時にそれぞれオンする１対のスイッチとを備える、請求項７または８記載の処理回路。 A pair of P and N channels are connected in common with each gate and drain connected to each channel between one output terminal of the N channel current mirror circuit and the power supply terminal and between one output terminal of the P channel current mirror circuit and the ground terminal. A MOS transistor;
One end of each pair of P and N channel MOS transistors is connected to the drain for each channel to output the pair of P and N channel differential bias voltage, and the other end is connected to the power supply terminal and the ground terminal for each channel. The processing circuit according to claim 7, further comprising a pair of switches that are turned on in each mode. 前記１対のＰおよびＮチャネル電流ミラー回路の入力端が、前記１対のＰおよびＮチャネル差動バイアス電圧の出力ノードである、請求項７または８記載の処理回路。   9. The processing circuit according to claim 7, wherein an input terminal of the pair of P and N channel current mirror circuits is an output node of the pair of P and N channel differential bias voltage. １対の正転および反転入力端子をそれぞれ入力接続し１対のＮおよびＰチャネル差動バイアス電圧によりそれぞれ定電流制御された１対のＮおよびＰ受け差動増幅器と、
前記Ｎ受け差動増幅器の出力線−電源端子間および前記Ｐ受け差動増幅器の出力線−接地端子間にそれぞれ接続され１対のＰおよびＮチャネル定電流バイアス電圧をそれぞれゲートに入力した１対のＰおよびＮチャネル定電流ＭＯＳトランジスタと、
前記１対のＮおよびＰ受け差動増幅器の出力線間に並列接続され１対のＰおよびＮチャネルシフトバイアス電圧にゲートを接続しレベルシフタとして機能する１対のＰおよびＮチャネルシフトＭＯＳトランジスタと、
出力端子−電源端子間および出力端子−接地端子間にそれぞれ接続され前記１対のＮおよびＰ受け差動増幅器の出力線をそれぞれゲートに接続した１対のＰおよびＮチャネル出力段ＭＯＳトランジスタとを備える差動ＡＢ級増幅回路。 A pair of N and P receiving differential amplifiers, each of which is connected to a pair of normal and inverting input terminals and is controlled in constant current by a pair of N and P channel differential bias voltages;
A pair of P and N channel constant current bias voltages connected to each other between the output line and the power supply terminal of the N receiving differential amplifier and between the output line and the ground terminal of the P receiving differential amplifier, respectively. P and N channel constant current MOS transistors,
A pair of P and N channel shift MOS transistors connected in parallel between the output lines of the pair of N and P receiving differential amplifiers and connected to a pair of P and N channel shift bias voltages with their gates functioning as level shifters;
A pair of P and N channel output stage MOS transistors connected between the output terminal and the power supply terminal and between the output terminal and the ground terminal and respectively connected to the gates of the output lines of the pair of N and P receiving differential amplifiers. A differential class AB amplifier circuit.
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