JP2005116915A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2005116915A
JP2005116915A JP2003351595A JP2003351595A JP2005116915A JP 2005116915 A JP2005116915 A JP 2005116915A JP 2003351595 A JP2003351595 A JP 2003351595A JP 2003351595 A JP2003351595 A JP 2003351595A JP 2005116915 A JP2005116915 A JP 2005116915A
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JP
Japan
Prior art keywords
semiconductor chip
semiconductor device
bent portion
metal wire
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003351595A
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Japanese (ja)
Inventor
Osamu Isaki
治 伊佐木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kanto Sanyo Semiconductors Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Kanto Sanyo Semiconductors Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kanto Sanyo Semiconductors Co Ltd, Sanyo Electric Co Ltd filed Critical Kanto Sanyo Semiconductors Co Ltd
Priority to JP2003351595A priority Critical patent/JP2005116915A/en
Publication of JP2005116915A publication Critical patent/JP2005116915A/en
Pending legal-status Critical Current

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    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can solve the problem that, in the conventional semiconductor device, the looped forms of thin metallic wires connecting electrode pads and leads to each other cannot be made lower in height and, accordingly, a package becomes thicker in thickness. <P>SOLUTION: In this semiconductor device, the thin metallic wires 11 are partially brought into contact with a silicon nitride film 3 formed on the surface of a semiconductor chip 1. In addition, the thin metallic wires 11 are separated upward from the outer peripheral end 21 of the chip 1. Consequently, the thin metallic wires 11 are brought into contact with the side face 22 of the chip 1, and the occurrence of short circuits can be prevented. Moreover, since the looped forms of the metallic wires 11 can be made lower in height from the surface of the chip 1, the thickness of the package can be reduced. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明の半導体装置では、半導体チップ上面のボンディング電極と外部端子とを金属細線を介して電気的に接続する技術に関する。   The semiconductor device according to the present invention relates to a technique for electrically connecting a bonding electrode on an upper surface of a semiconductor chip and an external terminal through a thin metal wire.

従来の半導体装置において、配線抵抗の低減を図るため、直径の太い金属細線が用いられていた。そして、該金属細線を用いるために、金属細線のループ形状が改良され、金属細線が、所望のパッケージサイズ内に収まるようにされていた。（例えば、特許文献１。）。   In a conventional semiconductor device, a thin metal wire having a large diameter has been used in order to reduce wiring resistance. In order to use the fine metal wires, the loop shape of the fine metal wires has been improved so that the fine metal wires can be accommodated within a desired package size. (For example, Patent Document 1).

また、従来の半導体装置において、ワイヤボンディングを行う２点間では、金属細線のループ形状が改良され、ワイヤの形状保持力の向上が図れていた。そして、金属細線が、モールド時の樹脂圧により倒れたり、曲がったりすることを防いでいた（例えば、特許文献２。）。   Further, in the conventional semiconductor device, the loop shape of the fine metal wire is improved between two points where wire bonding is performed, and the wire shape retention force is improved. And it prevented that a metal fine wire fell down by the resin pressure at the time of a molding, or bent (for example, patent document 2).

また、従来のワイヤボンダーにおいて、最適なボンディングパラメータが設定され、ボンディングワイヤのオープン不良及びショート不良の発生が防止されていた（例えば、特許文献３。）。
特許第３２７６８９９号公報（第３−４頁、第１図） 特許第３１８９１１５号公報（第５−７頁、第１図） 特開平６−１３２３４７号公報（第５−８頁、第４図） Moreover, in the conventional wire bonder, the optimal bonding parameter was set, and the open defect and the short defect of the bonding wire were prevented (for example, Patent Document 3).
Japanese Patent No. 3276899 (page 3-4, Fig. 1) Japanese Patent No. 3189115 (page 5-7, Fig. 1) JP-A-6-132347 (page 5-8, FIG. 4)

従来の半導体装置において、半導体装置の多機能化や高性能化に伴い、半導体チップ表面の電極パッド数は、増加する傾向にある。電極パッドは、半導体チップの外周部に配置される。そして、金属細線は、半導体チップの外周部から上方へ弧を成し、リード端子と接続する。そのことで、例えば、電極パッドとリード端子とを接続する金属細線が、チップ端部でショートすることを防止していた。   In a conventional semiconductor device, the number of electrode pads on the surface of a semiconductor chip tends to increase as the functionality of the semiconductor device increases and the performance increases. The electrode pad is disposed on the outer periphery of the semiconductor chip. The fine metal wire forms an arc upward from the outer periphery of the semiconductor chip and is connected to the lead terminal. This prevents, for example, a short metal wire connecting the electrode pad and the lead terminal at the end of the chip.

しかしながら、電極パッド数の増加に伴い、全ての電極パッドを半導体チップの外周部に配置することが、困難であった。そのため、電極パッドは、半導体チップの外周部だけでなく、半導体チップの中央領域へと配置された。   However, with the increase in the number of electrode pads, it has been difficult to arrange all the electrode pads on the outer periphery of the semiconductor chip. For this reason, the electrode pads are arranged not only in the outer peripheral portion of the semiconductor chip but also in the central region of the semiconductor chip.

そして、チップの中央領域に配置された電極パッドでは、金属細線がチップ端部でショートすることを防ぐために、金属細線のループ形状を高くする必要があった。その結果、パッケージの厚みが、厚くなる問題が発生した。   And in the electrode pad arrange | positioned in the center area | region of a chip | tip, in order to prevent a metal fine wire short-circuiting at a chip | tip edge part, it was necessary to make the loop shape of a metal fine wire high. As a result, a problem that the thickness of the package becomes thick has occurred.

上述した従来の課題に鑑みてなされたもので、本発明の半導体装置では、半導体チップと、前記半導体チップの周囲に設けられた外部端子と、前記半導体チップのボンディング電極と前記外部端子とを電気的に接続する金属細線とを有する半導体装置において、前記金属細線の延在部の一部が、前記半導体チップの表面に当接していることを特徴とする。本発明の半導体装置では、半導体チップ上面において、金属細線が、低いループ形状となり、パッケージ厚みを薄くすることができる。   In view of the above-described conventional problems, in the semiconductor device of the present invention, a semiconductor chip, an external terminal provided around the semiconductor chip, a bonding electrode of the semiconductor chip, and the external terminal are electrically connected. In the semiconductor device having a thin metal wire to be connected, a part of the extending portion of the thin metal wire is in contact with the surface of the semiconductor chip. In the semiconductor device of the present invention, the thin metal wire has a low loop shape on the upper surface of the semiconductor chip, and the package thickness can be reduced.

更に、本発明の半導体装置では、前記半導体チップの表面には絶縁層が形成されており、前記金属細線は、前記絶縁層に当接していることを特徴とする。本発明の半導体装置では、金属細線は、半導体チップ表面と当接するが、半導体チップ表面には絶縁層が設けられている。この構造により、金属細線は、半導体基板とショートすることはない。   Furthermore, in the semiconductor device of the present invention, an insulating layer is formed on the surface of the semiconductor chip, and the fine metal wires are in contact with the insulating layer. In the semiconductor device of the present invention, the fine metal wire contacts the surface of the semiconductor chip, but an insulating layer is provided on the surface of the semiconductor chip. With this structure, the fine metal wire does not short-circuit with the semiconductor substrate.

更に、本発明の半導体装置では、前記金属細線は、前記半導体チップの外周端部から上方及び外側に離間していることを特徴とする。一般に、金属細線は、半導体チップの周囲では、半導体チップの外周端部に近づく。しかしながら、本発明の半導体装置では、金属細線は、半導体チップの外周端部の近傍で、該外周端部から上方及び外側へと離間する。そして、金属細線は、半導体基板とショートすることはない。   Further, in the semiconductor device of the present invention, the fine metal wires are spaced upward and outward from the outer peripheral end of the semiconductor chip. In general, the fine metal wire approaches the outer peripheral end of the semiconductor chip around the semiconductor chip. However, in the semiconductor device of the present invention, the fine metal wires are separated upward and outward from the outer peripheral end portion in the vicinity of the outer peripheral end portion of the semiconductor chip. The fine metal wire does not short-circuit with the semiconductor substrate.

また、本発明の半導体装置では、半導体チップと、前記半導体チップの周囲に設けられた外部端子と、前記半導体チップのボンディング電極と前記外部端子とを電気的に接続する金属細線とを有する半導体装置において、前記金属細線は、前記ボンディング電極と接続する接続部から第１の屈曲部、第２の屈曲部及び第３の屈曲部を有し、前記第２の屈曲部の頂部は、前記半導体チップ表面と前記金属細線の２本分より狭い範囲で離間していることを特徴とする。本発明の半導体装置では、金属細線は、少なくとも３つの屈曲部を有している。第２の屈曲部の頂部は、半導体チップ表面から金属細線２本分より狭い範囲で離間する。しかしながら、金属細線は低いループ形状であり、パッケージの厚みが薄くなる。   In the semiconductor device of the present invention, the semiconductor device includes a semiconductor chip, an external terminal provided around the semiconductor chip, and a thin metal wire that electrically connects the bonding electrode of the semiconductor chip and the external terminal. The thin metal wire has a first bent portion, a second bent portion, and a third bent portion from a connecting portion connected to the bonding electrode, and the top portion of the second bent portion is the semiconductor chip. It is characterized in that the surface is separated in a range narrower than two metal wires. In the semiconductor device of the present invention, the fine metal wire has at least three bent portions. The top of the second bent portion is separated from the surface of the semiconductor chip in a range narrower than two fine metal wires. However, the thin metal wire has a low loop shape, and the thickness of the package is reduced.

更に、本発明の半導体装置では、前記第１の屈曲部の頂部は、前記ボンディング電極表面から前記金属細線の３本分の高さより低い位置に配置されていることを特徴とする。本発明の半導体装置では、第１の屈曲部の頂部は、半導体チップ表面から金属細線３本分より狭い範囲で離間している。そして、ループの最頂部となる箇所が、半導体チップ表面に近い位置となり、パッケージの厚みが薄くなる。   Furthermore, in the semiconductor device of the present invention, the top of the first bent portion is disposed at a position lower than the height of the three fine metal wires from the surface of the bonding electrode. In the semiconductor device of the present invention, the top of the first bent portion is separated from the surface of the semiconductor chip in a range narrower than three metal wires. And the location used as the top part of a loop becomes a position near the semiconductor chip surface, and the thickness of a package becomes thin.

本発明の半導体装置では、半導体チップ上面のボンディング電極と外部端子とを接続する金属細線の一部が、半導体チップ表面を覆う絶縁層と当接している。そして、金属細線は、半導体チップの外周端部において、該チップ外周端部から上方へと離間している。この構造により、金属細線は、半導体チップ表面及び外周端部において、半導体基板とショートすることはない。   In the semiconductor device of the present invention, a part of the thin metal wire connecting the bonding electrode on the upper surface of the semiconductor chip and the external terminal is in contact with the insulating layer covering the surface of the semiconductor chip. The fine metal wires are spaced upward from the outer peripheral end of the semiconductor chip at the outer peripheral end of the semiconductor chip. With this structure, the fine metal wire is not short-circuited with the semiconductor substrate at the semiconductor chip surface and at the outer peripheral edge.

更に、本発明の半導体装置では、金属細線のループ形状において、最頂部となる第１の屈曲部の頂部が、チップ表面近傍に配置されるので、パッケージの厚みが薄くなる。   Furthermore, in the semiconductor device of the present invention, the top of the first bent portion that is the top in the loop shape of the thin metal wire is disposed in the vicinity of the chip surface, so that the thickness of the package is reduced.

以下に、本発明における半導体装置において、図１〜図４を参照して説明する。図１は、リードフレーム上に固着された半導体チップとポストとの接続構造を説明する斜視図である。図２（Ａ）は、金属細線の一部が半導体チップ表面と当接する構造を説明する断面図である。図２（Ｂ）は、金属細線の一部が半導体チップ表面から若干離間する構造を説明する断面図である。図３は、金属細線が半導体チップの電極とポストとを接続する構造を説明する断面図である。図４（Ａ）及び（Ｂ）は、樹脂モールドされたパッケージを説明する断面図である。   Hereinafter, a semiconductor device according to the present invention will be described with reference to FIGS. FIG. 1 is a perspective view for explaining a connection structure between a semiconductor chip fixed on a lead frame and a post. FIG. 2A is a cross-sectional view illustrating a structure in which a part of the thin metal wire comes into contact with the surface of the semiconductor chip. FIG. 2B is a cross-sectional view illustrating a structure in which a part of the thin metal wire is slightly separated from the surface of the semiconductor chip. FIG. 3 is a cross-sectional view for explaining a structure in which a thin metal wire connects an electrode of a semiconductor chip and a post. 4A and 4B are cross-sectional views illustrating a resin-molded package.

図１に示すように、本実施の形態では、例えば、半導体チップ１として、ＭＯＳＦＥＴ（Ｍｅｔａｌ Ｏｘｉｄｅ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｌｅｄ Ｅｆｆｅｃｔ
Ｔｒａｎｓｉｓｔｅｒ）を用いて説明する。具体的には、銅（Ｃｕ）のリードフレーム（以下、Ｃｕフレームと呼ぶ。）に半導体チップ１が実装された構造を示している。 As shown in FIG. 1, in the present embodiment, for example, as a semiconductor chip 1, a MOSFET (Metal Oxide Semiconductor Field Effect)
A description will be given using a (Transistor). Specifically, a structure in which the semiconductor chip 1 is mounted on a copper (Cu) lead frame (hereinafter referred to as a Cu frame) is shown.

尚、本実施の形態において、リードフレームの材料は、Ｆｅ−Ｎｉを主材料としても良いし、他の金属材料でも良い。また、リードフレームの代わりに、プリント基板、フレキシブルシート等を支持基板として採用したパッケージに適用しても良い。   In the present embodiment, the lead frame material may be Fe-Ni as a main material or other metal material. Further, instead of the lead frame, the present invention may be applied to a package that employs a printed circuit board, a flexible sheet, or the like as a support substrate.

図示したように、例えば、Ｃｕフレームのアイランド２には、例えば、半田等の導電ペースト１４（図２参照）を介して半導体チップ１が固着されている。半導体チップ１表面には、絶縁層として、シリコン酸化膜（図示せず）、シリコン窒化膜（ＳｉＮ）３等が形成されている。本実施の形態では、ＳｉＮ層３は、パッシベーション膜として機能する。そして、例えば、アルミニウム（Ａｌ）から成るゲート電極４、ソース電極５の劣化防止を図る。そして、ＳｉＮ膜３には、２つの孔６、７が形成されている。孔６、７からは、ソース電極５、ゲート電極４が露出している。   As illustrated, for example, the semiconductor chip 1 is fixed to the island 2 of the Cu frame via a conductive paste 14 (see FIG. 2) such as solder. A silicon oxide film (not shown), a silicon nitride film (SiN) 3 and the like are formed on the surface of the semiconductor chip 1 as an insulating layer. In the present embodiment, the SiN layer 3 functions as a passivation film. For example, deterioration of the gate electrode 4 and the source electrode 5 made of aluminum (Al) is prevented. Two holes 6 and 7 are formed in the SiN film 3. The source electrode 5 and the gate electrode 4 are exposed from the holes 6 and 7.

アイランド２からは、ドレイン端子８が、延在している。そして、アイランド２の近傍には、金属細線１１の一端と接続するポスト９、１０が配置されている。ポスト９、１０からは、それぞれソース端子１２、ゲート端子１３となるリードが延在している。金属細線１１は、例えば、金線から成る。そして、金属細線１１は、ソース電極５とポスト９とを電気的に接続している。また、金属細線１１は、ゲート電極４とポスト１０とを電気的に接続している。ドレイン端子８、ソース端子１２及びゲート端子１３は、樹脂パッケージ１５（図４参照）や金属パッケージ等から外部リードとして導出する。   A drain terminal 8 extends from the island 2. In the vicinity of the island 2, posts 9 and 10 connected to one end of the thin metal wire 11 are arranged. From the posts 9 and 10, leads serving as the source terminal 12 and the gate terminal 13 respectively extend. The thin metal wire 11 is made of, for example, a gold wire. The thin metal wire 11 electrically connects the source electrode 5 and the post 9. Further, the fine metal wire 11 electrically connects the gate electrode 4 and the post 10. The drain terminal 8, the source terminal 12, and the gate terminal 13 are led out as external leads from a resin package 15 (see FIG. 4), a metal package, or the like.

図２（Ａ）に示すように、金属細線１１は、例えば、ソース電極５とボールボンディングし、ポスト９とステッチボンディングしている。丸印で図示したように、金属細線１１には、ソース電極５とポスト９との間に、少なくとも第１の屈曲部２３、第２の屈曲部２４及び第３の屈曲部２５が形成されている。金属細線１１の第２の屈曲部２４及びその近傍領域は、半導体チップ１表面のＳｉＮ膜３と当接している。   As shown in FIG. 2A, the fine metal wire 11 is, for example, ball-bonded to the source electrode 5 and stitch-bonded to the post 9. As illustrated by the circles, at least the first bent portion 23, the second bent portion 24, and the third bent portion 25 are formed on the thin metal wire 11 between the source electrode 5 and the post 9. Yes. The second bent portion 24 of the fine metal wire 11 and the vicinity thereof are in contact with the SiN film 3 on the surface of the semiconductor chip 1.

具体的に述べると、金属細線１１は、アルファベットのＭ字形状のループとなる。金属細線１１は、ソース電極５上面でバンプ２６を介して、ボールボンディングにより接続している。金属細線１１には、バンプ２６から延在した箇所に、第１の屈曲部２３が形成されている。第１の屈曲部２３は、半導体チップ１表面に対し、上方に凸な曲線となる。第２の屈曲部２４は、半導体チップ１表面に対し、下方に凸な曲線となる。そして、第３の屈曲部２５は、半導体チップ１表面に対し、上方に凸な曲線となる。その後、金属細線１１は、Ｃｕフレームのポスト９上面で、ステッチボンディングにより、接続している。   More specifically, the fine metal wire 11 becomes an alphabetic M-shaped loop. The fine metal wires 11 are connected by ball bonding via bumps 26 on the upper surface of the source electrode 5. In the thin metal wire 11, a first bent portion 23 is formed at a portion extending from the bump 26. The first bent portion 23 is a curved line that protrudes upward with respect to the surface of the semiconductor chip 1. The second bent portion 24 has a downwardly convex curve with respect to the surface of the semiconductor chip 1. The third bent portion 25 is a curved line that protrudes upward with respect to the surface of the semiconductor chip 1. Thereafter, the fine metal wires 11 are connected by stitch bonding on the upper surface of the post 9 of the Cu frame.

図示したように、金属細線１１は、第３の屈曲部２５からポスト９へと延在し、チップ外周端部２１及びチップ側面２２に対して、離間する。そして、本実施の形態では、少なくとも絶縁層で被覆されていないチップ側面２２と金属細線１１とが当接し、ショートしない構造となる。つまり、金属細線１１は、チップ外周端部２１に対し、最低離間距離ｔ７を有することで、チップ側面２２を介してショートすることはない。   As shown in the drawing, the fine metal wire 11 extends from the third bent portion 25 to the post 9 and is separated from the chip outer peripheral end portion 21 and the chip side surface 22. In the present embodiment, at least the chip side surface 22 that is not covered with the insulating layer and the metal thin wire 11 are in contact with each other, so that a short circuit is not caused. That is, the metal thin wire 11 is not short-circuited via the chip side surface 22 by having the minimum separation distance t7 with respect to the chip outer peripheral end portion 21.

更に、金属細線１１が、少なくともチップ外周端部２１の近傍領域では、チップ表面に対して上方に凸な曲線となる。そして、第３の屈曲部２５は、半導体チップ１表面の上方で、チップ外周端部２１側に位置している。あるいは、第３の屈曲部２５は、半導体チップ１に対し、チップ外周端部２１よりも外側に位置している。   Further, the metal thin wire 11 is a curved line protruding upward with respect to the chip surface in at least the region near the chip outer peripheral end 21. The third bent portion 25 is located on the chip outer peripheral end 21 side above the surface of the semiconductor chip 1. Alternatively, the third bent portion 25 is located outside the chip outer peripheral end portion 21 with respect to the semiconductor chip 1.

ここで、図３を用いて、従来例の問題点について述べる。金属細線３５には、１つの屈曲部３６が形成され、金属細線３５とチップ外周端部３７との離間距離が考慮される。そして、従来の構造においても、金属細線３５とチップ外周端部２１との間は、最低離間距離ｔ７だけは必要とされる。この構造を実現させるためには、半導体チップ３１表面と屈曲部３６の頂部との離間距離ｔ３は、広くなる傾向にある。   Here, problems of the conventional example will be described with reference to FIG. One thin bent portion 36 is formed in the fine metal wire 35, and the separation distance between the fine metal wire 35 and the chip outer peripheral end portion 37 is considered. In the conventional structure, only the minimum separation distance t7 is required between the fine metal wire 35 and the chip outer peripheral end portion 21. In order to realize this structure, the separation distance t3 between the surface of the semiconductor chip 31 and the top of the bent portion 36 tends to increase.

例えば、金属細線３５とポスト３４との接続位置を半導体チップ３１の近傍にする場合、ショート防止を考慮すれば、自然と離間距離ｔ３は広くなる。この場合、パッケージの厚みが厚くなる。一方、金属細線３５とポスト３４との接続位置を半導体チップ３１の遠方にする場合、屈曲部３６がチップ外周端部２１側へスライドでき、離間距離ｔ３を狭くすることは可能である。しかし、この場合には、アイランド３２とポスト３４との位置が離れ、必然的にパッケージ幅が大きくなる。   For example, when the connection position between the thin metal wire 35 and the post 34 is set in the vicinity of the semiconductor chip 31, the separation distance t3 is naturally increased in consideration of prevention of short circuit. In this case, the package becomes thick. On the other hand, when the connection position between the fine metal wire 35 and the post 34 is located far from the semiconductor chip 31, the bent portion 36 can slide to the chip outer peripheral end 21 side, and the separation distance t3 can be reduced. In this case, however, the island 32 and the post 34 are separated from each other, and the package width is inevitably increased.

しかしながら、本実施の形態では、図示したように、第３の屈曲部２５の位置により、金属細線１１とチップ外周端部２１との離間距離が、調整可能である。第３の屈曲部２５がチップ外周端部２１側に配置されることで、金属細線１１とポスト９との接続箇所が、半導体チップ１側へとできる。そして、アイランド２とポスト９との離間距離が狭められるので、パッケージ幅を縮小することができる。尚、第３の屈曲部２５が、チップ外周端部２５に対し、半導体チップ１の外側に位置する場合でも良い。この場合には、より確実に金属細線１１とチップ外周端部２５との離間距離を確保できる。   However, in the present embodiment, as shown in the drawing, the distance between the fine metal wire 11 and the chip outer peripheral end 21 can be adjusted by the position of the third bent portion 25. By arranging the third bent portion 25 on the chip outer peripheral end portion 21 side, the connection portion between the fine metal wire 11 and the post 9 can be directed to the semiconductor chip 1 side. Since the distance between the island 2 and the post 9 is reduced, the package width can be reduced. Note that the third bent portion 25 may be positioned outside the semiconductor chip 1 with respect to the chip outer peripheral end portion 25. In this case, the separation distance between the fine metal wire 11 and the chip outer peripheral end 25 can be ensured more reliably.

図４（Ａ）及び（Ｂ）に示す構造を比較する。ここで、両構造においても、半導体チップ１の厚み等、同じ条件下で比較を行う。両構造の場合でも、パッケージ１５表面と金属細線１１との最低かぶりｔ４は同じである。つまり、金属細線１１のループ形状の相違が、パッケージ厚みの相違となる。図４（Ｂ）に示す形状の場合には、９００μｍ程度のパッケージ厚みｔ６となる。一方、図４（Ａ）に示す形状の場合には、５００μｍ程度のパッケージ厚みｔ５となる。   The structures shown in FIGS. 4A and 4B are compared. Here, in both structures, the comparison is performed under the same conditions such as the thickness of the semiconductor chip 1. Even in the case of both structures, the minimum fog t4 between the surface of the package 15 and the thin metal wire 11 is the same. That is, the difference in the loop shape of the thin metal wire 11 is the difference in the package thickness. In the case of the shape shown in FIG. 4B, the package thickness t6 is about 900 μm. On the other hand, in the case of the shape shown in FIG. 4A, the package thickness t5 is about 500 μm.

つまり、本実施の形態では、第３の屈曲部２５は、チップ外周端部２１側に配置されることで、半導体チップ１表面の近傍に配置される。そして、第１の屈曲部２３の頂部が、ループの最頂部となる。第１の屈曲部２３の頂部は、ソース電極５の表面から金属細線１１の３本分程度、離間している。この構造により、金属細線１１の低ループ形状を実現し、パッケージの厚みを薄くすることができる。   That is, in the present embodiment, the third bent portion 25 is disposed in the vicinity of the surface of the semiconductor chip 1 by being disposed on the chip outer peripheral end portion 21 side. And the top part of the 1st bending part 23 turns into the top part of a loop. The top of the first bent portion 23 is separated from the surface of the source electrode 5 by about three metal wires 11. With this structure, the low loop shape of the fine metal wires 11 can be realized, and the thickness of the package can be reduced.

次に、図２（Ｂ）に示すように、金属細線１１が、半導体チップ１表面に当接せず、ＳｉＮ膜３表面から離間距離ｔ２を有する場合でも良い。そして、離間距離ｔ２は、ＳｉＮ膜３表面から、例えば、金属細線１１の２本分程度以下である。しかしながら、離間距離ｔ２は、金属細線１１の２本分程度以下の場合に限定するものではない。様々な使用用途に応じて、離間距離ｔ２の設計変更は可能である。   Next, as shown in FIG. 2B, the metal thin wire 11 may not contact the surface of the semiconductor chip 1 but may have a separation distance t2 from the surface of the SiN film 3. The separation distance t2 is, for example, about two or less of the metal thin wires 11 from the surface of the SiN film 3. However, the separation distance t <b> 2 is not limited to the case where the distance is equal to or less than about two metal thin wires 11. The design of the separation distance t2 can be changed according to various usages.

また、図２に示すように、本実施の形態では、第１の屈曲部の頂部が、金属細線のループ形状において、最頂部に位置しているが、この場合に限定するものではない。例えば、第３の屈曲部の頂部が、最頂部となっても良い。また、金属細線に複数の屈曲部が形成され、その中の任意の屈曲部の頂部が、最頂部と成っても良い。つまり、パッケージの厚みが薄くなるように、低ループ形状が実現できれば、種々の設計変更は可能である。更に、上述したように、第１の屈曲部の頂部が、半導体チップ表面から金属細線３本分程度、離間する場合に限定するものではない。様々な使用用途に応じて、該離間距離の設計変更は可能である。   Moreover, as shown in FIG. 2, in this Embodiment, the top part of the 1st bending part is located in the top part in the loop shape of a metal fine wire, However, It does not limit to this case. For example, the top of the third bent portion may be the top. Moreover, a some bending part may be formed in a metal fine wire, and the top part of the arbitrary bending part in it may turn into the top part. That is, various design changes are possible if a low loop shape can be realized so that the thickness of the package is reduced. Furthermore, as described above, the first bent portion is not limited to the case where the top portion of the first bent portion is separated from the semiconductor chip surface by about three metal wires. The design of the separation distance can be changed according to various uses.

尚、半導体チップとして、ＭＯＳＦＥＴを用いる場合について説明したが、この場合に限定する必要はない。その他にも、半導体チップとして、例えば、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ−Ｇａｔｅ−Ｂｉｐｏｌａｒ−Ｔｒａｎｓｉｓｔｏｒ）、バイポーラトランジスタ、ＭＯＳトランジスタ、ＩＣ（Ｉｎｔｅｇｒａｔｅｄ Ｃｉｒｃｕｉｔ）等を用いた場合にも、同様な効果を得ることができる。ＩＣチップの場合には、近年の多機能化により、ボンディング電極数が増加する傾向がある。そして、ＩＣチップ表面では、チップ外周部だけでは、電極が全て配置されず、ＩＣチップ中央領域へと電極が配置されている。この場合、上述した金属細線のループ形状により、パッケージサイズの縮小を実現できる。   In addition, although the case where MOSFET was used as a semiconductor chip was demonstrated, it is not necessary to limit to this case. In addition, the same effect can be obtained when, for example, an IGBT (Insulated-Gate-Bipolar-Transistor), a bipolar transistor, a MOS transistor, an IC (Integrated Circuit), or the like is used as the semiconductor chip. In the case of an IC chip, the number of bonding electrodes tends to increase due to recent multifunctionalization. On the surface of the IC chip, not all the electrodes are arranged only at the outer periphery of the chip, and the electrodes are arranged in the central area of the IC chip. In this case, the package size can be reduced by the loop shape of the thin metal wire described above.

次に、以下に、本発明における半導体装置の製造方法において、図５〜図７を参照として説明する。図５は、リードフレーム上に半導体チップを固着する工程を説明する斜視図である。図６及び図７は、ワイヤボンディング工程を説明する図である。   Next, a method for manufacturing a semiconductor device according to the present invention will be described below with reference to FIGS. FIG. 5 is a perspective view for explaining a process of fixing the semiconductor chip on the lead frame. 6 and 7 are diagrams for explaining the wire bonding process.

先ず、図５に示すように、厚さが約１００〜２５０μｍ程度のＣｕフレームを準備する。Ｃｕフレームには、通常、アイランド２、アイランド２から連続して延在するドレイン端子８、ポスト９、１０、ソース端子１２、ゲート端子１３とから成る１ユニットが、多数形成されている。   First, as shown in FIG. 5, a Cu frame having a thickness of about 100 to 250 μm is prepared. In the Cu frame, usually, a large number of one unit comprising an island 2, a drain terminal 8, posts 9, 10, a source terminal 12, and a gate terminal 13 extending continuously from the island 2 are formed.

その後、アイランド２表面にＡｇペーストなどの導電ペースト１４を塗布し、半導体チップ１を固着する。   Thereafter, a conductive paste 14 such as an Ag paste is applied to the surface of the island 2 to fix the semiconductor chip 1.

次に、図１に示すように、ゲート電極４とポスト１０とを金属細線１１で接続する。また、ソース電極５とポスト９とを金属細線１１で接続する。   Next, as shown in FIG. 1, the gate electrode 4 and the post 10 are connected by a thin metal wire 11. Further, the source electrode 5 and the post 9 are connected by a thin metal wire 11.

尚、図示はしていないが、アイランド２やポスト９、１０上には導電ペースト１４との接着性を考慮して銀メッキや金メッキを施す場合もある。   Although not shown, silver plating or gold plating may be applied on the island 2 or the posts 9 and 10 in consideration of the adhesiveness with the conductive paste 14.

次に、金属細線１１の一部が、シリコン窒化膜３と当接するように、ループ形状を形成する。以下に、図６及び図７を参照として、金属細線１１の接続方法を説明する。   Next, a loop shape is formed so that a part of the thin metal wire 11 comes into contact with the silicon nitride film 3. Below, the connection method of the metal fine wire 11 is demonstrated with reference to FIG.6 and FIG.7.

先ず、図６（Ａ）に示すように、金ボールをソース電極４表面にボールボンディングする。そして、キャピラリ４１を、例えば、金属細線１１の３本分程度、矢印Ｓ１方向に水平移動させる。その後、キャピラリ４１をＳ２（上方）方向へと垂直移動させる。この移動により、金属細線１１には、第１の屈曲部２３が形成される。また、キャピラリ４１の移動量は、適宜、変更が可能である。   First, as shown in FIG. 6A, a gold ball is ball bonded to the surface of the source electrode 4. Then, the capillary 41 is moved horizontally in the direction of the arrow S1, for example, about three metal thin wires 11. Thereafter, the capillary 41 is vertically moved in the S2 (upward) direction. By this movement, the first bent portion 23 is formed in the fine metal wire 11. Further, the amount of movement of the capillary 41 can be changed as appropriate.

次に、図６（Ｂ）に示すように、キャピラリ４１を、矢印Ｓ３方向に水平移動させ、その後、キャピラリ４１をＳ４（上方）方向へと垂直移動させる。この移動により、金属細線１１には、第２の屈曲部２４が形成される。   Next, as shown in FIG. 6B, the capillary 41 is moved horizontally in the arrow S3 direction, and then the capillary 41 is moved vertically in the S4 (upward) direction. By this movement, the second bent portion 24 is formed in the fine metal wire 11.

次に、図７（Ａ）に示すように、キャピラリ４１を、矢印Ｓ５方向に水平移動させる。そして、キャピラリ４１をＳ６方向（下方）へと垂直移動させる。この移動により、金属細線１１には、第３の屈曲部２５が形成される。   Next, as shown in FIG. 7A, the capillary 41 is moved horizontally in the arrow S5 direction. Then, the capillary 41 is vertically moved in the S6 direction (downward). By this movement, the third bent portion 25 is formed in the fine metal wire 11.

最後に、図７（Ｂ）に示すように、キャピラリ４１をＳ７（上方）方向へと、適宜、移動させる。その後、クランパ（図示せず）で金属細線１１を挟み、固定する。その後、金属細線１１をクランパで固定した状態で、Ｓ８方向へとキャピラリ４１を移動させる。そして、ポスト９上面で、金属細線１１をステッチボンディングする。   Finally, as shown in FIG. 7B, the capillary 41 is appropriately moved in the S7 (upward) direction. Thereafter, the fine metal wire 11 is sandwiched and fixed by a clamper (not shown). Thereafter, the capillary 41 is moved in the S8 direction with the fine metal wire 11 fixed by a clamper. Then, the fine metal wire 11 is stitch-bonded on the upper surface of the post 9.

この工程により、図２（Ａ）に示すように、金属細線１１の第２の屈曲部２４及びその近傍領域が、半導体チップ１表面に形成されたＳｉＮ膜３と当接する。あるいは、図２（Ｂ）に示すように、金属細線１１の第２の屈曲部２４及びその近傍領域が、ＳｉＮ膜３近傍に位置する。   As a result of this step, as shown in FIG. 2A, the second bent portion 24 of the fine metal wire 11 and the region near the second bent portion 24 come into contact with the SiN film 3 formed on the surface of the semiconductor chip 1. Alternatively, as shown in FIG. 2B, the second bent portion 24 of the fine metal wire 11 and the vicinity thereof are located in the vicinity of the SiN film 3.

最後に、トランスファーモールドにより、樹脂パッケージ１５を形成する。その後、ダイシングにより、個々の半導体装置に分割される。そして、樹脂パッケージ１５からは、ドレイン端子８、ソース端子１２及びゲート端子１３が露出する。   Finally, the resin package 15 is formed by transfer molding. Then, it is divided into individual semiconductor devices by dicing. Then, the drain terminal 8, the source terminal 12 and the gate terminal 13 are exposed from the resin package 15.

尚、本実施の形態では、樹脂パッケージの形成する場合で説明したが、この場合に限定する必要はない。例えば、金属パッケージの場合でも、同様な効果を得ることができる。その他、本発明の要旨を逸脱しない範囲で、種々の変更が可能である。   In the present embodiment, the case where a resin package is formed has been described. However, the present invention is not limited to this case. For example, the same effect can be obtained even in the case of a metal package. In addition, various modifications can be made without departing from the scope of the present invention.

本発明の半導体装置に関し、リードフレーム上に固着された半導体チップと金属細線の接続する構造を説明する斜視図である。1 is a perspective view illustrating a structure for connecting a semiconductor chip fixed on a lead frame and a thin metal wire in the semiconductor device of the present invention. 本発明の半導体装置における金属細線のループ形状を説明するための（Ａ）断面図（Ｂ）断面図である。It is (A) sectional drawing (B) sectional drawing for demonstrating the loop shape of the metal fine wire in the semiconductor device of this invention. 従来の半導体装置における金属細線のループ形状を説明するための断面図である。It is sectional drawing for demonstrating the loop shape of the metal fine wire in the conventional semiconductor device. 本発明の半導体装置における樹脂モールドされたパッケージを説明するための（Ａ）断面図（Ｂ）断面図である。It is (A) sectional drawing (B) sectional drawing for demonstrating the resin-molded package in the semiconductor device of this invention. 本発明の半導体装置の製造方法を説明するための斜視図である。It is a perspective view for demonstrating the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法を説明するための（Ａ）断面図（Ｂ）断面図である。It is (A) sectional drawing (B) sectional drawing for demonstrating the manufacturing method of the semiconductor device of this invention. 本発明の半導体装置の製造方法に関し、金属細線のループ形状を形成する工程を説明するための（Ａ）断面図（Ｂ）断面図である。It is (A) sectional drawing (B) sectional drawing for demonstrating the process of forming the loop shape of a metal fine wire regarding the manufacturing method of the semiconductor device of this invention.

符号の説明Explanation of symbols

１、３１ 半導体チップ
２、３２ アイランド
３、３３ シリコン窒化膜
４ ゲート電極
５ ソース電極
６、７ 孔
８ ドレイン端子
９、１０、３４ ポスト
１１、３５ 金属細線
１２ ソース端子
１３ ゲート端子
１４ 導電ペースト
１５ 樹脂パッケージ
２１、３７ チップ外周端部
２２ チップ側面
２３ 第１の屈曲部
２４ 第２の屈曲部
２５ 第３の屈曲部
２６ バンプ
３６ 屈曲部
４１ キャピラリ DESCRIPTION OF SYMBOLS 1, 31 Semiconductor chip 2, 32 Island 3, 33 Silicon nitride film 4 Gate electrode 5 Source electrode 6, 7 Hole 8 Drain terminal 9, 10, 34 Post 11, 35 Metal fine wire 12 Source terminal 13 Gate terminal 14 Conductive paste 15 Resin Package 21, 37 Chip outer peripheral edge 22 Chip side surface 23 First bent portion 24 Second bent portion 25 Third bent portion 26 Bump 36 Bent portion 41 Capillary

Claims (12)

半導体チップと、
前記半導体チップの周囲に設けられた外部端子と、
前記半導体チップのボンディング電極と前記外部端子とを電気的に接続する金属細線とを有する半導体装置において、
前記金属細線の延在部の一部が、前記半導体チップの表面に当接していることを特徴とする半導体装置。 A semiconductor chip;
External terminals provided around the semiconductor chip;
In the semiconductor device having a fine metal wire that electrically connects the bonding electrode of the semiconductor chip and the external terminal,
A part of the extending portion of the thin metal wire is in contact with the surface of the semiconductor chip. 前記半導体チップの表面には絶縁層が形成されており、前記金属細線は、前記絶縁層に当接していることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein an insulating layer is formed on a surface of the semiconductor chip, and the thin metal wires are in contact with the insulating layer. 前記金属細線は、前記半導体チップの外周端部から上方及び外側に離間していることを特徴とする請求項１または請求項２に記載の半導体装置。   3. The semiconductor device according to claim 1, wherein the thin metal wires are spaced upward and outward from an outer peripheral end of the semiconductor chip. 前記金属細線は、前記ボンディング電極と接続する接続部から第１の屈曲部、第２の屈曲部及び第３の屈曲部を有し、前記金属細線は、前記第２の屈曲部及びその近傍領域で前記半導体チップ表面と当接することを特徴とする請求項１に記載の半導体装置。   The thin metal wire has a first bent portion, a second bent portion, and a third bent portion from a connection portion connected to the bonding electrode, and the thin metal wire includes the second bent portion and a region near the second bent portion. The semiconductor device according to claim 1, wherein the semiconductor device is in contact with the surface of the semiconductor chip. 前記金属細線は、金線であることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the thin metal wire is a gold wire. 前記半導体チップは、ディスクリート型トランジスタまたはＩＣであることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the semiconductor chip is a discrete transistor or an IC. 半導体チップと、
前記半導体チップの周囲に設けられた外部端子と、
前記半導体チップのボンディング電極と前記外部端子とを電気的に接続する金属細線とを有する半導体装置において、
前記金属細線は、前記ボンディング電極と接続する接続部から第１の屈曲部、第２の屈曲部及び第３の屈曲部を有し、前記第２の屈曲部の頂部は、前記半導体チップ表面から前記金属細線の２本分より狭い範囲で離間していることを特徴とする半導体装置。 A semiconductor chip;
External terminals provided around the semiconductor chip;
In the semiconductor device having a fine metal wire that electrically connects the bonding electrode of the semiconductor chip and the external terminal,
The thin metal wire has a first bent portion, a second bent portion, and a third bent portion from a connecting portion connected to the bonding electrode, and a top portion of the second bent portion extends from the surface of the semiconductor chip. A semiconductor device characterized in that the semiconductor devices are spaced apart in a range narrower than two of the thin metal wires. 前記第１の屈曲部の頂部は、前記ボンディング電極表面から前記金属細線の３本分の高さより低い位置に配置されていることを特徴とする請求項７に記載の半導体装置。   8. The semiconductor device according to claim 7, wherein a top portion of the first bent portion is disposed at a position lower than a height of three of the thin metal wires from the surface of the bonding electrode. 前記半導体チップの表面には絶縁層が形成されていることを特徴とする請求項７または請求項８に記載の半導体装置。   The semiconductor device according to claim 7, wherein an insulating layer is formed on a surface of the semiconductor chip. 前記金属細線は、前記半導体チップの外周端部から上方及び外側に離間していることを特徴とする請求項７から請求項９のいずれかに記載の半導体装置。   10. The semiconductor device according to claim 7, wherein the thin metal wire is spaced upward and outward from an outer peripheral end of the semiconductor chip. 11. 前記金属細線は、金線であることを特徴とする請求項７に記載の半導体装置。   The semiconductor device according to claim 7, wherein the thin metal wire is a gold wire. 前記半導体チップは、ディスクリート型トランジスタまたはＩＣであることを特徴とする請求項７に記載の半導体装置。   The semiconductor device according to claim 7, wherein the semiconductor chip is a discrete transistor or an IC.
JP2003351595A 2003-10-10 2003-10-10 Semiconductor device Pending JP2005116915A (en)

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Cited By (6)

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JP2009021499A (en) * 2007-07-13 2009-01-29 Toshiba Corp Laminated semiconductor device
KR100925379B1 (en) 2007-06-27 2009-11-09 가부시키가이샤 신가와 Semiconductor device and wire bonding method
JP2010087403A (en) * 2008-10-02 2010-04-15 Elpida Memory Inc Semiconductor device
KR101143836B1 (en) * 2006-10-27 2012-05-04 삼성테크윈 주식회사 Semiconductor package and method for forming wire loop of the semiconductor package
JP2015043465A (en) * 2014-12-01 2015-03-05 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． Semiconductor device
WO2022259328A1 (en) * 2021-06-07 2022-12-15 株式会社新川 Wire bonding device and wire bonding method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101143836B1 (en) * 2006-10-27 2012-05-04 삼성테크윈 주식회사 Semiconductor package and method for forming wire loop of the semiconductor package
KR100925379B1 (en) 2007-06-27 2009-11-09 가부시키가이샤 신가와 Semiconductor device and wire bonding method
JP2009021499A (en) * 2007-07-13 2009-01-29 Toshiba Corp Laminated semiconductor device
US7968993B2 (en) 2007-07-13 2011-06-28 Kabushiki Kaisha Toshiba Stacked semiconductor device and semiconductor memory device
JP2010087403A (en) * 2008-10-02 2010-04-15 Elpida Memory Inc Semiconductor device
JP2015043465A (en) * 2014-12-01 2015-03-05 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． Semiconductor device
WO2022259328A1 (en) * 2021-06-07 2022-12-15 株式会社新川 Wire bonding device and wire bonding method

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