JP2005072250A - High frequency power semiconductor device - Google Patents

High frequency power semiconductor device Download PDF

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JP2005072250A
JP2005072250A JP2003299994A JP2003299994A JP2005072250A JP 2005072250 A JP2005072250 A JP 2005072250A JP 2003299994 A JP2003299994 A JP 2003299994A JP 2003299994 A JP2003299994 A JP 2003299994A JP 2005072250 A JP2005072250 A JP 2005072250A
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main terminal
power semiconductor
main
semiconductor device
case
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JP4175980B2 (en
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Yoshihisa Oguri
慶久 小栗
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Mitsubishi Electric Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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Abstract

<P>PROBLEM TO BE SOLVED: To deal with a skin effect perfectly by increasing the surface area of an external output electrode without increasing a package size in a power semiconductor device having the external output electrode. <P>SOLUTION: The power semiconductor device includes a plurality of main terminals which pass main current of a power semiconductor element, and which are supported by a case made of a resin surrounding the power semiconductor element, so that the main terminals have a large main terminal forming a region bonding one end of a bonding wire connected to the power semiconductor element to an inside end; and a small main terminal forming an external connecting part by extending from the large main terminal and projecting its extended end from the case. The small main terminal and an auxiliary main terminal opposed to the case through the insulating layer of the same material are arranged, and as the laminated main terminal, the main current can be branched. The large main terminal of the adjacent laminated main terminal is arranged at a predetermined gap in a vertical direction on a surface to be bonded, and the insulating layer of the same material as the case is provided in the gap. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体素子を有して高周波スイッチングに使用される電力用半導体装置に関する。   The present invention relates to a power semiconductor device having a semiconductor element and used for high-frequency switching.

従来の電力用半導体装置では、放熱板上に、はんだを介して導電性の板材を有した絶縁性のセラミック基板が構成される。更にそれら基板・導電性板材上にはんだを介してスイツチング用素子が構成され、それら素子の各々は周知のワイヤ配線により結線されている。   In a conventional power semiconductor device, an insulating ceramic substrate having a conductive plate material is formed on a heat sink via a solder. Further, switching elements are formed on these substrates and conductive plates via solder, and each of these elements is connected by a well-known wire wiring.

このような電力用半導体装置において、外部出力用電極は、１枚の銅材若しくはアルミニウム材などをプレス加工して形成される。該電極は、ケース内に挿入、若しくははんだ付けされている。   In such a power semiconductor device, the external output electrode is formed by pressing one piece of copper material or aluminum material. The electrode is inserted into the case or soldered.

このような従来の電力用半導体装置における外部出力用電極は、１枚の導電材から構成されているので、高周波動作による表皮効果に対応するためには電極の幅を増加させねばならない。そうすると結果としてパッケージサイズが大きくなってしまう、という問題点があった。   Since the external output electrode in such a conventional power semiconductor device is composed of a single conductive material, the width of the electrode must be increased in order to cope with the skin effect caused by high-frequency operation. As a result, there is a problem that the package size becomes large as a result.

特許文献１では、高周波領域にて使用される伝送線路において、表皮効果による抵抗増加を低減するために、誘電膜を介して複数積層することが記載されている。特許文献２では、半導体電力変換装置の主回路導体を表皮効果対策として絶縁コーティングした薄板導体を複数枚積層することが記載されている。特許文献３では、高周波用ＩＣ、又はトランジスタのリードを表皮効果対策として積層したものが記載されている。更に、特許文献４では、パワーモジュールの電極端子の表皮効果対策として表面積を増加させること、具体的にはスリットを設けることが記載されている。
特開平９−９３００５号公報 特開平８−１４９７９５号公報 特開昭６２−２１９６４８号公報 特開平６−６１４０９号公報 Patent Document 1 describes that a plurality of layers are laminated via a dielectric film in a transmission line used in a high frequency region in order to reduce an increase in resistance due to a skin effect. Patent Document 2 describes that a plurality of thin plate conductors that are insulation-coated on the main circuit conductor of a semiconductor power conversion device are laminated as a countermeasure against the skin effect. In Patent Document 3, a high frequency IC or a transistor lead laminated as a skin effect countermeasure is described. Furthermore, Patent Document 4 describes that the surface area is increased as a countermeasure against the skin effect of the electrode terminal of the power module, specifically, that a slit is provided.
JP 9-93005 A Japanese Patent Application Laid-Open No. H8-149795 JP-A-62-219648 JP-A-6-61409

本発明は、外部出力用電極を備える電力用半導体装置において、パッケージサイズを増大することなく、外部出力用電極の表面積を増加させ表皮効果に十全に対応することを目的とする。   It is an object of the present invention to increase the surface area of an electrode for external output and fully cope with the skin effect without increasing the package size in a power semiconductor device including the electrode for external output.

本発明は、上記の目的を達成するために為されたものである。本発明に係る電力用半導体装置は、
電力用半導体素子を囲鐃する樹脂製のケースで前記電力用半導体素子の主電流を流す複数の主端子を支持し、
該主端子が、内側端部に前記電力用半導体素子と接続するボンディングワイヤの一端をボンデイングする領域をなす大幅主端子部と、該大幅主端子部から延在しその延在端が前記ケースより突出し外部接続部をなす小幅主端子部とで形成された電力用半導体装置である。その電力用半導体装置において、
前記小幅主端子部と、前記ケースと同一材質の絶縁層を介し対向する補助主端子とを配設し積層主端子とし、前記小幅主端子部と前記補助主端子の夫々に前記主電流を分流させ得るようにすると共に、隣接する前記積層主端子の前記大幅主端子部が前記ボンディングを行なう面に鉛直方向に互いに所定の隙間をおいて配設され、前記隙間に前記ケースと同一材質の絶縁層を配設したことを特徴とする。 The present invention has been made to achieve the above object. A power semiconductor device according to the present invention includes:
Supporting a plurality of main terminals through which the main current of the power semiconductor element flows in a resin case surrounding the power semiconductor element,
The main terminal has a large main terminal portion forming an area for bonding one end of a bonding wire connected to the power semiconductor element on the inner end portion, and the extended end extends from the large main terminal portion, and the extended end is formed from the case. This is a power semiconductor device formed by a narrow main terminal portion protruding and forming an external connection portion. In the power semiconductor device,
The narrow main terminal portion and an auxiliary main terminal facing each other through an insulating layer made of the same material as the case are disposed to form a laminated main terminal, and the main current is divided into the narrow main terminal portion and the auxiliary main terminal, respectively. The large main terminal portions of the adjacent laminated main terminals are arranged with a predetermined gap in the vertical direction on the bonding surface, and the gap is made of the same material as the case. A layer is provided.

本発明を利用することにより、以下のような効果を得ることができる。   By using the present invention, the following effects can be obtained.

主端子として、大幅主端子部と小幅主端子部とを設け、その大幅主端子部を絶縁層を介し重ね合せると共に、外部接続部を小幅としたので、隣接する主端子を接近させ配設することができる。よって、パッケージサイズの小型化を図り得るだけでなく、小幅主端子部を絶縁層を介し分離し主電流を分流させるので、高周波電流を流す場合表皮効果による電流集中が分散され、抵抗値の低減による損失低減を図ることができる。また、絶縁層をパッケージのケースの成形と同時に行ない得るので、積層主端子の製作や固定を容易且つ廉価とすることができる。   As the main terminals, a large main terminal portion and a narrow main terminal portion are provided, and the large main terminal portions are overlapped via an insulating layer and the external connection portion is made small, so that adjacent main terminals are arranged close to each other. be able to. Therefore, not only can the package size be reduced, but the main current is shunted by separating the narrow main terminal part through the insulating layer, so that current concentration due to the skin effect is dispersed and the resistance value is reduced when high-frequency current is passed. It is possible to reduce loss due to. Further, since the insulating layer can be formed simultaneously with the molding of the package case, the laminated main terminal can be easily and inexpensively manufactured and fixed.

主端子が薄板であっても電流容量を著しく増大できる電力用半導体装置を簡単な構造で提供できる。   Even if the main terminal is a thin plate, a power semiconductor device capable of remarkably increasing the current capacity can be provided with a simple structure.

以下において、図面を参照しつつ本発明に係る好適な実施の形態を説明する。   Hereinafter, preferred embodiments according to the present invention will be described with reference to the drawings.

実施の形態１．
図１は、本発明の実施の形態１に係る電力用半導体装置の平面図である。ベース板２上にセラミックス基板６が設定され、更に該セラミックス基板６上に、半導体素子８やダイオード１０が設置される。結線のためにワイヤ１２が利用されている。半導体装置全体はケース４により覆われる。 Embodiment 1 FIG.
FIG. 1 is a plan view of a power semiconductor device according to Embodiment 1 of the present invention. A ceramic substrate 6 is set on the base plate 2, and a semiconductor element 8 and a diode 10 are further installed on the ceramic substrate 6. A wire 12 is used for connection. The entire semiconductor device is covered with a case 4.

この実施の形態１における電力用半導体装置では、外部出力用電極１４としてインサート式の積層電極が利用されている。図２は、図１の電力用半導体装置の“ＢＢ”での、（１）縦断面図と、（２）そのうちの外部出力用電極１４の拡大図である。図２に示すように、外部出力用電極１４は、主として導電材から構成されているが内部に絶縁層１６を挟み込む。このように絶縁層１６を導電材の内部に挟み込むことによって、外部出力用電極１４の表面積が増大し、よって表皮効果に十全に対応できる。   In the power semiconductor device according to the first embodiment, an insert-type laminated electrode is used as the external output electrode 14. 2 is (1) a longitudinal sectional view and (2) an enlarged view of the external output electrode 14 in “BB” of the power semiconductor device of FIG. As shown in FIG. 2, the external output electrode 14 is mainly made of a conductive material, but sandwiches an insulating layer 16 therein. By sandwiching the insulating layer 16 in the conductive material in this way, the surface area of the external output electrode 14 is increased, and thus the skin effect can be fully accommodated.

なお、図２（２）の外部出力用電極１４は、複数の（２枚の）導電板を接合して形成されている。   Note that the external output electrode 14 in FIG. 2B is formed by joining a plurality of (two) conductive plates.

図５は、実施の形態１における外部出力用電極１４の導電材部分の斜視図を示す。図５の該導電材部分は、銅材板やアルミニウム板から適宜折り曲げられて形成されている。このとき絶縁層が充填されるべき隙間が設けられる。図５（１）（２）に明確に示されるように、外部出力用電極１４は、大幅主端子部３４と小幅主端子部３２とから構成される。上記の折り曲げが完成すると、小幅主端子部３２の折り返しの先端部は半田２８により大幅主端子部３４表面に固定される。このように絶縁層１６を挟むべき隙間を含む小幅主端子部３２は導電材の折り曲げにより形成されてもよいし、導電材の貼り合わせにより形成されてもよい（図２（２）参照）。   FIG. 5 is a perspective view of the conductive material portion of the external output electrode 14 in the first embodiment. The conductive material portion in FIG. 5 is formed by being appropriately bent from a copper plate or an aluminum plate. At this time, a gap to be filled with the insulating layer is provided. As clearly shown in FIGS. 5A and 5B, the external output electrode 14 includes a large main terminal portion 34 and a narrow main terminal portion 32. When the above-described bending is completed, the folded front end portion of the narrow main terminal portion 32 is largely fixed to the surface of the main terminal portion 34 by the solder 28. As described above, the narrow main terminal portion 32 including the gap to sandwich the insulating layer 16 may be formed by bending a conductive material, or may be formed by bonding conductive materials (see FIG. 2B).

また、大幅主端子部３４は、各種素子と接続するためのボンディングワイヤ２６の一端をボンデイングする領域をなす（図４参照）。   Further, the large main terminal portion 34 forms a region for bonding one end of the bonding wire 26 for connection to various elements (see FIG. 4).

外部出力用電極１４の電力用半導体装置への設定において、外部出力用電極１４は個々に独立していることから、それら外部出力用電極１４の間隔を詰めることにより、装置全体を十分に小さいパッケージサイズとすることができる。このとき大幅主端子部３４同士が重なることがあり得るが、そのような場合には間に絶縁材（層）を挟むようにすればよい。   In setting the external output electrode 14 to the power semiconductor device, the external output electrodes 14 are independent from each other. Therefore, by reducing the distance between the external output electrodes 14, the entire device can be packaged sufficiently small. Can be size. At this time, the main terminal portions 34 may overlap each other. In such a case, an insulating material (layer) may be sandwiched therebetween.

図４は、図５の外部出力用電極１４が設けられた電力用半導体装置における縦断面図である。特に、外部出力用電極１４の小幅主端子部３２を縦断する断面図である。小幅主端子部３２の周囲は絶縁材１６で固定されるが、小幅主端子部３２に形成される隙間にも同じ絶縁材が層１６をなして充填される。   4 is a longitudinal sectional view of the power semiconductor device provided with the external output electrode 14 of FIG. In particular, it is a cross-sectional view in which the narrow main terminal portion 32 of the external output electrode 14 is vertically cut. Although the periphery of the narrow main terminal portion 32 is fixed by the insulating material 16, the same insulating material is filled in the gap 16 formed in the narrow main terminal portion 32 in the layer 16.

図３は、（１）実施の形態１に係る外部出力用電極１４が設けられた電力用半導体装置の斜視図と、（２）その一部の拡大図である。（１）に示される電力用半導体装置において、例えば、図の点線に沿って電極１４を折り曲げ、ブスバと接続する部位を形成することができる（図３（２））。図３（１）に示される外部出力用電極１４にて、絶縁層１６の上端部に一致して折り曲げ位置を設定するのは、その折り曲げ位置より上方はブスバ１８と接合するため電流容量増加が不要であるからである。   3 is a perspective view of a power semiconductor device provided with (1) the external output electrode 14 according to the first embodiment, and (2) an enlarged view of a part thereof. In the power semiconductor device shown in (1), for example, the electrode 14 can be bent along the dotted line in the figure to form a portion connected to the bus bar (FIG. 3 (2)). In the external output electrode 14 shown in FIG. 3 (1), the bending position is set to coincide with the upper end of the insulating layer 16, and the current capacity is increased because it is joined to the bus bar 18 above the bending position. This is because it is unnecessary.

図３（２）は、外部出力用電極１４とブスバ１８との接合例を示す。外部出力用電極１４の上端部は適宜折り曲げられている。ブスバ１８と外部出力用電極１４とには孔（ブスバ孔２２と電極孔２４）が空けられ、それら孔を貫くねじ２０により外部出力用電極１４とブスバ１８との接合が固定される。   FIG. 3 (2) shows an example of joining the external output electrode 14 and the bus bar 18. The upper end portion of the external output electrode 14 is appropriately bent. The bus bar 18 and the external output electrode 14 are formed with holes (bus bar holes 22 and electrode holes 24), and the connection between the external output electrode 14 and the bus bar 18 is fixed by a screw 20 penetrating the holes.

本発明の実施の形態１に係る電力用半導体装置の平面図である。1 is a plan view of a power semiconductor device according to a first embodiment of the present invention. 図１の電力用半導体装置の“ＢＢ”での、（１）縦断面図と、（２）そのうちの外部出力用電極の拡大図である。FIG. 2 is a (1) longitudinal sectional view and (2) an enlarged view of an external output electrode in “BB” of the power semiconductor device of FIG. 1. （１）実施の形態１に係る外部出力用電極が設けられた電力用半導体装置の斜視図と、（２）その一部の拡大図である。1A is a perspective view of a power semiconductor device provided with an external output electrode according to Embodiment 1, and FIG. 2B is a partial enlarged view thereof. 外部出力用電極が設けられた電力用半導体装置における縦断面図である。It is a longitudinal cross-sectional view in the power semiconductor device provided with the electrode for external outputs. 実施の形態１における外部出力用電極の導電材部分の斜視図を示す。FIG. 3 is a perspective view of a conductive material portion of the external output electrode in the first embodiment.

符号の説明Explanation of symbols

２ ベース板、 ４ ケース、 ６ セラミックス基板、 ８ 素子、 １０ ダイオード、 １２ ワイヤ、 １４ インサート積層電極、 １６ 絶縁層、 １８ ブスバ、 ２０ ねじ、 ２２ ブスバ孔、 ２４ 電極孔、 ２６ ボンディングワイヤ、 ２８ 半田、 ３０ ナット、 ３２ 小幅主端子部、 ３４ 大幅主端子部。

2 base plate, 4 case, 6 ceramic substrate, 8 element, 10 diode, 12 wire, 14 insert laminated electrode, 16 insulating layer, 18 bus bar, 20 screw, 22 bus bar hole, 24 electrode hole, 26 bonding wire, 28 solder, 30 Nut, 32 Narrow main terminal, 34 Large main terminal.

Claims (2)

電力用半導体素子を囲鐃する樹脂製のケースで前記電力用半導体素子の主電流を流す複数の主端子を支持し、
該主端子が、内側端部に前記電力用半導体素子と接続するボンディングワイヤの一端をボンデイングする領域をなす大幅主端子部と、該大幅主端子部から延在しその延在端が前記ケースより突出し外部接続部をなす小幅主端子部とで形成された電力用半導体装置において、
前記小幅主端子部と、前記ケースと同一材質の絶縁層を介し対向する補助主端子とを配設し積層主端子とし、前記小幅主端子部と前記補助主端子の夫々に前記主電流を分流させ得るようにすると共に、隣接する前記積層主端子の前記大幅主端子部が前記ボンディングを行なう面に鉛直方向に互いに所定の隙間をおいて配設され、前記隙間に前記ケースと同一材質の絶縁層を配設したことを特徴とする電力用半導体装置。 Supporting a plurality of main terminals through which the main current of the power semiconductor element flows in a resin case surrounding the power semiconductor element,
The main terminal has a large main terminal portion forming an area for bonding one end of a bonding wire connected to the power semiconductor element on the inner end portion, and the extended end extends from the large main terminal portion, and the extended end is formed from the case. In the power semiconductor device formed with the narrow main terminal portion protruding and forming the external connection portion,
The narrow main terminal portion and an auxiliary main terminal facing each other through an insulating layer made of the same material as the case are disposed to form a laminated main terminal, and the main current is divided into the narrow main terminal portion and the auxiliary main terminal, respectively. The large main terminal portions of the adjacent laminated main terminals are arranged with a predetermined gap in the vertical direction on the bonding surface, and the gap is insulated with the same material as the case. A power semiconductor device comprising a layer. 延在端を折り曲げ、その先端を大幅主端子部まで折り返し、該折り返しの先端部を前記大幅主端子部に導電性接着材にて接着し前記折返し部で補助主電極を構成したことを特徴とする請求項１に記載の電力用半導体装置。

The extended end is bent, the tip is folded back to the main terminal portion, the tip end portion of the folded back is bonded to the significant main terminal portion with a conductive adhesive, and the folded main portion constitutes the auxiliary main electrode. The power semiconductor device according to claim 1.

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7817374B2 (en) 2007-05-01 2010-10-19 Tdk Corporation Thin film device with lead conductor film of increased surface area

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7817374B2 (en) 2007-05-01 2010-10-19 Tdk Corporation Thin film device with lead conductor film of increased surface area

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