JP2005070627A - Liquid crystal driving device and control method thereof - Google Patents

Liquid crystal driving device and control method thereof Download PDF

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JP2005070627A
JP2005070627A JP2003302934A JP2003302934A JP2005070627A JP 2005070627 A JP2005070627 A JP 2005070627A JP 2003302934 A JP2003302934 A JP 2003302934A JP 2003302934 A JP2003302934 A JP 2003302934A JP 2005070627 A JP2005070627 A JP 2005070627A
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operational amplifier
signal
output
sample
switch
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Masaharu Takahashi
正晴 高橋
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Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
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Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To correct a signal voltage which is inputted from a sampling and holding circuit to an operational amplifier. <P>SOLUTION: A signal driver 20 comprises a sampling and holding circuit 11 of two systems, a single operational amplifier 12, and a switch Swd connected between an output terminal of the operational amplifier 12 and an output terminal Vout. In the sampling and holding circuit 11 of two systems, electric charge of an image signal is alternately stored in S/H capacitors C1 and C2 via switches Swa1 and Swa2 correspondingly to each signal line of a liquid crystal panel. When a signal voltage, corresponding to electric charge stored in the S/H capacitors C1 and C2, is outputted from the output terminal Vout in response to turning-on of the switch Swd, the electric charge of the image signal of which the electric charge has been stored in the S/H capacitors C1 and C2 during a turning-off period of the switch Swd, just before this turning-on of the switch Swd is stored in a parasitic capacity Ci of the operational amplifier 12, so that a signal voltage, corresponding to electric charge stored in the S/H capacitors C1 and C2, is corrected and outputted from the output terminal Vout. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は液晶駆動装置およびその制御方法に関し、特に１出力が２系統からなるサンプルホールド回路と、サンプルホールド回路の２系統に共通接続された単一の演算増幅器とを有する液晶駆動装置とその制御方法に関する。   The present invention relates to a liquid crystal driving device and a control method therefor, and more particularly to a liquid crystal driving device having a sample-and-hold circuit having one output of two systems and a single operational amplifier commonly connected to the two systems of the sample-and-hold circuit and its control. Regarding the method.

液晶駆動装置として、１出力が２系統からなるサンプルホールド回路と、サンプルホールド回路の２系統に共通接続された単一の演算増幅器とを有する信号ドライバが用いられている（例えば、特許文献１を参照。）。以下、特許文献１を参考にして、従来の信号ドライバ１０について図３を参照して説明する。図３に示す信号ドライバ１０は、信号ドライバの出力回路部を示し、各信号ライン毎に同一の構成を有しているため、一出力回路についてのみ示す。図３において、信号ドライバ１０は、２系統のサンプルホールド回路１１と、単一の演算増幅器１２により構成されている。   As a liquid crystal driving device, a signal driver having a sample-and-hold circuit having one output of two systems and a single operational amplifier commonly connected to the two systems of the sample-and-hold circuit is used (for example, see Patent Document 1). reference.). Hereinafter, a conventional signal driver 10 will be described with reference to FIG. The signal driver 10 shown in FIG. 3 shows the output circuit portion of the signal driver, and since it has the same configuration for each signal line, only one output circuit is shown. In FIG. 3, the signal driver 10 includes two systems of sample and hold circuits 11 and a single operational amplifier 12.

サンプルホールド回路１１の第１の経路は、アナログスイッチ（以下、単にスイッチという）Ｓｗａ１とスイッチＳｗｂ１を直列に接続して構成され、スイッチＳｗａ１とスイッチＳｗｂ１の接続点には、他端側が低電位電源Ｖｓｓに接続されたＳ／ＨコンデンサＣ１が接続されている。一方、サンプルホールド回路１１の第２の経路は、スイッチＳｗａ２とスイッチＳｗｂ２を直列に接続して構成され、スイッチＳｗａ２とスイッチＳｗｂ２の接続点には、他端側が低電位電源Ｖｓｓに接続されたＳ／ＨコンデンサＣ２が接続されている。サンプルホールド回路１１の２系統には単一の演算増幅器１２が共通接続されている。演算増幅器１２は、ボルテージフォロア接続されており、演算増幅器１２の出力端子が出力端子Ｖｏｕｔに接続されている。演算増幅器１２の非反転入力端子部分には寄生容量Ｃｉが存在している。   The first path of the sample and hold circuit 11 is configured by connecting an analog switch (hereinafter simply referred to as a switch) Swa1 and a switch Swb1 in series, and the other end of the connection point between the switch Swa1 and the switch Swb1 is a low potential power source. An S / H capacitor C1 connected to Vss is connected. On the other hand, the second path of the sample-and-hold circuit 11 is configured by connecting the switch Swa2 and the switch Swb2 in series, and the other end side is connected to the low potential power supply Vss at the connection point of the switch Swa2 and the switch Swb2. / H capacitor C2 is connected. A single operational amplifier 12 is commonly connected to the two systems of the sample hold circuit 11. The operational amplifier 12 is voltage follower connected, and the output terminal of the operational amplifier 12 is connected to the output terminal Vout. A parasitic capacitance Ci exists in the non-inverting input terminal portion of the operational amplifier 12.

次に、上述した信号ドライバ１０の基本的な動作について、図４を参照して説明する。外部から供給され、水平同期信号（１Ｈ）に同期する制御信号ＩＮＨに基づいて、スイッチＳｗａ１〜Ｓｗｂ２のＯＮ／ＯＦＦ動作が制御される。制御信号ＩＮＨの最初の立ち上がりから２番目の立ち上がりまでのサイクル１の期間中に、スイッチＳｗａ１がＯＮ、スイッチＳｗｂ１がＯＦＦすると、画像信号の電荷がスイッチＳｗａ１を介してＳ／ＨコンデンサＣ１に蓄積される。一方、このときスイッチＳｗａ２はＯＦＦ、スイッチＳｗｂ２はＯＮ状態にあるため、Ｓ／ＨコンデンサＣ２に蓄積されていた電荷に応じた信号電圧が演算増幅器１２により増幅されて出力端子Ｖｏｕｔに出力される。   Next, the basic operation of the signal driver 10 described above will be described with reference to FIG. Based on a control signal INH supplied from the outside and synchronized with the horizontal synchronization signal (1H), ON / OFF operations of the switches Swa1 to Swb2 are controlled. If the switch Swa1 is turned on and the switch Swb1 is turned off during the cycle 1 from the first rise to the second rise of the control signal INH, the charge of the image signal is accumulated in the S / H capacitor C1 via the switch Swa1. The On the other hand, since the switch Swa2 is OFF and the switch Swb2 is ON at this time, the signal voltage corresponding to the electric charge accumulated in the S / H capacitor C2 is amplified by the operational amplifier 12 and output to the output terminal Vout.

次に、制御信号ＩＮＨの２番目の立ち上がりから３番目の立ち上がりまでのサイクル２の期間中に、スイッチＳｗａ１がＯＦＦ、スイッチＳｗｂ１がＯＮすると、サイクル１においてＳ／ＨコンデンサＣ１に蓄積された電荷に応じた信号電圧が演算増幅器１２により増幅されて出力端子Ｖｏｕｔに出力される。一方、スイッチＳｗａ２はＯＮ、スイッチＳｗｂ２はＯＦＦ状態にあるため、画像信号の電荷がスイッチＳｗａ２を介してＳ／ＨコンデンサＣ２に蓄積される。続いて、サイクル３の期間では、上述したサイクル１と同様に、画像信号の電荷がスイッチＳｗａ１を介してＳ／ＨコンデンサＣ１に蓄積され、サイクル２においてＳ／ＨコンデンサＣ２に蓄積された電荷に応じた信号電圧が演算増幅器１２により増幅されて出力端子Ｖｏｕｔに出力される。このようにして、信号ドライバ１０は、液晶パネルの各信号ラインに対応して、画像信号を２系統のサンプルホールド回路により交互に取り込み、そのサンプルホールド回路から信号電圧を交互に演算増幅器１２により増幅して出力端子Ｖｏｕｔから出力し、液晶表示パネルの各液晶画素に信号電圧を印加して、画像信号に応じた表示出力を行う。   Next, when the switch Swa1 is turned off and the switch Swb1 is turned on during the cycle 2 from the second rising edge to the third rising edge of the control signal INH, the charge accumulated in the S / H capacitor C1 in the cycle 1 is changed. The corresponding signal voltage is amplified by the operational amplifier 12 and output to the output terminal Vout. On the other hand, since the switch Swa2 is ON and the switch Swb2 is in the OFF state, the charge of the image signal is accumulated in the S / H capacitor C2 via the switch Swa2. Subsequently, in the period of cycle 3, as in cycle 1 described above, the charge of the image signal is accumulated in the S / H capacitor C1 via the switch Swa1, and the charge accumulated in the S / H capacitor C2 in cycle 2 is The corresponding signal voltage is amplified by the operational amplifier 12 and output to the output terminal Vout. In this way, the signal driver 10 alternately captures image signals by the two system sample and hold circuits corresponding to each signal line of the liquid crystal panel, and alternately amplifies the signal voltage from the sample and hold circuits by the operational amplifier 12. Then, the signal is output from the output terminal Vout, a signal voltage is applied to each liquid crystal pixel of the liquid crystal display panel, and display output corresponding to the image signal is performed.

上述の信号ドライバ１０は、演算増幅器１２の非反転入力端子部分に寄生容量Ｃｉが存在するため、２系統のサンプルホールド回路のＳ／ＨコンデンサＣ１，Ｃ２に蓄積されていた電荷に応じた信号電圧がスイッチＳｗｂ１，Ｓｗｂ２のＯＮにより交互に演算増幅器１２に入力されると、前回の入力時の信号電圧により寄生容量Ｃｉに電荷が蓄積され、次回の信号電圧の入力時に寄生容量Ｃｉに蓄積されている電荷分によりＳ／ＨコンデンサＣ１，Ｃ２に蓄積されていた電荷に応じた信号電圧が変動し、演算増幅器１２に入力される信号電圧が変化し、演算増幅器１２から画像信号に応じた出力電圧が得られず、表示画質が低下する虞がある。特許文献１では、演算増幅器の入力電位を初期化するプリチャージ回路によりこの問題を解決している。
特開２０００−２０００６９号公報（図１、図５、図９、図１０） In the signal driver 10 described above, since the parasitic capacitance Ci exists in the non-inverting input terminal portion of the operational amplifier 12, the signal voltage corresponding to the charges accumulated in the S / H capacitors C1 and C2 of the two systems of sample and hold circuits. Is alternately input to the operational amplifier 12 when the switches Swb1 and Swb2 are turned on, the charge is accumulated in the parasitic capacitance Ci by the signal voltage at the previous input, and is accumulated in the parasitic capacitance Ci at the next input of the signal voltage. The signal voltage corresponding to the charges accumulated in the S / H capacitors C1 and C2 fluctuates depending on the amount of charge that is present, the signal voltage input to the operational amplifier 12 changes, and the output voltage corresponding to the image signal from the operational amplifier 12 May not be obtained, and the display image quality may deteriorate. In Patent Document 1, this problem is solved by a precharge circuit that initializes an input potential of an operational amplifier.
Japanese Unexamined Patent Publication No. 2000-200069 (FIGS. 1, 5, 9, and 10)

ところで、上述のプリチャージ回路により演算増幅器の入力電位を初期化する構成の場合、Ｓ／ＨコンデンサＣ１，Ｃ２に蓄積される電荷に応じた信号電圧が画像信号に応じて変化するのに対して、プリチャージ回路により初期化される演算増幅器の入力電位は一定であるため、その初期化された入力電位はＳ／ＨコンデンサＣ１，Ｃ２に蓄積される電荷に応じた信号電圧とは常には等しくならず、演算増幅器１２に入力される信号電圧が変化するという問題はまだ残っており、演算増幅器１２から画像信号に応じた出力電圧が得られず、表示画質が低下する虞がまだある。
従って、本発明の目的は、演算増幅器から画像信号に応じた出力電圧が得られるようにした液晶駆動装置およびその制御方法を提供することである。 By the way, in the case of the configuration in which the input potential of the operational amplifier is initialized by the precharge circuit, the signal voltage corresponding to the charges accumulated in the S / H capacitors C1 and C2 changes according to the image signal. Since the input potential of the operational amplifier initialized by the precharge circuit is constant, the initialized input potential is always equal to the signal voltage corresponding to the charges accumulated in the S / H capacitors C1 and C2. However, there still remains a problem that the signal voltage input to the operational amplifier 12 changes, and the output voltage corresponding to the image signal cannot be obtained from the operational amplifier 12, and there is still a possibility that the display image quality is deteriorated.
Accordingly, an object of the present invention is to provide a liquid crystal driving device and a control method therefor in which an output voltage corresponding to an image signal can be obtained from an operational amplifier.

本発明の液晶駆動装置は、１出力が２系統からなるサンプルホールド回路と、サンプルホールド回路の２系統に共通接続された単一の演算増幅器とを有する液晶駆動装置において、 前記サンプルホールド回路の２系統により交互にサンプルホールドされた各信号電圧を前記演算増幅器からスイッチを介して出力端子に交互に出力するとともに、前記各出力の直前の前記スイッチのＯＦＦ期間中に前記各信号電圧と同じ画像信号を前記サンプルホールド回路により再サンプリングして前記演算増幅器の入力に供給することを特徴とする。
本発明の液晶駆動装置の制御方法は、１出力が２系統からなるサンプルホールド回路と、サンプルホールド回路の２系統に共通接続された単一の演算増幅器とを有する液晶駆動装置の制御方法において、前記サンプルホールド回路の２系統によりサンプルホールドされた各信号電圧を前記演算増幅器から出力端子に出力するとき、前記各出力の直前に前記各信号電圧と同じ画像信号を前記サンプルホールド回路により再サンプリングして前記演算増幅器の入力に供給することを特徴とする。
上記手段によれば、サンプルホールド回路の２系統によりサンプルホールドされた各信号電圧を演算増幅器から出力端子に出力するとき、各出力の直前に各信号電圧と同じ画像信号をサンプルホールド回路により再サンプリングして演算増幅器に供給するので、同じ画像信号の電荷が演算増幅器の寄生容量Ｃｉに蓄積され、信号電圧が補正されて出力される。 The liquid crystal driving device according to the present invention is a liquid crystal driving device having a sample and hold circuit having one output of two systems and a single operational amplifier commonly connected to the two systems of the sample and hold circuit. Each signal voltage sampled and held alternately by the system is alternately output from the operational amplifier to the output terminal via the switch, and the same image signal as each signal voltage during the OFF period of the switch immediately before each output Is resampled by the sample and hold circuit and supplied to the input of the operational amplifier.
The control method of the liquid crystal drive device of the present invention is a control method of a liquid crystal drive device having a sample hold circuit having one output of two systems and a single operational amplifier commonly connected to the two systems of the sample hold circuit. When each signal voltage sampled and held by the two systems of the sample and hold circuit is output from the operational amplifier to the output terminal, the same image signal as the signal voltage is resampled by the sample and hold circuit immediately before each output. To the input of the operational amplifier.
According to the above means, when each signal voltage sampled and held by the two systems of the sample and hold circuit is output from the operational amplifier to the output terminal, the same image signal as each signal voltage is resampled by the sample and hold circuit immediately before each output. Therefore, the charge of the same image signal is accumulated in the parasitic capacitance Ci of the operational amplifier, and the signal voltage is corrected and output.

本発明によれば、出力の直前にサンプルホールドされた信号電圧と同じ画像信号をサンプルホールド回路により再サンプリングして演算増幅器に供給するので、再サンプリングと同時に画像信号の電荷が演算増幅器の寄生容量Ｃｉに蓄積され、演算増幅器に入力される信号電圧は補正され、液晶表示装置の表示画質の向上を図ることができる。   According to the present invention, the same image signal as the signal voltage sampled and held immediately before output is resampled by the sample and hold circuit and supplied to the operational amplifier. The signal voltage stored in Ci and input to the operational amplifier is corrected, and the display image quality of the liquid crystal display device can be improved.

以下に、本発明の一実施形態の液晶駆動装置としての信号ドライバ２０について図１を参照して説明する。図１に示す信号ドライバ２０は、信号ドライバの出力回路部を示し、演算増幅器１２の出力端子と出力端子Ｖｏｕｔ間にスイッチＳｗｄが接続されている点以外は、図３に示す信号ドライバ１０と基本的な構成が同一であり同一符号を付して、その構成の説明を省略する。   Hereinafter, a signal driver 20 as a liquid crystal driving device according to an embodiment of the present invention will be described with reference to FIG. A signal driver 20 shown in FIG. 1 shows an output circuit section of the signal driver, and is basically the same as the signal driver 10 shown in FIG. The same structure is the same, the same reference numerals are attached, and the description of the structure is omitted.

次に、上述した信号ドライバ２０の基本的な動作について、図２を参照して説明する。
外部から供給され、水平同期信号（１Ｈ）に同期する制御信号ＩＮＨに基づいて、スイッチＳｗａ１〜Ｓｗｂ２，ＳｗｄのＯＮ／ＯＦＦ動作が制御される。
（サイクル１：制御信号ＩＮＨの最初の立ち上がりエッジから２番目の立ち上がりエッジまで）サイクル１の期間中、スイッチＳｗｂ１はＯＦＦ状態である。最初の立ち上がりエッジより所定クロック遅延した時刻Ｔ１から２番目の立ち上がりエッジまでの期間中に、スイッチＳｗａ１がＯＮし、画像信号の電荷がスイッチＳｗａ１を介してＳ／ＨコンデンサＣ１に蓄積される。一方、サイクル１の期間中、スイッチＳｗｂ２はＯＮ状態にあるため、先のサイクルでＳ／ＨコンデンサＣ２に蓄積されていた電荷に応じた信号電圧が演算増幅器１２に供給され演算増幅器１２から増幅された信号電圧が出力されている状態である。この状態において、最初の立ち上がりエッジから時刻Ｔ１までの期間中に、スイッチＳｗａ２がＯＮし、先のサイクルにＳ／ＨコンデンサＣ２に電荷が蓄積されたと同じ画像信号の電荷がスイッチＳｗａ２およびスイッチＳｗｂ２を介して演算増幅器１２の寄生容量Ｃｉに蓄積されるため、演算増幅器１２に供給される信号電圧は、Ｓ／ＨコンデンサＣ２からの信号電圧が補正されていることになる。そして、制御信号ＩＮＨの最初の立ち下がりエッジでスイッチＳｗｄはＯＮし、このときからスイッチＳｗｄがＯＦＦする２番目の立ち上がりエッジまで出力端子Ｖｏｕｔから補正された信号電圧が出力される。 Next, the basic operation of the signal driver 20 described above will be described with reference to FIG.
Based on a control signal INH supplied from the outside and synchronized with the horizontal synchronization signal (1H), ON / OFF operations of the switches Swa1 to Swb2 and Swd are controlled.
(Cycle 1: From the first rising edge to the second rising edge of the control signal INH) During the cycle 1, the switch Swb1 is in the OFF state. During a period from time T1 delayed by a predetermined clock from the first rising edge to the second rising edge, the switch Swa1 is turned on, and the charge of the image signal is accumulated in the S / H capacitor C1 via the switch Swa1. On the other hand, since the switch Swb2 is in the ON state during the cycle 1, the signal voltage corresponding to the electric charge accumulated in the S / H capacitor C2 in the previous cycle is supplied to the operational amplifier 12 and amplified from the operational amplifier 12. The signal voltage is output. In this state, during the period from the first rising edge to time T1, the switch Swa2 is turned on, and the charges of the same image signal that has accumulated in the S / H capacitor C2 in the previous cycle cause the switches Swa2 and Swb2 to switch. Therefore, the signal voltage supplied to the operational amplifier 12 is corrected by the signal voltage from the S / H capacitor C2. Then, the switch Swd is turned on at the first falling edge of the control signal INH, and the corrected signal voltage is output from the output terminal Vout until the second rising edge at which the switch Swd is turned off.

（サイクル２：制御信号ＩＮＨの２番目の立ち上がりエッジから３番目の立ち上がりエッジまで）サイクル２の期間中、スイッチＳｗｂ１はＯＮ状態にあるため、サイクル１でＳ／ＨコンデンサＣ１に蓄積されていた電荷に応じた信号電圧が演算増幅器１２に供給され演算増幅器１２から増幅された信号電圧が出力されている状態である。この状態において、２番目の立ち上がりエッジから２番目の立ち上がりエッジより所定クロック遅延した時刻Ｔ２までの期間中に、スイッチＳｗａ１がＯＮし、サイクル１にＳ／ＨコンデンサＣ１に電荷が蓄積されたと同じ画像信号の電荷がスイッチＳｗａ１およびスイッチＳｗｂ１を介して演算増幅器１２の寄生容量Ｃｉに蓄積されるため、演算増幅器１２に供給される信号電圧は、Ｓ／ＨコンデンサＣ１からの信号電圧が補正されていることになる。そして、制御信号ＩＮＨの２番目の立ち下がりエッジでスイッチＳｗｄはＯＮし、このときからスイッチＳｗｄがＯＦＦする３番目の立ち上がりエッジまで出力端子Ｖｏｕｔから補正された信号電圧が出力される。一方、サイクル２の期間中、スイッチＳｗｂ２はＯＦＦ状態である。時刻Ｔ２から３番目の立ち上がりエッジまでの期間中に、スイッチＳｗａ２がＯＮし、画像信号の電荷がスイッチＳｗａ２を介してＳ／ＨコンデンサＣ２に蓄積される。   (Cycle 2: From the second rising edge to the third rising edge of the control signal INH) Since the switch Swb1 is in the ON state during the cycle 2, the charge accumulated in the S / H capacitor C1 in the cycle 1 In this state, a signal voltage corresponding to is supplied to the operational amplifier 12 and the amplified signal voltage is output from the operational amplifier 12. In this state, the switch Swa1 is turned on during the period from the second rising edge to the time T2 delayed by a predetermined clock from the second rising edge, and the same image as the charge is accumulated in the S / H capacitor C1 in the cycle 1 Since the signal charge is accumulated in the parasitic capacitance Ci of the operational amplifier 12 via the switch Swa1 and the switch Swb1, the signal voltage supplied to the operational amplifier 12 is corrected by the signal voltage from the S / H capacitor C1. It will be. Then, the switch Swd is turned on at the second falling edge of the control signal INH, and the corrected signal voltage is output from the output terminal Vout until the third rising edge at which the switch Swd is turned off. On the other hand, during the cycle 2, the switch Swb2 is in the OFF state. During the period from time T2 to the third rising edge, the switch Swa2 is turned on, and the charge of the image signal is accumulated in the S / H capacitor C2 via the switch Swa2.

（サイクル３：制御信号ＩＮＨの３番目の立ち上がりエッジから４番目の立ち上がりエッジまで）続いて、サイクル３の期間では、上述したサイクル１と同様に、３番目の立ち上がりエッジより所定クロック遅延した時刻Ｔ３から４番目の立ち上がりエッジまでの期間中に、画像信号の電荷がスイッチＳｗａ１を介してＳ／ＨコンデンサＣ１に蓄積され、サイクル２でＳ／ＨコンデンサＣ２に蓄積されていた電荷に応じた信号電圧が演算増幅器１２に供給され演算増幅器１２から増幅された信号電圧が出力されるとき、３番目の立ち上がりエッジから時刻Ｔ３までの期間中に、サイクル２にＳ／ＨコンデンサＣ２に電荷が蓄積されたと同じ画像信号の電荷がスイッチＳｗａ２およびスイッチＳｗｂ２を介して演算増幅器１２の寄生容量Ｃｉに蓄積される。このようにして、信号ドライバ２０は、液晶パネルの各信号ラインに対応して、画像信号を２系統のサンプルホールド回路１１により交互に取り込み、そのサンプルホールド回路１１から補正された信号電圧を交互に演算増幅器１２により増幅して出力端子Ｖｏｕｔから出力し、液晶表示パネルの各液晶画素に信号電圧を印加して、画像信号に応じた表示出力を行う。   (Cycle 3: From the third rising edge to the fourth rising edge of the control signal INH) Subsequently, in the period of cycle 3, time T3 delayed by a predetermined clock from the third rising edge, as in cycle 1 described above. During the period from the first rising edge to the fourth rising edge, the charge of the image signal is accumulated in the S / H capacitor C1 via the switch Swa1, and the signal voltage corresponding to the charge accumulated in the S / H capacitor C2 in cycle 2 Is supplied to the operational amplifier 12 and when the amplified signal voltage is output from the operational amplifier 12, the charge is accumulated in the S / H capacitor C2 in the cycle 2 during the period from the third rising edge to the time T3. The charge of the same image signal is transferred to the parasitic capacitance Ci of the operational amplifier 12 via the switch Swa2 and the switch Swb2. It is the product. In this way, the signal driver 20 alternately captures image signals by the two systems of sample and hold circuits 11 corresponding to each signal line of the liquid crystal panel, and alternately corrects the signal voltages corrected from the sample and hold circuits 11. Amplified by the operational amplifier 12 and output from the output terminal Vout, a signal voltage is applied to each liquid crystal pixel of the liquid crystal display panel, and display output corresponding to the image signal is performed.

以上に説明したように、Ｓ／ＨコンデンサＣ１，Ｃ２に蓄積されていた電荷に応じた信号電圧がスイッチＳｗｄのＯＮにより出力端子Ｖｏｕｔから出力されるとき、このスイッチＳｗｄのＯＮの直前のスイッチＳｗｄのＯＦＦ期間中に、Ｓ／ＨコンデンサＣ１，Ｃ２に電荷が蓄積されたと同じ画像信号の電荷がスイッチＳｗａ１，Ｓｗａ２およびスイッチＳｗｂ１，Ｓｗｂ２を介して演算増幅器１２の寄生容量Ｃｉに蓄積されるので、出力端子ＶｏｕｔからはＳ／ＨコンデンサＣ１，Ｃ２に蓄積されていた電荷に応じた信号電圧が補正されて出力される。   As described above, when the signal voltage corresponding to the electric charge accumulated in the S / H capacitors C1 and C2 is output from the output terminal Vout when the switch Swd is turned on, the switch Swd immediately before the switch Swd is turned on. Since the charge of the same image signal as the charge is accumulated in the S / H capacitors C1 and C2 is accumulated in the parasitic capacitance Ci of the operational amplifier 12 via the switches Swa1 and Swa2 and the switches Swb1 and Swb2 during the OFF period of From the output terminal Vout, the signal voltage corresponding to the charges accumulated in the S / H capacitors C1 and C2 is corrected and output.

本発明の一実施形態の液晶駆動装置としての信号ドライバ２０の回路図。The circuit diagram of the signal driver 20 as a liquid crystal drive device of one Embodiment of this invention. 図１に示す信号ドライバ２０の動作を説明するタイミングチャート。2 is a timing chart for explaining the operation of the signal driver 20 shown in FIG. 1. 従来の信号ドライバ１０の回路図。1 is a circuit diagram of a conventional signal driver 10. FIG. 図３に示す信号ドライバ１０の動作を説明するタイミングチャート。4 is a timing chart for explaining the operation of the signal driver 10 shown in FIG. 3.

符号の説明Explanation of symbols

１１ サンプルホールド回路
１２ 演算増幅器
Ｓｗａ１，Ｓｗａ２，Ｓｗｂ１，Ｓｗｂ２，Ｓｗｄ アナログスイッチ
Ｃ１，Ｃ２ Ｓ／Ｈコンデンサ 11 Sample hold circuit 12 Operational amplifier Swa1, Swa2, Swb1, Swb2, Swd Analog switch C1, C2 S / H capacitor

Claims (2)

１出力が２系統からなるサンプルホールド回路と、サンプルホールド回路の２系統に共通接続された単一の演算増幅器とを有する液晶駆動装置において、
前記サンプルホールド回路の２系統により交互にサンプルホールドされた各信号電圧を前記演算増幅器からスイッチを介して出力端子に交互に出力するとともに、前記各出力の直前の前記スイッチのＯＦＦ期間中に前記各信号電圧と同じ画像信号を前記サンプルホールド回路により再サンプリングして前記演算増幅器の入力に供給することを特徴とする液晶駆動装置。 In a liquid crystal driving device having a sample-and-hold circuit in which one output has two systems, and a single operational amplifier commonly connected to the two systems of the sample-and-hold circuit,
Each signal voltage alternately sampled and held by the two systems of the sample and hold circuit is alternately output from the operational amplifier to the output terminal via the switch, and each of the signal voltages is output during the OFF period of the switch immediately before each output. A liquid crystal driving device characterized in that the same image signal as a signal voltage is resampled by the sample and hold circuit and supplied to the input of the operational amplifier. １出力が２系統からなるサンプルホールド回路と、サンプルホールド回路の２系統に共通接続された単一の演算増幅器とを有する液晶駆動装置の制御方法において、
前記サンプルホールド回路の２系統によりサンプルホールドされた各信号電圧を前記演算増幅器から出力端子に出力するとき、前記各出力の直前に前記各信号電圧と同じ画像信号を前記サンプルホールド回路により再サンプリングして前記演算増幅器の入力に供給することを特徴とする液晶駆動装置の制御方法。 In a control method of a liquid crystal driving device having a sample-and-hold circuit having one output of two systems and a single operational amplifier commonly connected to the two systems of sample-and-hold circuits
When each signal voltage sampled and held by the two systems of the sample and hold circuit is output from the operational amplifier to the output terminal, the same image signal as the signal voltage is resampled by the sample and hold circuit immediately before each output. And supplying to the input of the operational amplifier.
JP2003302934A 2003-08-27 2003-08-27 Liquid crystal driving device and control method thereof Pending JP2005070627A (en)

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100670494B1 (en) 2005-04-26 2007-01-16 매그나칩 반도체 유한회사 Driving circuit and driving method of liquid crystal display divice
KR100776489B1 (en) * 2006-02-09 2007-11-16 삼성에스디아이 주식회사 Data driver and driving method thereof
KR100805587B1 (en) 2006-02-09 2008-02-20 삼성에스디아이 주식회사 Digital-Analog Converter and Data driver, Flat Panel Display device using thereof
US7564393B2 (en) 2007-02-13 2009-07-21 Samsung Electronics Co., Ltd. Digital to analog converter and method for digital to analog conversion
US8059140B2 (en) 2006-02-09 2011-11-15 Samsung Mobile DIsplay Co., Inc. Data driver and flat panel display device using the same
US8619013B2 (en) 2006-01-20 2013-12-31 Samsung Display Co., Ltd. Digital-analog converter, data driver, and flat panel display device using the same
JP2015002507A (en) * 2013-06-18 2015-01-05 凸版印刷株式会社 Switch circuit
JP2015073148A (en) * 2013-10-01 2015-04-16 セイコーＮｐｃ株式会社 Sample-and-hold circuit

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100670494B1 (en) 2005-04-26 2007-01-16 매그나칩 반도체 유한회사 Driving circuit and driving method of liquid crystal display divice
US7990351B2 (en) 2005-04-26 2011-08-02 Magnachip Semiconductor Ltd. Driving circuit for liquid crystal display device
US8619013B2 (en) 2006-01-20 2013-12-31 Samsung Display Co., Ltd. Digital-analog converter, data driver, and flat panel display device using the same
KR100776489B1 (en) * 2006-02-09 2007-11-16 삼성에스디아이 주식회사 Data driver and driving method thereof
KR100805587B1 (en) 2006-02-09 2008-02-20 삼성에스디아이 주식회사 Digital-Analog Converter and Data driver, Flat Panel Display device using thereof
US7944458B2 (en) 2006-02-09 2011-05-17 Samsung Mobile Display Co., Ltd. Digital-analog converter, data driver, and flat panel display device using the same
US8059140B2 (en) 2006-02-09 2011-11-15 Samsung Mobile DIsplay Co., Inc. Data driver and flat panel display device using the same
US7564393B2 (en) 2007-02-13 2009-07-21 Samsung Electronics Co., Ltd. Digital to analog converter and method for digital to analog conversion
KR100911652B1 (en) * 2007-02-13 2009-08-10 삼성전자주식회사 Integrated circuit, source driver having the same, and display device having the source driver
JP2015002507A (en) * 2013-06-18 2015-01-05 凸版印刷株式会社 Switch circuit
JP2015073148A (en) * 2013-10-01 2015-04-16 セイコーＮｐｃ株式会社 Sample-and-hold circuit

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