JP2005033130A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2005033130A
JP2005033130A JP2003273455A JP2003273455A JP2005033130A JP 2005033130 A JP2005033130 A JP 2005033130A JP 2003273455 A JP2003273455 A JP 2003273455A JP 2003273455 A JP2003273455 A JP 2003273455A JP 2005033130 A JP2005033130 A JP 2005033130A
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film
electrode
semiconductor
substrate
semiconductor wafer
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JP3767585B2 (en
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Ichiji Kondo
市治 近藤
Keiji Mayama
恵次 真山
Shoji Miura
昭二 三浦
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Denso Corp
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Denso Corp
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  • Engineering & Computer Science (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To prevent a semiconductor wafer from being warped to an utmost in manufacturing in a semiconductor chip wherein a metal electrode including an external connection Ni film is provided on an Al electrode formed on the front surface of a semiconductor substrate, and a rear electrode is provided on the rear surface of the semiconductor substrate. <P>SOLUTION: In the semiconductor chip wherein an Al electrode 11 is provided on a front surface 1a, which is an element formation surface, of a semiconductor substrate 1 and a rear electrode 4 is formed on the rear surface 1b of the semiconductor substrate 1, a metal electrode 13 configured by laminating an Ni plating layer 13a and an Au plating layer 13b successively from the side of a front surface is formed on the front surface of the Al electrode 11, the rear electrode 4 is composed of an Ni film 4b formed by physical vapor deposition, and the film stress of the Ni film 4b is three-times or more as large as the film stress of the Ni plating layer 13a in the metal electrode 13. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体基板の表面に形成されたアルミニウム電極の表面に対してはんだ付けやワイヤボンディング等が行われる外部接続用の金属電極を形成するとともに、半導体基板の裏面に裏面電極を形成してなる半導体装置に関し、例えば、ＩＧＢＴ（絶縁ゲート型バイポーラトランジスタ）等のパワー素子等に好適である。   The present invention forms a metal electrode for external connection that is soldered or wire bonded to the surface of an aluminum electrode formed on the surface of a semiconductor substrate, and forms a back electrode on the back surface of the semiconductor substrate. For example, the semiconductor device is suitable for a power element such as an IGBT (Insulated Gate Bipolar Transistor).

この種の半導体装置としては、例えば、ＩＧＢＴ等、半導体基板の素子形成面である基板表面にアルミニウム電極を形成し、基板裏面に裏面電極を形成し、表面側のアルミニウム電極に対してヒートシンク等をはんだ付けするようにしたものが提案されている（例えば、特許文献１、特許文献２参照）。   As this type of semiconductor device, for example, an IGBT, such as an IGBT, is formed with an aluminum electrode on the substrate surface, which is an element formation surface of the semiconductor substrate, a back electrode is formed on the back surface of the substrate, A soldering type has been proposed (see, for example, Patent Document 1 and Patent Document 2).

このような半導体装置の場合、フリップチップ技術のバンプ電極（例えば、特許文献３参照）を応用して、半導体基板の基板表面上において、アルミニウム電極の上に保護膜を形成し、この保護膜に開口部を形成した後、この開口部から臨むアルミニウム電極の表面上に、はんだ付け用の金属電極をメッキにより形成することが望まれる。
特開２００２−１１０８９３号公報 特開２００３−１１００６４号公報 特開昭６３−３０５５３２号公報 In the case of such a semiconductor device, a bump electrode of flip chip technology (for example, see Patent Document 3) is applied, and a protective film is formed on the aluminum electrode on the surface of the semiconductor substrate. After forming the opening, it is desired to form a metal electrode for soldering on the surface of the aluminum electrode facing the opening by plating.
JP 2002-110893 A JP 2003-110064 A JP-A 63-305532

本発明者らは、この種の半導体装置について試作検討を行った。図１１は、本発明者らの試作品としての半導体装置の要部を示す概略断面図である。   The inventors of the present invention conducted a trial production of this type of semiconductor device. FIG. 11 is a schematic cross-sectional view showing a main part of a semiconductor device as a prototype of the present inventors.

このような半導体装置は、シリコン半導体等からなる半導体ウェハにおいて、チップ単位毎に、周知の半導体プロセス技術を用いて製造され、ダイシングカット等により最終的にチップに分断されることで形成される。   Such a semiconductor device is formed in a semiconductor wafer made of a silicon semiconductor or the like by using a well-known semiconductor process technology for each chip unit and finally divided into chips by dicing cut or the like.

すなわち、熱拡散やイオン注入等により半導体基板１の基板表面１ａに素子（図示せず）を形成するとともに、アルミニウム（以下、Ａｌという）からなるＡｌ電極１１を形成する。   That is, an element (not shown) is formed on the substrate surface 1a of the semiconductor substrate 1 by thermal diffusion, ion implantation, or the like, and an Al electrode 11 made of aluminum (hereinafter referred to as Al) is formed.

その上に、ポリイミド等からなる保護膜１２を形成するとともに、この保護膜１２に開口部１２ａを形成する。そして、この開口部１２ａから臨むＡｌ電極１１の表面上に、はんだ付け用の金属電極１３をメッキ等により形成する。   A protective film 12 made of polyimide or the like is formed thereon, and an opening 12a is formed in the protective film 12. Then, a metal electrode 13 for soldering is formed on the surface of the Al electrode 11 facing the opening 12a by plating or the like.

ここで、金属電極１３は無電解メッキを行うことにより、下側からニッケル（Ｎｉ）メッキ層１３ａ、金（Ａｕ）メッキ層１３ｂが積層された無電解Ｎｉ／Ａｕメッキ膜として構成した。一方、半導体基板１の基板裏面１ｂには、スパッタ等の物理的気相成長法によりＮｉ膜を含む膜からなる裏面電極４が形成される。   Here, the metal electrode 13 is configured as an electroless Ni / Au plating film in which a nickel (Ni) plating layer 13a and a gold (Au) plating layer 13b are laminated from the lower side by performing electroless plating. On the other hand, a back electrode 4 made of a film containing a Ni film is formed on the substrate back surface 1b of the semiconductor substrate 1 by a physical vapor deposition method such as sputtering.

このようなはんだ付け用の金属電極１３は、マスクを用いずに無電解Ｎｉ／Ａｕメッキにより形成することができるため、低コストであるというメリットがある。しかし、一方では、金属電極１３に対してはんだ６０を接合するため、金属電極１３におけるＮｉメッキ層１３ａの膜厚が大きいものとなる。例えば、Ｎｉメッキ層１３ａの膜厚は５μｍ程度となる。   Since such a metal electrode 13 for soldering can be formed by electroless Ni / Au plating without using a mask, there is an advantage that the cost is low. However, on the other hand, since the solder 60 is joined to the metal electrode 13, the thickness of the Ni plating layer 13a in the metal electrode 13 is large. For example, the film thickness of the Ni plating layer 13a is about 5 μm.

これは、はんだ６０を構成する金属（例えばＳｎ）のＮｉメッキ層１３ａへの拡散が生じ、Ｎｉとはんだ構成金属との合金層が形成されることではんだ接合がなされることによる。つまり、金属電極１３におけるＮｉメッキ層１３ａが薄いものであると、はんだ接合の強度が不十分となってしまう。   This is because the metal constituting the solder 60 (for example, Sn) diffuses into the Ni plating layer 13a, and the solder layer is formed by forming an alloy layer of Ni and the solder constituent metal. In other words, if the Ni plating layer 13a in the metal electrode 13 is thin, the strength of the solder joint will be insufficient.

このようなＮｉメッキ層１３ａは、膜応力が引っ張り応力であるうえに、その膜厚が大きいので、Ｎｉメッキ層１３ａの全応力が大きいものとなる。その結果、半導体装置の製造工程において、金属電極１３の形成後に、半導体ウェハは、金属電極１３側すなわち基板表面１ａ側が凹となり基板裏面１ｂ側が凸となるように大きく反ることになる。   Such a Ni plating layer 13a has not only a tensile stress but also a large film thickness, so that the total stress of the Ni plating layer 13a is large. As a result, in the manufacturing process of the semiconductor device, after the formation of the metal electrode 13, the semiconductor wafer is greatly warped so that the metal electrode 13 side, that is, the substrate surface 1a side is concave and the substrate back surface 1b side is convex.

このような半導体ウェハにおける大きな反りは、本発明者らの検討では、数ｍｍ程度にも及んでおり、後工程での処理、検査に不具合を生じる。さらに、半導体ウェハをダイシングカットしてチップとした後においても、上記反りの影響が及ぶため、半導体装置の実装時等においても不具合が発生する。   Such a large warp in the semiconductor wafer reaches about several millimeters in the study by the present inventors, and causes a problem in processing and inspection in a later process. Further, even after the semiconductor wafer is diced and cut into chips, the influence of the warp is exerted, and thus a problem occurs even when the semiconductor device is mounted.

そこで本発明は上記問題に鑑み、半導体基板の基板表面に形成されたＡｌ電極の上に外部接続用のＮｉ膜を含む金属電極を設け、半導体基板の基板裏面に裏面電極を設けてなる半導体装置において、製造時における半導体ウェハの反りを極力抑制できるようにすることを目的とする。   In view of the above problems, the present invention provides a semiconductor device in which a metal electrode including a Ni film for external connection is provided on an Al electrode formed on a substrate surface of a semiconductor substrate, and a back electrode is provided on the back surface of the semiconductor substrate. It is an object of the present invention to make it possible to suppress the warpage of the semiconductor wafer during manufacturing as much as possible.

上記目的を達成するため、鋭意検討した結果、裏面電極にＮｉ膜を用いるようにし、この基板表面のＮｉ膜と基板裏面のＮｉ膜との膜応力のバランスを考慮すれば、半導体ウェハの反りを従来に比べて大幅に低減できることを実験的に見いだした。   In order to achieve the above object, as a result of intensive studies, a Ni film is used for the back electrode, and if the balance of the film stress between the Ni film on the substrate surface and the Ni film on the substrate back surface is taken into account, the warpage of the semiconductor wafer can be reduced. We have found experimentally that it can be significantly reduced compared to the prior art.

本発明者らの検討によれば、半導体装置の製造工程において、汎用装置を用いた場合には、半導体ウェハの反りは１ｍｍ以下に抑えることが望ましい。   According to the study by the present inventors, when a general-purpose device is used in the semiconductor device manufacturing process, it is desirable to suppress the warpage of the semiconductor wafer to 1 mm or less.

また、本発明者らが、半導体ウェハの反りに対応した治具、すなわち反り対応の専用装置を作製し、この専用装置を用いて適切に半導体装置の製造を行うようにした場合であっても、適切に対応可能な半導体ウェハの反りの大きさは、せいぜい３ｍｍ以下である。   Further, even when the present inventors have produced a jig corresponding to warpage of a semiconductor wafer, that is, a dedicated device for warping, and appropriately manufactured a semiconductor device using this dedicated device. The warp size of a semiconductor wafer that can be appropriately handled is at most 3 mm or less.

つまり、半導体ウェハの反りは最悪でも３ｍｍ以下程度に抑えることが望ましい。そして、製造時における半導体ウェハの反りを３ｍｍ以下に抑えることを指標として、実験検討した結果、当該指標を満足するような半導体基板の基板表面のＮｉ膜の膜応力と基板裏面のＮｉ膜の膜応力との関係を実験的に見出した。その知見に基づいて本発明が創出されたのである。   That is, it is desirable to suppress the warpage of the semiconductor wafer to about 3 mm or less at the worst. Then, as a result of conducting an experimental study with an index of suppressing the warpage of the semiconductor wafer during manufacturing to 3 mm or less, the film stress of the Ni film on the substrate surface of the semiconductor substrate and the film of the Ni film on the back surface of the substrate satisfying the index. The relationship with stress was found experimentally. The present invention has been created based on this knowledge.

すなわち、請求項１に記載の発明では、半導体基板（１）における素子が形成された面である基板表面（１ａ）にＡｌからなるＡｌ電極（１１）を備え、前記半導体基板における前記基板表面とは反対側の基板裏面（１ｂ）に裏面電極（４）を備えてなる半導体装置において、前記Ａｌ電極の表面には、メッキ形成されたＮｉメッキ層（１３ａ）を含む外部接続用の金属電極（１３）が形成されており、前記裏面電極は物理的気相成長法により形成されたＮｉ膜（４ｂ）を含み、前記Ｎｉ膜の膜応力が前記金属電極における前記Ｎｉメッキ層の膜応力の３倍以上であることを特徴とする。   That is, according to the first aspect of the present invention, an Al electrode (11) made of Al is provided on a substrate surface (1a) which is a surface on which an element is formed in the semiconductor substrate (1), and the substrate surface in the semiconductor substrate is In the semiconductor device having the back electrode (4) on the opposite substrate back surface (1b), an external connection metal electrode including a plated Ni plating layer (13a) is formed on the surface of the Al electrode. 13), the back electrode includes a Ni film (4b) formed by physical vapor deposition, and the film stress of the Ni film is 3 of the film stress of the Ni plating layer in the metal electrode. It is characterized by being more than double.

ここで、膜応力としては、一般に知られているように、内部応力（単位：ＰａまたはＮ／ｍ2）と、この内部応力に膜の膜厚を乗じた全応力（単位：Ｎ／ｍ）とがあるが、本発明では、膜応力とは、内部応力のことである。 Here, as generally known, the film stress is an internal stress (unit: Pa or N / m 2 ) and a total stress (unit: N / m) obtained by multiplying the internal stress by the film thickness of the film. However, in the present invention, the film stress is an internal stress.

このように、裏面電極（４）を物理的気相成長法により形成されたＮｉ膜（４ｂ）からなるものとし、当該Ｎｉ膜の膜応力を金属電極（１３）におけるＮｉメッキ層（１３ａ）の膜応力の３倍以上とすれば、製造時における半導体ウェハ（１００）の反りを３ｍｍ以下に抑えることができる（図８参照）。   As described above, the back electrode (4) is made of the Ni film (4b) formed by physical vapor deposition, and the film stress of the Ni film is measured on the Ni plating layer (13a) of the metal electrode (13). If the film stress is three times or more, the warp of the semiconductor wafer (100) during manufacturing can be suppressed to 3 mm or less (see FIG. 8).

よって、本発明によれば、従来に比べて製造時における半導体ウェハ（１００）の反りを極力抑制することができる。   Therefore, according to this invention, the curvature of the semiconductor wafer (100) at the time of manufacture can be suppressed as much as possible compared with the past.

ここで、請求項２に記載の発明のように、裏面電極（４）のＮｉ膜（４ｂ）の膜応力を２．７×１０8Ｐａ以上とし、金属電極（１３）におけるＮｉメッキ層（１３ａ）の膜応力を８．９×１０7Ｐａ以下とすることができる。 Here, as in the invention described in claim 2, the film stress of the Ni film (4b) of the back electrode (4) is set to 2.7 × 10 8 Pa or more, and the Ni plating layer (13a) in the metal electrode (13) is formed. ) Film stress of 8.9 × 10 7 Pa or less.

それによれば、裏面電極（４）のＮｉ膜（４ｂ）の膜応力を金属電極（１３）におけるＮｉメッキ層（１３ａ）の膜応力の３倍以上とすることを、適切に実現することができる。   According to this, it is possible to appropriately realize the film stress of the Ni film (4b) of the back electrode (4) to be three times or more of the film stress of the Ni plating layer (13a) of the metal electrode (13). .

請求項３に記載の発明では、請求項１または２に記載の半導体装置において、前記半導体基板（１）の厚さが２００μｍ以下であることを特徴とする。   According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the thickness of the semiconductor substrate (1) is 200 μm or less.

このように、半導体基板（１）の厚さすなわち半導体ウェハ（１００）の厚さが２００μｍ以下と薄い場合、半導体ウェハの反りが生じやすい。そのような場合に対して、請求項１に記載の手段を採用することは、効果的である。   Thus, when the thickness of the semiconductor substrate (1), that is, the thickness of the semiconductor wafer (100) is as thin as 200 μm or less, the warp of the semiconductor wafer is likely to occur. In such a case, it is effective to adopt the means described in claim 1.

請求項４に記載の発明では、請求項１〜請求項３に記載の半導体装置において、前記半導体基板（１）の前記基板表面（１ａ）の全面積に対する前記Ａｌ電極（１１）の占める占有面積の比率が３０％以上であることを特徴とする。   According to a fourth aspect of the present invention, in the semiconductor device according to the first to third aspects, the Al electrode (11) occupies the entire area of the substrate surface (1a) of the semiconductor substrate (1). The ratio is 30% or more.

このように、半導体基板（１）の基板表面（１ａ）全域に対するＡｌ電極（１１）の占有率が３０％以上である場合、半導体基板の基板表面において、Ｎｉメッキ層（１３ａ）もその占有率に近い比率で多く存在することになり、半導体ウェハ（１００）の反りが大きくなりやすい。そのような場合に対して、請求項１に記載の手段を採用することは、効果的である。   Thus, when the occupation rate of the Al electrode (11) over the entire substrate surface (1a) of the semiconductor substrate (1) is 30% or more, the Ni plating layer (13a) is also occupied on the substrate surface of the semiconductor substrate. Therefore, the warpage of the semiconductor wafer (100) tends to increase. In such a case, it is effective to adopt the means described in claim 1.

また、請求項５に記載の発明では、請求項１ないし４のいずれか一つに記載の半導体装置において、前記金属電極（１３）上にはＳｎを主成分とするはんだが接続されるものであり、前記ニッケルメッキ層（１３ａ）の膜厚は少なくとも５μｍ程度以上に調整されていることを特徴としている。   According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, a solder containing Sn as a main component is connected to the metal electrode (13). The thickness of the nickel plating layer (13a) is adjusted to at least about 5 μm or more.

なお、上記各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示す一例である。   In addition, the code | symbol in the bracket | parenthesis of each said means is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.

以下、本発明を図に示す実施形態について説明する。図１は、本発明の実施形態に係る半導体装置１０を用いた実装構造を示す概略断面図である。また、図２は、本実施形態の要部拡大図であって、（ａ）は図１中の半導体装置１０におけるエミッタ電極２の近傍部の拡大断面図、（ｂ）は図１中の半導体装置１０におけるコレクタ電極４の一部を拡大して示す概略断面図である。   DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments shown in the drawings will be described below. FIG. 1 is a schematic cross-sectional view showing a mounting structure using a semiconductor device 10 according to an embodiment of the present invention. 2 is an enlarged view of the main part of the present embodiment, where (a) is an enlarged cross-sectional view of the vicinity of the emitter electrode 2 in the semiconductor device 10 in FIG. 1, and (b) is the semiconductor in FIG. FIG. 2 is a schematic cross-sectional view showing a part of a collector electrode 4 in the device 10 in an enlarged manner.

図１に示すように、本実施形態では、半導体装置としては、ＩＧＢＴ（絶縁ゲート型バイポーラトランジスタの略称）が形成された半導体チップ１０を採用したものとしている。   As shown in FIG. 1, in this embodiment, a semiconductor chip 10 on which an IGBT (abbreviation of an insulated gate bipolar transistor) is formed is used as a semiconductor device.

そして、この半導体チップ１０の実装形態としては、半導体チップ１０をその両面にはんだ付けされたヒートシンク２０、３０、４０によって挟み込み、さらに樹脂５０にてモールドした構成としている。以下、この実装形態を両面はんだ付けモールド構造ということにする。   As a mounting form of the semiconductor chip 10, the semiconductor chip 10 is sandwiched between the heat sinks 20, 30, and 40 soldered to both surfaces and further molded with the resin 50. Hereinafter, this mounting form is referred to as a double-sided soldering mold structure.

半導体チップ１０は、シリコン半導体等の半導体基板１を本体として構成されている。この半導体基板１の厚みは例えば７０μｍ〜４００μｍ程度のものにすることができる。なお、半導体基板１の厚さは、半導体ウェハの状態で研削等を行うことにより調整できる。   The semiconductor chip 10 is configured with a semiconductor substrate 1 such as a silicon semiconductor as a main body. The thickness of the semiconductor substrate 1 can be, for example, about 70 μm to 400 μm. Note that the thickness of the semiconductor substrate 1 can be adjusted by grinding or the like in the state of the semiconductor wafer.

以下、半導体チップ１０すなわち半導体基板１の外表面のうち、図１中の上面側に相当する素子形成面側の面を基板表面１ａといい、一方、半導体チップ１０すなわち半導体基板１の外表面のうち、上記基板表面１ａとは反対側の面（図１中の下面側に相当）を基板裏面１ｂという。   Hereinafter, of the outer surfaces of the semiconductor chip 10, that is, the semiconductor substrate 1, the surface on the element forming surface side corresponding to the upper surface side in FIG. Of these, the surface opposite to the substrate surface 1a (corresponding to the lower surface side in FIG. 1) is referred to as substrate back surface 1b.

なお、図示しないが、半導体基板１の基板表面１ａ側には、熱拡散やイオン注入等により不純物拡散層が形成されることにより、トランジスタ等の素子が形成されている。   Although not shown, an element such as a transistor is formed on the substrate surface 1a side of the semiconductor substrate 1 by forming an impurity diffusion layer by thermal diffusion, ion implantation, or the like.

そして、半導体チップ１０の基板表面１ａにはエミッタ電極２およびゲート電極３が形成されており、基板表面１ａとは反対側の基板裏面１ｂには裏面電極としてのコレクタ電極４が形成されている。   An emitter electrode 2 and a gate electrode 3 are formed on the substrate surface 1a of the semiconductor chip 10, and a collector electrode 4 as a back electrode is formed on the substrate back surface 1b opposite to the substrate surface 1a.

ここで、エミッタ電極２には、はんだ６０を介して第１のヒートシンク２０が接合されており、さらに、第１のヒートシンク２０の外側には、はんだ６０を介して第２のヒートシンク３０が接合されている。   Here, the first heat sink 20 is joined to the emitter electrode 2 via the solder 60, and the second heat sink 30 is joined to the outside of the first heat sink 20 via the solder 60. ing.

また、ゲート電極３にはボンディングワイヤ７０が接続されており、このボンディングワイヤ７０を介して、ゲート電極３と半導体チップ１０の周辺に設けられた外部接続用のリード８０とが結線され電気的に接続されている。   A bonding wire 70 is connected to the gate electrode 3, and the gate electrode 3 and an external connection lead 80 provided around the semiconductor chip 10 are connected via the bonding wire 70 to be electrically connected. It is connected.

また、コレクタ電極４は、はんだ６０を介して第３のヒートシンク４０と接合されている。ここで、はんだ６０としては、鉛フリーはんだが用いられるが、例えば、鉛フリーはんだとしては、Ｓｎ−Ａｇ−Ｃｕ系はんだやＳｎ−Ｎｉ−Ｃｕ系はんだ等、Ｓｎを主成分とするはんだを採用することができる。   Further, the collector electrode 4 is joined to the third heat sink 40 via the solder 60. Here, lead-free solder is used as the solder 60. For example, Sn-Ag-Cu solder or Sn-Ni-Cu solder such as Sn-Ag-Cu solder is used as the lead-free solder. can do.

また、ヒートシンク２０、３０、４０は銅（Ｃｕ）等の熱伝導性に優れた材料からなるものである。ボンディングワイヤ７０は、一般的なＡｌや金（Ａｕ）等からなるワイヤをワイヤボンディング法により形成したものである。   The heat sinks 20, 30, and 40 are made of a material having excellent thermal conductivity such as copper (Cu). The bonding wire 70 is formed by forming a wire made of general Al, gold (Au), or the like by a wire bonding method.

ここで、エミッタ電極２およびゲート電極３の詳細な構成は図２（ａ）に示される。図２（ａ）はエミッタ電極２を表しているが、ゲート電極３についても、接続相手がはんだ６０とボンディングワイヤ７０との違いはあるものの、当該エミッタ電極２と同様の構成となっている。   Here, the detailed structure of the emitter electrode 2 and the gate electrode 3 is shown by Fig.2 (a). Although FIG. 2A shows the emitter electrode 2, the gate electrode 3 has the same configuration as the emitter electrode 2, although the connection partner is a solder 60 and a bonding wire 70.

図２（ａ）に示すように、半導体基板１の基板表面１ａ上に、ＡｌからなるＡｌ電極１１が形成されている。Ａｌ電極１１は、蒸着やスパッタ等の物理的気相成長法（ＰＶＤ法）により形成されたＡｌの膜であり、例えば、膜厚は５μｍ程度のものとすることができる。   As shown in FIG. 2A, an Al electrode 11 made of Al is formed on the substrate surface 1 a of the semiconductor substrate 1. The Al electrode 11 is an Al film formed by physical vapor deposition (PVD method) such as vapor deposition or sputtering. For example, the film thickness can be about 5 μm.

このＡｌ電極１１の上には、電気絶縁性材料からなる保護膜１２が形成されている。この保護膜１２は、例えばポリイミド系樹脂等の電気絶縁性材料を用いたスピンコート法により成膜することができる。   A protective film 12 made of an electrically insulating material is formed on the Al electrode 11. The protective film 12 can be formed by a spin coating method using an electrically insulating material such as a polyimide resin.

また、この保護膜１２には、Ａｌ電極１１の表面を開口させる開口部１２ａが形成されている。この開口部１２ａは、例えばフォトリソグラフ技術を用いたエッチングを行うことにより形成することができる。   In addition, an opening 12 a that opens the surface of the Al electrode 11 is formed in the protective film 12. The opening 12a can be formed, for example, by performing etching using a photolithography technique.

そして、開口部１２ａから臨むＡｌ電極１１の表面上には、金属電極１３が形成されている。この金属電極１３は外部接続用の電極であって、エミッタ電極２においてははんだ付け用のものとして構成され、ゲート電極３においてはワイヤボンディング用のものとして構成されている。   A metal electrode 13 is formed on the surface of the Al electrode 11 facing the opening 12a. The metal electrode 13 is an electrode for external connection. The emitter electrode 2 is configured for soldering, and the gate electrode 3 is configured for wire bonding.

本実施形態では、金属電極１３は、Ａｌ電極１１の表面側からＮｉメッキ層１３ａ、Ａｕメッキ層１３ｂが順次無電解メッキにより形成され積層されてなる膜すなわち無電解Ｎｉ／Ａｕメッキ膜としている。メッキ形成時の各膜厚は、例えば、Ｎｉメッキ層１３ａは、少なくとも５μｍ程度にすることができ、Ａｕメッキ層１３ｂは、０．１μｍ程度にすることができる。   In this embodiment, the metal electrode 13 is a film in which a Ni plating layer 13a and an Au plating layer 13b are sequentially formed from the surface side of the Al electrode 11 by electroless plating, that is, an electroless Ni / Au plating film. For example, the Ni plating layer 13a can have a thickness of about 5 μm and the Au plating layer 13b can have a thickness of about 0.1 μm.

このように、本実施形態では、エミッタ電極２およびゲート電極３は、Ａｌ電極１１と無電解Ｎｉ／Ａｕメッキ膜である金属電極１３との積層膜として構成されたものとなっている。   Thus, in this embodiment, the emitter electrode 2 and the gate electrode 3 are comprised as a laminated film of the Al electrode 11 and the metal electrode 13 which is an electroless Ni / Au plating film.

また、図１において、半導体基板１の基板裏面１ｂに形成され第３のヒートシンク４０とはんだ付けされているコレクタ電極４は、裏面電極として構成されるものであって、基板裏面１ｂの略全面にスパッタや蒸着等の物理的気相成長法（ＰＶＤ法）により形成されたＮｉ膜からなる。   Further, in FIG. 1, the collector electrode 4 formed on the substrate back surface 1b of the semiconductor substrate 1 and soldered to the third heat sink 40 is configured as a back surface electrode, and is formed on the substantially entire surface of the substrate back surface 1b. It consists of a Ni film formed by a physical vapor deposition method (PVD method) such as sputtering or vapor deposition.

ここで、コレクタ電極４がＮｉ膜からなることとは、コレクタ電極４がＮｉ膜のみからなるものでもよいし、Ｎｉ膜と他の膜との積層膜からなるものでもよいことを意味している。   Here, the collector electrode 4 being made of a Ni film means that the collector electrode 4 may be made of only a Ni film or a laminated film of a Ni film and another film. .

図２（ｂ）では、上記図１に示す半導体チップ１０において本例のコレクタ電極４の一部が拡大して示されている。本例では、半導体基板１の基板裏面１ｂにはスパッタにより成膜されたＡｌ膜５が設けられており、コレクタ電極４は、このＡｌ膜５の表面に形成されている。   FIG. 2B shows an enlarged part of the collector electrode 4 of the present example in the semiconductor chip 10 shown in FIG. In this example, an Al film 5 formed by sputtering is provided on the substrate back surface 1 b of the semiconductor substrate 1, and the collector electrode 4 is formed on the surface of the Al film 5.

具体的には、本例の裏面電極は、基板裏面１ｂ側から順次、Ａｌ（アルミ）膜５、コレクタ電極４を構成するＴｉ（チタン）膜４ａ、Ｎｉ膜４ｂ、Ａｕ膜４ｃが、各々スパッタにより積層形成されたＡｌ／Ｔｉ／Ｎｉ／Ａｕ膜としている。   Specifically, the back electrode of this example is formed by sequentially forming an Al (aluminum) film 5 and a Ti (titanium) film 4a, a Ni film 4b, and an Au film 4c constituting the collector electrode 4 from the substrate back surface 1b side. Thus, an Al / Ti / Ni / Au film is formed by lamination.

これら裏面電極における各膜の膜厚は、形成時において、例えば、Ａｌ（アルミ）膜５は２００〜２５０ｎｍ程度、Ｔｉ（チタン）膜４ａは２００〜２５０ｎｍ程度、Ｎｉ膜４ｂは５５０〜６８０ｎｍ程度、Ａｕ膜４ｃは１００〜１２０ｎｍ程度の膜厚とすることができる。   The film thickness of each film on these back electrodes is, for example, about 200 to 250 nm for the Al (aluminum) film 5, about 200 to 250 nm for the Ti (titanium) film 4 and about 550 to 680 nm for the Ni film 4b. The Au film 4c can have a thickness of about 100 to 120 nm.

本実施形態では、このように基板表面１ａ側の金属電極１３および裏面電極としてのコレクタ電極４において、ともにＮｉ膜を構成要素としている。   In this embodiment, both the metal electrode 13 on the substrate surface 1a side and the collector electrode 4 serving as the back electrode use Ni films as constituent elements.

そして、ここにおいて、裏面電極であるコレクタ電極４のＮｉ膜４ｂの膜応力を金属電極１３におけるＮｉメッキ層１３ａの膜応力の３倍以上としている。   Here, the film stress of the Ni film 4 b of the collector electrode 4, which is the back electrode, is set to three times or more of the film stress of the Ni plating layer 13 a in the metal electrode 13.

ここで、膜応力としては、一般に知られているように、内部応力（単位：ＰａまたはＮ／ｍ2）と、この内部応力に膜の膜厚を乗じた全応力（単位：Ｎ／ｍ）とがあるが、本実施形態では、膜応力とは、内部応力のことである。 Here, as generally known, the film stress is an internal stress (unit: Pa or N / m 2 ) and a total stress (unit: N / m) obtained by multiplying the internal stress by the film thickness of the film. In this embodiment, the film stress is an internal stress.

そして、この膜応力は周知の方法で求められる。すなわち、測定すべき膜を例えば半導体ウェハの一面に形成し、その半導体ウェハの反りを求め、この求められた反りからストーニーの式を用いて容易に算出することができる。なお、半導体ウェハ１００の反った状態およびその反りｔは、図３に示される。   And this film | membrane stress is calculated | required by a known method. That is, for example, a film to be measured can be formed on one surface of a semiconductor wafer, the warpage of the semiconductor wafer can be obtained, and the calculated warpage can be easily calculated using the Stony equation. The warped state of the semiconductor wafer 100 and the warp t are shown in FIG.

具体的には、コレクタ電極４のＮｉ膜４ｂの膜応力を２．７×１０8Ｐａ以上とし、金属電極１３におけるＮｉメッキ層１３ａの膜応力を８．９×１０7Ｐａ以下とすることで、上記膜応力の関係が適切に実現される。 Specifically, the film stress of the Ni film 4b of the collector electrode 4 is set to 2.7 × 10 8 Pa or more, and the film stress of the Ni plating layer 13a in the metal electrode 13 is set to 8.9 × 10 7 Pa or less. The relationship of the film stress is appropriately realized.

ここで、Ｎｉメッキ層１３ａの膜応力を変えることは、例えば、メッキに用いる添加剤の量を調整することで容易に可能である。また、コレクタ電極４のＮｉ膜４ｂの膜応力は、その膜密度を変えることで可能である。そして、コレクタ電極４におけるＮｉ膜４ｂの膜密度を変えることは、例えばスパッタにおけるアルゴン圧を変えることで容易に可能である。   Here, it is possible to easily change the film stress of the Ni plating layer 13a by adjusting the amount of the additive used for plating, for example. The film stress of the Ni film 4b of the collector electrode 4 can be changed by changing the film density. The film density of the Ni film 4b in the collector electrode 4 can be easily changed, for example, by changing the argon pressure in sputtering.

また、半導体チップ１０においては、基板表面１ａ側の電極２、３は、パターニングされた形状であるが、基板裏面１ｂ側のコレクタ電極４は、基板裏面１ｂのほぼ全域に形成されている。   In the semiconductor chip 10, the electrodes 2 and 3 on the substrate surface 1 a side have a patterned shape, but the collector electrode 4 on the substrate back surface 1 b side is formed almost over the entire substrate back surface 1 b.

図４は、半導体チップ１０における基板表面１ａ側からみたときのエミッタ電極２およびゲート電極３におけるＡｌ電極１１の平面パターンの一例を示す平面図であり、Ａｌ電極１１の表面には便宜上ハッチングが施してある。ここで、本実施形態では、半導体基板１の基板表面１ａの全面積に対するＡｌ電極１１の占める占有面積の比率が３０％以上８０％以下程度となっている。   FIG. 4 is a plan view showing an example of a planar pattern of the Al electrode 11 in the emitter electrode 2 and the gate electrode 3 when viewed from the substrate surface 1a side in the semiconductor chip 10. The surface of the Al electrode 11 is hatched for convenience. It is. Here, in the present embodiment, the ratio of the occupied area of the Al electrode 11 to the total area of the substrate surface 1a of the semiconductor substrate 1 is about 30% to 80%.

また、上記図１において、樹脂５０は第２のヒートシンク３０と第３のヒートシンク４０との間に充填され、当該ヒートシンク３０、４０間に位置する構成部品を封止している。   In FIG. 1, the resin 50 is filled between the second heat sink 30 and the third heat sink 40 to seal the components located between the heat sinks 30 and 40.

ここで、リード８０については、ボンディングワイヤ７０との接続部が樹脂５０にて封止されている。このような樹脂５０としてはエポキシ系樹脂等、通常のモールド材料を採用することができる。   Here, with respect to the lead 80, the connection portion with the bonding wire 70 is sealed with the resin 50. As such a resin 50, a normal molding material such as an epoxy resin can be employed.

このようにして、本実施形態における半導体チップ１０の実装構造が構成されている。この実装構造では、半導体チップ１０からの発熱を熱伝導性にも優れたはんだ６０を介して各ヒートシンク２０、３０、４０に伝え、放熱を行うことができるようになっている。つまり、本実施形態では、半導体チップ１０の表裏両面１ａ、１ｂからの放熱が可能となっている。   Thus, the mounting structure of the semiconductor chip 10 in this embodiment is configured. In this mounting structure, heat generated from the semiconductor chip 10 can be transmitted to the heat sinks 20, 30, 40 via the solder 60 having excellent thermal conductivity so that heat can be dissipated. That is, in the present embodiment, heat can be radiated from the front and back surfaces 1 a and 1 b of the semiconductor chip 10.

また、各ヒートシンク２０、３０、４０は半導体チップ１０との電気的な経路となっている。つまり、第１および第２のヒートシンク２０、３０を介して半導体チップ１０のエミッタ電極２の導通が図られ、第３のヒートシンク４０を介して半導体チップ１０のコレクタ電極４の導通が図られるようになっている。   Each heat sink 20, 30, 40 is an electrical path to the semiconductor chip 10. That is, the emitter electrode 2 of the semiconductor chip 10 is conducted through the first and second heat sinks 20 and 30 and the collector electrode 4 of the semiconductor chip 10 is conducted through the third heat sink 40. It has become.

次に、半導体チップ１０の製造方法および製造された半導体チップ１０の実装方法について、図５および図６も参照して述べる。   Next, a method for manufacturing the semiconductor chip 10 and a method for mounting the manufactured semiconductor chip 10 will be described with reference to FIGS.

図５は、本製造方法に用いる半導体ウェハ１００の概略平面図であり、ダイシングライン（スクライブライン）によって多数のチップ単位Ｕが区画されている。図６は、半導体チップ１０の製造方法を示す工程図であり、半導体ウェハ１００の概略断面図として示してある。   FIG. 5 is a schematic plan view of the semiconductor wafer 100 used in this manufacturing method, and a large number of chip units U are partitioned by dicing lines (scribe lines). FIG. 6 is a process diagram showing a method for manufacturing the semiconductor chip 10, and is shown as a schematic cross-sectional view of the semiconductor wafer 100.

まず、図５、図６（ａ）に示すように、半導体ウェハ１００を用意する。そして、図示しないが、この半導体ウェハ１００の表面１００ａにはチップ単位毎に注入や拡散等によりトランジスタ等の素子が形成されている。   First, as shown in FIGS. 5 and 6A, a semiconductor wafer 100 is prepared. Although not shown, elements such as transistors are formed on the surface 100a of the semiconductor wafer 100 by injection, diffusion, or the like for each chip.

次に、半導体ウェハ１００の表面１００ａにスパッタやフォトリソグラフ技術等を用いてＡｌ電極１１を形成し（図６（ｂ）参照）、Ａｌ電極１１の上に保護膜１２をスピンコート法等を用いて形成し、フォトエッチング等により保護膜１２に開口部１２ａを形成する（図６（ｃ）参照）。   Next, an Al electrode 11 is formed on the surface 100a of the semiconductor wafer 100 using sputtering or photolithography technology (see FIG. 6B), and a protective film 12 is formed on the Al electrode 11 using a spin coating method or the like. An opening 12a is formed in the protective film 12 by photoetching or the like (see FIG. 6C).

次に、開口部１２ａから臨むＡｌ電極１１の表面に、無電解メッキにより無電解Ｎｉ／Ａｕメッキ膜としての金属膜１３を形成する（図６（ｄ）参照）。このようにして、Ａｌ電極１１および金属電極１３より構成されるエミッタ電極２およびゲート電極３ができあがる。   Next, a metal film 13 as an electroless Ni / Au plating film is formed by electroless plating on the surface of the Al electrode 11 facing the opening 12a (see FIG. 6D). In this way, the emitter electrode 2 and the gate electrode 3 composed of the Al electrode 11 and the metal electrode 13 are completed.

次に、半導体ウェハ１００をその裏面側より研削してウェハ厚を調整した後、の裏面１００ｂに、スパッタによりＡｌ膜５を成膜し、さらに、Ｔｉ膜４ａ、Ｎｉ膜４ｂ、Ａｕ膜４ｃを順次成膜する。   Next, after the semiconductor wafer 100 is ground from the back surface side to adjust the wafer thickness, the Al film 5 is formed on the back surface 100b by sputtering, and the Ti film 4a, Ni film 4b, and Au film 4c are further formed. Films are sequentially formed.

こうして、裏面電極としてのコレクタ電極４ができあがる（図６（ｅ）参照）。しかる後、ダイシングカットを行い、半導体ウェハ１００をチップ単位毎に分断することにより、半導体装置としての半導体チップ１０ができあがる。   Thus, the collector electrode 4 as the back electrode is completed (see FIG. 6E). Thereafter, dicing cut is performed and the semiconductor wafer 100 is divided into chip units, whereby the semiconductor chip 10 as a semiconductor device is completed.

この半導体チップ１０の実装方法は次の通りである。   The mounting method of the semiconductor chip 10 is as follows.

半導体チップ１０における各電極２〜４の表面にはんだ６０を配設する。そして、半導体チップ１０に対してはんだ６０を介して第１および第３のヒートシンク２０、４０を接合し、ワイヤボンディングを行って半導体チップ１０のゲート電極３とリード８０とをボンディングワイヤ７０により電気的に接続する。   Solder 60 is disposed on the surfaces of the electrodes 2 to 4 in the semiconductor chip 10. Then, the first and third heat sinks 20 and 40 are joined to the semiconductor chip 10 via the solder 60, and wire bonding is performed to electrically connect the gate electrode 3 and the lead 80 of the semiconductor chip 10 with the bonding wire 70. Connect to.

その後、第１のヒートシンク２０の外側に第２のヒートシンク３０をはんだ６０を介して接合する。続いて、樹脂５０によるモールドを行う。こうして、上記図１に示す実装構造が完成する。   Thereafter, the second heat sink 30 is joined to the outside of the first heat sink 20 via the solder 60. Subsequently, molding with the resin 50 is performed. Thus, the mounting structure shown in FIG. 1 is completed.

なお、この実装時のはんだ溶融等の熱履歴により、表面側、裏面側の各電極において金属膜相互間および金属膜とはんだとの間で合金層が生成される。   Note that an alloy layer is generated between the metal films and between the metal film and the solder in each electrode on the front surface side and the back surface side due to the thermal history such as solder melting at the time of mounting.

ところで、本実施形態の半導体チップ１０においては、裏面電極であるコレクタ電極４をＰＶＤ法により形成されたＮｉ膜４ｂからなるものとし、当該Ｎｉ膜４ｂの膜応力を、基板表面４ａ側の金属電極１３におけるＮｉメッキ層１３ａの膜応力の３倍以上としている。このようにした根拠について述べる。   By the way, in the semiconductor chip 10 of the present embodiment, the collector electrode 4 as the back electrode is made of the Ni film 4b formed by the PVD method, and the film stress of the Ni film 4b is applied to the metal electrode on the substrate surface 4a side. 13 or more than the film stress of the Ni plating layer 13a. The basis for this will be described.

図７は、Ｎｉ膜応力比と半導体ウェハ１００の反り（単位：ｍｍ）との関係を調べた結果を示す図である。   FIG. 7 is a diagram showing the results of examining the relationship between the Ni film stress ratio and the warpage (unit: mm) of the semiconductor wafer 100.

ここで、図７において、Ｎｉ膜応力比は、「裏面Ｎｉ膜応力」すなわち裏面電極であるコレクタ電極４のＮｉ膜４ｂの膜応力を、「表面Ｎｉ膜応力」すなわち基板表面１ａ側の金属電極１３におけるＮｉメッキ層１３ａの膜応力で割った比（裏面膜応力／表面Ｎｉ膜応力）である。   Here, in FIG. 7, the Ni film stress ratio is the “back Ni film stress”, that is, the film stress of the Ni film 4b of the collector electrode 4 which is the back electrode, and the “surface Ni film stress”, ie, the metal electrode on the substrate surface 1a side. 13 is a ratio (back surface film stress / front surface Ni film stress) divided by the film stress of the Ni plating layer 13a.

また、半導体ウェハ１００の反りについては、上記図６（ｅ）に示すようにエミッタ電極２、ゲート電極３、コレクタ電極４を表裏両面に形成した半導体ウェハ１００において、上記図３に示す反りｔを求めたものである。   As for the warpage of the semiconductor wafer 100, the warp t shown in FIG. 3 is applied to the semiconductor wafer 100 in which the emitter electrode 2, the gate electrode 3, and the collector electrode 4 are formed on both the front and back surfaces as shown in FIG. It is what I have sought.

ここで、半導体ウェハ１００は、図３に示すように、エミッタ、ゲート電極２、３が形成されている表面１００ａが凹、コレクタ電極４が形成されている裏面１００ｂが凸となるように反る。   Here, as shown in FIG. 3, the semiconductor wafer 100 warps so that the front surface 100a on which the emitter and gate electrodes 2 and 3 are formed is concave and the back surface 100b on which the collector electrode 4 is formed is convex. .

この図７においては、半導体ウェハ１００は、サイズが直径６インチ、厚さが７０μｍ〜４００μｍのものを用いた。また、チップ単位すなわち上記半導体チップ１０でみた場合、半導体基板１の基板表面１ａの全面積に対するＡｌ電極１１の占める占有面積の比率は、３０％以上８０％以下程度である。   In FIG. 7, a semiconductor wafer 100 having a size of 6 inches in diameter and a thickness of 70 μm to 400 μm was used. Further, when viewed in chip units, that is, the semiconductor chip 10, the ratio of the occupied area of the Al electrode 11 to the total area of the substrate surface 1a of the semiconductor substrate 1 is about 30% to 80%.

さらに、この図７に関する半導体ウェハ１００においては、当該ウェハ１００の表面１００ａに形成した金属電極１３のうちＮｉメッキ層１３ａの厚さは５μｍ程度、Ａｕメッキ層１３ｂの厚さは０．１μｍ程度とし、一方、裏面１００ｂに形成したＡｌ膜５を２００ｎｍ程度、コレクタ電極４のうちＴｉ膜４ａについては２００ｎｍ程度、Ｎｉ膜４ｂについては５５０ｎｍ程度、Ａｕ膜４ｃについては１００ｎｍ程度の膜厚とした。   Further, in the semiconductor wafer 100 related to FIG. 7, the Ni plating layer 13a has a thickness of about 5 μm and the Au plating layer 13b has a thickness of about 0.1 μm among the metal electrodes 13 formed on the surface 100a of the wafer 100. On the other hand, the Al film 5 formed on the back surface 100b has a thickness of about 200 nm, and the collector electrode 4 has a thickness of about 200 nm for the Ti film 4a, about 550 nm for the Ni film 4b, and about 100 nm for the Au film 4c.

このような半導体ウェハ１００において、Ｎｉ膜応力比の調整は、表面Ｎｉ膜応力および裏面Ｎｉ膜応力を変えることで行った。上述したように、表面Ｎｉ膜応力すなわちＮｉメッキ層１３ａの膜応力を変えることは、例えば、メッキに用いる添加剤の量を調整することで容易に可能である。   In such a semiconductor wafer 100, the Ni film stress ratio was adjusted by changing the front Ni film stress and the back Ni film stress. As described above, the surface Ni film stress, that is, the film stress of the Ni plating layer 13a can be easily changed by, for example, adjusting the amount of the additive used for plating.

また、上述したが、裏面Ｎｉ膜応力すなわちコレクタ電極４のＮｉ膜４ｂの膜応力は、その膜密度を変えることで可能であり、Ｎｉ膜４ｂの膜密度を変えることは、例えばスパッタにおけるアルゴン圧を変えることで容易に可能である。   As described above, the back surface Ni film stress, that is, the film stress of the Ni film 4b of the collector electrode 4 can be changed by changing the film density. For example, the argon film pressure in sputtering can be changed. It is possible easily by changing.

図８は、この裏面Ｎｉ膜４ｂについて、その膜応力（単位：ＭＰａ）とその膜密度（任意単位）との関係を具体的に調べた結果を示す図である。この図８に示す結果の場合、コレクタ電極４のＮｉ膜４ｂをスパッタで形成する際にアルゴン圧を変えることで膜密度を変えた。   FIG. 8 is a diagram showing the results of a specific examination of the relationship between the film stress (unit: MPa) and the film density (arbitrary unit) of the back Ni film 4b. In the case of the result shown in FIG. 8, the film density was changed by changing the argon pressure when forming the Ni film 4b of the collector electrode 4 by sputtering.

限定するものではないが、そのスパッタ条件は、パワーについては２ｎｍ／ｓｅｃの成膜レートとなるように調整し、温度は１８０℃として、アルゴン圧を変えていった。アルゴン圧が大きくなるにつれて、膜密度は小さくなる。ここでは、アルゴン圧を５ｍＴｏｒｒ〜２５ｍＴｏｒｒまで変えていった。   Although not limited, the sputtering conditions were adjusted such that the power was a film formation rate of 2 nm / sec, the temperature was 180 ° C., and the argon pressure was changed. As the argon pressure increases, the film density decreases. Here, the argon pressure was changed from 5 mTorr to 25 mTorr.

図８に示されるように、裏面Ｎｉ膜４ｂの膜密度すなわちコレクタ電極４のＮｉ膜４ｂの膜密度が大きくなるにつれて、裏面Ｎｉ膜４ｂの膜応力も大きくなっていくことがわかる。   As shown in FIG. 8, it can be seen that as the film density of the back Ni film 4b, that is, the Ni film 4b of the collector electrode 4 increases, the film stress of the back Ni film 4b also increases.

このようにして、半導体ウェハ１００において、Ｎｉ膜応力比を変えていき、そのときの半導体ウェハ１００の反りｔ（単位：ｍｍ）を調べた結果が、上記図７に示されている。   FIG. 7 shows the result of examining the warp t (unit: mm) of the semiconductor wafer 100 while changing the Ni film stress ratio in the semiconductor wafer 100 in this manner.

図７に示すように、Ｎｉ膜応力比が大きくなるにつれて、半導体ウェハ１００の反りは小さくなっていくことがわかる。具体的には、Ｎｉ膜応力比が３以上であれば半導体ウェハ１００の反りは、専用装置に対応可能な３ｍｍ以下に抑えられ、さらには、Ｎｉ膜応力比がほぼ４になれば半導体ウェハ１００の反りは、汎用装置に対応可能な１ｍｍ以下に抑えられる。   As shown in FIG. 7, it can be seen that the warpage of the semiconductor wafer 100 decreases as the Ni film stress ratio increases. Specifically, if the Ni film stress ratio is 3 or more, the warp of the semiconductor wafer 100 can be suppressed to 3 mm or less, which is compatible with a dedicated device, and if the Ni film stress ratio is approximately 4, the semiconductor wafer 100 is suppressed. The warpage is suppressed to 1 mm or less which is compatible with general-purpose devices.

このように、裏面電極であるコレクタ電極４をＰＶＤ法により形成されたＮｉ膜４ｂからなるものとし、当該Ｎｉ膜４ｂの膜応力を金属電極１３におけるＮｉメッキ層１３ａの膜応力の３倍以上とすれば、製造時における半導体ウェハ１００の反りを３ｍｍ以下に抑えることができる。   Thus, the collector electrode 4 as the back electrode is made of the Ni film 4b formed by the PVD method, and the film stress of the Ni film 4b is three times or more of the film stress of the Ni plating layer 13a in the metal electrode 13. If it does, the curvature of the semiconductor wafer 100 at the time of manufacture can be restrained to 3 mm or less.

よって、本実施形態によれば、従来に比べて製造時における半導体ウェハ１００の反りを極力抑制することができる。   Therefore, according to the present embodiment, it is possible to suppress the warpage of the semiconductor wafer 100 during manufacturing as much as possible as compared with the conventional case.

また、コレクタ電極４のＮｉ膜４ｂの膜応力を２．７×１０8Ｐａ以上とし、金属電極１３におけるＮｉメッキ層１３ａの膜応力を８．９×１０7Ｐａ以下とすることで、上記膜応力の関係すなわちＮｉ膜応力比が３倍以上という関係が適切に実現される。この根拠は、上記図８にて例示される。 Further, the film stress of the Ni film 4b of the collector electrode 4 is set to 2.7 × 10 8 Pa or more, and the film stress of the Ni plating layer 13a in the metal electrode 13 is set to 8.9 × 10 7 Pa or less. The relationship of stress, that is, the relationship that the Ni film stress ratio is three times or more is appropriately realized. The basis for this is illustrated in FIG.

図８に示されている裏面Ｎｉ膜４ｂの膜応力の最小値は、２．７×１０8Ｐａである。本発明者らの検討によれば、この最小膜応力未満の範囲では、裏面Ｎｉ膜４ｂの膜密度が小さすぎてしまい、基板裏面１ｂ側に接合されるはんだ６０（上記図１、図２（ｂ）参照）の異常拡散が発生しやすくなる。すると、基板裏面１ｂ側でのはんだ接合強度が確保しにくくなってしまう。 The minimum value of the film stress of the back Ni film 4b shown in FIG. 8 is 2.7 × 10 8 Pa. According to the study by the present inventors, in the range below the minimum film stress, the film density of the back Ni film 4b is too small, and the solder 60 joined to the substrate back surface 1b side (see FIGS. 1 and 2 above). The abnormal diffusion of b) is likely to occur. Then, it becomes difficult to ensure the solder joint strength on the substrate back surface 1b side.

このようなことから、裏面Ｎｉ膜４ｂの膜密度を適度な大きさに維持するためにも、その膜応力は２．７×１０8Ｐａ以上であることが好ましい。そして、このことと、上述したＮｉ膜応力比が３以上であることとの関係から、基板表面１ａ側の金属電極１３におけるＮｉメッキ層１３ａの膜応力は８．９×１０7Ｐａ以下が好ましいことが、導き出される。 For this reason, the film stress is preferably 2.7 × 10 8 Pa or more in order to maintain the film density of the back Ni film 4b at an appropriate level. Then, from the relationship between this and the above-described Ni film stress ratio of 3 or more, the film stress of the Ni plating layer 13a in the metal electrode 13 on the substrate surface 1a side is preferably 8.9 × 10 7 Pa or less. Is derived.

また、上述したように、本実施形態では、半導体基板１の厚みは例えば７０μｍ〜４００μｍ程度のものにできるが、特に、２００μｍ以下とすることで上述した反り抑制の効果が有効に発揮される。   Further, as described above, in the present embodiment, the thickness of the semiconductor substrate 1 can be, for example, about 70 μm to 400 μm. In particular, when the thickness is 200 μm or less, the above-described warp suppressing effect is effectively exhibited.

図９は、半導体基板１の厚さ（単位：μｍ）と半導体ウェハ１００の反り（単位ｍｍ）との関係について調べた結果を示す図である。   FIG. 9 is a diagram showing the results of examining the relationship between the thickness (unit: μm) of the semiconductor substrate 1 and the warp (unit: mm) of the semiconductor wafer 100.

ここにおいて、半導体基板１の厚さは、そのまま、半導体ウェハ１００の厚さとなる。また、半導体ウェハ１００の反りについては、上記図７の場合と同じように、各電極２〜４を表裏両面に形成した半導体ウェハ１００において、上記図３に示す反りｔを求めたものである。   Here, the thickness of the semiconductor substrate 1 becomes the thickness of the semiconductor wafer 100 as it is. As for the warp of the semiconductor wafer 100, the warp t shown in FIG. 3 is obtained in the semiconductor wafer 100 in which the electrodes 2 to 4 are formed on both the front and back surfaces, as in the case of FIG.

また、図９において、半導体ウェハ１００のサイズは直径６インチとし、半導体基板１の基板表面１ａの全面積に対するＡｌ電極１１の占める占有面積の比率は７０％となるようにした。また、表面Ｎｉ膜応力を８．９×１０7Ｐａとし、裏面Ｎｉ膜応力を２．７×１０8Ｐａとして、Ｎｉ膜応力比は３とした。 In FIG. 9, the size of the semiconductor wafer 100 is 6 inches in diameter, and the ratio of the occupied area of the Al electrode 11 to the total area of the substrate surface 1a of the semiconductor substrate 1 is 70%. Further, the surface Ni film stress was 8.9 × 10 7 Pa, the back surface Ni film stress was 2.7 × 10 8 Pa, and the Ni film stress ratio was 3.

そして、図９では、研削によって、半導体ウェハ１００の厚さ、すなわち半導体基板１の厚さを変えていき、そのようにしたときの半導体ウェハ１００の反りを調べた結果が示されている。   FIG. 9 shows the result of examining the warpage of the semiconductor wafer 100 when the thickness of the semiconductor wafer 100, that is, the thickness of the semiconductor substrate 1 is changed by grinding, and the warp of the semiconductor wafer 100 in such a manner is shown.

図９に示すように、大きな反りを生じやすい厚さ２００μｍ以下の半導体ウェハ１００であっても、半導体ウェハ１００の反りは３ｍｍ以下に抑えられている。   As shown in FIG. 9, even if the semiconductor wafer 100 has a thickness of 200 μm or less which is likely to cause a large warp, the warp of the semiconductor wafer 100 is suppressed to 3 mm or less.

また、上述したように、本実施形態では、半導体基板１の基板表面１ａの全面積に対するＡｌ電極１１の占める占有面積の比率（以下、Ａｌ電極占有率という）は、３０％〜８０％程度のものにできる。   Further, as described above, in the present embodiment, the ratio of the occupied area occupied by the Al electrode 11 to the total area of the substrate surface 1a of the semiconductor substrate 1 (hereinafter referred to as the Al electrode occupation ratio) is about 30% to 80%. Can be a thing.

このＡｌ電極占有率が大きいということは、半導体基板１の基板表面１ａにおいて、Ｎｉメッキ層１３ａもそのＡｌ電極占有率に近い比率で多く存在することになり、その結果、半導体ウェハ１００の反りが大きくなりやすい。   The fact that the Al electrode occupancy is large means that the Ni plating layer 13a is also present at a ratio close to the Al electrode occupancy on the substrate surface 1a of the semiconductor substrate 1, and as a result, the warp of the semiconductor wafer 100 occurs. Easy to grow.

特に、このＡｌ電極占有率が３０％以上のものでは、半導体ウェハ１００の反りが大きくなりやすいため、本実施形態の対策を採ることにより上述した反り抑制の効果が有効に発揮される。   In particular, when the Al electrode occupancy is 30% or more, the warp of the semiconductor wafer 100 tends to be large. Therefore, by taking the measures of the present embodiment, the above-described warp suppression effect is effectively exhibited.

図１０は、Ａｌ電極占有率（単位：％）と半導体ウェハ１００の反り（単位：ｍｍ）との関係を調べた結果を示す図である。   FIG. 10 is a diagram showing the results of examining the relationship between the Al electrode occupation ratio (unit:%) and the warp (unit: mm) of the semiconductor wafer 100.

ここで、Ａｌ電極占有率は、半導体ウェハ１００に形成されるＡｌ電極１１のサイズを変えることで変えていった。また、半導体ウェハ１００の反りについては上記図７と同様に、各電極２〜４を表裏両面に形成した半導体ウェハ１００において、上記図３に示す反りｔを求めたものである。   Here, the Al electrode occupation ratio is changed by changing the size of the Al electrode 11 formed on the semiconductor wafer 100. Further, as for the warpage of the semiconductor wafer 100, the warpage t shown in FIG. 3 is obtained for the semiconductor wafer 100 in which the electrodes 2 to 4 are formed on both the front and back surfaces, as in FIG.

また、図１０においては、半導体ウェハ１００のサイズは直径６インチとし、その厚さは７０μｍと比較的薄いものとした。また、この図１０においては、表面Ｎｉ膜応力を８．９×１０7Ｐａとし、裏面Ｎｉ膜応力を２．７×１０8Ｐａとして、Ｎｉ膜応力比は３とした。 In FIG. 10, the size of the semiconductor wafer 100 is 6 inches in diameter, and its thickness is relatively thin, 70 μm. In FIG. 10, the surface Ni film stress was 8.9 × 10 7 Pa, the back Ni film stress was 2.7 × 10 8 Pa, and the Ni film stress ratio was 3.

図１０に示すように、Ａｌ電極占有率が３０％以上である場合であっても、上述したＮｉ膜応力を３以上とした関係を満足させることにより、半導体ウェハ１００の反りを３ｍｍ以下に抑えることができる。   As shown in FIG. 10, even when the Al electrode occupation ratio is 30% or more, the warp of the semiconductor wafer 100 is suppressed to 3 mm or less by satisfying the above-described relationship in which the Ni film stress is 3 or more. be able to.

以上述べてきたように、本実施形態では、半導体基板１における基板表面１ａにＡｌ電極１１を備え、半導体基板１における基板裏面１ｂに裏面電極４を備えてなる半導体装置としての半導体チップ１０が提供される。   As described above, in the present embodiment, the semiconductor chip 10 is provided as a semiconductor device including the Al electrode 11 on the substrate surface 1a of the semiconductor substrate 1 and the back electrode 4 on the substrate back surface 1b of the semiconductor substrate 1. Is done.

そして、この半導体チップ１０においては、Ａｌ電極１１の表面に、当該表面側からＮｉメッキ層１３ａ、Ａｕメッキ層１３ｂが順次無電解メッキにより積層されてなる金属電極１３が形成されており、裏面電極４はＰＶＤ法により形成されたＮｉ膜４ｂからなり、該Ｎｉ膜４ｂの膜応力が金属電極１３におけるＮｉメッキ層１３ａの膜応力の３倍以上であることを主たる特徴としている。   In this semiconductor chip 10, a metal electrode 13 is formed on the surface of the Al electrode 11, in which a Ni plating layer 13 a and an Au plating layer 13 b are sequentially laminated from the surface side by electroless plating. 4 is composed of the Ni film 4b formed by the PVD method, and the main feature is that the film stress of the Ni film 4b is three times or more of the film stress of the Ni plating layer 13a in the metal electrode 13.

なお、上述したように、このような特徴を有する金属電極１３としては、接続相手がはんだ６０であるエミッタ電極２の金属電極１３の場合だけではなく、接続相手がボンディングワイヤ７０であるゲート電極３の金属電極１３の場合についても、同様のものである。   As described above, the metal electrode 13 having such characteristics is not limited to the case of the metal electrode 13 of the emitter electrode 2 whose connection partner is the solder 60, but the gate electrode 3 whose connection partner is the bonding wire 70. The same applies to the case of the metal electrode 13.

つまり、本実施形態の金属電極１３は、外部接続用のものであって、はんだやボンディングワイヤといった外部接続部材以外にも、その他の外部接続部材と接続されるものであってもよい。   That is, the metal electrode 13 of the present embodiment is for external connection, and may be connected to other external connection members in addition to the external connection members such as solder and bonding wires.

また、半導体装置の実装形態は、上記したヒートシンク２０〜４０を用いた両面はんだ付けモールド構造に限定されるものではなく、例えば、リードフレームやプリント基板等を用いた実装を行うようにしてもよい。   Further, the mounting form of the semiconductor device is not limited to the double-sided soldering mold structure using the heat sinks 20 to 40 described above. For example, mounting using a lead frame or a printed board may be performed. .

また、本発明においては、上記Ｎｉ膜応力比が３以上であることを要部構成とするものであり、その他、半導体ウェハのサイズや厚さ、半導体基板に形成される素子の種類等は適宜設計変更してもよい。   In the present invention, the Ni film stress ratio is 3 or more, and the main part is configured. In addition, the size and thickness of the semiconductor wafer, the type of elements formed on the semiconductor substrate, etc. The design may be changed.

本発明の実施形態に係る半導体装置としての半導体チップを用いた実装構造を示す概略断面図である。It is a schematic sectional drawing which shows the mounting structure using the semiconductor chip as a semiconductor device which concerns on embodiment of this invention. （ａ）は図１中の半導体チップにおけるエミッタ電極の近傍部の拡大断面図であり、（ｂ）は図１中の半導体チップにおけるコレクタ電極の一部を拡大して示す概略断面図である。(A) is an enlarged sectional view of the vicinity of the emitter electrode in the semiconductor chip in FIG. 1, and (b) is a schematic sectional view showing an enlarged part of the collector electrode in the semiconductor chip in FIG. 半導体ウェハの反りの様子を示す図である。It is a figure which shows the mode of the curvature of a semiconductor wafer. 半導体チップの基板表面におけるＡｌ電極の平面パターンの一例を示す平面図である。It is a top view which shows an example of the plane pattern of Al electrode in the board | substrate surface of a semiconductor chip. 半導体チップの製造に用いる半導体ウェハの概略平面図である。It is a schematic plan view of the semiconductor wafer used for manufacture of a semiconductor chip. 半導体チップの製造方法を示す工程図である。It is process drawing which shows the manufacturing method of a semiconductor chip. Ｎｉ膜応力比と半導体ウェハの反りとの関係を調べた結果を示す図である。It is a figure which shows the result of having investigated the relationship between Ni film | membrane stress ratio and the curvature of a semiconductor wafer. 裏面Ｎｉ膜の膜応力とその膜密度との関係を具体的に調べた結果を示す図である。It is a figure which shows the result of having investigated concretely the relationship between the film | membrane stress of a back surface Ni film | membrane, and its film | membrane density. 半導体基板の厚さと半導体ウェハの反りとの関係について調べた結果を示す図である。It is a figure which shows the result investigated about the relationship between the thickness of a semiconductor substrate, and the curvature of a semiconductor wafer. Ａｌ電極占有率と半導体ウェハの反りとの関係を調べた結果を示す図である。It is a figure which shows the result of having investigated the relationship between Al electrode occupation rate and the curvature of a semiconductor wafer. 本発明者らの試作品としての半導体装置の要部を示す概略断面図である。It is a schematic sectional drawing which shows the principal part of the semiconductor device as a prototype of the present inventors.

符号の説明Explanation of symbols

１…半導体基板、１ａ…半導体基板の基板表面、
１ｂ…半導体基板の基板裏面、４…裏面電極としてのコレクタ電極、
４ｂ…コレクタ電極のＮｉ膜、１０…半導体装置としての半導体チップ、
１１…Ａｌ電極、１３…金属電極、１３ａ…Ｎｉメッキ層、
１３ｂ…Ａｕメッキ層、１００…半導体ウェハ。 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 1a ... The substrate surface of a semiconductor substrate,
1b ... back surface of semiconductor substrate, 4 ... collector electrode as back electrode,
4b ... Ni film of collector electrode, 10 ... Semiconductor chip as semiconductor device,
11 ... Al electrode, 13 ... Metal electrode, 13a ... Ni plating layer,
13b ... Au plating layer, 100 ... semiconductor wafer.

Claims (5)

半導体基板（１）における素子が形成された面である基板表面（１ａ）にアルミニウムからなるアルミニウム電極（１１）を備え、前記半導体基板における前記基板表面とは反対側の基板裏面（１ｂ）に裏面電極（４）を備えてなる半導体装置において、
前記アルミニウム電極の表面には、メッキ形成されたニッケルメッキ層（１３ａ）を含む外部接続用の金属電極（１３）が形成されており、
前記裏面電極は物理的気相成長法により形成されたニッケル膜（４ｂ）を含み、前記ニッケル膜の膜応力が前記金属電極における前記ニッケルメッキ層の膜応力の３倍以上であることを特徴とする半導体装置。 An aluminum electrode (11) made of aluminum is provided on a substrate surface (1a) that is a surface on which an element is formed in a semiconductor substrate (1), and a back surface on a substrate back surface (1b) opposite to the substrate surface in the semiconductor substrate. In the semiconductor device comprising the electrode (4),
On the surface of the aluminum electrode, a metal electrode (13) for external connection including a nickel plating layer (13a) formed by plating is formed,
The back electrode includes a nickel film (4b) formed by physical vapor deposition, and the film stress of the nickel film is more than three times the film stress of the nickel plating layer in the metal electrode. Semiconductor device. 前記ニッケル膜（４ｂ）の膜応力が２．７×１０8Ｐａ以上であり、前記ニッケルメッキ層（１３ａ）の膜応力が８．９×１０7Ｐａ以下であることを特徴とする請求項１に記載の半導体装置。 The film stress of the nickel film (4b) is 2.7 × 10 8 Pa or more, and the film stress of the nickel plating layer (13a) is 8.9 × 10 7 Pa or less. A semiconductor device according to 1. 前記半導体基板（１）の厚さが２００μｍ以下であることを特徴とする請求項１または２に記載の半導体装置。 The semiconductor device according to claim 1, wherein the semiconductor substrate has a thickness of 200 μm or less. 前記半導体基板（１）の前記基板表面（１ａ）の全面積に対する前記アルミニウム電極（１１）の占める占有面積の比率が３０％以上であることを特徴とする請求項１ないし３のいずれか一つに記載の半導体装置。 4. The ratio of the occupied area occupied by the aluminum electrode (11) to the total area of the substrate surface (1a) of the semiconductor substrate (1) is 30% or more. A semiconductor device according to 1. 前記金属電極（１３）上にはＳｎを主成分とするはんだが接続されるものであり、前記ニッケルメッキ層（１３ａ）の膜厚は少なくとも５μｍ程度以上に調整されていることを特徴とする請求項１ないし４のいずれか一つに記載の半導体装置。
Solder mainly composed of Sn is connected to the metal electrode (13), and the thickness of the nickel plating layer (13a) is adjusted to at least about 5 μm or more. Item 5. The semiconductor device according to any one of Items 1 to 4.
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