JP2004502265A5 - - Google Patents

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Publication number
JP2004502265A5
JP2004502265A5 JP2002505624A JP2002505624A JP2004502265A5 JP 2004502265 A5 JP2004502265 A5 JP 2004502265A5 JP 2002505624 A JP2002505624 A JP 2002505624A JP 2002505624 A JP2002505624 A JP 2002505624A JP 2004502265 A5 JP2004502265 A5 JP 2004502265A5
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JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2002505624A
Other languages
Japanese (ja)
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JP2004502265A (ja
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/IL2000/000327 external-priority patent/WO2002001570A1/en
Publication of JP2004502265A publication Critical patent/JP2004502265A/ja
Publication of JP2004502265A5 publication Critical patent/JP2004502265A5/ja
Withdrawn legal-status Critical Current

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JP2002505624A 2000-06-07 2000-06-07 小型コールアウトメモリ Withdrawn JP2004502265A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IL2000/000327 WO2002001570A1 (en) 2000-06-07 2000-06-07 Call out memory with reduced surface

Publications (2)

Publication Number Publication Date
JP2004502265A JP2004502265A (ja) 2004-01-22
JP2004502265A5 true JP2004502265A5 (xx) 2004-12-24

Family

ID=11042980

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002505624A Withdrawn JP2004502265A (ja) 2000-06-07 2000-06-07 小型コールアウトメモリ

Country Status (6)

Country Link
EP (1) EP1295296A1 (xx)
JP (1) JP2004502265A (xx)
CN (1) CN1375102A (xx)
AU (1) AU5098900A (xx)
IL (1) IL147999A0 (xx)
WO (1) WO2002001570A1 (xx)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2790009C (en) * 2010-02-18 2017-01-17 Katsumi Inoue Memory having information refinement detection function, information detection method using memory, device including memory, information detection method, method for using memory, and memory address comparison circuit
US10061732B2 (en) * 2013-05-15 2018-08-28 Tactotek Oy Enabling arrangement for an electronic device with housing-integrated functionalities and method therefor
US20210318441A1 (en) 2018-08-07 2021-10-14 Groundprobe Pty Ltd Wall visualisation from virtual point of view

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3140695B2 (ja) * 1996-10-17 2001-03-05 川崎製鉄株式会社 連想メモリ装置
AU1092599A (en) * 1997-10-30 1999-05-24 Netlogic Microsystems, Inc. Synchronous content addressable memory with single cycle operation

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