JP2004327903A - Resin sealed semiconductor device and its manufacturing method - Google Patents

Resin sealed semiconductor device and its manufacturing method Download PDF

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JP2004327903A
JP2004327903A JP2003123550A JP2003123550A JP2004327903A JP 2004327903 A JP2004327903 A JP 2004327903A JP 2003123550 A JP2003123550 A JP 2003123550A JP 2003123550 A JP2003123550 A JP 2003123550A JP 2004327903 A JP2004327903 A JP 2004327903A
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terminal
resin
etched surface
semiconductor device
die pad
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JP4373122B2 (en
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Masachika Masuda
正親 増田
Chikao Ikenaga
知加雄 池永
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Dai Nippon Printing Co Ltd
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Dai Nippon Printing Co Ltd
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Priority to JP2003123550A priority Critical patent/JP4373122B2/en
Priority to US10/821,173 priority patent/US7405468B2/en
Publication of JP2004327903A publication Critical patent/JP2004327903A/en
Priority to US12/213,277 priority patent/US20080251902A1/en
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Publication of JP4373122B2 publication Critical patent/JP4373122B2/en
Priority to US12/801,896 priority patent/US8653647B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
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    • H01L2924/01082—Lead [Pb]

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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a thinned and high mass-productivity structure in a resin-sealed semiconductor device wherein a semiconductor element is laminated on a semiconductor element in a peripheral pad array as one package. <P>SOLUTION: Respective terminal members are aligned in the same direction to respectively align on one plane front and rear surfaces of an external terminal part 111 and a terminal surface of an internal terminal part 112, a half etching surface 150a of a die pad 150 is directed oppositely to a half etching surface 114a of a lead part to align a non-etching surface that is not the half etching surface, on one plane with a non-etching surface of the external terminal part on the half etching surface side of the terminal member, and the terminal surface side of the internal terminal part is disposed on the half etching surface side of the lead part in each terminal member to expose the non-half etching surface and the outside surface of each external terminal part and to dispose the other surfaces within a resin for resin sealing. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、エッチング形成した端子部材とダイパッドを用いた、小型、薄型の樹脂封止型半導体装置と、その製造方法に関する。
【０００２】
【従来の技術】
近年、電子機器の小型化に対応するために、電子機器に搭載される半導体部品を高密度に実装することが要求され、それにともなって、半導体部品の小型化、薄型化が進んでおり、更なる薄型化を廉価に達成できるパッケージが求められている。
このような状況のもと、薄型化に対応するものとして、特開平１１−３０７６７５号公報に記載の接続用リードの上面及び下面を露出させた構造の樹脂封止型半導体装置や、特開平１１−２６０９８９号公報に記載の接続用リードの一部を露出して外部端子としている樹脂封止型半導体装置が提案されている。
特開平１１−３０７６７５号や 特開平１１−２６０９８９号公報に記載のものは、ダイパッドの一面を外部に露出し、露出した面でない方の面上に半導体装置を搭載する構造で、面付け状態で一括してモールドを行うには、不適な構造である。
また、特開平１１−３０７６７５号や 特開平１１−２６０９８９号公報には、ペリフェラルパッド配列の半導体素子上に更に半導体素子を積層して１つのパッケージとした樹脂封止型半導体装置で、量産性の良い構造のものを開示されていない。
【０００３】
【特許文献１】
特開平１１−３０７６７５号公報
【特許文献２】
特開平１１−２６０９８９号公報
【０００４】
【発明が解決しようとする課題】
上記のように、近年、半導体部品の小型化、薄型化が進んでおり、更なる薄型化を廉価に達成できるパッケージが求められており、この対応が求められていた。
本発明はこれらに対応するもので、具体的には、半導体部品の更なる小型化、薄型化を廉価に達成でき、量産性に適し、且つ、耐湿性、放熱性に優れた、ＱＦＮ（Ｑｕａｄ Ｆｌａｔ Ｎｏｎｌｅａｄ）パッケージあるいはＳＯＮ（Ｓｍａｌｌ Ｏｕｔｌｉｎｅ Ｎｏｎｌｅａｄ）パッケージ構造の半導体装置を提供しようとするものである。
更に、ペリフェラルパッド配列の半導体素子上に１つ以上の半導体素子を積層して１つのパッケージとした樹脂封止型半導体装置で、薄型で量産性の良い構造のものを提供しようとするものである。
同時に、このような樹脂封止型半導体装置の製造方法を提供しようとするものである。
【０００５】
【課題を解決するための手段】
本発明の樹脂封止型半導体装置は、外部回路と接続するための外部端子部と、半導体素子と接続するための内部端子部をその一部として含むリード部とを、一体的に連結してなる端子部材で、且つ、ハーフエッチング加工法を用いて、加工用素材から、外部端子部の少なくとも一部を加工用素材の厚さの厚肉にし、リード部をハーフエッチングにて薄肉にしている端子部材を、複数個と、前記加工用素材から、ハーフエッチング加工法を用いて、全体を薄肉にして形成されたダイパッド１つと、半導体素子１つとを用い、半導体素子をダイパッドに搭載し、半導体素子の所定の端子部と所定の端子部材の内部端子部とをワイヤボンディング接続して、樹脂封止した樹脂封止型半導体装置であって、各端子部材を同じ向きにし、外部端子部の表裏の面および内部端子部の端子面が、それぞれ、一平面上に、揃うようにし、周辺部に、外部端子部を外側に向けて、内部端子部を内側に向けて、各端子部材を配しており、ダイパッドのハーフエッチング面の向きは、リード部のハーフエッチング面の向きとは反対にして、そのハーフエッチング面でない非エッチング面を端子部材のハーフエッチング面側の外部端子部の非エッチング面と一平面上に、揃うようにしており、半導体素子の端子面を、端子部材のハーフエッチング面側と同じ向きにし、その裏面を、ダイパッドの非エッチング面側に搭載しており、各端子部材のリード部のハーフエッチング面側に内部端子部の端子面側を配し、リード部のハーフエッチング面側でない各端子部材の非ハーフエッチング面と、各外部端子部の外側側面とを、露出させ、これ以外を樹脂中にして樹脂封止されていることを特徴とするものである。
あるいは、本発明の樹脂封止型半導体装置は、外部回路と接続するための外部端子部と、半導体素子と接続するための内部端子部をその一部として含むリード部とを、一体的に連結してなる端子部材で、且つ、ハーフエッチング加工法を用いて、加工用素材から、外部端子部の少なくとも一部を加工用素材の厚さの厚肉にし、リード部をハーフエッチングにて薄肉にしている端子部材を、複数個と、前記加工用素材から、ハーフエッチング加工法を用いて、全体を薄肉にして形成されたダイパッド１つと、半導体素子複数個を用い、前記半導体素子複数個を積層した状態としてダイパッドに搭載し、各半導体素子の所定の端子部と所定の端子部材の内部端子部とをワイヤボンディング接続して、樹脂封止した樹脂封止型半導体装置であって、各端子部材を同じ向きにし、外部端子部の表裏の面および内部端子部の端子面が、それぞれ、一平面上に、揃うようにし、周辺部に、外部端子部を外側、内部端子部側を内側に向けて、各端子部材を配しており、ダイパッドのハーフエッチング面の向きは、リード部のハーフエッチング面の向きとは反対にして、そのハーフエッチング面でない非エッチング面を端子部材のハーフエッチング面側の外部端子部の非エッチング面と一平面上に、揃うようにしており、ダイパッド側の半導体素子をペリフェラルパッド配列の半導体素子とし、その端子面を、端子部材のハーフエッチング面側と同じ向きにし、その裏面を、ダイパッドの非エッチング面側に搭載し、更に、前記ダイパッド側の半導体素子の端子面でない裏面上に、一番上以外をペリフェラルパッド配列の半導体素子として、順次、その裏面側を前記ダイパッド側の半導体素子側に向けて、半導体素子を重ねて搭載しており、各端子部材のリードのハーフエッチング面側に内部端子部の端子面側を配し、リード部のハーフエッチング面側でない各端子部材の非ハーフエッチング面と、各外部端子部の外側側面とを、露出させ、これ以外を樹脂中にして樹脂封止されていることを特徴とするものである。
そして上記の樹脂封止型半導体装置おいて、樹脂封止されて、全体が板状方形であることを特徴とするものである。
【０００６】
また、本発明の樹脂封止型半導体装置は、外部回路と接続するための外部端子部と、半導体素子と接続するための内部端子部をその一部として含むリード部とを、一体的に連結してなる端子部材で、且つ、ハーフエッチング加工法を用いて、加工用素材から、外部端子部の少なくとも一部を加工用素材の厚さの厚肉にし、リード部をハーフエッチングにて薄肉にしている端子部材を、複数個と、前記加工用素材から、ハーフエッチング加工法を用いて、全体を薄肉にして形成されたダイパッド１つと、半導体素子１つとを用い、半導体素子をダイパッドに搭載し、半導体素子の所定の端子部と所定の端子部材の内部端子部とをワイヤボンディング接続して、樹脂封止した樹脂封止型半導体装置であって、各端子部材を同じ向きにし、外部端子部の表裏の面および内部端子部の端子面が、それぞれ、一平面上に、揃うようにし、周辺部に、外部端子部を外側に向けて、内部端子部を内側に向けて、各端子部材を配しており、ダイパッドのハーフエッチング面の向きは、リード部のハーフエッチング面の向きとは反対にして、そのハーフエッチング面でない非エッチング面を端子部材のハーフエッチング面側の外部端子部の非エッチング面と一平面上に、揃うようにしており、半導体素子の端子面を、端子部材のハーフエッチング面側と同じ向きにして、その裏面を、ダイパッドの非エッチング面側に搭載しており、各端子部材のリード部のハーフエッチング面側に内部端子部の端子面を配し、リード部のハーフエッチング面側でない各端子部材の非ハーフエッチング面と、各端子部材の外側側面を含む側面部とを露出させ、これ以外を樹脂中にして樹脂封止されていることを特徴とするものである。
あるいはまた、本発明の樹脂封止型半導体装置は、外部回路と接続するための外部端子部と、半導体素子と接続するための内部端子部をその一部として含むリード部とを、一体的に連結してなる端子部材で、且つ、ハーフエッチング加工法を用いて、加工用素材から、外部端子部の少なくとも一部を加工用素材の厚さの厚肉にし、リード部をハーフエッチングにて薄肉にしている端子部材を、複数個と、前記加工用素材から、ハーフエッチング加工法を用いて、全体を薄肉にして形成されたダイパッド１つと、半導体素子複数個を用い、前記半導体素子複数個を積層した状態としてダイパッドに搭載し、各半導体素子の所定の端子部と所定の端子部材の内部端子部とをワイヤボンディング接続して、樹脂封止した樹脂封止型半導体装置であって、各端子部材を同じ向きにし、外部端子部の表裏の面および内部端子部の端子面が、それぞれ、一平面上に、揃うようにし、周辺部に、外部端子部を外側、内部端子部側を内側に向けて、各端子部材を配しており、ダイパッドのハーフエッチング面の向きは、リード部のハーフエッチング面の向きとは反対にして、そのハーフエッチング面でない非エッチング面を端子部材のハーフエッチング面側の外部端子部の非エッチング面と一平面上に、揃うようにしており、ダイパッド側の半導体素子をペリフェラルパッド配列の半導体素子とし、その端子面を、端子部材のハーフエッチング面側と同じ向きにし、その裏面を、ダイパッドの非エッチング面側に搭載し、更に、前記ダイパッド側の半導体素子の端子面でない裏面上に、一番上以外をペリフェラルパッド配列の半導体素子として、順次、その裏面側を前記ダイパッド側の半導体素子側に向けて、半導体素子を重ねて搭載しており、各端子部材のリード部のハーフエッチング面側に内部端子部の端子面を配し、リード部のハーフエッチング面側でない各端子部材の非ハーフエッチング面と、各端子部材の外側側面を含む側面部とを露出させ、これ以外を樹脂中にして樹脂封止されていることを特徴とするものである。
【０００７】
そして、上記の樹脂封止型半導体装置において、外部端子部の外側側面部に切り欠け部を設けていることを特徴とするものである。
また、上記の樹脂封止型半導体装置において、端子部材は、Ｃｕ、Ｃｕ系合金、４２％Ｎｉ−Ｆｅ系合金からなることを特徴とするものである。
また、上記の樹脂封止型半導体装置において、内部端子部の端子面および外部端子部の表裏の端子面に、半田めっき層、金めっき層、銀めっき層、パラジウムめっき層、錫めっき層から選ばれた１つの金属めっき層を、接続用のめっき層として設けていることを特徴とするものである。
【０００８】
第１の本発明の樹脂封止型半導体装置の製造方法は、請求項１ないし３のいずれかに記載の樹脂封止型半導体装置の製造方法であって、順に、（ａ）１つの樹脂封止型半導体装置の各端子部材とダイパッドの配置に対応した、端子部材およびダイパッドの配置を１単位として、ハーフエッチング技術を用いたエッチング加工にて、端子部材の外部端子部側を支持部で連結した状態で、面付けして形成し、面付け形成された加工シートを得る加工工程と、（ｂ）接続用の表面めっきを施すめっき処理工程と、（ｃ）加工シートを固定した状態で、面付け分だけ、半導体素子を位置決めして、ダイパッド上に搭載する半導体素子搭載工程と、（ｄ）この状態で、各半導体素子について、その端子と端子部材の内部端子部の端子面とをワイヤボンディング接続するワイヤボンディング工程と、（ｅ）面付け形成された加工シートのハーフエッチング面側を覆うように平面状に、モールド用のテープを貼る、平面状に貼る、テープ貼り工程と、（ｆ）モールド用のテープ側は、テープに添わせ、反対側はキャビティを設けるように、表裏をモールド固定用の平板にて囲み、加工シート全体について、一括してモールドを行う、一括モールド工程と、（ｇ）表裏のモールド固定用の平板、テープを除去し、切断用のテープを貼り、該切断用のテープとは反対側からダイシングソーにて切断して、樹脂封止型半導体装置を１個づつに個片化して得る個片化工程と、を行うことを特徴とするものである。
【０００９】
第２の本発明の樹脂封止型半導体装置の製造方法は、請求項４ないし５のいずれかに記載の樹脂封止型半導体装置の製造方法であって、順に、（ａ１）１つの樹脂封止型半導体装置の各端子部材とダイパッドの配置に対応した、端子部材およびダイパッドの配置を１単位として、ハーフエッチング技術を用いたエッチング加工にて、端子部材の外部端子部側を支持部で連結した状態で、面付けして形成し、面付け形成された加工シートを得る加工工程と、（ｂ１）接続用の表面めっきを施すめっき処理工程と、（ｃ１）加工シートを固定した状態で、面付け分だけ、半導体素子を位置決めして、ダイパッド上に搭載する半導体素子搭載工程と、（ｄ１）この状態で、各半導体素子について、その端子と端子部材の内部端子部の端子面とをワイヤボンディング接続するワイヤボンディング工程と、（ｅ１）面付け形成された加工シートのハーフエッチング面側を覆うように平面状に、モールド用のテープを貼る、平面状に貼る、テープ貼り工程と、（ｆ１）モールド用のテープ側は、テープに添わせ、モールド固定用の平板にて固定し、反対側には、所定の面付け数をまかなう所定の型を設け、前記モールド固定用の平板と前記型間を樹脂で埋めるモールドを行う、モールド工程と、（ｇ１）モールド固定用の平板、テープを除去し、切断用のテープを貼り、該切断用のテープとは反対側からダイシングソーにて切断して、樹脂封止型半導体装置を１個づつに個片化して得る個片化工程と、を行うことを特徴とするものである。
【００１０】
【作用】
本発明の樹脂封止型半導体装置は、このような構成にすることにより、半導体部品の更なる小型化、薄型化を廉価に達成でき、量産性に適し、且つ、耐湿性、放熱性に優れたＱＦＮパッケージあるいはＳＯＮパッケージ構造の半導体装置の提供を可能にしている。
更に、ペリフェラルパッド配列の半導体素子上に１つ以上の半導体素子を積層して１つのパッケージとした樹脂封止型半導体装置で、薄型で量産性の良い構造の半導体装置の提供を可能にしている。
この半導体素子積層構造の場合、半導体チップの薄化に対応して、１つのパッケージ内に半導体素子を３次元方向に積層したパッケージでシステムＬＳＩを実現するシステムパッケージ（システムインパッケージあるいはＳＩＪとも言う）としての適用を可能としている。
即ち、ハーフエッチング法にて作製され、外部端子部の少なくとも一部を加工用素材の厚さの厚肉にし、内部端子部をその一部として含むリード部とを、一体的に連結してなる端子部材と、加工用素材からハーフエッチング加工法を用いて全体を薄肉にして形成されたダイパッドと、半導体素子とを用い、具体的には、端子部材を同じ向きにし、外部端子部の表裏の面および内部端子部の端子面が、それぞれ、一平面上に、揃うようにし、周辺部に、外部端子部を外側、内部端子部側を内側に向けて、各端子部材を配しており、リード部のハーフエッチング面側でない各端子部材の非ハーフエッチング面と、各外部端子部の外側側面とを、露出させ、あるいは、リード部のハーフエッチング面側でない各端子部材の非ハーフエッチング面と、各外部端子部の外側側面とを、露出させ、これ以外を樹脂中にして樹脂封止されていることにより、これを達成している。
また、ワイヤボンディング接続をとっていることにより、接続作業性を良いものとし、且つ、接続信頼性を良いものとしている。
また、後述する、本発明の樹脂封止型半導体装置の製造方法により、面付け状態で作製でき、量産性の良い構造といえる。
特に、樹脂封止されて、全体が板状方形で、リード部のハーフエッチング面側でない各端子部材の非ハーフエッチング面と、外部端子部の外側側面とを露出させ、これ以外を樹脂中にして樹脂封止されている場合には、樹脂封止工程（モールド工程）において、特別な型を設ける必要はなく、一括モールドが簡単に行え、量産性、設備の面からも好ましい構造と言える。
詳しくは、ダイパッドのハーフエッチング面の向きは、リード部のハーフエッチング面の向きとは反対にして、そのハーフエッチング面でない非エッチング面を端子部材のハーフエッチング面側の外部端子の非エッチング面と一平面上に、揃うようにしていることにより、一括モールドがし易いものとしている。
また、ダイパッドのハーフエッチング面側がを封止用樹脂で満たされることから、チップへのクラック、欠けが生じにくいものとし、樹脂封止により耐湿性を向上させることができる。
また、前述のようなダイパッドと端子部材との位置関係から、ダイパッドより大サイズの半導体素子を搭載することを可能としている。
また、リード部のハーフエッチング面側でない各端子部材の非ハーフエッチング面と、各外部端子部の外側側面とを、露出させ、あるいは、リード部のハーフエッチング面側でない各端子部材の非ハーフエッチング面と、各外部端子部の外側側面とを、露出させていることにより、放熱性の良いものとしている。
尚、外部端子部の外側側面部に切り欠け部を設けていることにより、個片化の際の切断を容易なものとしている。
端子部材としては、Ｃｕ、Ｃｕ系合金、４２％Ｎｉ−Ｆｅ系合金からなるものが挙げられる。
また、内部端子部の端子面および外部端子部の表裏の端子面に、半田めっき層、金めっき層、銀めっき層、パラジウムめっき層、錫めっき層から選ばれた１つの金属めっき層を、接続用のめっき層としていることにより、ワイヤボンディング接続を信頼性良いものとしている。
【００１１】
第１の本発明の樹脂封止型半導体装置の製造方法は、このような構成にすることにより、請求項１ないし３の発明の薄型の樹脂封止型半導体装置を、量産性良く製造できるものとしている。
また、第２の本発明の樹脂封止型半導体装置の製造方法は、このような構成にすることにより、請求項４ないし５の発明の薄型の樹脂封止型半導体装置を、量産性良く製造できるものとしている。
【００１２】
【発明の実施の形態】
本発明の実施の形態を図に基づいて説明する。
図１（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第１の例の断面図で、図１（ｂ）は図１（ａ）のＡ１側から透視してみた図で、図２（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第２の例の断面図で、図２（ｂ）は図２（ａ）のＢ１側から透視してみた図で、図３（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第３の例の断面図で、図３（ｂ）は図３（ａ）のＣ１側から透視してみた図で、図４（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第４の例の断面図で、図４（ｂ）は図４（ａ）のＤ１側から透視してみた図で、図５（ａ）、図５（ｂ）はそれぞれ第１の例、第３の例の変形例の断面図で、図６は本発明の樹脂封止型半導体装置の製造方法の実施の形態の１例の製造工程の一部を示した工程断面図で、図７は図６に続く工程を示した工程断面図で、図８はダイシングソーによる切断状態を示した図である。
尚、図１（ａ）は図１（ｂ）のＡ１−Ａ２側から見た図で、図２（ａ）は図２（ｂ）のＢ１−Ｂ２側から見た図で、図３（ａ）は図３（ｂ）のＣ１−Ｃ２側から見た図で、図４（ａ）は図４（ｂ）のＤ１−Ｄ２側から見た図である。
また、図７（ｇ）における両方向矢印は、ダイシングソーの昇降方向を示している。
図１〜図８中、１１０は端子部材、１１１は外部端子部、１１２は内部端子部、１１２ａ、１１２ｂは端子面、１１４はリード部、１１４ａはハーフエッチング面、１１６は切り欠け部、１１７、１１７ａは非エッチング面、１１８は側面、１２０、１２０Ａは半導体素子（半導体チップあるいは単にチップとも言う）、１２０ａは端子面、１２０ｂは裏面、１２１は端子、１２５、１２５Ａは半導体素子（半導体チップあるいは単にチップとも言う）、１２５ａは端子面、１２５ｂは裏面、１２６、１２６Ａは端子、１２８、１２８Ａは半導体素子（半導体チップあるいは単にチップとも言う）、１２８ａは端子面、１２８ｂは裏面、１２９、１２９Ａは端子、１３０、１３５、１３５Ａはボンディングワイヤ、１３６、１３６Ａはボンディングワイヤ、１４０は封止用樹脂、１５０はダイパッド、１５０ａはハーフエッチング面、１５０ｂは非エッチング面、２１０は加工用素材、２１０Ａは加工シート、２２０はレジスト、２２５は開口、２３０は端子部材、２３１は外部端子部、２３２は内部端子部、２３４はリード部、２３５は凹部、２３５Ａは切り欠け部、２３６は支持部（連結部とも言う）、２３７は非エッチング面（露出面）、２３８は側面、２４０はダイパッド、２５０は半導体素子、２５１は端子、２６０はボンディングワイヤ、２７１、２７２はモールド固定用の平板、２８０は（モールド用の）テープ、２８５は（切断用の）テープ、２９０は封止用樹脂、４０１は単位の樹脂封止型半導体装置、４１０Ａは加工シート、４１５は枠部、４１６は治具孔、４１７は長孔部、４８５は切断ラインである。
【００１３】
はじめに、本発明の樹脂封止型半導体装置の実施の形態の第１の例を図１に基づいて説明する。
第１の例は、外部回路と接続するための外部端子部１１２と、半導体素子と接続するための内部端子部１１１をその一部として含むリード部１１４とを、一体的に連結してなる端子部材で、且つ、ハーフエッチング加工法を用いて、加工用素材（図示していない）から、外部端子部１１２の少なくとも一部を加工用素材の厚さの厚肉にし、リード部１１４をハーフエッチングにて薄肉にしている端子部材１１０を、複数個と、前記加工用素材から、ハーフエッチング加工法を用いて、全体を薄肉にして形成されたダイパッド１５０と、対向する２辺に沿い端子が配列されたペリフェラルパッド配列の半導体素子１２０とを用い、半導体素子１２０の所定の端子部１２１と所定の端子部材の内部端子部１１２とをワイヤボンディング接続して、樹脂封止した平板状方形の樹脂封止型半導体装置で、端子部材１１０をその対向する２辺に沿い配置したＳＯＮタイプの半導体装置である。
そして、各端子部材１１０を同じ向きにし、外部端子部１１１の表裏の面および内部端子部１１２の端子面が、それぞれ、一平面上に、揃うようにし、
周辺部に、外部端子部１１１を外側に向けて、内部端子部１１２を内側に向けて、各端子部材１１０を配しており、ダイパッド１５０のハーフエッチング面１５０ａの向きは、リード部１１４のハーフエッチング面１１４ａの向きとは反対にして、そのハーフエッチング面でない非エッチング面１５０ｂを端子部材１１０のハーフエッチング面１１４ａ側の外部端子部の非エッチング面１１７ａ、と一平面上に、揃うようにしている。
また、半導体素子１２０の端子面１２０ａを、端子部材１１０のハーフエッチング面側１１４ａと同じ向きにし、その裏面１２０ｂを、ダイパッド１５０の非エッチング面１５０ａ側に搭載しており、各端子部材１１０のリード部１１４のハーフエッチング面１１４ａ側に内部端子部１１１の端子面側を配し、リード部１１４のハーフエッチング面１１４ａ側でない各端子部材１１０の非ハーフエッチング面１１７と、各外部端子部１１１の外側側面１１８とを、露出させ、これ以外を樹脂１４０中にして樹脂封止されている。
尚、ここでは、ダイパッド１５０より大きい半導体素子１２０を用いている。
【００１４】
本例は、端子部材１１０の加工用素材（図示していない）の一面（ここでは非エッチング面１１７のこと）側が、露出するようにして樹脂封止していることにより、薄型化が達成できる。
また、半導体素子自体の厚さの薄化に伴ない、薄型化が達成できる。
本例では、加工用素材の厚さと半導体素子の総厚により、その厚さは決まる。また、本例においては、ワイヤボンディング接続をとっていることにより、接続作業性を良いものとし、且つ、接続信頼性を良いものとしている。
また、本例は、後述する、（図６、図７に示す）本発明の樹脂封止型半導体装置の製造方法により、面付け状態で作製できる、量産性に適した構造といえる。また、本例は、樹脂封止工程（モールド工程）においては、特別な形状にキャビティーを設ける必要はなく、平板状のものでその両側を抑えた状態でモールドが簡単に行える構造で、設備の面からも好ましい構造と言える。
【００１５】
端子部材１１０は、Ｃｕ、Ｃｕ系合金、４２％Ｎｉ−Ｆｅ系合金等が挙げられるが、通常は、導電性等から、Ｃｕ、Ｃｕ系合金が用いられる。
第１の例においては、外部端子部１１２の外側側面の端子面１１２ｂは切断部で、それ以外の表面には、接続用のめっき層が設けられている。
接続用のめっき層としては、半田めっき層、金めっき層、銀めっき層、パラジウムめっき層、錫めっき層から選ばれた１つの金属めっき層が用いられる。
封止用樹脂１４０としては、通常、エポキシ系のものが用いられるが、これに限定はされない。
【００１６】
次に、本発明の樹脂封止型半導体装置の実施の形態の第２の例を図２に基づいて説明する。
第２の例は、外部回路と接続するための外部端子部１１２と、半導体素子と接続するための内部端子部１１１をその一部として含むリード部１１４とを、一体的に連結してなる端子部材で、且つ、ハーフエッチング加工法を用いて、加工用素材（図示していない）から、外部端子部１１２の少なくとも一部を加工用素材の厚さの厚肉にし、リード部１１４をハーフエッチングにて薄肉にしている端子部材１１０を、複数個と、前記加工用素材から、ハーフエッチング加工法を用いて、全体を薄肉にして形成されたダイパッド１５０と、その４辺に沿い端子が配列されたペリフェラルパッド配列の半導体素子１２０Ａとを用い、半導体素子１２０の所定の端子部１２１と所定の端子部材の内部端子部１１２とをワイヤボンディング接続して、樹脂封止した平板状方形の樹脂封止型半導体装置で、端子部材１１０をその対向する２辺に沿い配置したＱＦＮタイプの半導体装置である。第２の例においては、端子部材１１０の配列を周辺の４辺に沿うように配設している。
端子部材１１０の配列、半導体素子１２０Ａ以外は第１の例と同じであり、半導体素子１２０Ａ以外の各部については、第１の例のものと同じである。
そして、第２の例も、第１の例と同様に、リード部１１４のハーフエッチング面１１４ａ側でない各端子部材１１０の非ハーフエッチング面１１７と、各外部端子部１１１の外側側面１１８とを、露出させ、これ以外を樹脂１４０中にして樹脂封止されている。
第２の例も端子部材１１０の加工用素材（図示していない）の一面（ここでは非エッチング面１１７のこと）側が、露出するようにして樹脂封止していることにより、薄型化が達成できる。
ここでも、ダイパッド１５０より大きい半導体素子１２０を用いている。
また、本例においても、ワイヤボンディング接続をとっていることにより、接続作業性を良いものとし、且つ、接続信頼性を良いものとしている。
また、本例も、基本的には、第１の例とほぼ同じように面付け状態で作製でき、量産性に適した構造と言える。
また、第１の例と同様に、樹脂封止工程（モールド工程）においては、特別な形状にキャビティーを設ける必要はなく、平板状のものでその両側を抑えた状態でモールドが簡単に行える構造で、設備の面からも好ましい構造と言える。
各部については第１の例と同じものが用いられる。
【００１７】
次に、本発明の樹脂封止型半導体装置の実施の形態の第３の例を図３に基づいて説明する。
第３の例の樹脂封止型半導体装置も、第１の例と同様、外部回路と接続するための外部端子部１１１と、半導体素子と接続するための内部端子部１１２をその一部として含むリード部１１４とを、一体的に連結してなる端子部材で、且つ、ハーフエッチング加工法を用いて、加工用素材から、外部端子部の少なくとも一部を加工用素材の厚さの厚肉にし、リード部をハーフエッチングにて薄肉にしている端子部材１１０を、複数個と、前記加工用素材から、ハーフエッチング加工法を用いて、全体を薄肉にして形成されたダイパッド１５０と、その対向する２辺に沿いパッドが配置されたペリフェラルパッド配列の２つの半導体素子１２５、１２５Ａとを用い、２つの半導体素子１２５、１２５Ａを積層した状態でダイパッドに搭載し、各半導体素子の所定の端子部と所定の端子部材の内部端子部とをワイヤボンディング接続して、樹脂封止した、ＳＯＮタイプの樹脂封止型半導体装置である。
そして、第１の例と同様、各端子部材１１０を同じ向きにし、外部端子部１１１の表裏の面および内部端子部１１２の端子面が、それぞれ、一平面上に、揃うようにし、周辺部に、外部端子部１１１を外側に向けて、内部端子部１１２を内側に向けて、各端子部材を配しており、ダイパッドのハーフエッチング面の向きは、リード部のハーフエッチング面の向きとは反対にして、そのハーフエッチング面でない非エッチング面を端子部材のハーフエッチング面側の外部端子の非エッチング面と一平面上に、揃うようにしている。
第３の例においては、ダイパッド１５０側の半導体素子１２５の端子面１２５ａを、端子部材１１０のハーフエッチング面１１４ａ側と同じ向きにし、その裏面１２５ｂを、ダイパッド１５０の非エッチング面１５０ｂ側に搭載し、更に、該ダイパッド１５０側の半導体素子１２５の端子面１２５ａ上に、もう１つの半導体素子１２５Ａをその裏面にて重ねて搭載している。
そして、各端子部材１１０のリード部１１４のハーフエッチング面１１４ａ側に内部端子部１１２の端子面側を配し、リード部１１４のハーフエッチング面１１４ａ側でない各端子部材の非ハーフエッチング面１１７と、各外部端子部の外側の側面１１８とを、露出させ、これ以外を樹脂中にして樹脂封止されている。半導体素子１２５、１２５Ａの端子１２６、１２６Ａの端子部材１１０との接続は、リード部１１４のエッチング面１１４ａで行なっている。
【００１８】
第３の例も端子部材１１０の加工用素材（図示していない）の一面（ここでは非エッチング面１１７のこと）側が、第１の例と同様、露出するようにして樹脂封止していることにより、半導体素子を１つのパッケージ内に重ね搭載するタイプのものにおいて、薄型化が達成できる。
半導体素子を２個用いるが基本的には第１の例と同様にして、面付けで作製することができる、量産性に適した構造で、また、第１の例と同様に、樹脂封止工程（モールド工程）においては、特別な形状にキャビティーを設ける必要はなく、平板状のものでその両側を抑えた状態でモールドが簡単に行える構造で、設備の面からも好ましい構造と言える。
各部については第１の例と同じものが用いられる。
【００１９】
次に、本発明の樹脂封止型半導体装置の実施の形態の第４の例を図４に基づいて説明する。
第４の例の樹脂封止型半導体装置も、第１の例と同様、外部回路と接続するための外部端子部１１１と、半導体素子と接続するための内部端子部１１２をその一部として含むリード部１１４とを、一体的に連結してなる端子部材で、且つ、ハーフエッチング加工法を用いて、加工用素材から、外部端子部の少なくとも一部を加工用素材の厚さの厚肉にし、リード部をハーフエッチングにて薄肉にしている端子部材１１０を、複数個と、前記加工用素材から、ハーフエッチング加工法を用いて、全体を薄肉にして形成されたダイパッド１５０と、その４辺に沿いパッドが配置されたペリフェラルパッド配列の２つの半導体素子１２８、１２８Ａとを用い、２つの半導体素子１２８、１２８Ａを積層した状態でダイパッドに搭載し、各半導体素子の所定の端子部と所定の端子部材の内部端子部とをワイヤボンディング接続して、樹脂封止した、ＱＦＮタイプの樹脂封止型半導体装置である。
本例は、第３の例において、その対向する２辺に沿いパッドが配置されたペリフェラルパッド配列の半導体装置１２５、１２５Ａに代え、その４辺に沿いパッドが配置されたペリフェラルパッド配列の半導体装置１８５、１８５Ａを用い、更に、端子部材１１０を周辺４辺に沿い配設した形態のものである。
半導体素子１２８、１２９Ａの端子１２９、１２９Ａの端子部材との接続は、リード部１１４のエッチング面１１４ａで行なっている。
【００２０】
第４の例も端子部材１１０の加工用素材（図示していない）の一面（ここでは非エッチング面１１７のこと）側が、第１の例と同様、露出するようにして樹脂封止していることにより、薄型化が達成できる。
本例も、半導体素子を２個用いるが基本的には第１の例と同様にして、面付けで作製することができ、量産性に適した構造で、また、第１の例と同様に、樹脂封止工程（モールド工程）においては、特別な形状にキャビティーを設ける必要はなく、平板状のものでその両側を抑えた状態でモールドが簡単に行える構造で、設備の面からも好ましい構造と言える。
各部については第１の例と同じものが用いられる。
【００２１】
第１の例、第３の例の変形例としては、樹脂のモールド領域がこれらとは若干異なり、
リード部１１４のハーフエッチング面１１４ａ側でない各端子部材の非ハーフエッチング面１１７と、各端子部材の外側側面１８を含む側面部１９とを露出させ、これ以外を樹脂中にして樹脂封止されている形態の、それぞれ、図５（ａ）、図５（ｂ）に示すものが挙げられる。
勿論、第２の例、第４の例の変形例として、同様の形態を採るものを挙げることができる。
第３の例、第４の例の変形例としては、それぞれ、第３の例において、半導体素子１２５Ａをセンターパッド配列の半導体素子に置き換えたもの、第４の例において、半導体素子１２８Ａをセンターパッド配列の半導体素子に置き換えたものが挙げられる。
第３の例において、半導体素子１２５、１２５Ａを、３個以上の半導体素子に置き換え、あるいは、第４の例において、半導体素子１２８、１２５８を、３個以上の半導体素子に置き換え、これらの半導体素子を積層した状態とし、各半導体素子の所定の端子部と所定の端子部材の内部端子部とをワイヤボンディング接続して、樹脂封止した樹脂封止型半導体装置も変形例として挙げられる。
この場合、ダイパッド側の半導体素子をペリフェラルパッド配列の半導体素子とし、その端子面を、端子部材のハーフエッチング面側と同じ向きにし、その裏面を、ダイパッドの非エッチング面側に搭載し、更に、前記ダイパッド側の半導体素子の端子面でない裏面上に、一番上以外をペリフェラルパッド配列の半導体素子として、順次、その裏面側を前記ダイパッド側の半導体素子側に向けて、半導体素子を重ねて搭載している。
【００２２】
次いで、第１の例の樹脂封止型半導体装置の製造方法の１例を図６、図７に基づいて説明する。
尚、これを以って、本発明の樹脂封止型半導体装置の製造方法の実施の形態の１例の説明に代える。
先ず、加工用素材２１０の両面に所定形状にレジスト２２０を配設し（図６（ａ））、１つの樹脂封止型半導体装置の端子部材の配置に対応した、端子部材の配置を１単位として、この配置状態に、ハーフエッチング技術を用いたエッチング加工法にて、両面からエッチングを行い、端子部材２３０を、支持部２３６にて連結した状態で、面付けして形成する。（図６（ｂ））
これにより、１つの樹脂封止型半導体装置の端子部材の配置に対応した、端子部材の配置を１単位として、これが支持部２３６にて連結され面付けされた、加工シート２１０Ａを得る。
加工用素材２１０としては、Ｃｕ、Ｃｕ系合金、４２合金（Ｎｉ４２％−Ｆｅ合金）等が用いられ、エッチング液としては、塩化第二鉄溶液が用いられる。
また、レジスト３２０としては、耐エッチング性のもので、所望の解像性を有し、処理性の良いものであれば特に限定はされない。
次いで、レジスト２２０を除去（図６（ｃ））後、洗浄処理等を施し、全面に接続用の表面めっきを施した（図示していない）後、面付け形成され、表面めっきが施された加工シート２１０Ａのハーフエッチング面２３４ａ側ではない側に、面付け分の数だけ、半導体素子２５０を所定の位置に位置決めして、ダイパッド２４０に載せ、この状態で、各半導体素子２５０について、その端子２５１と端子部材２３０の内部端子部（図１の１１１に相当）のハーフエッチング面である端子面とをワイヤボンディング接続する。（図６（ｄ））
次いで、モールド用のテープ２８０を、加工シート３２０Ａのハーフエッチング面２３４ａ側を覆うように、平面状に貼り、 更に、表裏をモールド固定用の平板２７１、２７２にて挟み、加工シート２１０Ａ全体について、一括してモールドを行う。（図７（ｅ））
尚、加工シート２１０Ａの端子部材２３０を支持する支持部２３６は、通りぬけ孔等を設けたもので、モールドの際、各面付け間モールド用の樹脂が通りぬけできるような形状になっている。
【００２３】
次いで、表裏のモールド固定用の平板２７１、２７２を除去し、更にテープ２８０を除去し（図７（ｆ））、切断用のテープ２８５を貼り（図７（ｇ））、該切断用のテープ２８５とは反対側からダイシングソー（図示していない）にて切断して、樹脂封止型半導体装置を１個づつに個片化して得る。（図７（ｈ））
ダイシングソー（図示していない）による切断状態は、例えば、図８（ａ）や、図８（ｂ）のようになる。
尚、図８において、単位の樹脂封止型半導体装置４０１は、切断ライン４８５にて互いに分けられた各領域であり、ここでは、説明を分かり易くするため図示していないが、図７（ｇ）の支持部２３６を凹部２３５で切断する。
加工シート２１０Ａは、フレームとも呼ばれる。
また、この切断面が、作製される樹脂封止型半導体装置の外部端子の外側側面２３８となる。
尚、切り欠け部２３５Ａの切断された面でない面には接続用のめっきが配設されておりこの部分は接続用に利用し易い。
このようにして、図１に示す第１の例の樹脂封止型半導体装置は製造することができる。
【００２４】
第２の例〜第４の例の製造は、半導体素子と端子部材のリード部との位置関係は異なる、あるいは、半導体素子を積層する工程やワイヤボンディング工程が余分にあっても、大筋は、上記第１の例の製造と同様にして行うことができる。
【００２５】
図５に示す、第１の例、第３の例の変形例のように、リード部１１４のハーフエッチング面１１４ａ側でない各端子部材の非ハーフエッチング面１１７と、各端子部材の外側側面１８を含む側面部１９とを露出させ、これ以外を樹脂中にして樹脂封止されている形態のものの、樹脂モールドは、図６〜図７に示す製造方法のように面付け状態で半導体素子を搭載し、更にワイヤボンディング接続を行った後、露出させる外部端子部の端子面は、上記製造法方と同様、平板で抑え、反対側に、所定の型を用いて所定のキャビティーを形成して、分割方式により、繰り返し行う。
例えば、図８（ａ）に示す、１６個分の型を用い、領域Ｇ毎に繰り返して行う。
他の変形例の製造についても、半導体素子を積層する工程やワイヤボンディング工程が余分にあっても、大筋は、第１の例の製造、あるいは、図５に示す、第１の例、第３の例の変形例についての製造方法と同様にして行うことができる。
【００２６】
【発明の効果】
本発明は、上記のように、更なる小型化、薄型化を廉価に達成でき、量産性に適し、且つ、耐湿性、放熱性に優れたＱＦＮパッケージあるいはＳＯＮパッケージ構造の半導体装置の提供を可能にした。
特に、積層型のＱＦＮパッケージあるいはＳＯＮパッケージ構造の樹脂封止型半導体装置で、このような半導体装置の提供を可能にした。
同時に、このような薄型の樹脂封止型半導体装置の製造方法の提供を可能とした。
【図面の簡単な説明】
【図１】図１（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第１の例の断面図で、図１（ｂ）は図１（ａ）のＡ１側から透視してみた図である。
【図２】図２（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第２の例の断面図で、図２（ｂ）は図２（ａ）のＢ１側から透視してみた図である。
【図３】図３（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第３の例の断面図で、図３（ｂ）は図３（ａ）のＣ１側から透視してみた図である。
【図４】図４（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第４の例の断面図で、図４（ｂ）は図４（ａ）のＤ１側から透視してみた図である。
【図５】図５（ａ）、図５（ｂ）はそれぞれ第１の例、第３の例の変形例の断面図である。
【図６】本発明の樹脂封止型半導体装置の製造方法の実施の形態の１例の製造工程の一部を示した工程断面図である。
【図７】図６に続く工程を示した工程断面図である。
【図８】ダイシングソーによる切断状態を示した図である。
【符号の説明】
１１０ 端子部材
１１１ 外部端子部
１１２ 内部端子部
１１２ａ、１１２ｂ 端子面
１１４ リード部
１１４ａ ハーフエッチング面
１１６ 切り欠け部
１１７、１１７ａ 非エッチング面
１１８ 側面
１２０、１２０Ａ 半導体素子（半導体チップあるいは単にチップとも言う）
１２０ａ 端子面
１２０ｂ 裏面
１２１ 端子
１２５、１２５Ａ 半導体素子（半導体チップあるいは単にチップとも言う）
１２５ａ 端子面
１２５ｂ 裏面
１２６、１２６Ａ 端子
１２８、１２８Ａ 半導体素子（半導体チップあるいは単にチップとも言う）
１２８ａ 端子面
１２８ｂ 裏面
１２９、１２９Ａ 端子
１３０、１３５、１３５Ａ ボンディングワイヤ
１３６、１３６Ａ ボンディングワイヤ
１４０ 封止用樹脂
１５０ ダイパッド
１５０ａ ハーフエッチング面
１５０ｂ 非エッチング面
２１０ 加工用素材
２１０Ａ 加工シート
２２０ レジスト
２２５ 開口
２３０ 端子部材
２３１ 外部端子部
２３２ 内部端子部
２３４ リード部
２３５ 凹部
２３５Ａ 切り欠け部
２３６ 支持部（連結部とも言う）
２３７ 非エッチング面（露出面）
２３８ 側面
２４０ ダイパッド
２５０ 半導体素子
２５１ 端子
２６０ ボンディングワイヤ
２７１、２７２ モールド固定用の平板
２８０ （モールド用の）テープ、２８５は（切断用の）テープ
２９０ 封止用樹脂
４０１ 単位の樹脂封止型半導体装置
４１０Ａ 加工シート
４１５ 枠部
４１６ 治具孔
４１７ 長孔部
４８５ 切断ライン[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a small and thin resin-sealed semiconductor device using a terminal member and a die pad formed by etching, and a method of manufacturing the same.
[0002]
[Prior art]
In recent years, in order to respond to the miniaturization of electronic devices, it has been required to mount semiconductor components mounted on electronic devices at a high density, and accordingly, semiconductor components have become smaller and thinner. There is a demand for a package that can achieve a thinner device at a lower cost.
Under such circumstances, a resin-sealed semiconductor device having a structure in which the upper and lower surfaces of connection leads are exposed as disclosed in JP-A-11-307675, JP-A-260989 proposes a resin-sealed semiconductor device in which a part of a connection lead is exposed and used as an external terminal.
Japanese Patent Application Laid-Open Nos. 11-307675 and 11-260989 have a structure in which one surface of a die pad is exposed to the outside, and a semiconductor device is mounted on a surface that is not the exposed surface. This is an unsuitable structure for performing molding all at once.
JP-A-11-307675 and JP-A-11-260989 disclose a resin-encapsulated semiconductor device in which a semiconductor element is further laminated on a semiconductor element having a peripheral pad array to form a single package. No good structure is disclosed.
[0003]
[Patent Document 1]
JP-A-11-307675
[Patent Document 2]
JP-A-11-260989
[0004]
[Problems to be solved by the invention]
As described above, in recent years, semiconductor components have been reduced in size and thickness, and packages capable of achieving further reduction in thickness at low cost have been demanded.
The present invention corresponds to these, and specifically, a QFN (Quad) that can achieve further miniaturization and thinning of semiconductor components at low cost, is suitable for mass production, and is excellent in moisture resistance and heat dissipation. An object of the present invention is to provide a semiconductor device having a Flat Nonlead (Package) package or a Small Outline Nonlead (SON) package structure.
Furthermore, another object is to provide a resin-encapsulated semiconductor device in which one or more semiconductor elements are stacked on a semiconductor element having a peripheral pad arrangement to form a single package, which is thin and has a structure with good mass productivity. .
At the same time, an object is to provide a method for manufacturing such a resin-sealed semiconductor device.
[0005]
[Means for Solving the Problems]
The resin-encapsulated semiconductor device of the present invention integrally connects an external terminal portion for connecting to an external circuit and a lead portion including an internal terminal portion for connecting to a semiconductor element as a part thereof. The terminal member is formed by using a half-etching processing method, and at least a part of the external terminal portion is made thicker than the processing material from the processing material, and the lead portion is thinned by half-etching. A semiconductor device is mounted on a die pad by using a plurality of terminal members and one die pad formed by using a half-etching method from the above-mentioned processing material, and using a half-etching method, and a semiconductor element. A resin-sealed semiconductor device in which a predetermined terminal portion of an element and an internal terminal portion of a predetermined terminal member are wire-bonded to form a resin-sealed resin device. And the terminal surfaces of the internal terminal portions are aligned on one plane, respectively, and the terminal members are arranged around the periphery, with the external terminal portions facing outward and the internal terminal portions facing inward. The direction of the half-etched surface of the die pad is opposite to the direction of the half-etched surface of the lead portion, and the non-etched surface that is not the half-etched surface is the non-etched surface of the external terminal portion on the half-etched surface side of the terminal member. The terminal surface of the semiconductor element is oriented in the same direction as the half-etched surface side of the terminal member, and the back surface is mounted on the non-etched surface side of the die pad. The terminal surface side of the internal terminal portion is arranged on the half-etched surface side of the lead portion, and the non-half-etched surface of each terminal member that is not the half-etched surface side of the lead portion and the outside of each external terminal portion. A side surface, is exposed, is characterized in that the addition to this resin-sealed in the resin.
Alternatively, the resin-encapsulated semiconductor device of the present invention integrally connects an external terminal portion for connecting to an external circuit and a lead portion including as a part thereof an internal terminal portion for connecting to a semiconductor element. Using a half-etching method, at least a part of the external terminal portion is made thicker to the thickness of the processing material, and the lead portion is made thinner by half-etching. A plurality of terminal members, a die pad formed by using a half-etching method from the material for processing, a thin die as a whole, a plurality of semiconductor elements, and the plurality of semiconductor elements are stacked. A resin-encapsulated semiconductor device, which is mounted on a die pad as a state in which a predetermined terminal portion of each semiconductor element and an internal terminal portion of a predetermined terminal member are connected by wire bonding, and is resin-sealed, With the terminal members in the same direction, the front and back surfaces of the external terminal unit and the terminal surface of the internal terminal unit should be aligned on one plane, respectively. The half-etched surface of the die pad is oriented in the opposite direction to the half-etched surface of the lead, and the non-etched surface that is not the half-etched surface is half-etched of the terminal member. The semiconductor element on the die pad side is a semiconductor element of a peripheral pad array, and the terminal surface is the same as the half-etched surface side of the terminal member. Orientation, the back surface is mounted on the non-etching surface side of the die pad, and the other than the top is placed on the back surface other than the terminal surface of the semiconductor element on the die pad side. As the semiconductor elements of the general pad arrangement, semiconductor elements are sequentially mounted with the back side facing the semiconductor element side on the die pad side, and the terminal of the internal terminal portion is mounted on the half-etched surface side of the lead of each terminal member. The surface side is disposed, the non-half-etched surface of each terminal member that is not the half-etched surface side of the lead portion, and the outer side surface of each external terminal portion are exposed, and the other portions are resin-sealed. It is characterized by the following.
In the above-described resin-sealed semiconductor device, the semiconductor device is resin-sealed, and is entirely plate-shaped square.
[0006]
Further, in the resin-encapsulated semiconductor device of the present invention, an external terminal portion for connecting to an external circuit and a lead portion including an internal terminal portion for connecting to a semiconductor element as a part thereof are integrally connected. Using a half-etching method, at least a part of the external terminal portion is made thicker to the thickness of the processing material, and the lead portion is made thinner by half-etching. A plurality of terminal members are formed from the above-mentioned processing material, and one half of the die pad is formed by using a half-etching method, and one semiconductor element is used. The semiconductor element is mounted on the die pad. A resin-sealed semiconductor device in which a predetermined terminal portion of a semiconductor element and an internal terminal portion of a predetermined terminal member are wire-bonded to be resin-sealed, wherein each terminal member is oriented in the same direction; The front and back surfaces and the terminal surfaces of the internal terminal portions are aligned on one plane, respectively, and the outer terminal portions are directed outward, the internal terminal portions are directed toward the peripheral portion, and each terminal member is disposed. The direction of the half-etched surface of the die pad is opposite to the direction of the half-etched surface of the lead portion, and the non-etched surface that is not the half-etched surface is the same as that of the external terminal portion on the half-etched surface side of the terminal member. On the same plane as the etching surface, it is aligned, the terminal surface of the semiconductor element is oriented in the same direction as the half etching surface side of the terminal member, and the back surface is mounted on the non-etching surface side of the die pad, The terminal surface of the internal terminal portion is arranged on the half-etched surface side of the lead portion of each terminal member, and the non-half-etched surface of each terminal member that is not the half-etched surface side of the lead portion; Exposing a side surface portion including the outer side, and is characterized in that the addition to this resin-sealed in the resin.
Alternatively, the resin-encapsulated semiconductor device of the present invention integrally includes an external terminal portion for connecting to an external circuit and a lead portion including an internal terminal portion for connecting to a semiconductor element as a part thereof. Using a half-etching method, at least a part of the external terminal portion is made thicker to the thickness of the processing material, and the lead portion is thinned by half-etching. A plurality of terminal members, and a die pad formed by using a half-etching method from the material for processing, and using a half-etching method, and a plurality of semiconductor elements. A resin-encapsulated semiconductor device in which the semiconductor device is mounted on a die pad in a stacked state, and a predetermined terminal portion of each semiconductor element and an internal terminal portion of a predetermined terminal member are connected by wire bonding to be resin-sealed. The terminal members are oriented in the same direction so that the front and back surfaces of the external terminal portion and the terminal surface of the internal terminal portion are aligned on one plane, respectively. Each terminal member is arranged with the inside facing inward, and the direction of the half-etched surface of the die pad is opposite to the direction of the half-etched surface of the lead portion, and the non-etched surface that is not the half-etched surface is the terminal member. The non-etched surface of the external terminal portion on the half-etched surface side is flush with the non-etched surface, and the semiconductor element on the die pad side is a semiconductor element of a peripheral pad array, and the terminal surface is on the half-etched surface side of the terminal member. In the same direction as above, the back surface is mounted on the non-etched surface side of the die pad, and further, on the back surface that is not the terminal surface of the semiconductor element on the die pad side, except the top. As semiconductor elements of the referential pad arrangement, semiconductor elements are sequentially mounted with the back side facing the semiconductor element side on the die pad side, and the internal terminal section is provided on the half-etched surface side of the lead section of each terminal member. And the non-half-etched surface of each terminal member, which is not the half-etched surface side of the lead portion, and the side surface portion including the outer side surface of each terminal member are exposed, and the other portions are placed in a resin and resin-sealed. It is characterized by having been done.
[0007]
Further, in the above-mentioned resin-sealed semiconductor device, a cutout portion is provided on an outer side surface portion of the external terminal portion.
Further, in the above resin-sealed semiconductor device, the terminal member is made of Cu, a Cu-based alloy, or a 42% Ni—Fe-based alloy.
Further, in the above resin-encapsulated semiconductor device, the terminal surface of the internal terminal portion and the terminal surface of the front and back of the external terminal portion are selected from a solder plating layer, a gold plating layer, a silver plating layer, a palladium plating layer, and a tin plating layer. The one metal plating layer provided is provided as a plating layer for connection.
[0008]
A method for manufacturing a resin-sealed semiconductor device according to the first aspect of the present invention is a method for manufacturing a resin-sealed semiconductor device according to any one of claims 1 to 3, wherein (a) one resin sealed The external terminal portion side of the terminal member is connected to the support portion by etching using half-etching technology, with the arrangement of the terminal member and the die pad corresponding to the arrangement of each terminal member and the die pad of the stop type semiconductor device as one unit. In a state where the processed sheet is fixed, the processing step of obtaining a processed sheet that is formed by imposition, (b) a plating processing step of applying surface plating for connection, and (c) a state in which the processed sheet is fixed, A semiconductor element mounting step of positioning the semiconductor element by the amount of the imposition and mounting the semiconductor element on the die pad; and (d) in this state, for each semiconductor element, wire-bond the terminal and the terminal surface of the internal terminal portion of the terminal member. (E) applying a molding tape in a planar shape so as to cover the half-etched surface side of the processed sheet formed by imposition, attaching in a planar shape, applying a tape, and (f) A) a mold molding step of enclosing the front and back sides with a mold fixing flat plate so that the mold tape side is attached to the tape and the opposite side is provided with a cavity, and molding the entire processing sheet at once; (G) The mold fixing flat plate and the tape on the front and back are removed, a cutting tape is attached, and cut with a dicing saw from the side opposite to the cutting tape to form one resin-encapsulated semiconductor device. And a singulation step of individually singulation.
[0009]
A method for manufacturing a resin-sealed semiconductor device according to a second aspect of the present invention is a method for manufacturing a resin-sealed semiconductor device according to any one of claims 4 to 5, wherein (a1) one resin sealed The external terminal portion side of the terminal member is connected to the support portion by etching using half-etching technology, with the arrangement of the terminal member and the die pad corresponding to the arrangement of each terminal member and the die pad of the stop type semiconductor device as one unit. In a state where the processed sheet is fixed, the processing step of obtaining a processed sheet formed by imposition, (b1) a plating processing step of performing surface plating for connection, and (c1) a state where the processed sheet is fixed, A semiconductor element mounting step of positioning and mounting the semiconductor element on the die pad by an amount corresponding to the imposition; (d1) In this state, for each semiconductor element, the terminals and the terminal surfaces of the internal terminal portions of the terminal members are wiped. A wire bonding step for bonding connection; (e1) a step of applying a molding tape in a plane so as to cover the half-etched surface side of the imposed and formed work sheet; ) The mold tape side is attached to the tape and fixed with a mold fixing flat plate. On the opposite side, a predetermined mold is provided to cover a predetermined number of impositions, and the mold fixing flat plate and the mold are provided. (G1) Remove the flat plate and tape for fixing the mold, attach a cutting tape, and cut with a dicing saw from the side opposite to the cutting tape. A step of singulating the resin-encapsulated semiconductor device one by one.
[0010]
[Action]
With such a configuration, the resin-encapsulated semiconductor device of the present invention can achieve further reduction in size and thickness of semiconductor components at low cost, is suitable for mass production, and is excellent in moisture resistance and heat dissipation. It is possible to provide a semiconductor device having a QFN package or SON package structure.
Furthermore, a resin-encapsulated semiconductor device in which one or more semiconductor elements are stacked on a semiconductor element having a peripheral pad arrangement to form a single package makes it possible to provide a semiconductor device having a thin and mass-produced structure. .
In the case of this semiconductor element laminated structure, a system package (also referred to as a system-in-package or SIJ) that realizes a system LSI with a package in which semiconductor elements are stacked in a three-dimensional direction in one package corresponding to thinning of a semiconductor chip. It is possible to apply as.
That is, at least a part of the external terminal portion is made thick by the thickness of the processing material, and is integrally connected to a lead portion including the internal terminal portion as a part thereof. Using a terminal member, a die pad formed entirely from a processing material by using a half-etching method, and a semiconductor element.Specifically, the terminal member is made to have the same direction, and the front and back of the external terminal portion are formed. Each terminal member is arranged such that the surface and the terminal surface of the internal terminal portion are aligned on one plane, respectively, and the external terminal portion is directed outward and the internal terminal portion side is directed inward in the peripheral portion, The non-half-etched surface of each terminal member that is not on the half-etched surface side of the lead portion, and the outer side surface of each external terminal portion is exposed, or the non-half-etched surface of each terminal member that is not on the half-etched surface side of the lead portion. , An outer side surface of the external terminal portion, is exposed, by being sealed with resin in the resin other than this, we have achieved this.
Further, by employing wire bonding connection, the connection workability is improved and the connection reliability is improved.
In addition, by the method for manufacturing a resin-sealed semiconductor device of the present invention, which will be described later, it can be manufactured in an imposed state, and it can be said that the structure has good mass productivity.
In particular, the resin-encapsulated, plate-like square as a whole, the non-half-etched surface of each terminal member that is not the half-etched surface side of the lead portion, and the outer side surface of the external terminal portion are exposed. When the resin sealing is performed, it is not necessary to provide a special mold in the resin sealing step (molding step), the batch molding can be easily performed, and it can be said that the structure is preferable in terms of mass productivity and equipment.
Specifically, the direction of the half-etched surface of the die pad is opposite to the direction of the half-etched surface of the lead portion, and the non-etched surface that is not the half-etched surface is the same as the non-etched surface of the external terminal on the half-etched surface side of the terminal member. The fact that they are aligned on one plane facilitates batch molding.
Further, since the half-etched surface side of the die pad is filled with the sealing resin, cracks and chips on the chip are less likely to occur, and moisture resistance can be improved by resin sealing.
Also, the positional relationship between the die pad and the terminal member as described above makes it possible to mount a semiconductor element having a size larger than that of the die pad.
Also, the non-half-etched surface of each terminal member that is not on the half-etched surface side of the lead portion and the outer side surface of each external terminal portion are exposed, or the non-half-etched surface of each terminal member that is not on the half-etched surface side of the lead portion. By exposing the surface and the outer side surface of each external terminal portion, good heat dissipation is achieved.
In addition, since the notch is provided on the outer side surface of the external terminal portion, it is easy to cut the wafer into individual pieces.
Examples of the terminal member include those made of Cu, a Cu-based alloy, and a 42% Ni-Fe-based alloy.
In addition, one metal plating layer selected from a solder plating layer, a gold plating layer, a silver plating layer, a palladium plating layer, and a tin plating layer is connected to the terminal surface of the internal terminal portion and the front and back terminal surfaces of the external terminal portion. By using the plating layer for the wire bonding, the wire bonding connection is made highly reliable.
[0011]
According to the first method of manufacturing a resin-encapsulated semiconductor device of the present invention, the thin resin-encapsulated semiconductor device of the first to third aspects of the present invention can be manufactured with high productivity by adopting such a configuration. And
Further, according to the second method of manufacturing a resin-encapsulated semiconductor device of the present invention, by adopting such a configuration, the thin resin-encapsulated semiconductor device of the fourth or fifth invention can be manufactured with good mass productivity. I can do it.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
An embodiment of the present invention will be described with reference to the drawings.
FIG. 1A is a cross-sectional view of a first example of an embodiment of the resin-sealed semiconductor device of the present invention, and FIG. 1B is a view seen through from the A1 side in FIG. 1A. FIG. 2A is a cross-sectional view of a second embodiment of the resin-sealed semiconductor device according to the present invention, and FIG. 2B is a view seen from the B1 side of FIG. 2A. FIG. 3A is a sectional view of a third embodiment of the resin-sealed semiconductor device according to the present invention, and FIG. 3B is a perspective view of FIG. 3A from the C1 side. FIG. 4A is a cross-sectional view of a fourth embodiment of the resin-sealed semiconductor device according to the present invention, and FIG. 4B is a perspective view from the D1 side of FIG. 4A. FIGS. 5A and 5B are cross-sectional views of a modified example of the first example and the third example, respectively, and FIG. 6 shows a method of manufacturing a resin-sealed semiconductor device of the present invention. Process break showing a part of the manufacturing process of one example of the embodiment In FIG, 7 is a process sectional view illustrating a step following FIG. 6, FIG. 8 is a view showing a cut state by the dicing saw.
1A is a diagram viewed from the A1-A2 side in FIG. 1B, FIG. 2A is a diagram viewed from the B1-B2 side in FIG. 2B, and FIG. 4) is a view from the C1-C2 side in FIG. 3B, and FIG. 4A is a view from the D1-D2 side in FIG. 4B.
Further, the double-headed arrow in FIG. 7G indicates the direction in which the dicing saw moves up and down.
1 to 8, 110 is a terminal member, 111 is an external terminal, 112 is an internal terminal, 112a and 112b are terminal surfaces, 114 is a lead, 114a is a half-etched surface, 116 is a cutout, 117, 117a is a non-etched surface, 118 is a side surface, 120 and 120A are semiconductor elements (also referred to as semiconductor chips or simply chips), 120a is a terminal surface, 120b is a back surface, 121 is a terminal, and 125 and 125A are semiconductor elements (a semiconductor chip or simply a chip). 125a is a terminal surface, 125b is a back surface, 126 and 126A are terminals, 128 and 128A are semiconductor elements (also referred to as semiconductor chips or simply chips), 128a is a terminal surface, 128b is a back surface, and 129 and 129A are terminals , 130, 135 and 135A are bonding wires and 136 and 136A are bonding wires. 140, a die pad, 150a is a half-etched surface, 150b is a non-etched surface, 210 is a processing material, 210A is a processing sheet, 220 is a resist, 225 is an opening, 230 is a terminal member, 231 Is an external terminal portion, 232 is an internal terminal portion, 234 is a lead portion, 235 is a concave portion, 235A is a cutout portion, 236 is a supporting portion (also referred to as a connecting portion), 237 is a non-etched surface (exposed surface), and 238 is a side surface. , 240 is a die pad, 250 is a semiconductor element, 251 is a terminal, 260 is a bonding wire, 271 and 272 are flat plates for fixing a mold, 280 is a tape (for a mold), 285 is a tape for a (cutting), and 290 is a seal. Resin for stopping, 401 is a resin-sealed semiconductor device of a unit, 410A is a processing sheet, 415 is a frame portion, 416 is a jig hole, 17 elongated hole, 485 is a cutting line.
[0013]
First, a first embodiment of the resin-sealed semiconductor device according to the present invention will be described with reference to FIG.
In the first example, a terminal is formed by integrally connecting an external terminal portion 112 for connecting to an external circuit and a lead portion 114 that includes an internal terminal portion 111 for connecting to a semiconductor element as a part thereof. Using a member and a half-etching method, at least a part of the external terminal portion 112 is made thicker than the material for processing from a material for processing (not shown), and the lead portion 114 is half-etched. A plurality of terminal members 110 are thinned, and a die pad 150 is formed from the processing material by using a half-etching method, and the terminals are arranged along two opposing sides. Using the semiconductor element 120 having the peripheral pad arrangement, the predetermined terminal portion 121 of the semiconductor element 120 and the internal terminal portion 112 of the predetermined terminal member are connected by wire bonding, In the resin sealed semiconductor device of a flat square with sealed fat sealing a semiconductor device SON type arranged along the terminal member 110 to the two sides thereof facing.
Then, the respective terminal members 110 are oriented in the same direction, and the front and back surfaces of the external terminal portion 111 and the terminal surface of the internal terminal portion 112 are respectively aligned on one plane,
In the peripheral portion, each terminal member 110 is disposed with the external terminal portion 111 facing outward and the internal terminal portion 112 facing inward. The orientation of the half-etched surface 150a of the die pad 150 is the half of the lead portion 114. The direction of the etched surface 114a is reversed, and the non-etched surface 150b, which is not the half-etched surface, is flush with the non-etched surface 117a of the external terminal portion on the half-etched surface 114a side of the terminal member 110 so as to be aligned with one plane. I have.
Further, the terminal surface 120a of the semiconductor element 120 is oriented in the same direction as the half-etched surface side 114a of the terminal member 110, and the back surface 120b is mounted on the non-etched surface 150a side of the die pad 150. The terminal surface side of the internal terminal portion 111 is arranged on the half-etched surface 114a side of the portion 114, and the non-half-etched surface 117 of each terminal member 110 which is not the half-etched surface 114a side of the lead portion 114 and the outside of each external terminal portion 111 The side surface 118 is exposed, and the other parts are sealed in the resin 140 with the resin 140 remaining.
Here, a semiconductor element 120 larger than the die pad 150 is used.
[0014]
In this example, the terminal member 110 is sealed with a resin so that one surface (here, the non-etched surface 117) side of a processing material (not shown) is exposed, thereby achieving a reduction in thickness. .
In addition, a reduction in thickness can be achieved with a reduction in the thickness of the semiconductor element itself.
In this example, the thickness is determined by the thickness of the processing material and the total thickness of the semiconductor element. Further, in this example, the connection workability is improved and the connection reliability is improved by adopting the wire bonding connection.
In addition, this example can be said to be a structure suitable for mass productivity, which can be manufactured in an imposed state by a method for manufacturing a resin-sealed semiconductor device of the present invention (shown in FIGS. 6 and 7), which will be described later. Also, in this example, in the resin sealing step (molding step), it is not necessary to provide a cavity in a special shape, and the structure is such that the molding can be easily performed in a state of being flat with both sides suppressed. It can be said that the structure is preferable also from the viewpoint of.
[0015]
As the terminal member 110, Cu, a Cu-based alloy, a 42% Ni-Fe-based alloy, or the like can be used, but usually, Cu or a Cu-based alloy is used because of conductivity or the like.
In the first example, the terminal surface 112b on the outer side surface of the external terminal portion 112 is a cut portion, and the other surface is provided with a plating layer for connection.
As the plating layer for connection, one metal plating layer selected from a solder plating layer, a gold plating layer, a silver plating layer, a palladium plating layer, and a tin plating layer is used.
As the sealing resin 140, an epoxy resin is usually used, but the resin is not limited to this.
[0016]
Next, a second embodiment of the resin-sealed semiconductor device according to the present invention will be described with reference to FIG.
In a second example, a terminal is formed by integrally connecting an external terminal portion 112 for connecting to an external circuit and a lead portion 114 which includes an internal terminal portion 111 for connecting to a semiconductor element as a part thereof. Using a member and a half-etching method, at least a part of the external terminal portion 112 is made thicker than the material for processing from a material for processing (not shown), and the lead portion 114 is half-etched. A plurality of terminal members 110 are thinned, and a die pad 150 is formed from the processing material by using a half-etching method so as to be entirely thin, and terminals are arranged along four sides thereof. A predetermined terminal part 121 of the semiconductor element 120 and an internal terminal part 112 of a predetermined terminal member are connected by wire bonding using the semiconductor element 120A having the peripheral pad arrangement. In the resin sealed semiconductor device sealed flat square, a semiconductor device of the QFN type arranged along the terminal member 110 to the two sides thereof facing. In the second example, the arrangement of the terminal members 110 is arranged along four peripheral sides.
The arrangement other than the arrangement of the terminal members 110 and the semiconductor element 120A is the same as that of the first example, and each part other than the semiconductor element 120A is the same as that of the first example.
In the second example, similarly to the first example, the non-half-etched surface 117 of each terminal member 110 that is not on the half-etched surface 114a side of the lead portion 114 and the outer side surface 118 of each external terminal portion 111 are formed. It is exposed, and the other parts are sealed in a resin 140.
In the second example as well, the terminal member 110 is sealed with a resin so that one side (here, the non-etched surface 117) of a processing material (not shown) is exposed, thereby achieving a reduction in thickness. it can.
Here, the semiconductor element 120 larger than the die pad 150 is used.
Also in this example, the connection workability is improved and the connection reliability is improved by adopting the wire bonding connection.
Also, this example can be basically manufactured in an imposition state almost in the same manner as the first example, and can be said to be a structure suitable for mass production.
Further, similarly to the first example, in the resin sealing step (molding step), it is not necessary to provide a cavity in a special shape, and the molding can be easily performed in a state where both sides are suppressed with a flat plate shape. It can be said that the structure is preferable from the viewpoint of facilities.
The same components as those in the first example are used for each part.
[0017]
Next, a third embodiment of the resin-sealed semiconductor device according to the present invention will be described with reference to FIG.
The resin-encapsulated semiconductor device of the third example also includes, as in the first example, an external terminal portion 111 for connecting to an external circuit and an internal terminal portion 112 for connecting to a semiconductor element as a part thereof. A terminal member integrally connected to the lead portion 114, and at least a part of the external terminal portion is made thicker from the processing material by using a half-etching method. A plurality of terminal members 110 whose lead portions are thinned by half-etching, and a die pad 150 formed by using a half-etching method from the above-mentioned processing material and having a thin overall shape, and a die pad 150 opposed thereto. Using two semiconductor elements 125 and 125A in a peripheral pad array in which pads are arranged along two sides, the two semiconductor elements 125 and 125A are mounted on a die pad in a stacked state, and each half is mounted on a die pad. An internal terminal portion of the predetermined terminal portion and the predetermined terminal member body element by wire bonding connection, sealed with a resin, a resin-sealed semiconductor device of the SON type.
Then, similarly to the first example, the respective terminal members 110 are oriented in the same direction so that the front and back surfaces of the external terminal portion 111 and the terminal surface of the internal terminal portion 112 are respectively aligned on one plane, and The terminal members are arranged with the external terminal portion 111 facing outward and the internal terminal portion 112 facing inward, and the direction of the half-etched surface of the die pad is opposite to the direction of the half-etched surface of the lead portion. The non-etched surface, which is not the half-etched surface, is flush with the non-etched surface of the external terminal on the half-etched surface side of the terminal member.
In the third example, the terminal surface 125a of the semiconductor element 125 on the die pad 150 side is oriented in the same direction as the half-etched surface 114a side of the terminal member 110, and the back surface 125b is mounted on the non-etched surface 150b side of the die pad 150. Further, another semiconductor element 125A is mounted on the terminal surface 125a of the semiconductor element 125 on the die pad 150 side on the back surface thereof.
Then, the terminal surface side of the internal terminal portion 112 is arranged on the half-etched surface 114a side of the lead portion 114 of each terminal member 110, and the non-half-etched surface 117 of each terminal member which is not the half-etched surface 114a side of the lead portion 114; The outer side surface 118 of each external terminal portion is exposed, and the other portions are resin-sealed with the remaining portions in resin. The terminals 126 of the semiconductor elements 125, 125A and the terminals 126A of the semiconductor elements 125A are connected to the terminal members 110 on the etched surfaces 114a of the lead portions 114.
[0018]
In the third example, one side (here, the non-etched surface 117) side of the processing material (not shown) of the terminal member 110 is resin-sealed so as to be exposed as in the first example. Thus, in a type in which semiconductor elements are stacked and mounted in one package, a reduction in thickness can be achieved.
Although two semiconductor elements are used, they can be manufactured by imposition basically in the same manner as in the first example, and have a structure suitable for mass production. Also, as in the first example, resin sealing In the process (molding process), it is not necessary to provide a cavity in a special shape, and it is a plate-shaped structure in which molding can be easily performed with both sides thereof suppressed, which is a preferable structure from the viewpoint of equipment.
The same components as those in the first example are used for each part.
[0019]
Next, a fourth embodiment of the resin-sealed semiconductor device according to the present invention will be described with reference to FIG.
The resin-encapsulated semiconductor device of the fourth example also includes, as in the first example, an external terminal portion 111 for connecting to an external circuit and an internal terminal portion 112 for connecting to a semiconductor element as a part thereof. A terminal member integrally connected to the lead portion 114, and at least a part of the external terminal portion is made thicker from the processing material by using a half-etching method. A plurality of terminal members 110 whose lead portions are thinned by half-etching; a die pad 150 formed by using the half-etching method from the raw material; Are mounted on a die pad in a state where two semiconductor elements 128 and 128A are stacked in a peripheral pad array in which pads are arranged along the semiconductor chip. An internal terminal portion of the predetermined terminal portion and the predetermined terminal member and wire bonding connection, sealed with a resin, a QFN type resin-encapsulated semiconductor device.
This example is different from the third example in that the semiconductor devices 125 and 125A in which the pads are arranged along two opposing sides thereof are replaced with the semiconductor devices in the peripheral pad arrangement where pads are arranged along four sides thereof. 185, 185A, and further, terminal members 110 are arranged along four peripheral sides.
The connection of the terminals 129 and 129A of the semiconductor elements 128 and 129A to the terminal members is made on the etching surface 114a of the lead portion 114.
[0020]
Also in the fourth example, one side (here, the non-etched surface 117) side of the processing material (not shown) of the terminal member 110 is resin-sealed so as to be exposed as in the first example. Thereby, a reduction in thickness can be achieved.
This example also uses two semiconductor elements, but can be fabricated by imposition basically in the same manner as the first example, and has a structure suitable for mass production. In the resin sealing step (molding step), it is not necessary to provide a cavity in a special shape, and it is a flat plate-shaped structure in which molding can be easily performed with both sides suppressed, which is preferable from the viewpoint of equipment. It can be called a structure.
The same components as those in the first example are used for each part.
[0021]
As a modified example of the first example and the third example, a resin mold region is slightly different from these,
The non-half-etched surface 117 of each terminal member, which is not on the half-etched surface 114a side of the lead portion 114, and the side surface portion 19 including the outer side surface 18 of each terminal member are exposed, and the other portions are sealed in a resin. 5 (a) and 5 (b), respectively.
Of course, as a modified example of the second example and the fourth example, there can be cited one that adopts a similar form.
As a modification of the third example and the fourth example, the semiconductor element 125A is replaced with a semiconductor element having a center pad arrangement in the third example, and the semiconductor element 128A is replaced with a center pad in the fourth example. One that has been replaced with an array of semiconductor elements is given.
In the third example, the semiconductor elements 125 and 125A are replaced with three or more semiconductor elements. In the fourth example, the semiconductor elements 128 and 1258 are replaced with three or more semiconductor elements. A resin-sealed type semiconductor device in which a predetermined terminal portion of each semiconductor element and an internal terminal portion of a predetermined terminal member are connected by wire bonding to form a resin-sealed state is also a modified example.
In this case, the semiconductor element on the die pad side is a semiconductor element of a peripheral pad array, the terminal surface is oriented in the same direction as the half-etched surface side of the terminal member, and the back surface is mounted on the non-etched surface side of the die pad. On the back surface that is not the terminal surface of the semiconductor element on the die pad side, semiconductor elements are stacked on top of each other except for the top as a semiconductor element of a peripheral pad array, and sequentially with the back side facing the semiconductor element side on the die pad side. are doing.
[0022]
Next, an example of a method for manufacturing the resin-encapsulated semiconductor device of the first example will be described with reference to FIGS.
It should be noted that the description of the embodiment of the method of manufacturing the resin-sealed semiconductor device of the present invention is replaced with the description of the embodiment.
First, a resist 220 is provided in a predetermined shape on both surfaces of the processing material 210 (FIG. 6A), and the arrangement of the terminal members corresponding to the arrangement of the terminal members of one resin-encapsulated semiconductor device is one unit. In this arrangement state, etching is performed from both sides by an etching method using a half-etching technique, and the terminal members 230 are formed by imposing while being connected by the support portions 236. (FIG. 6 (b))
As a result, a processed sheet 210A is obtained, in which the arrangement of the terminal members corresponding to the arrangement of the terminal members of one resin-encapsulated semiconductor device is set as one unit and connected and imposed on the support portion 236.
Cu, a Cu-based alloy, a 42 alloy (Ni 42% -Fe alloy), or the like is used as the processing material 210, and a ferric chloride solution is used as the etching solution.
Further, the resist 320 is not particularly limited as long as it has etching resistance, has a desired resolution, and has good processability.
Next, after the resist 220 was removed (FIG. 6C), a cleaning process and the like were performed, a surface plating for connection was performed on the entire surface (not shown), and an imposition was formed, and the surface plating was performed. On the side other than the half-etched surface 234a side of the processing sheet 210A, the semiconductor elements 250 are positioned at predetermined positions by the number of impositions and placed on the die pad 240. In this state, the terminals of each semiconductor element 250 251 and a terminal surface which is a half-etched surface of the internal terminal portion (corresponding to 111 in FIG. 1) of the terminal member 230 are connected by wire bonding. (FIG. 6 (d))
Next, a molding tape 280 is stuck in a flat shape so as to cover the half-etched surface 234a side of the processing sheet 320A, and the front and back are sandwiched between flat plates 271 and 272 for fixing the mold. Perform molding in a lump. (FIG. 7 (e))
The support portion 236 for supporting the terminal member 230 of the processing sheet 210A is provided with a through hole or the like, and has a shape such that the resin for molding between the impositions can pass through during molding. .
[0023]
Next, the flat plates 271 and 272 for fixing the mold on the front and back are removed, the tape 280 is further removed (FIG. 7F), and a tape 285 for cutting is attached (FIG. 7G). The resin-encapsulated semiconductor device is cut into individual pieces by cutting it with a dicing saw (not shown) from the side opposite to 285. (FIG. 7 (h))
The cutting state by a dicing saw (not shown) is, for example, as shown in FIGS. 8A and 8B.
Note that, in FIG. 8, the resin-sealed semiconductor device 401 as a unit is each region separated from each other by a cutting line 485, and is not illustrated here for easy understanding of description. The supporting portion 236 is cut at the concave portion 235.
The processing sheet 210A is also called a frame.
This cut surface becomes the outer side surface 238 of the external terminal of the resin-sealed semiconductor device to be manufactured.
In addition, plating for connection is provided on a surface other than the cut surface of the cutout portion 235A, and this portion is easily used for connection.
Thus, the resin-sealed semiconductor device of the first example shown in FIG. 1 can be manufactured.
[0024]
In the manufacture of the second to fourth examples, even if the positional relationship between the semiconductor element and the lead portion of the terminal member is different, or even if the step of laminating the semiconductor elements and the step of wire bonding are extra, It can be performed in the same manner as in the manufacture of the first example.
[0025]
5, the non-half-etched surface 117 of each terminal member that is not on the half-etched surface 114a side of the lead portion 114 and the outer side surface 18 of each terminal member, as in the first example and the modification of the third example. The semiconductor device is mounted in an imposed state as in the manufacturing method shown in FIGS. Then, after further performing wire bonding connection, the terminal surface of the external terminal portion to be exposed is held down by a flat plate as in the above-mentioned manufacturing method, and a predetermined cavity is formed on the opposite side using a predetermined mold. Is repeatedly performed by a division method.
For example, the process is repeatedly performed for each region G using 16 molds shown in FIG.
Regarding the manufacture of the other modified examples, even if the step of laminating the semiconductor elements and the wire bonding step are extra, the outline is that the manufacture of the first example or the first and third examples shown in FIG. Can be performed in the same manner as the manufacturing method of the modification of the example.
[0026]
【The invention's effect】
As described above, the present invention can provide a semiconductor device having a QFN package or a SON package structure that can achieve further miniaturization and thinning at low cost, is suitable for mass production, and has excellent moisture resistance and heat dissipation. I made it.
In particular, such a semiconductor device can be provided in a resin-sealed semiconductor device having a stacked QFN package or SON package structure.
At the same time, it has become possible to provide a method for manufacturing such a thin resin-encapsulated semiconductor device.
[Brief description of the drawings]
FIG. 1A is a cross-sectional view of a first embodiment of a resin-sealed semiconductor device according to the present invention, and FIG. 1B is a perspective view from the A1 side in FIG. 1A. FIG.
FIG. 2A is a cross-sectional view of a second embodiment of the resin-sealed semiconductor device according to the present invention, and FIG. 2B is a perspective view from the B1 side in FIG. 2A. FIG.
3A is a cross-sectional view of a third embodiment of the resin-sealed semiconductor device according to the present invention, and FIG. 3B is a perspective view from the C1 side of FIG. 3A. FIG.
FIG. 4A is a cross-sectional view of a fourth embodiment of the resin-sealed semiconductor device according to the present invention, and FIG. 4B is a perspective view from the D1 side in FIG. 4A. FIG.
FIGS. 5A and 5B are cross-sectional views of modified examples of the first and third examples, respectively.
FIG. 6 is a process cross-sectional view showing a part of the manufacturing process of one example of the embodiment of the method of manufacturing the resin-sealed semiconductor device of the present invention.
FIG. 7 is a process cross-sectional view showing a process following FIG. 6;
FIG. 8 is a diagram showing a cutting state by a dicing saw.
[Explanation of symbols]
110 terminal member
111 External terminal
112 Internal terminal
112a, 112b Terminal surface
114 Lead
114a half-etched surface
116 Notch
117, 117a Unetched surface
118 side view
120, 120A semiconductor element (also referred to as semiconductor chip or simply chip)
120a Terminal surface
120b back side
121 terminal
125, 125A semiconductor element (also referred to as semiconductor chip or simply chip)
125a Terminal surface
125b back side
126, 126A terminal
128, 128A semiconductor element (also called semiconductor chip or simply chip)
128a terminal surface
128b back side
129, 129A terminal
130, 135, 135A Bonding wire
136, 136A Bonding wire
140 Resin for sealing
150 die pad
150a half-etched surface
150b Unetched surface
210 Material for processing
210A Processing sheet
220 resist
225 opening
230 terminal member
231 External terminal
232 Internal terminal
234 Lead
235 recess
235A notch
236 Support part (also called connection part)
237 Non-etched surface (exposed surface)
238 sides
240 die pad
250 semiconductor element
251 terminal
260 Bonding wire
271, 272 Mold fixing plate
280 tape (for molding), 285 tape (for cutting)
290 Resin for sealing
401 unit resin-encapsulated semiconductor device
410A processing sheet
415 Frame
416 Jig hole
417 Slot
485 cutting line

Claims (10)

外部回路と接続するための外部端子部と、半導体素子と接続するための内部端子部をその一部として含むリード部とを、一体的に連結してなる端子部材で、且つ、ハーフエッチング加工法を用いて、加工用素材から、外部端子部の少なくとも一部を加工用素材の厚さの厚肉にし、リード部をハーフエッチングにて薄肉にしている端子部材を、複数個と、前記加工用素材から、ハーフエッチング加工法を用いて、全体を薄肉にして形成されたダイパッド１つと、半導体素子１つとを用い、半導体素子をダイパッドに搭載し、半導体素子の所定の端子部と所定の端子部材の内部端子部とをワイヤボンディング接続して、樹脂封止した樹脂封止型半導体装置であって、各端子部材を同じ向きにし、外部端子部の表裏の面および内部端子部の端子面が、それぞれ、一平面上に、揃うようにし、周辺部に、外部端子部を外側に向けて、内部端子部を内側に向けて、各端子部材を配しており、ダイパッドのハーフエッチング面の向きは、リード部のハーフエッチング面の向きとは反対にして、そのハーフエッチング面でない非エッチング面を端子部材のハーフエッチング面側の外部端子部の非エッチング面と一平面上に、揃うようにしており、半導体素子の端子面を、端子部材のハーフエッチング面側と同じ向きにし、その裏面を、ダイパッドの非エッチング面側に搭載しており、各端子部材のリード部のハーフエッチング面側に内部端子部の端子面側を配し、リード部のハーフエッチング面側でない各端子部材の非ハーフエッチング面と、各外部端子部の外側側面とを、露出させ、これ以外を樹脂中にして樹脂封止されていることを特徴とする樹脂封止型半導体装置。A terminal member formed by integrally connecting an external terminal portion for connecting to an external circuit and a lead portion including a part of an internal terminal portion for connecting to a semiconductor element, and a half-etching method. From the material for processing, at least a part of the external terminal portion is made thicker to the thickness of the material for processing, and a plurality of terminal members, the lead portions of which are thinned by half-etching, The semiconductor element is mounted on the die pad by using one die pad and one semiconductor element formed as a whole by using a half-etching method from a material, and a predetermined terminal portion of the semiconductor element and a predetermined terminal member. A resin-encapsulated semiconductor device in which the internal terminal portions are wire-bonded and resin-encapsulated, each terminal member is oriented in the same direction, and the front and back surfaces of the external terminal portion and the terminal surface of the internal terminal portion are Each terminal member is arranged on one plane so that they are aligned, the peripheral terminal is directed outward, the internal terminal is directed inside, and the orientation of the half-etched surface of the die pad is The direction of the half-etched surface of the lead portion is reversed, and the non-etched surface that is not the half-etched surface is flush with the non-etched surface of the external terminal portion on the half-etched surface side of the terminal member. The terminal surface of the semiconductor element is oriented in the same direction as the half-etched surface side of the terminal member, and the back surface is mounted on the non-etched surface side of the die pad. The terminal surface side of the portion is arranged, the non-half-etched surface of each terminal member that is not the half-etched surface side of the lead portion, and the outer side surface of each external terminal portion are exposed, and other portions are exposed. Resin-sealed semiconductor device characterized by being sealed with resin and in the fat. 外部回路と接続するための外部端子部と、半導体素子と接続するための内部端子部をその一部として含むリード部とを、一体的に連結してなる端子部材で、且つ、ハーフエッチング加工法を用いて、加工用素材から、外部端子部の少なくとも一部を加工用素材の厚さの厚肉にし、リード部をハーフエッチングにて薄肉にしている端子部材を、複数個と、前記加工用素材から、ハーフエッチング加工法を用いて、全体を薄肉にして形成されたダイパッド１つと、半導体素子複数個を用い、前記半導体素子複数個を積層した状態としてダイパッドに搭載し、、各半導体素子の所定の端子部と所定の端子部材の内部端子部とをワイヤボンディング接続して、樹脂封止した樹脂封止型半導体装置であって、各端子部材を同じ向きにし、外部端子部の表裏の面および内部端子部の端子面が、それぞれ、一平面上に、揃うようにし、周辺部に、外部端子部を外側、内部端子部側を内側に向けて、各端子部材を配しており、ダイパッドのハーフエッチング面の向きは、リード部のハーフエッチング面の向きとは反対にして、そのハーフエッチング面でない非エッチング面を端子部材のハーフエッチング面側の外部端子部の非エッチング面と一平面上に、揃うようにしており、ダイパッド側の半導体素子をペリフェラルパッド配列の半導体素子とし、その端子面を、端子部材のハーフエッチング面側と同じ向きにし、その裏面を、ダイパッドの非エッチング面側に搭載し、更に、前記ダイパッド側の半導体素子の端子面でない裏面上に、一番上以外をペリフェラルパッド配列の半導体素子として、順次、その裏面側を前記ダイパッド側の半導体素子側に向けて、半導体素子を重ねて搭載しており、各端子部材のリードのハーフエッチング面側に内部端子部の端子面側を配し、リード部のハーフエッチング面側でない各端子部材の非ハーフエッチング面と、各外部端子部の外側側面とを、露出させ、これ以外を樹脂中にして樹脂封止されていることを特徴とする樹脂封止型半導体装置。A terminal member formed by integrally connecting an external terminal portion for connecting to an external circuit and a lead portion including a part of an internal terminal portion for connecting to a semiconductor element, and a half-etching method. From the material for processing, at least a part of the external terminal portion is made thicker to the thickness of the material for processing, and a plurality of terminal members, the lead portions of which are thinned by half-etching, From a material, using a half-etching method, one die pad formed as a whole with a small thickness, using a plurality of semiconductor elements, mounting the plurality of semiconductor elements in a stacked state on the die pad, and mounting each semiconductor element A resin-sealed semiconductor device in which a predetermined terminal portion and an internal terminal portion of a predetermined terminal member are wire-bonded and resin-sealed. And the terminal surfaces of the internal terminal portions are aligned on one plane, respectively, and each terminal member is arranged in the peripheral portion, with the external terminal portion facing outward and the internal terminal portion side facing inward. The direction of the half-etched surface of the die pad is opposite to the direction of the half-etched surface of the lead portion, and the non-etched surface that is not the half-etched surface coincides with the non-etched surface of the external terminal portion on the half-etched surface side of the terminal member. The semiconductor element on the die pad side is a semiconductor element with a peripheral pad array, the terminal surface is oriented in the same direction as the half-etched surface side of the terminal member, and the back surface is the non-etched surface of the die pad. On the back surface of the semiconductor device on the die pad side, which is not the terminal surface, and the other than the top as a semiconductor device in a peripheral pad array. The semiconductor elements are stacked and mounted with their back sides facing the semiconductor element side on the die pad side, and the terminal surface side of the internal terminal portion is arranged on the half-etched surface side of the lead of each terminal member. A non-half-etched surface of each terminal member that is not the half-etched surface side and an outer side surface of each external terminal portion, and the other portions are resin-sealed. Type semiconductor device. 請求項１ないし２に記載の樹脂封止型半導体装置おいて、樹脂封止されて、全体が板状方形であることを特徴とする樹脂封止型半導体装置。3. The resin-sealed semiconductor device according to claim 1, wherein the semiconductor device is resin-sealed and has a plate-like rectangular shape as a whole. 外部回路と接続するための外部端子部と、半導体素子と接続するための内部端子部をその一部として含むリード部とを、一体的に連結してなる端子部材で、且つ、ハーフエッチング加工法を用いて、加工用素材から、外部端子部の少なくとも一部を加工用素材の厚さの厚肉にし、リード部をハーフエッチングにて薄肉にしている端子部材を、複数個と、前記加工用素材から、ハーフエッチング加工法を用いて、全体を薄肉にして形成されたダイパッド１つと、半導体素子１つとを用い、半導体素子をダイパッドに搭載し、半導体素子の所定の端子部と所定の端子部材の内部端子部とをワイヤボンディング接続して、樹脂封止した樹脂封止型半導体装置であって、各端子部材を同じ向きにし、外部端子部の表裏の面および内部端子部の端子面が、それぞれ、一平面上に、揃うようにし、周辺部に、外部端子部を外側に向けて、内部端子部を内側に向けて、各端子部材を配しており、ダイパッドのハーフエッチング面の向きは、リード部のハーフエッチング面の向きとは反対にして、そのハーフエッチング面でない非エッチング面を端子部材のハーフエッチング面側の外部端子部の非エッチング面と一平面上に、揃うようにしており、半導体素子の端子面を、端子部材のハーフエッチング面側と同じ向きにして、その裏面を、ダイパッドの非エッチング面側に搭載しており、各端子部材のリード部のハーフエッチング面側に内部端子部の端子面を配し、リード部のハーフエッチング面側でない各端子部材の非ハーフエッチング面と、各端子部材の外側側面を含む側面部とを露出させ、これ以外を樹脂中にして樹脂封止されていることを特徴とする樹脂封止型半導体装置。A terminal member formed by integrally connecting an external terminal portion for connecting to an external circuit and a lead portion including a part of an internal terminal portion for connecting to a semiconductor element, and a half-etching method. From the material for processing, at least a part of the external terminal portion is made thicker to the thickness of the material for processing, and a plurality of terminal members, the lead portions of which are thinned by half-etching, The semiconductor element is mounted on the die pad by using one die pad and one semiconductor element formed as a whole by using a half-etching method from a material, and a predetermined terminal portion of the semiconductor element and a predetermined terminal member. A resin-encapsulated semiconductor device in which the internal terminal portions are wire-bonded and resin-encapsulated, each terminal member is oriented in the same direction, and the front and back surfaces of the external terminal portion and the terminal surface of the internal terminal portion are Each terminal member is arranged on one plane so that they are aligned, the peripheral terminal is directed outward, the internal terminal is directed inside, and the orientation of the half-etched surface of the die pad is The direction of the half-etched surface of the lead portion is reversed, and the non-etched surface that is not the half-etched surface is flush with the non-etched surface of the external terminal portion on the half-etched surface side of the terminal member. The terminal surface of the semiconductor element is oriented in the same direction as the half-etched surface side of the terminal member, and the back surface is mounted on the non-etched surface side of the die pad. The terminal surface of the terminal portion is arranged, and the non-half-etched surface of each terminal member, which is not the half-etched surface side of the lead portion, and the side surface portion including the outer side surface of each terminal member are exposed. Resin-sealed semiconductor device characterized by being sealed with resin in the resin other than. 外部回路と接続するための外部端子部と、半導体素子と接続するための内部端子部をその一部として含むリード部とを、一体的に連結してなる端子部材で、且つ、ハーフエッチング加工法を用いて、加工用素材から、外部端子部の少なくとも一部を加工用素材の厚さの厚肉にし、リード部をハーフエッチングにて薄肉にしている端子部材を、複数個と、前記加工用素材から、ハーフエッチング加工法を用いて、全体を薄肉にして形成されたダイパッド１つと、半導体素子複数個を用い、前記半導体素子複数個を積層した状態としてダイパッドに搭載し、各半導体素子の所定の端子部と所定の端子部材の内部端子部とをワイヤボンディング接続して、樹脂封止した樹脂封止型半導体装置であって、各端子部材を同じ向きにし、外部端子部の表裏の面および内部端子部の端子面が、それぞれ、一平面上に、揃うようにし、周辺部に、外部端子部を外側、内部端子部側を内側に向けて、各端子部材を配しており、ダイパッドのハーフエッチング面の向きは、リード部のハーフエッチング面の向きとは反対にして、そのハーフエッチング面でない非エッチング面を端子部材のハーフエッチング面側の外部端子部の非エッチング面と一平面上に、揃うようにしており、ダイパッド側の半導体素子をペリフェラルパッド配列の半導体素子とし、その端子面を、端子部材のハーフエッチング面側と同じ向きにし、その裏面を、ダイパッドの非エッチング面側に搭載し、更に、前記ダイパッド側の半導体素子の端子面でない裏面上に、一番上以外をペリフェラルパッド配列の半導体素子として、順次、その裏面側を前記ダイパッド側の半導体素子側に向けて、半導体素子を重ねて搭載しており、各端子部材のリード部のハーフエッチング面側に内部端子部の端子面を配し、リード部のハーフエッチング面側でない各端子部材の非ハーフエッチング面と、各端子部材の外側側面を含む側面部とを露出させ、これ以外を樹脂中にして樹脂封止されていることを特徴とする樹脂封止型半導体装置。A terminal member formed by integrally connecting an external terminal portion for connection to an external circuit and a lead portion including a part of an internal terminal portion for connection to a semiconductor element, and a half-etching method. From the material for processing, at least a part of the external terminal portion is made thicker to the thickness of the material for processing, and a plurality of terminal members, the lead portions of which are thinned by half-etching, Using a half-etching method from a material, one die pad formed as a whole is thinned, and a plurality of semiconductor elements are used. The plurality of semiconductor elements are stacked and mounted on the die pad. A resin-encapsulated semiconductor device in which terminal portions of a predetermined terminal member and an internal terminal portion of a predetermined terminal member are wire-bonded to form a resin-encapsulated semiconductor device. Each terminal member is arranged such that the surface and the terminal surface of the internal terminal portion are aligned on one plane, respectively, and the external terminal portion is directed outward and the internal terminal portion side is directed inward in the peripheral portion, The direction of the half-etched surface of the die pad is opposite to the direction of the half-etched surface of the lead portion, and the non-etched surface that is not the half-etched surface is flush with the non-etched surface of the external terminal portion on the half-etched surface side of the terminal member. The semiconductor element on the die pad side is a semiconductor element with a peripheral pad array, the terminal surface is oriented in the same direction as the half-etched surface side of the terminal member, and the back surface is on the non-etched surface side of the die pad. On the back surface other than the terminal surface of the semiconductor element on the die pad side, the other than the top as a semiconductor element of a peripheral pad array, sequentially The semiconductor elements are stacked and mounted with the back side facing the semiconductor element side on the die pad side, and the terminal surface of the internal terminal portion is arranged on the half-etched surface side of the lead portion of each terminal member. A non-half-etched surface of each terminal member, which is not a half-etched surface side, and a side surface portion including an outer side surface of each terminal member are exposed, and the other portions are sealed in a resin by resin. Stop type semiconductor device. 請求項１ないし５のいずれかに記載の樹脂封止型半導体装置において、外部端子部の外側側面部に切り欠け部を設けていることを特徴とする樹脂封止型半導体装置。The resin-sealed semiconductor device according to claim 1, wherein a notch is provided on an outer side surface of the external terminal. 請求項１ないし６のいずれかに記載の樹脂封止型半導体装置おいて、端子部材は、Ｃｕ、Ｃｕ系合金、４２％Ｎｉ−Ｆｅ系合金からなることを特徴とする樹脂封止型半導体装置。7. The resin-sealed semiconductor device according to claim 1, wherein the terminal member is made of Cu, a Cu-based alloy, or a 42% Ni-Fe-based alloy. . 請求項１ないし７のいずれかに記載の樹脂封止型半導体装置において、内部端子部の端子面および外部端子部の表裏の端子面に、半田めっき層、金めっき層、銀めっき層、パラジウムめっき層、錫めっき層から選ばれた１つの金属めっき層を、接続用のめっき層として設けていることを特徴とする樹脂封止型半導体装置。The resin-encapsulated semiconductor device according to any one of claims 1 to 7, wherein a solder plating layer, a gold plating layer, a silver plating layer, and a palladium plating are provided on the terminal surfaces of the internal terminal portions and the front and back terminal surfaces of the external terminal portions. A resin-encapsulated semiconductor device, wherein one metal plating layer selected from a layer and a tin plating layer is provided as a plating layer for connection. 請求項１ないし３のいずれかに記載の樹脂封止型半導体装置の製造方法であって、順に、（ａ）１つの樹脂封止型半導体装置の各端子部材とダイパッドの配置に対応した、端子部材およびダイパッドの配置を１単位として、ハーフエッチング技術を用いたエッチング加工にて、端子部材の外部端子部側を支持部で連結した状態で、面付けして形成し、面付け形成された加工シートを得る加工工程と、（ｂ）接続用の表面めっきを施すめっき処理工程と、（ｃ）加工シートを固定した状態で、面付け分だけ、半導体素子を位置決めして、ダイパッド上に搭載する半導体素子搭載工程と、（ｄ）この状態で、各半導体素子について、その端子と端子部材の内部端子部の端子面とをワイヤボンディング接続するワイヤボンディング工程と、（ｅ）面付け形成された加工シートのハーフエッチング面側を覆うように平面状に、モールド用のテープを貼る、平面状に貼る、テープ貼り工程と、（ｆ）モールド用のテープ側は、テープに添わせ、反対側はキャビティを設けるように、表裏をモールド固定用の平板にて囲み、加工シート全体について、一括してモールドを行う、一括モールド工程と、（ｇ）表裏のモールド固定用の平板、テープを除去し、切断用のテープを貼り、該切断用のテープとは反対側からダイシングソーにて切断して、樹脂封止型半導体装置を１個づつに個片化して得る個片化工程と、を行うことを特徴とする樹脂封止型半導体装置の製造方法。The method for manufacturing a resin-encapsulated semiconductor device according to claim 1, wherein (a) terminals corresponding to the arrangement of each terminal member and the die pad of one resin-encapsulated semiconductor device. With the arrangement of the member and the die pad as one unit, the processing is performed by imposing, with the external terminal portion side of the terminal member being connected by the support portion, by etching using a half-etching technique. A processing step of obtaining a sheet, (b) a plating step of applying surface plating for connection, and (c) in a state where the processed sheet is fixed, the semiconductor element is positioned and mounted on the die pad by an imposition amount. A semiconductor element mounting step; (d) a wire bonding step of wire bonding connecting a terminal of each semiconductor element to a terminal surface of an internal terminal portion of a terminal member in this state; A tape for molding is applied in a flat shape so as to cover the half-etched surface side of the formed processing sheet, a tape is applied in a flat shape, and (f) the tape side for the molding is attached to the tape. The opposite side is surrounded by a flat plate for fixing the mold so as to provide a cavity, and the entire processing sheet is collectively molded. (G) A flat plate and a tape for fixing the front and back molds. Is removed, a cutting tape is applied, and the cutting tape is cut with a dicing saw from the side opposite to the cutting tape to obtain a resin-encapsulated semiconductor device by dividing into individual pieces. And a method for manufacturing a resin-encapsulated semiconductor device. 請求項４ないし５のいずれかに記載の樹脂封止型半導体装置の製造方法であって、順に、（ａ１）１つの樹脂封止型半導体装置の各端子部材とダイパッドの配置に対応した、端子部材およびダイパッドの配置を１単位として、ハーフエッチング技術を用いたエッチング加工にて、端子部材の外部端子部側を支持部で連結した状態で、面付けして形成し、面付け形成された加工シートを得る加工工程と、（ｂ１）接続用の表面めっきを施すめっき処理工程と、（ｃ１）加工シートを固定した状態で、面付け分だけ、半導体素子を位置決めして、ダイパッド上に搭載する半導体素子搭載工程と、（ｄ１）この状態で、各半導体素子について、その端子と端子部材の内部端子部の端子面とをワイヤボンディング接続するワイヤボンディング工程と、（ｅ１）面付け形成された加工シートのハーフエッチング面側を覆うように平面状に、モールド用のテープを貼る、平面状に貼る、テープ貼り工程と、（ｆ１）モールド用のテープ側は、テープに添わせ、モールド固定用の平板にて固定し、反対側には、所定の面付け数をまかなう所定の型を設け、前記モールド固定用の平板と前記型間を樹脂で埋めるモールドを行う、モールド工程と、（ｇ１）モールド固定用の平板、テープを除去し、切断用のテープを貼り、該切断用のテープとは反対側からダイシングソーにて切断して、樹脂封止型半導体装置を１個づつに個片化して得る個片化工程と、を行うことを特徴とする樹脂封止型半導体装置の製造方法。6. The method for manufacturing a resin-encapsulated semiconductor device according to claim 4, wherein (a1) a terminal corresponding to the arrangement of each terminal member and the die pad of one resin-encapsulated semiconductor device. With the arrangement of the member and the die pad as one unit, the processing is performed by imposing, with the external terminal portion side of the terminal member being connected by the support portion, by etching using a half-etching technique. A processing step of obtaining a sheet, (b1) a plating processing step of applying surface plating for connection, and (c1) a semiconductor element is positioned and mounted on the die pad by an amount corresponding to an imposition while the processing sheet is fixed. A semiconductor element mounting step, and (d1) a wire bonding step of performing wire bonding connection between a terminal of each semiconductor element and a terminal surface of an internal terminal portion of a terminal member in this state. e1) A tape for molding is applied in a planar shape so as to cover the half-etched surface side of the processed sheet formed by imposition, a tape attaching step, and (f1) a tape is applied to the tape side for molding. In addition, fixed with a mold fixing flat plate, on the opposite side, provided a predetermined mold to cover a predetermined number of imposition, perform a mold to fill the gap between the mold fixing flat plate and the mold with a resin, Molding step, (g1) The mold fixing flat plate and tape are removed, a cutting tape is attached, and cut with a dicing saw from the side opposite to the cutting tape to obtain a resin-encapsulated semiconductor device. A method for manufacturing a resin-encapsulated semiconductor device, comprising: performing an individualizing step of obtaining individual semiconductor devices one by one.
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