JP2004327742A - Process for producing wiring board with solder bump - Google Patents

Process for producing wiring board with solder bump Download PDF

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Publication number
JP2004327742A
JP2004327742A JP2003120791A JP2003120791A JP2004327742A JP 2004327742 A JP2004327742 A JP 2004327742A JP 2003120791 A JP2003120791 A JP 2003120791A JP 2003120791 A JP2003120791 A JP 2003120791A JP 2004327742 A JP2004327742 A JP 2004327742A
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Japan
Prior art keywords
solder
pad
opening
wiring board
layer
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Pending
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JP2003120791A
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Japanese (ja)
Inventor
Kenji Nakamura
憲志 中村
Tatsuumi Sakamoto
達海 坂元
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Kyocera Corp
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Kyocera Corp
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Priority to JP2003120791A priority Critical patent/JP2004327742A/en
Publication of JP2004327742A publication Critical patent/JP2004327742A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a process for producing a wiring board with solder bumps in which a micropad and a solder bump can be bonded rigidly. <P>SOLUTION: The process for producing a wiring board comprises a step for forming, on the surface of an insulating substrate 1 having wiring conductors 2, with a plurality of solder bonding pads 3 connected with the wiring conductors 2 and a resin layer 4 having an opening 4a for exposing the central part of the pad 3, a step for applying a metal layer 11 forming solid solution with solder on the inner side face of the opening 4a, and a step for forming a solder bump 5 by coating the inner surface of the opening 4a with solder paste and then heating the solder paste. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【0001】
【発明の属する技術分野】
本発明は、半導体素子や抵抗器等の電子部品を搭載するための半田バンプ付き配線基板の製造方法に関するものである。
【0002】
【従来の技術】
近年、半導体素子等の電子部品を搭載するために用いられる配線基板には、ガラス繊維基材に熱硬化性樹脂を含浸させて成る絶縁板と銅箔等から成る配線導体層とを交互に複数積層して成るプリント基板や、絶縁板上に熱硬化性樹脂およびフィラーから成る絶縁層と銅めっき層から成る配線導体層とを複数積層して成るビルドアップ基板が用いられてきている。そして、このようなプリント基板やビルドアップ基板等の配線基板の上面には、半導体素子等の電子部品の電極を接続するためのパッドが形成されているとともに、パッドの中央部を露出させる開口部を有する樹脂層が被着されており、さらに、開口部内で露出したパッド上には電子部品とパッドとを接合するための半田バンプが形成されている。
【0003】
そして、このような半田バンプ付きの配線基板においては、電子部品をその各電極がそれぞれ対応する半田バンプに当接するようにして配線基板の上面に載置し、これらを電気炉等の加熱装置で加熱して半田バンプを溶融させて半田バンプと電子部品の電極とを接合することによって、電子部品が配線基板上に実装される。この際使用される半田バンプ形成用の半田ペーストに含まれる半田粉末としては、Sn−Pb共晶半田等の共晶半田が使用されるのが一般的である。
【0004】
なお、このような半田バンプ付きの配線基板は、内部および表面の少なくとも一方に複数の配線導体を有する絶縁基板の表面に、配線導体に接続された円形状の複数のパッド、およびこれらのパッドの中央部を露出させる開口部を有する樹脂層を被着し、次にパッド上にフラックスおよび半田粉末から成る半田ペーストを従来周知のスクリーン印刷法により半田バンプの形成に必要な量だけ印刷塗布し、これを加熱して半田ペースト中の半田粉末を溶融させ固化させてパッド上に半田バンプを形成することによって製作されている。
【0005】
【特許文献1】
特開2002−217531号公報
【0006】
【発明が解決しようとする課題】
しかしながら、近年、高集積化が進むICやLSI等の半導体素子を搭載する半導体素子収納用パッケージや各種電子部品を搭載する混成集積回路装置等に適用される配線基板においては、電子部品接続用のパッドの小型化および高密度配列化が要求されており、例えばパッドの開口部に露出した部位の直径が90μm以下で配列間隔(パッド中心間の間隔)が150μm以下のものが出現するようになってきている。
【0007】
このように微細で、樹脂層の開口部内に露出したパッド上にSn−Pb共晶半田等の半田粉末を含む半田ペーストを印刷塗布し、半田粉末を加熱すると、共晶温度に達した時点で半田が固相から液相へと瞬時に変化して溶融するため、瞬時に液相となって溶融した半田の表面張力により、半田がパッドに十分に濡れる前にパッドから浮き上がった状態で球状となってしまい、その結果、半田バンプとパッドとが良好に接合されないという問題点を有していた。
【0008】
したがって、本発明はかかる従来の問題点に鑑み完成されたものであり、その目的は、パッドと半田バンプとを確実に接合することが可能な半田バンプ付き配線基板およびその製造方法を提供することにある。
【0009】
【課題を解決するための手段】
本発明の配線基板の製造方法は、配線導体を有する絶縁基板の表面に、前記配線導体に接続された複数の半田接合用のパッドおよび該パッドの中央部を露出させる開口部を有する樹脂層を形成する工程と、前記開口部の内側面に半田との固溶体を形成する金属層を被着する工程と、前記開口部の内面に半田ペーストを塗布し加熱することによって半田バンプを形成する工程とを具備していることを特徴とするものである。
【0010】
本発明の半田バンプ付き配線基板の製造方は、樹脂層に形成された開口部の内側面に半田との固溶体を形成する金属層を被着し、開口部内に内側に半田ペーストを塗布し加熱することによって開口部の内側に接合された半田バンプを形成することから、半田バンプは開口部の内側面に被着させた金属層に良好に濡れて接合されるため、開口部内に十分に入り込んだ状態でパッドと接合される。その結果、半田バンプとパッドとが強固に接合された接続信頼性に優れる半田バンプ付き配線基板を提供することができる。
【0011】
【発明の実施の形態】
本発明の半田バンプ付き配線基板を以下に詳細に説明する。図1は、本発明の半田バンプ付き配線基板の実施の形態の一例を示す断面図であり、図2は図1の半田バンプ付き配線基板の要部拡大断面図である。また、図3は本発明の半田バンプ付き配線基板の製造方法を説明するための工程毎の要部拡大断面図である。
【0012】
まず、本発明の半田バンプ付き配線基板(以下、単に配線基板ともいう)について説明する。図1において、1は絶縁基板、2は配線導体、3は半田接合用のパッド、4は樹脂層、5は半田バンプであり、主にこれらで本発明の配線基板が構成されている。なお、図1の例では外部リードピン6を有する例を示したが、外部リードピン6は必ずしも必要ではなく、外部リードピン6に代えて半田から成る外部接続用の端子等を設けてもよい。
【0013】
本発明における絶縁基板1は、例えばガラス繊維を縦横に織り込んだガラス織物にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂を含浸させて成る板状の芯体1aの上下面に、エポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂から成る絶縁層1bをそれぞれ複数層ずつ積層して成り、芯体1aや各絶縁層1bの表面には銅箔や銅めっき層等の導体層から成る複数の配線導体2が形成されている。
【0014】
芯体1aは、厚みが0.3〜1.5mm程度であり、その上面から下面にかけて直径0.1〜1.0mm程度の複数の貫通孔7を有している。各貫通孔7の内面には配線導体2の一部が被着されており、芯体1aの上下面に形成された配線導体2同士が貫通孔7内の配線導体2を介して電気的に接続されている。
【0015】
この芯体1aは、ガラス織物に未硬化の熱硬化性樹脂を含浸させたシートを作製して熱硬化性樹脂を熱硬化させた後、これに上下面間にわたる貫通孔7をドリル等を用いて形成することにより製作される。また、芯体1aの上下面の配線導体2は、芯体1a用のシートの上下面の全面に厚みが3〜50μm程度の銅箔を貼着し、この銅箔をシートの硬化後にエッチング加工することにより、芯体1aの上下面に所定のパターンに形成される。また、貫通孔7内の配線導体2は、芯体1aに貫通孔7を設けた後に、貫通孔7の内面に無電解めっき法や電解めっき法により厚みが3〜50μm程度の銅めっき層を形成することにより貫通孔7の内面に被着形成される。
【0016】
さらに、芯体1aは、貫通孔7の内部にエポキシ樹脂やビスマレイミドトリアジン樹脂等の熱硬化性樹脂から成る樹脂柱8が充填されている。樹脂柱8は、貫通孔7を塞ぐとともに貫通孔7の直上および直下の絶縁層1bの部位にそれぞれ接続されることにより、芯体1aの上下面の絶縁層1bを強固に固定することができる。この樹脂柱8は、未硬化のペースト状の熱硬化性樹脂を貫通孔7内にスクリーン印刷法により充填し、これを熱硬化させた後、その上下端面を平坦に研磨することにより形成される。そして、樹脂柱8を有する芯体1aの上下面に絶縁層1bが積層される。
【0017】
芯体1aの上下面に積層された絶縁層1bは、それぞれの厚みが20〜60μm程度であり、各絶縁層1bの上下面間にわたって直径30〜100μm程度の複数の貫通孔9が形成されており、これらの貫通孔9内には配線導体2の一部が被着形成されている。これらの絶縁層1bは、配線導体2を高密度に配線するための絶縁間隔を形成するためのものである。そして、絶縁層1bの上層側の配線導体2と下層側の配線導体2とを、貫通孔9内の配線導体2を介して電気的に接続することにより高密度配線を立体的に形成可能としている。
【0018】
この絶縁層1bは、厚みが20〜60μm程度の未硬化の熱硬化性樹脂のフィルムを芯体1aの上下面に貼着し、これを熱硬化させるとともにレーザ加工により貫通孔9を穿孔し、さらにその上に次の絶縁層1bを同様にして順次積層することによって形成される。なお、各絶縁層1bの表面および貫通孔9内に被着された配線導体2は、各絶縁層1bを形成する毎に各絶縁層1bの表面および貫通孔9内に5〜50μm程度の厚みの銅めっき層を公知のセミアディティブ法やサブトラクティブ法等のパターン形成法により所定のパターンに被着させることによって形成される。
【0019】
さらに、最表層の絶縁層1b上には樹脂層4が被着されている。樹脂層4は、例えば耐半田性を有する(半田の融点では変形等を生じない)アクリル変性エポキシ樹脂にシリカやタルク等の無機物粉末フィラーを30〜70質量%程度分散させた絶縁材料から成り、表層の配線導体2同士の電気的絶縁信頼性を高めるとともに、パッド3やピン接合パッド10の絶縁基板1への接合強度を大きくする作用をなす。
【0020】
この樹脂層4は、厚みが10〜50μm程度であり、感光性を有する未硬化樹脂ペーストをロールコーター法やスクリーン印刷法により最表層の絶縁層1b上に塗布し、これを乾燥させた後、露光および現像処理を行なってパッド3やピン接合パッド10の中央部を露出させる開口部4a,4bを形成した後、これを熱硬化させることによって形成される。または、樹脂層4用の未硬化の樹脂フィルムを最上層の絶縁層1b上に貼着した後、これを熱硬化させ、しかる後、パッド3やピン接合パッド10に対応する位置にレーザ光を照射し、硬化した樹脂フィルムを部分的に除去することによってパッド3やピン接合パッド10を露出させて成る開口部4a,4bを有するように形成される。
【0021】
また、絶縁基板1の上下面間にわたって形成された配線導体2は電子部品の各電極を外部電気回路基板の配線導体等に接続するための導電路として機能し、絶縁基板1の上面の電子部品の実装領域にある配線導体2の部位の一部が、電子部品の各電極に、錫を63質量%および鉛を37質量%含む錫63−鉛37共晶半田、錫96.5−銀3.5共晶半田、錫96−銀3.5−銅0.5非共晶半田等の低融点半田から成る半田バンプ5を介してパッド3に接合される。また、絶縁基板1の下面に露出した配線導体2の部位の一部が、外部電気回路基板の配線導体等に接続される外部リードピン6を接合するためのピン接合パッド10に電気的に接続されている。
【0022】
パッド3やピン接合パッド10は、配線導体2に接続された導体層から成る円形状のパターンの外周部を樹脂層4により15〜35μm程度の幅で被覆してその外周縁を画定することにより、露出する直径が、パッド3であれば50〜200μm程度、ピン接合パッド10であれば0.5〜2.5mm程度になるように形成されている。このように、パッド3およびピン接合パッド10の外周部を樹脂層4により被覆することによって、パッド3同士やピン接合パッド10同士の電気的な短絡が有効に防止されるとともに、パッド3やピン接合パッド10の絶縁基板1に対する接合強度を高くすることができる。
【0023】
また、パッド3には半田バンプ5が接合されている。半田バンプ5は、錫63−鉛37共晶半田、96.5−銀3.5共晶半田、錫96−銀3.5−銅0.5非共晶半田等の低融点半田から成り、パッド3と電子部品とを電気的および機械的に接続する接続端子として機能する。そして、電子部品の各電極がそれぞれ対応する半田バンプ5に当接するようにして絶縁基板1上に電子部品を載置し、これらを電気炉などの加熱装置で加熱して半田バンプ5を溶融させ固化させることにより半田バンプ5と電子部品の電極とが接続される。
【0024】
また、ピン接合パッド10には、銅や鉄−ニッケル−コバルト合金等の金属から成る外部リードピン6が半田バンプ5よりも融点が高い半田を介して接合されている。外部リードピン6は、絶縁基板1に実装される電子部品を外部電気回路基板に電気的に接続するための端子部材として機能し、外部リードピン6を外部電気回路基板の配線導体に半田やソケットを介して接続することにより、電子部品が外部電気回路に電気的に接続されることとなる。
【0025】
次に、本発明の配線基板の製造方法について以下に説明する。
【0026】
先ず、図3(a)に示すように、配線導体2を有する絶縁基板1の上面に、配線導体2に接続されたパッド3、およびパッド3の中央部を露出させる開口部4aを有する樹脂層4を形成する。パッド3は、絶縁基板1を構成する最上層の絶縁層1b上に、5〜20μm程度の厚みの銅めっき層を公知のセミアディティブ法やサブトラクティブ法等のパターン形成法により所定のパターンに被着させることによって形成される。
【0027】
また、樹脂層4は、感光性を有する未硬化樹脂ペーストをロールコーター法やスクリーン印刷法によって最上層の絶縁層1b上に塗布し、これを乾燥させた後、露光および現像処理を行なってパッド3の中央部を露出させる開口部4aを形成した後、これを熱硬化させることによって形成される。または、樹脂層4用の未硬化の樹脂フィルムを最上層の絶縁層1b上に貼着した後、これを熱硬化させ、しかる後、パッド3に対応する位置にレーザ光を照射し、硬化した樹脂フィルムを部分的に除去することによって、パッド3の中央部を露出させる開口部4aを有するように形成される。
【0028】
次に図3(b)に示すうように、樹脂層4の開口部4aの内側面に半田との固溶体を形成する金属層11を被着する。金属層11を被着するには、樹脂層4の表面に開口部4aを露出させるめっきレジスト層を被着し、露出している開口部4aの内側面に無電解めっき法により半田との固溶体を形成する金属層11を被着した後、めっきレジスト層を剥離する方法等が採用される。
【0029】
なお、金属層11としては、厚みが0.01〜0.1μmの無電解金めっき層や厚みが0.1〜1μm程度の無電解銅めっき層が好ましい。金属層11を厚みが0.01〜0.1μmの無電解金めっき層や厚みが0.1〜1μm程度の無電解銅めっき層とすることにより金属層11が半田バンプ5中に良好に固溶する。また、半田バンプ5用の半田ペーストに含有される半田よりも先に溶融しないように融点が半田バンプ5用の半田ペーストに含有される半田よりも10℃以上高いものが好ましい。
【0030】
次に、図3(c)に示すように、樹脂層4の開口部4a内に露出したパッド3の中央部に、半田粉末およびフラックスを含有する半田ペースト21を従来周知のスクリーン印刷法を採用して印刷塗布する。半田粉末としては粒径が3〜25μm程度の球状の半田が使用される。このような半田粉末としては、錫63−鉛37共晶半田、錫96.5−銀3.5共晶半田、錫96−銀3.5−銅0.5非共晶半田等の低融点半田が使用できる。
【0031】
次に、図3(d)に示すように、半田ペースト21を加熱することにより半田ペースト21中の半田粉末および金属層11を溶融させてパッド3に接合された半田バンプ5を形成する。このとき、本発明の製造方法によれば、溶融した半田が開口部4aの内側面の金属層11と良好に濡れて溶融することにより、開口部4a内に十分に入り込でパッド3に接合され、その結果、半田バンプ5とパッド3とが良好に接合された半田バンプ付き配線基板を提供することができる。なお、金属層11は半田バンプ5中に固溶して層としては消滅する。
【0032】
本発明において、金属層11は開口部4aの内側面に形成されているが、開口部4aの内側面ばかりでなく、開口部4aの底面(パッド3の露出表面)にも形成されていてもよい。この場合、溶融した半田が開口部4aの内側面および底面の金属層11に良好に濡れて接合されるため、さらに半田バンプ5の接合性が高まることとなる。
【0033】
かくして、本発明の配線基板は、絶縁基板1の上面に電子部品をその電極が半田バンプ5に当接するようにして載置し、半田バンプ5を加熱溶融させて電子部品の電極とパッド3とを接合することにより製品としての電子装置となる。
【0034】
なお、本発明は上述の実施の形態の例に限定されず、本発明の要旨を逸脱しない範囲内で種々の変更を施すことは何ら差し支えない。例えば上述の実施の形態例では、金属層11は無電解めっき法により被着させたが、真空蒸着法やスパッタリング法により被着させてもよい。
【0035】
【発明の効果】
本発明の半田バンプ付き配線基板の製造方は、樹脂層に形成された開口部の内側面に半田との固溶体を形成する金属層を被着し、開口部内に内側に半田ペーストを塗布し加熱することによって開口部の内側に接合された半田バンプを形成することから、半田バンプは開口部の内側面に被着させた金属層に良好に濡れて接合されるため、開口部内に十分に入り込んだ状態でパッドと接合される。その結果、半田バンプとパッドとが強固に接合された接続信頼性に優れる半田バンプ付き配線基板を提供することができる。
【図面の簡単な説明】
【図1】本発明の製造方法により製作される半田バンプ付き配線基板の実施の形態の一例を示す断面図である。
【図2】(a)〜(d)は本発明の半田バンプ付き配線基板の製造方法を説明するための工程毎の要部拡大断面図である。
【符号の説明】
1:絶縁基板
2:配線導体
3:パッド
4:樹脂層
4a:樹脂層の開口部
5:半田バンプ
11:金属層
21:半田ペースト
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a wiring board with solder bumps for mounting electronic components such as semiconductor elements and resistors.
[0002]
[Prior art]
In recent years, wiring boards used for mounting electronic components such as semiconductor elements have been alternately provided with a plurality of insulating plates made of glass fiber base material impregnated with a thermosetting resin and wiring conductor layers made of copper foil or the like. 2. Description of the Related Art Printed circuit boards formed by lamination, and build-up boards formed by laminating a plurality of insulating layers made of a thermosetting resin and a filler and wiring conductor layers made of a copper plating layer on an insulating plate have been used. On the upper surface of a wiring board such as a printed board or a build-up board, pads for connecting electrodes of electronic components such as semiconductor elements are formed, and an opening for exposing a central portion of the pad is provided. And a solder bump for joining the electronic component and the pad is formed on the pad exposed in the opening.
[0003]
In such a wiring board with solder bumps, the electronic component is placed on the upper surface of the wiring board such that each electrode thereof comes into contact with the corresponding solder bump, and these are placed in a heating device such as an electric furnace. By heating and melting the solder bumps to join the solder bumps to the electrodes of the electronic component, the electronic component is mounted on the wiring board. Eutectic solder such as Sn-Pb eutectic solder is generally used as the solder powder contained in the solder paste for forming the solder bumps used at this time.
[0004]
Note that such a wiring board with solder bumps has a plurality of circular pads connected to the wiring conductors, and a plurality of circular pads connected to the wiring conductors on the surface of an insulating substrate having a plurality of wiring conductors on at least one of the inside and the surface. A resin layer having an opening exposing a central portion is applied, and then a solder paste composed of a flux and a solder powder is printed and applied on a pad by a conventionally known screen printing method in an amount required for forming a solder bump, It is manufactured by heating this to melt and solidify the solder powder in the solder paste to form solder bumps on the pads.
[0005]
[Patent Document 1]
JP-A-2002-217531
[Problems to be solved by the invention]
However, in recent years, a wiring board applied to a semiconductor element storage package for mounting a semiconductor element such as an IC or an LSI, and a hybrid integrated circuit device for mounting various electronic parts, etc., in which the degree of integration is increasing, is not suitable for connecting electronic parts. There is a demand for miniaturization and high-density arrangement of pads. For example, there is a case where a diameter of a portion exposed to an opening of a pad is 90 μm or less and an arrangement interval (interval between pad centers) is 150 μm or less. Is coming.
[0007]
A solder paste containing a solder powder such as Sn-Pb eutectic solder is printed and applied on the fine and pad exposed in the opening of the resin layer, and when the solder powder is heated, when the eutectic temperature is reached, Since the solder changes instantaneously from the solid phase to the liquid phase and melts, the surface tension of the molten solder instantaneously changes to the liquid phase, and the solder floats from the pad before it fully wets the pad. As a result, there is a problem that the solder bumps and the pads are not joined well.
[0008]
Accordingly, the present invention has been completed in view of the conventional problems described above, and an object of the present invention is to provide a wiring board with solder bumps and a method of manufacturing the same, which can securely bond a pad and a solder bump. It is in.
[0009]
[Means for Solving the Problems]
The method for manufacturing a wiring board according to the present invention includes, on a surface of an insulating substrate having a wiring conductor, a resin layer having a plurality of solder bonding pads connected to the wiring conductor and an opening exposing a central portion of the pad. Forming, applying a metal layer that forms a solid solution with solder on the inner surface of the opening, and applying a solder paste to the inner surface of the opening and heating to form a solder bump; It is characterized by having.
[0010]
The method of manufacturing a wiring board with solder bumps according to the present invention includes applying a metal layer that forms a solid solution with solder to the inner surface of the opening formed in the resin layer, applying a solder paste inside the opening, and heating. By forming the solder bumps bonded inside the opening by performing, the solder bumps are sufficiently wet and bonded to the metal layer adhered to the inner surface of the opening, so that the solder bumps penetrate sufficiently into the opening. It is joined with the pad in the state. As a result, it is possible to provide a wiring board with solder bumps, in which the solder bumps and the pads are firmly joined and have excellent connection reliability.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
The wiring board with solder bumps of the present invention will be described in detail below. FIG. 1 is a sectional view showing an example of an embodiment of a wiring board with solder bumps of the present invention, and FIG. 2 is an enlarged sectional view of a main part of the wiring board with solder bumps of FIG. FIG. 3 is an enlarged cross-sectional view of a main part in each step for explaining the method of manufacturing a wiring board with solder bumps according to the present invention.
[0012]
First, a wiring board with solder bumps of the present invention (hereinafter, simply referred to as a wiring board) will be described. In FIG. 1, 1 is an insulating substrate, 2 is a wiring conductor, 3 is a pad for solder bonding, 4 is a resin layer, and 5 is a solder bump, and these mainly constitute a wiring substrate of the present invention. Although the example shown in FIG. 1 has the external lead pins 6, the external lead pins 6 are not necessarily required, and instead of the external lead pins 6, an external connection terminal made of solder or the like may be provided.
[0013]
The insulating substrate 1 according to the present invention has a plate-shaped core body 1a formed by impregnating a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin into a glass fabric in which glass fibers are woven vertically and horizontally. And a plurality of insulating layers 1b made of a thermosetting resin such as a bismaleimide triazine resin. The surface of the core 1a or each insulating layer 1b is made of a conductive layer such as a copper foil or a copper plating layer. A plurality of wiring conductors 2 are formed.
[0014]
The core 1a has a thickness of about 0.3 to 1.5 mm, and has a plurality of through holes 7 with a diameter of about 0.1 to 1.0 mm from the upper surface to the lower surface. A part of the wiring conductor 2 is attached to the inner surface of each through hole 7, and the wiring conductors 2 formed on the upper and lower surfaces of the core 1 a are electrically connected to each other through the wiring conductor 2 in the through hole 7. It is connected.
[0015]
The core 1a is prepared by preparing a sheet in which a glass fabric is impregnated with an uncured thermosetting resin and thermosetting the thermosetting resin, and then drilling a through hole 7 extending between the upper and lower surfaces using a drill or the like. It is manufactured by forming. The wiring conductors 2 on the upper and lower surfaces of the core 1a are formed by attaching a copper foil having a thickness of about 3 to 50 μm to the entire upper and lower surfaces of the sheet for the core 1a, and etching the copper foil after curing the sheet. By doing so, a predetermined pattern is formed on the upper and lower surfaces of the core 1a. Further, the wiring conductor 2 in the through-hole 7 is provided with a through-hole 7 in the core body 1a, and then a copper plating layer having a thickness of about 3 to 50 μm is formed on the inner surface of the through-hole 7 by an electroless plating method or an electrolytic plating method. By being formed, it is adhered to the inner surface of the through hole 7.
[0016]
Further, the core 1a is filled with a resin column 8 made of a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin inside the through hole 7. The resin pillar 8 closes the through hole 7 and is connected to portions of the insulating layer 1b immediately above and directly below the through hole 7, respectively, so that the insulating layers 1b on the upper and lower surfaces of the core 1a can be firmly fixed. . The resin pillar 8 is formed by filling an uncured paste-like thermosetting resin into the through-hole 7 by a screen printing method, thermally curing the same, and polishing the upper and lower end surfaces thereof flat. . Then, an insulating layer 1b is laminated on the upper and lower surfaces of the core body 1a having the resin columns 8.
[0017]
The insulating layers 1b stacked on the upper and lower surfaces of the core body 1a each have a thickness of about 20 to 60 μm, and a plurality of through holes 9 having a diameter of about 30 to 100 μm are formed between the upper and lower surfaces of each insulating layer 1b. A part of the wiring conductor 2 is formed in these through holes 9. These insulating layers 1b are for forming insulating intervals for wiring the wiring conductors 2 at high density. By electrically connecting the upper wiring conductor 2 and the lower wiring conductor 2 of the insulating layer 1b via the wiring conductor 2 in the through hole 9, a high-density wiring can be formed three-dimensionally. I have.
[0018]
The insulating layer 1b is formed by attaching an uncured thermosetting resin film having a thickness of about 20 to 60 μm to the upper and lower surfaces of the core body 1a, thermosetting the same, and forming a through hole 9 by laser processing. Further, it is formed by sequentially laminating the next insulating layer 1b in the same manner. The wiring conductor 2 attached to the surface of each insulating layer 1b and the inside of the through hole 9 has a thickness of about 5 to 50 μm on the surface of each insulating layer 1b and the inside of the through hole 9 every time the insulating layer 1b is formed. Is formed in a predetermined pattern by a known patterning method such as a semi-additive method or a subtractive method.
[0019]
Further, a resin layer 4 is provided on the outermost insulating layer 1b. The resin layer 4 is made of, for example, an insulating material in which about 30 to 70% by mass of an inorganic powder filler such as silica or talc is dispersed in an acrylic-modified epoxy resin having solder resistance (which does not deform at the melting point of solder). In addition to enhancing the electrical insulation reliability between the wiring conductors 2 on the surface layer, it has the effect of increasing the bonding strength of the pads 3 and the pin bonding pads 10 to the insulating substrate 1.
[0020]
The resin layer 4 has a thickness of about 10 to 50 μm, and is coated with an uncured resin paste having photosensitivity on the outermost insulating layer 1b by a roll coater method or a screen printing method, and after drying, Exposure and development are performed to form openings 4a and 4b for exposing the central portions of the pad 3 and the pin bonding pad 10, and then these are formed by heat curing. Alternatively, after an uncured resin film for the resin layer 4 is attached on the uppermost insulating layer 1b, it is thermally cured, and thereafter, a laser beam is applied to a position corresponding to the pad 3 or the pin bonding pad 10. Irradiated and cured resin film is partially removed to form openings 4a and 4b that expose pad 3 and pin bonding pad 10.
[0021]
The wiring conductor 2 formed between the upper and lower surfaces of the insulating substrate 1 functions as a conductive path for connecting each electrode of the electronic component to a wiring conductor or the like of the external electric circuit board. A part of the portion of the wiring conductor 2 in the mounting region of the present invention is applied to each electrode of the electronic component so that tin 63-lead 37 eutectic solder containing 63 mass% of tin and 37 mass% of lead, tin 96.5-silver 3 It is joined to the pad 3 via a solder bump 5 made of low melting point solder such as 0.5 eutectic solder, tin 96-silver 3.5-copper 0.5 non-eutectic solder. A part of the portion of the wiring conductor 2 exposed on the lower surface of the insulating substrate 1 is electrically connected to a pin bonding pad 10 for bonding an external lead pin 6 connected to a wiring conductor or the like of an external electric circuit board. ing.
[0022]
The pad 3 and the pin bonding pad 10 are formed by covering an outer peripheral portion of a circular pattern formed of a conductor layer connected to the wiring conductor 2 with a width of about 15 to 35 μm with a resin layer 4 and defining an outer peripheral edge thereof. The exposed diameter of the pad 3 is about 50 to 200 μm, and that of the pin bonding pad 10 is about 0.5 to 2.5 mm. As described above, by covering the outer peripheral portions of the pad 3 and the pin bonding pad 10 with the resin layer 4, an electrical short circuit between the pads 3 and the pin bonding pads 10 is effectively prevented, and the pads 3 and the pin bonding pads 10 are effectively prevented. The bonding strength of the bonding pad 10 to the insulating substrate 1 can be increased.
[0023]
Further, a solder bump 5 is bonded to the pad 3. The solder bumps 5 are made of low melting point solder such as tin 63-lead 37 eutectic solder, 96.5-silver 3.5 eutectic solder, tin 96-silver 3.5-copper 0.5 non-eutectic solder, It functions as a connection terminal for electrically and mechanically connecting the pad 3 and the electronic component. Then, the electronic component is placed on the insulating substrate 1 such that each electrode of the electronic component comes into contact with the corresponding solder bump 5, and these are heated by a heating device such as an electric furnace to melt the solder bump 5. By solidifying, the solder bumps 5 are connected to the electrodes of the electronic component.
[0024]
External lead pins 6 made of a metal such as copper or an iron-nickel-cobalt alloy are bonded to the pin bonding pad 10 via solder having a higher melting point than the solder bumps 5. The external lead pin 6 functions as a terminal member for electrically connecting an electronic component mounted on the insulating substrate 1 to an external electric circuit board, and connects the external lead pin 6 to a wiring conductor of the external electric circuit board via solder or a socket. In this case, the electronic component is electrically connected to the external electric circuit.
[0025]
Next, a method for manufacturing a wiring board of the present invention will be described below.
[0026]
First, as shown in FIG. 3A, on an upper surface of an insulating substrate 1 having a wiring conductor 2, a resin layer having a pad 3 connected to the wiring conductor 2 and an opening 4 a exposing a central portion of the pad 3. 4 is formed. The pad 3 is formed by coating a copper plating layer having a thickness of about 5 to 20 μm on the uppermost insulating layer 1b constituting the insulating substrate 1 in a predetermined pattern by a pattern forming method such as a known semi-additive method or a subtractive method. It is formed by putting on.
[0027]
The resin layer 4 is formed by applying an uncured resin paste having photosensitivity to the uppermost insulating layer 1b by a roll coater method or a screen printing method, and drying and then exposing and developing the pad. After forming an opening 4a for exposing the central portion of 3, an opening 4a is formed by heat curing. Alternatively, after an uncured resin film for the resin layer 4 is adhered to the uppermost insulating layer 1b, it is thermally cured, and thereafter, a position corresponding to the pad 3 is irradiated with laser light to be cured. By partially removing the resin film, the pad 3 is formed so as to have an opening 4 a exposing the central portion of the pad 3.
[0028]
Next, as shown in FIG. 3B, a metal layer 11 forming a solid solution with solder is applied to the inner surface of the opening 4a of the resin layer 4. To apply the metal layer 11, a plating resist layer that exposes the opening 4a is applied to the surface of the resin layer 4, and a solid solution with solder is applied to the inner surface of the exposed opening 4a by electroless plating. After the metal layer 11 is formed, the plating resist layer is peeled off.
[0029]
In addition, as the metal layer 11, an electroless gold plating layer having a thickness of 0.01 to 0.1 μm or an electroless copper plating layer having a thickness of about 0.1 to 1 μm is preferable. By forming the metal layer 11 as an electroless gold plating layer having a thickness of 0.01 to 0.1 μm or an electroless copper plating layer having a thickness of about 0.1 to 1 μm, the metal layer 11 can be firmly fixed in the solder bumps 5. Dissolve. Further, it is preferable that the melting point is higher by 10 ° C. or more than that of the solder contained in the solder paste for the solder bump 5 so as not to melt before the solder contained in the solder paste for the solder bump 5.
[0030]
Next, as shown in FIG. 3C, a solder paste 21 containing solder powder and flux is applied to the center of the pad 3 exposed in the opening 4a of the resin layer 4 by a conventionally well-known screen printing method. Print and apply. As the solder powder, a spherical solder having a particle size of about 3 to 25 μm is used. Examples of such a solder powder include tin 63-lead 37 eutectic solder, tin 96.5-silver 3.5 eutectic solder, and tin 96-silver 3.5-copper 0.5 non-eutectic solder. Solder can be used.
[0031]
Next, as shown in FIG. 3D, by heating the solder paste 21, the solder powder and the metal layer 11 in the solder paste 21 are melted to form the solder bumps 5 joined to the pads 3. At this time, according to the manufacturing method of the present invention, the molten solder satisfactorily wets and melts with the metal layer 11 on the inner side surface of the opening 4a, thereby sufficiently penetrating into the opening 4a and joining to the pad 3. As a result, a wiring board with solder bumps in which the solder bumps 5 and the pads 3 are satisfactorily joined can be provided. The metal layer 11 is dissolved in the solder bump 5 and disappears as a layer.
[0032]
In the present invention, the metal layer 11 is formed on the inner surface of the opening 4a, but may be formed not only on the inner surface of the opening 4a but also on the bottom surface (the exposed surface of the pad 3) of the opening 4a. Good. In this case, since the molten solder is satisfactorily wet and joined to the metal layer 11 on the inner side surface and the bottom surface of the opening 4a, the joining property of the solder bump 5 is further improved.
[0033]
Thus, in the wiring board of the present invention, the electronic component is placed on the upper surface of the insulating substrate 1 such that its electrodes are in contact with the solder bumps 5, and the solder bumps 5 are heated and melted so that the electrodes of the electronic components and the pads 3 are connected. Are joined to form an electronic device as a product.
[0034]
Note that the present invention is not limited to the above-described embodiment, and various changes may be made without departing from the spirit of the present invention. For example, in the above-described embodiment, the metal layer 11 is applied by an electroless plating method, but may be applied by a vacuum evaporation method or a sputtering method.
[0035]
【The invention's effect】
The method of manufacturing a wiring board with solder bumps according to the present invention includes applying a metal layer that forms a solid solution with solder to the inner surface of the opening formed in the resin layer, applying a solder paste inside the opening, and heating. The solder bumps are formed inside the opening by forming the solder bumps, so that the solder bumps are sufficiently wet and bonded to the metal layer adhered to the inner surface of the opening, so that the solder bumps sufficiently penetrate into the opening. It is joined with the pad in the state. As a result, it is possible to provide a wiring board with solder bumps, in which the solder bumps and the pads are firmly joined and have excellent connection reliability.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an example of an embodiment of a wiring board with solder bumps manufactured by a manufacturing method of the present invention.
FIGS. 2A to 2D are enlarged cross-sectional views of a main part in each step for explaining a method of manufacturing a wiring board with solder bumps according to the present invention.
[Explanation of symbols]
1: Insulating substrate 2: Wiring conductor 3: Pad 4: Resin layer 4a: Resin layer opening 5: Solder bump 11: Metal layer 21: Solder paste

Claims (1)

配線導体を有する絶縁基板の表面に、前記配線導体に接続された複数の半田接合用のパッドおよび該パッドの中央部を露出させる開口部を有する樹脂層を形成する工程と、前記開口部の内側面に半田との固溶体を形成する金属層を被着する工程と、前記開口部の内面に半田ペーストを塗布し加熱することによって半田バンプを形成する工程とを具備していることを特徴とする半田バンプ付き配線基板の製造方法。Forming, on a surface of an insulating substrate having a wiring conductor, a resin layer having a plurality of solder bonding pads connected to the wiring conductor and an opening exposing a central portion of the pad; A step of applying a metal layer that forms a solid solution with solder on the side surface, and a step of forming a solder bump by applying and heating a solder paste on the inner surface of the opening. Manufacturing method of wiring board with solder bumps.
JP2003120791A 2003-04-24 2003-04-24 Process for producing wiring board with solder bump Pending JP2004327742A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007115923A (en) * 2005-10-20 2007-05-10 Seiko Epson Corp Semiconductor device and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007115923A (en) * 2005-10-20 2007-05-10 Seiko Epson Corp Semiconductor device and manufacturing method thereof

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