JP2004221268A - Method for manufacturing laminated ceramic electronic component - Google Patents

Method for manufacturing laminated ceramic electronic component Download PDF

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Publication number
JP2004221268A
JP2004221268A JP2003006127A JP2003006127A JP2004221268A JP 2004221268 A JP2004221268 A JP 2004221268A JP 2003006127 A JP2003006127 A JP 2003006127A JP 2003006127 A JP2003006127 A JP 2003006127A JP 2004221268 A JP2004221268 A JP 2004221268A
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Prior art keywords
ceramic
internal electrode
ceramic layer
rate
shrinkage
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JP2003006127A
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Japanese (ja)
Inventor
Kenichi Kawasaki
健一 川崎
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a laminated ceramic electronic component, which can surely relieve internal stress generated by the difference of shrinkage between the internal electrode lamination part and the outer layer ceramic layer in the case of baking, and hardly generates structure defects. <P>SOLUTION: The method for manufacturing a laminated ceramic electronic component is provided with an internal electrode lamination part in which a plurality of internal electrodes are overlapped through ceramic layers, and outer layer ceramic layers arranged above and below the lamination part. The rate of the shrinkage rate change becomes maximum at a temperature T1, in the case of baking in the state that internal electrodes of the ceramic layers in the lamination part are formed. The rate of the shrinkage change in the case of baking of the outer layer ceramic layer becomes maximum at a temperature T2. A ceramic lamination which is not yet baked and in which difference between T1 and T2 is at most 60<SP>o</SP>C is prepared. A process for obtaining a sintered body, and a process for forming an external electrode which is electrically connected with the internal electrode on an outer surface of the sintered body are prepared. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

【0001】
【発明の属する技術分野】
本発明は、例えば積層セラミックコンデンサのような積層セラミック電子部品の製造方法に関し、より詳細には、内部電極が積層されている部分と外層セラミック層との収縮率差を改善する工程を備えた積層セラミック電子部品の製造方法に関する。
【0002】
【従来の技術】
従来、積層セラミックコンデンサなどの積層セラミック電子部品の製造に際しては、内部電極ペーストが印刷されたセラミックグリーンシートが積層され、かつ該内部電極が積層されている部分の上下に外層セラミック層を構成するために複数枚の内部電極ペーストが印刷されていないセラミックグリーンシートが積層されることにより、積層体が得られている。そして、この積層体が焼成されて焼結体が得られ、次に焼結体の外表面に外部電極が形成されている。
【0003】
焼成に際しては、内部電極の焼成収縮率がセラミックスの焼成収縮率に比べて高い。従って、セラミックグリーンシートを介して内部電極ペーストが積層されている内部電極積層部と、外層セラミック層とで収縮率差が生じる。よって、得られた焼結体において、内部電極積層部と外層セラミック層との間で歪みが生じたり、最終的にデラミネーションと称されている層間剥離現象が生じるという問題があった。
【0004】
下記の特許文献1に記載の方法では、このような問題を解決するために、内部電極ペーストが設けられたセラミックグリーンシートに比べて外層セラミック層を構成するセラミックグリーンシートの焼成収縮率が高くされている。すなわち、内部電極積層部と外層セラミック層との収縮率差を小さくするために、外層セラミック層を構成するセラミックグリーンシートの収縮率が高められている。
【0005】
また、下記の特許文献2では、外層セラミック層を構成するセラミックグリーンシートとして、内部電極ペーストの焼成収縮率に近い焼成収縮率を有するセラミックグリーンシートを用いる方法が開示されている。
【0006】
また、下記の特許文献3には、外層セラミック層を構成するセラミックグリーンシートとして、焼成に際しての収縮開始温度が、内部電極積層部を構成しているセラミックグリーンシートの収縮開始温度よりも低いセラミックグリーンシートを用いる方法が開示されている。
【0007】
【特許文献1】
特開昭59−47727号公報
【特許文献2】
特開平7−263272号公報
【特許文献3】
特開平9−97733号公報
【0008】
【発明が解決しようとする課題】
上記特許文献1,2に記載のように、内部電極積層部のセラミックグリーンシートと、外層セラミック層を構成するセラミックグリーンシートの焼成収縮率を近づける方法では、焼成に際しての内部電極積層部と外層セラミック層との間の焼成収縮率差が低減され、両者の焼成収縮率差により生じる内部応力を緩和することができる。しかしながら、内部電極積層部のセラミックグリーンシートまたは外層セラミック層を構成するセラミックグリーンシートの焼成収縮率だけを制御したとしても、上記収縮率差による内部応力を十分に緩和することはできなかった。
【0009】
構造欠陥は、主として、内部電極積層部と、外層セラミック層の間で生じる割合が高く、内部電極積層部と外層セラミック層の収縮率を制御し、上記内部応力を十分に緩和しなければならない。さもないと、最終的に得られた積層セラミック電子部品において、ある確率で構造欠陥が生じざるを得なかった。
【0010】
また、上記特許文献3に記載の方法では、外層セラミック層を構成しているセラミックグリーンシートの収縮開始温度と、内部電極積層部を構成しているセラミックグリーンシートの収縮開始温度が近づけられ、それによって焼成に際して生じる内部応力を緩和することができるが、やはり、内部応力を十分に緩和することはできなかった。
【0011】
本発明の目的は、上述した従来技術の欠点を解消し、焼成に際しての内部電極積層部と外層セラミック層との間の収縮挙動の差によって生じる内部応力をより確実に緩和することができ、従って構造欠陥が生じ難い積層セラミック電子部品の製造方法を提供することにある。
【0012】
【課題を解決するための手段】
本発明に係る積層セラミック電子部品の製造方法の広い局面によれば、複数の内部電極がセラミック層を介して重なり合っている内部電極積層部と、内部電極積層部の上方及び下方に配置された外層セラミック層とを有し、かつ前記外層セラミック層の焼成に際しての収縮率の変化率が最大となる温度を、前記内部電極積層部のセラミック層の内部電極が形成された状態での焼成に際しての収縮率の変化率が最大となる温度との差が60℃以下となるように構成した未焼成のセラミック積層体を用意する工程と、前記セラミック積層体を焼成し、焼結体を得る工程と、前記焼結体の外表面に、内部電極と電気的に接続される外部電極を形成する工程とを備える、積層セラミック電子部品の製造方法が提供される。
【0013】
本発明に係る製造方法のある特定の局面では、前記内部電極積層部のセラミック層及び外層セラミック層が、AサイトとBサイトとを有するセラミックスを主体とする組成物からなり、各組成物におけるAサイトイオンのモル濃度をA、Bサイトイオンのモル濃度をBとしたときに、前記内部電極積層部におけるモル比A/Bに比べて、外層セラミック層におけるモル比A/Bが低くされている。
【0014】
また、本発明に係る製造方法のより限定的な局面では、前記内部電極積層部のセラミック層及び前記外層セラミック層を構成する前記セラミックスが、チタン酸バリウム系セラミックスからなり、前記Aサイトがチタンイオンサイトであり、前記Bサイトがバリウムイオンサイトである。
【0015】
また、より好ましくは、上記内部電極積層部のセラミック層に比べて、外層セラミック層においてMn酸化物が多く含有され、それによって内部電極積層部のセラミック層の焼成に際しても、収縮率の変化率が最大となる温度と、外層セラミック層の焼成に際しての収縮率の変化率が最大となる温度との差がより一層近づけられる。
【0016】
【発明の実施の形態】
以下、本発明の具体的な実施例を説明することにより本発明を明らかにする。
本実施例の積層セラミック電子部品の製造方法では、まず、図2に示す未焼成のセラミック積層体1が用意される。未焼成のセラミック積層体1では、複数の内部電極2〜5がセラミック層6a〜6cを介して厚み方向に重なり合うように配置されている。この内部電極2〜5及びセラミック層6a〜6cが積層されている部分が内部電極積層部6を構成している。また、内部電極積層部6の上下には外層セラミック層7,8が配置されている。
【0017】
積層体1を得るにあたっては、セラミックグリーンシート上に内部電極を構成するための導電ペーストが印刷されたマザーのセラミックグリーンシートを用意する。このマザーのセラミックグリーンシートが複数枚積層され、さらに上下に外層セラミック層7,8を構成する適宜の枚数のセラミックグリーンシートが積層される。このようにして得られたマザーの積層体を個々の積層セラミックコンデンサ単位の積層体に切断することにより、セラミック積層体1が得られる。
【0018】
本実施例では、外層セラミック層7,8と、内部電極積層体部6を構成しているセラミック層6a〜6cの焼成に際しての収縮率の変化率が最大となる温度差が60℃以下となるように、内部電極積層部6のセラミックグリーンシート及び外層セラミック層7,8を構成しているセラミックスが構成されている。
【0019】
なお、焼成に際しての収縮率とは、焼成前の面方向の寸法に対して焼成後の面方向の寸法が収縮した率を示す。
上記セラミック積層体1が焼成されて、図3に示すセラミック焼結体9が得られる。さらに、セラミック焼結体9の両端面9a,9bに外部電極10,11が形成され、積層セラミックコンデンサ12が得られる。
【0020】
本実施例では、焼成に際して内部電極積層部のセラミック層6a〜6cの収縮率の変化率が最大となる温度と、外層セラミック層7,8の焼成に際しての収縮率の変化率が最大となる温度との差が60℃以下とされている。これを、図1を参照してより具体的に説明する。
【0021】
図1は、焼成に際しての収縮率の変化及び焼成工程における温度変化を示す図であり、曲線Aは内部電極積層部6のセラミック層6a〜6cの収縮率の変化を示し、曲線Bは実施例における外層セラミック層7,8の収縮率の変化を示し、曲線Cは後述の本発明以外の例の場合の外層セラミック層の収縮率変化を示し、実線Dは焼成温度の変化を示す。内部電極積層部6のセラミック層6a〜6cの焼成に際しての収縮率の変化率が最大となる温度とは、図1の曲線A中の、点A1の際の温度T1をいうものとする。すなわち、焼成に際しての収縮率の変化が最大となる部分が点A1であり、このときの温度T1が収縮率の変化率が最大となる温度である。同様に、外層セラミック層7,8の焼成に際しての収縮率の変化率が最大となる、点B1における温度T2が、収縮率の変化率が最大となる温度である。そして、この収縮率の変化率が最大となる温度T1,T2の差が60℃以下とされていることにより、本実施例では、内部電極積層部と外層セラミック層との間の収縮挙動の差による構造欠陥の発生を確実に抑制することができる。
【0022】
なお、上記のように、内部電極積層部6のセラミック層6a〜6cの収縮率の変化率の最大となる温度T1及び外層セラミック層7,8の焼成に際しての収縮率の変化率が最大となる温度T2の制御は、これらのセラミック層を構成しているセラミックスの組成を調整することにより行い得る。
【0023】
例えば、チタン酸バリウム系セラミックスを用いた場合、チタン酸バリウム系セラミックスは、AサイトとBサイトとを有するセラミックスである。言い換えれば、チタン酸バリウム系セラミックスはA(但し、x,y,zは組成によって変動するモル比を示す)で表わされる組成を有する。Aサイトがチタンイオンサイトであり、Bサイトがバリウムイオンサイトである。
【0024】
そして、外層セラミック層7,8に用いられるセラミックグリーンシートにおけるモル比A/Bを、内部電極積層部に用いられるセラミックグリーンシートにおけるモル比A/Bよりも低くすることにより、上記温度T1,T2の差を60℃以下とすることができる。
【0025】
もっとも、本発明では、上記のように、温度T1と温度T2の差を60℃以下とすることが必要ではあるが、このような温度差を実現するには、上記のようにモル比A/Bを制御する方法に限らず、Mn酸化物などの添加量の調整などの様々な方法を採用することができる。
【0026】
次に具体的な実験例につき説明する。以下の実験例では、外層セラミック層の組成を制御することにより、積層セラミック層の焼成に際しての収縮率の変化率が最大となる温度T2を制御した。
【0027】
まず、内部電極積層部のセラミック層を構成するために、Mn酸化物がチタン酸バリウム系セラミック粉末に対して0.1モル%、SiOが0.1モル%、バインダー樹脂が10モル%添加されており、かつモル比A/Bが1.0100である組成物を用いて構成されたマザーのセラミックグリーンシートを用意した。このマザーのセラミックグリーンシート上に、内部電極ペーストを印刷し、内部電極パターンを形成した。
【0028】
他方、下記の表1に示す組成のチタン酸バリウム系セラミックス組成物を用いて構成された条件No.1〜No.6の6種類の外層セラミック層構成用のマザーのセラミックグリーンシートを用意した。
【0029】
外層セラミック層を構成するマザーのセラミックグリーンシートでは、上記モル比A/Bを下記の表1に示したように異ならせただけでなく、チタン酸バリウム系セラミック粉末に対しMn酸化物、SiO粉末及びバインダー樹脂を下記の表1に示す割合でそれぞれ添加したものを用いた。
【0030】
上記内部電極パターンが印刷されたマザーのセラミックグリーンシートを200枚積層し、その上下に、No.1、No.2、No.3、No.4、No.5またはNo.6のマザーのセラミックグリーンシートをそれぞれ20枚積層し、マザーの積層体を得た。このマザーの積層体を個々の積層セラミックコンデンサ単位の積層体に切断し、未焼成のセラミック焼結体を得た。
【0031】
しかる後、上記積層体を焼成し、焼結体を得、両端面に外部電極を形成することにより積層セラミックコンデンサを作製した。
上記のようにして、内部電極積層数が200となり、長さ2.00×幅1.25×厚み1.25mmの積層セラミックコンデンサを作製した。
【0032】
上記のようにして外層セラミック層が条件No.1〜No.6に従って構成された積層セラミックコンデンサ及び該積層セラミックコンデンサを得るのに用いたセラミックグリーンシートについて、▲1▼収縮開始温度、▲2▼焼成後収縮率、▲3▼収縮率の変化率が最大となる温度差及び▲4▼構造欠陥発生率を評価した。結果を下記の表1に示す。
【0033】
なお、▲1▼収縮開始温度、▲2▼焼成後収縮率及び▲3▼収縮率の変化率が最大となる温度は、内部電極積層部と同じ構成の積層体と、外層セラミック層部と同じ構成の単板を試作し、これらについて実験を行って求めた値である。
【0034】
すなわち、上記積層体と単板を通常温度から1300℃の温度まで1.0℃/分の速度で昇温し、1300℃以上にした後、5.0℃/分の速度で降温する焼成試験を行い、収縮開始温度、焼成後収縮率及び収縮率の変化率の最大となる温度差を求めた。
【0035】
なお、図1の曲線A〜Cは、内部電極積層部のセラミック層と同じ組成の単板、条件No.3及び条件No.5の外層セラミック層部と同じ組成の単板、それぞれの収縮率の変化を示す。
【0036】
また、▲4▼構造欠陥発生率については、得られた積層セラミックコンデンサについて、超音波探傷試験機を用いて構造欠陥の有無を確認した。なお、評価数は1000個とし、1000個あたりの構造欠陥発生率を求めた。
【0037】
【表1】

Figure 2004221268
【0038】
条件No.1では、内部電極積層部におけるセラミックグリーンシートのモル比A/B比が1.0100、外層セラミック層のモル比A/Bが1.0100と等しくされており、すなわち従来の積層セラミックコンデンサと同様に構成されている。
【0039】
これに対して、条件No.2及び3では、外層セラミック層を構成するセラミックスのモル比A/Bが1.0070及び1.0050と低められている。そのため、条件No.2及び3の条件で得られた積層セラミックコンデンサでは、収縮率の変化率が最大となる温度差は、それぞれ、60℃及び30℃であり、構造欠陥発生率が、条件No.1の従来例に比べて低められた。
【0040】
さらに、Mnが0.2重量%で添加されている条件No.4においても、収縮率の変化率が最大となる温度差が50℃であるため、構造欠陥の発生率が0%であった。
【0041】
よって、上述の結果から、収縮率の変化率が最大である温度差が、60℃以下、より好ましくは50℃以下とした場合、構造欠陥発生率を著しく低め得ることがわかる。
【0042】
また、条件No.5では、外層セラミック層を構成するセラミックグリーンシートに焼結部材としてのSiOを多く添加し、外層セラミック層の収縮開始温度が1100℃に低められている。しかしながら、この場合には、外層セラミック層の焼成後収縮率が、内部電極積層部のセラミック層に比べて低くなり、従って構造欠陥発生率が4%と高かった。すなわち、条件No.5では、収縮開始温度が内部電極積層部に比べて外層セラミック層が1100℃と低かったので、図1に示されているように、収縮率の変化率が最大である温度差が80℃と大きかった。従って、構造欠陥発生率は4%と高かった。
【0043】
また、条件No.6の外層セラミック層を構成した場合には、バインダー樹脂を増加させることにより、外層セラミック層の焼成後収縮率が81%と小さくなり過ぎて、構造欠陥発生率が6%と著しく高まった。
【0044】
すなわち、表1の結果から、焼成に際しての内部電極積層部のセラミック層と外層セラミック層の収縮率の変化率が最大となる温度の差を60℃以下、より好ましくは50℃以下にすることにより、構造欠陥発生率を効果的に低め得ることがわかる。また、上記収縮率の変化率が最大となる温度差を小さくするには、上記のようにモル比A/Bを制御する方法、並びにMn酸化物を添加する方法が有効であることがわかる。
【0045】
従って、条件No.2〜6の比較からも明らかなように、収縮開始温度を制御するだけでは、構造欠陥発生率を低めることが困難であり、収縮率の変化率が最大である温度差を60℃以下、より好ましくは50℃以下とすることにより、焼成後収縮率差を低減し、ひいては構造欠陥発生率を低め得ることがわかる。
【0046】
また、条件No.4では、Mn酸化物が、内部電極積層部のセラミックグリーンシートに0.1モル%、外層セラミック層を構成するセラミックグリーンシートに0.2モル%添加されてたため、収縮率の変化率が最大となる温度差は50℃まで低められ、それによって構造欠陥発生率が0%とされている。すなわち、好ましくは、条件No.4のように、Mn酸化物などの収縮率の変化率が最大となる温度を低め得る添加物を外層セラミック層側に相対的に多く配合させることにより本発明に従って収縮率の変化率が最大となる温度差を60℃以下、より好ましくは50℃以下に容易に調整することができる。
【0047】
なお、上記実施例では、積層セラミックコンデンサの製造方法につき説明したが、本発明は、内部電極がセラミック層を介して積層されている内部電極積層部と、内部電極積層部の上下に外層セラミック層が配置されている積層セラミック電子部品の製造方法に一般に適用することができる。すなわち、多層基板や積層セラミックインダクタなどの様々な積層セラミック電子部品の製造方法に本発明を適用することができる。
【0048】
【発明の効果】
本発明に係る積層セラミック電子部品の製造方法では、外層セラミック層の焼成に際しての収縮率の変化率が最大となる温度と内部電極積層部のセラミック層の内部電極が形成された状態での焼成に際しての収縮率の変化率が最大となる温度との差が60℃以下、より好ましくは50℃以下とされているため、焼成後の構造欠陥の発生を効果的に抑制することができ、積層セラミック電子部品の良品率を高めることが可能となる。
【0049】
本発明において、内部電極積層部のセラミック層を構成する組成物のモル比A/Bに比べて、外層セラミック層におけるモル比A/Bが低くされている場合には、それによって焼成に際しての内部電極積層部を構成しているセラミック層の収縮率の変化率が最大となる温度と、外層セラミック層の焼成に際しての収縮率の変化率が最大となる温度の差を60℃以下に容易に設定することができる。
【0050】
また、上記積層セラミック電子部品に用いられる特に限定されないが、例えば、チタン酸バリウム系セラミックスからなる場合は、上記Aサイトがチタンイオンサイトであり、Bサイトがバリウムイオンサイトであり、チタンイオン及びバリウムイオンのモル比を上記のように制御することにより、内部電極積層部のセラミックス層の収縮率の変化率が最大となる温度と、外層セラミック層の収縮率の変化率が最大となる温度差を容易に60℃以下とすることができる。
【0051】
また、内部電極積層部のセラミック層に比べて、外層セラミック層においてMn酸化物を多く含有させた場合には、それによって内部電極積層部のセラミック層の焼成に際しての収縮率の変化率が最大となる温度と、外層セラミック層の焼成に際しての収縮率の変化率が最大となる温度との差を容易に60℃以下にすることができる。
【図面の簡単な説明】
【図1】本発明の実施例において、内部電極積層部のセラミック層用マザーのセラミックグリーンシートの焼成工程における収縮率曲線、モル比A/Bを低めた外層セラミック層用マザーのセラミックグリーンシートの焼成に際しての収縮率曲線及びガラス成分が増量された外層セラミック層用マザーのセラミックグリーンシートの収縮率曲線と、焼成工程における温度変化を示す図。
【図2】実施例において用意される未焼成のセラミック積層体を説明するための正面断面図。
【図3】実施例で得られる積層セラミックコンデンサを模式的に示す正面断面図。
【符号の説明】
1…セラミック積層体
2〜5…内部電極
6…内部電極積層部
6a〜6c…セラミック層
7,8…外層セラミック層
9,10…外部電極
11…積層セラミックコンデンサ[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a multilayer ceramic electronic component such as a multilayer ceramic capacitor, and more particularly, to a method for improving a difference in shrinkage between a portion where internal electrodes are stacked and an external ceramic layer. The present invention relates to a method for manufacturing a ceramic electronic component.
[0002]
[Prior art]
Conventionally, when manufacturing a multilayer ceramic electronic component such as a multilayer ceramic capacitor, a ceramic green sheet on which an internal electrode paste is printed is laminated, and an outer ceramic layer is formed above and below a portion where the internal electrode is laminated. A plurality of ceramic green sheets, on which the internal electrode paste is not printed, are laminated on each other to obtain a laminate. Then, the laminate is fired to obtain a sintered body, and then external electrodes are formed on the outer surface of the sintered body.
[0003]
During firing, the firing shrinkage of the internal electrode is higher than the firing shrinkage of the ceramic. Therefore, there is a difference in shrinkage between the internal electrode laminated portion where the internal electrode paste is laminated via the ceramic green sheet and the outer ceramic layer. Therefore, in the obtained sintered body, there is a problem that distortion occurs between the internal electrode laminated portion and the outer ceramic layer, and finally, a delamination phenomenon called delamination occurs.
[0004]
In the method described in Patent Document 1 below, in order to solve such a problem, the firing shrinkage of the ceramic green sheet constituting the outer ceramic layer is increased as compared with the ceramic green sheet provided with the internal electrode paste. ing. That is, in order to reduce the difference in shrinkage between the internal electrode laminated portion and the outer ceramic layer, the shrinkage of the ceramic green sheets constituting the outer ceramic layer is increased.
[0005]
Patent Document 2 below discloses a method in which a ceramic green sheet having a firing shrinkage rate close to the firing shrinkage rate of the internal electrode paste is used as the ceramic green sheet constituting the outer ceramic layer.
[0006]
Patent Document 3 below discloses a ceramic green sheet constituting an outer ceramic layer, wherein a ceramic green sheet having a shrinkage start temperature upon firing is lower than a shrinkage start temperature of a ceramic green sheet constituting an internal electrode laminated portion. A method using a sheet is disclosed.
[0007]
[Patent Document 1]
JP-A-59-47727 [Patent Document 2]
JP-A-7-263272 [Patent Document 3]
Japanese Patent Application Laid-Open No. 9-97733
[Problems to be solved by the invention]
As described in Patent Literatures 1 and 2, in the method of making the firing shrinkage ratio of the ceramic green sheet of the internal electrode laminated portion close to that of the ceramic green sheet constituting the outer ceramic layer, the internal electrode laminated portion and the outer layer ceramic during firing are reduced. The difference in firing shrinkage between the layers is reduced, and the internal stress caused by the difference in firing shrinkage between the two layers can be reduced. However, even if only the firing shrinkage rate of the ceramic green sheet of the internal electrode laminated portion or the ceramic green sheet constituting the outer ceramic layer is controlled, the internal stress due to the difference in the shrinkage rate cannot be sufficiently reduced.
[0009]
Structural defects mainly occur at a high rate between the internal electrode laminated portion and the outer ceramic layer, and it is necessary to control the shrinkage of the internal electrode laminated portion and the outer ceramic layer and sufficiently relax the internal stress. Otherwise, a structural defect had to occur at a certain probability in the finally obtained multilayer ceramic electronic component.
[0010]
Further, in the method described in Patent Document 3, the shrinkage start temperature of the ceramic green sheet forming the outer ceramic layer and the shrinkage start temperature of the ceramic green sheet forming the internal electrode laminated portion are brought close to each other. Can reduce the internal stress generated at the time of sintering, but also cannot sufficiently reduce the internal stress.
[0011]
An object of the present invention is to solve the above-mentioned drawbacks of the prior art, and to more reliably alleviate internal stress caused by a difference in shrinkage behavior between the internal electrode laminated portion and the outer ceramic layer during firing, and An object of the present invention is to provide a method for manufacturing a multilayer ceramic electronic component in which a structural defect hardly occurs.
[0012]
[Means for Solving the Problems]
According to the wide aspect of the method for manufacturing a multilayer ceramic electronic component according to the present invention, an internal electrode laminated portion in which a plurality of internal electrodes overlap via a ceramic layer, and an outer layer disposed above and below the internal electrode laminated portion A temperature at which the rate of change of the shrinkage rate during firing of the outer ceramic layer is maximized, the shrinkage during firing in a state where the internal electrodes of the ceramic layer of the internal electrode laminated portion are formed. A step of preparing an unfired ceramic laminate configured so that the difference between the rate of change of the rate and the temperature at which the rate of change becomes the maximum is 60 ° C. or less, and a step of firing the ceramic laminate to obtain a sintered body; Forming an external electrode electrically connected to an internal electrode on the outer surface of the sintered body.
[0013]
In a specific aspect of the manufacturing method according to the present invention, the ceramic layer and the outer ceramic layer of the internal electrode laminated portion are composed of a composition mainly composed of a ceramic having an A site and a B site. When the molar concentration of the site ions is A and the molar concentration of the B site ions is B, the molar ratio A / B in the outer ceramic layer is lower than the molar ratio A / B in the internal electrode laminated portion. .
[0014]
Further, in a more limited aspect of the manufacturing method according to the present invention, the ceramics constituting the ceramic layers and the outer ceramic layers of the internal electrode laminated portion are made of a barium titanate-based ceramic, and the A site is a titanium ion. And the B site is a barium ion site.
[0015]
More preferably, the outer ceramic layer contains a larger amount of Mn oxide than the ceramic layer of the internal electrode laminated portion, whereby the rate of change of the shrinkage rate is reduced even when the ceramic layer of the internal electrode laminated portion is fired. The difference between the maximum temperature and the temperature at which the rate of change of the shrinkage rate during firing of the outer ceramic layer is maximum is further reduced.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be clarified by describing specific examples of the present invention.
In the method of manufacturing a multilayer ceramic electronic component of the present embodiment, first, an unfired ceramic multilayer body 1 shown in FIG. 2 is prepared. In the unfired ceramic laminate 1, a plurality of internal electrodes 2 to 5 are arranged so as to overlap in the thickness direction via ceramic layers 6a to 6c. The portion where the internal electrodes 2 to 5 and the ceramic layers 6a to 6c are laminated constitutes the internal electrode laminated portion 6. Further, outer ceramic layers 7 and 8 are arranged above and below the internal electrode laminated portion 6.
[0017]
In order to obtain the laminate 1, a mother ceramic green sheet on which a conductive paste for forming an internal electrode is printed on a ceramic green sheet is prepared. A plurality of ceramic green sheets of the mother are laminated, and an appropriate number of ceramic green sheets constituting the outer ceramic layers 7 and 8 are further laminated on the upper and lower sides. The ceramic laminate 1 is obtained by cutting the mother laminate thus obtained into laminates of individual multilayer ceramic capacitor units.
[0018]
In the present embodiment, the temperature difference at which the rate of change of the shrinkage ratio during firing of the outer ceramic layers 7 and 8 and the ceramic layers 6a to 6c constituting the internal electrode laminate 6 is maximized is 60 ° C. or less. Thus, the ceramics constituting the ceramic green sheets of the internal electrode laminated portion 6 and the outer ceramic layers 7 and 8 are formed.
[0019]
Note that the shrinkage rate during firing refers to a rate at which the dimension in the plane direction after firing shrinks relative to the dimension in the plane direction before firing.
The ceramic laminate 1 is fired to obtain a ceramic sintered body 9 shown in FIG. Further, external electrodes 10 and 11 are formed on both end faces 9a and 9b of the ceramic sintered body 9, and a multilayer ceramic capacitor 12 is obtained.
[0020]
In the present embodiment, the temperature at which the rate of change of the shrinkage rate of the ceramic layers 6a to 6c of the internal electrode laminated portion at the time of firing becomes maximum, and the temperature at which the rate of change of the shrinkage rate at the time of firing the outer ceramic layers 7 and 8 becomes the maximum. Is 60 ° C. or less. This will be described more specifically with reference to FIG.
[0021]
FIG. 1 is a diagram showing a change in shrinkage during firing and a change in temperature during the firing step. Curve A shows change in shrinkage of ceramic layers 6a to 6c of internal electrode laminated portion 6, and curve B shows an example. , The change in the shrinkage rate of the outer ceramic layers 7 and 8 is shown, the curve C shows the change in the shrinkage rate of the outer ceramic layer in an example other than the present invention described later, and the solid line D shows the change in the firing temperature. The temperature at which the rate of change in the shrinkage rate during firing of the ceramic layers 6a to 6c of the internal electrode laminated portion 6 is the maximum is the temperature T1 at the point A1 in the curve A in FIG. That is, the point at which the change in the shrinkage rate during firing is the maximum is point A1, and the temperature T1 at this time is the temperature at which the change rate of the shrinkage rate is the maximum. Similarly, the temperature T2 at the point B1 at which the rate of change of the shrinkage rate during firing of the outer ceramic layers 7, 8 is the maximum is the temperature at which the rate of change of the shrinkage rate is the maximum. Since the difference between the temperatures T1 and T2 at which the rate of change of the shrinkage rate is maximum is set to 60 ° C. or less, in this embodiment, the difference in the shrinkage behavior between the internal electrode laminated portion and the outer ceramic layer is reduced. Can reliably suppress the occurrence of structural defects.
[0022]
As described above, the temperature T1 at which the change rate of the shrinkage rate of the ceramic layers 6a to 6c of the internal electrode laminated portion 6 becomes the maximum, and the change rate of the shrinkage rate at the time of firing the outer ceramic layers 7 and 8 become the maximum. Control of the temperature T2 can be performed by adjusting the composition of the ceramics constituting these ceramic layers.
[0023]
For example, when a barium titanate-based ceramic is used, the barium titanate-based ceramic is a ceramic having an A site and a B site. In other words, barium ceramics titanate having a composition represented by A x B y O z (where, x, y, z are a molar ratio that varies depending on the composition). The A site is a titanium ion site, and the B site is a barium ion site.
[0024]
By setting the molar ratio A / B in the ceramic green sheets used for the outer ceramic layers 7 and 8 to be lower than the molar ratio A / B in the ceramic green sheets used for the internal electrode laminated portions, the temperatures T1 and T2 are set. Can be 60 ° C. or less.
[0025]
However, in the present invention, as described above, the difference between the temperature T1 and the temperature T2 needs to be 60 ° C. or less, but in order to realize such a temperature difference, the molar ratio A / Not only the method of controlling B but also various methods such as adjustment of the amount of Mn oxide or the like can be adopted.
[0026]
Next, specific experimental examples will be described. In the following experimental examples, by controlling the composition of the outer ceramic layer, the temperature T2 at which the rate of change in the shrinkage rate during firing of the multilayer ceramic layer was maximized was controlled.
[0027]
First, in order to form the ceramic layer of the internal electrode laminated portion, 0.1 mol% of Mn oxide, 0.1 mol% of SiO 2 and 10 mol% of binder resin were added to the barium titanate-based ceramic powder. A mother ceramic green sheet prepared using a composition having a molar ratio A / B of 1.0100 was prepared. An internal electrode paste was printed on the mother ceramic green sheet to form an internal electrode pattern.
[0028]
On the other hand, the condition No. 1 formed using the barium titanate-based ceramic composition having the composition shown in Table 1 below. 1 to No. Six types of mother ceramic green sheets for six types of outer ceramic layers were prepared.
[0029]
In the mother ceramic green sheet constituting the outer ceramic layer, not only the molar ratio A / B was varied as shown in Table 1 below, but also the Mn oxide and SiO 2 were added to the barium titanate-based ceramic powder. A powder and a binder resin were used in the proportions shown in Table 1 below.
[0030]
200 mother ceramic green sheets on which the above internal electrode patterns were printed were laminated, and No. 1, No. 2, No. 3, no. 4, no. 5 or No. Twenty mother ceramic green sheets of No. 6 were laminated, thereby obtaining a mother laminate. The mother laminate was cut into laminates of individual multilayer ceramic capacitor units to obtain an unfired ceramic sintered body.
[0031]
Thereafter, the laminate was fired to obtain a sintered body, and external electrodes were formed on both end faces to produce a multilayer ceramic capacitor.
As described above, the number of laminated internal electrodes became 200, and a multilayer ceramic capacitor having a length of 2.00 × a width of 1.25 × a thickness of 1.25 mm was produced.
[0032]
As described above, when the outer ceramic layer is in the condition No. 1 to No. Regarding the multilayer ceramic capacitor constructed in accordance with No. 6 and the ceramic green sheet used to obtain the multilayer ceramic capacitor, (1) the shrinkage starting temperature, (2) the shrinkage rate after firing, and (3) the change rate of the shrinkage rate is maximum. The temperature difference and (4) the rate of occurrence of structural defects were evaluated. The results are shown in Table 1 below.
[0033]
The temperature at which (1) the shrinkage start temperature, (2) the shrinkage rate after firing, and (3) the temperature at which the rate of change of the shrinkage rate is the maximum is the same as that of the laminate having the same configuration as the internal electrode laminate and the outer ceramic layer. This is a value obtained by experimentally producing a single veneer having the above configuration and conducting experiments on these.
[0034]
That is, a firing test in which the temperature of the laminated body and the veneer is raised from a normal temperature to a temperature of 1300 ° C. at a rate of 1.0 ° C./min, is increased to 1300 ° C. or more, and then is lowered at a rate of 5.0 ° C./min. The shrinkage start temperature, the shrinkage rate after firing, and the temperature difference at which the rate of change of the shrinkage rate becomes maximum were determined.
[0035]
Note that curves A to C in FIG. 1 indicate a single plate having the same composition as the ceramic layer of the internal electrode laminated portion, and the condition No. No. 3 and condition no. 5 shows the change in the shrinkage of each veneer having the same composition as that of the outer ceramic layer portion of No. 5.
[0036]
Regarding (4) the occurrence rate of structural defects, the obtained multilayer ceramic capacitor was checked for the presence or absence of structural defects using an ultrasonic testing machine. The number of evaluations was 1,000, and the rate of occurrence of structural defects per 1000 was determined.
[0037]
[Table 1]
Figure 2004221268
[0038]
Condition No. In No. 1, the molar ratio A / B of the ceramic green sheet in the internal electrode laminated portion is equal to 1.0100, and the molar ratio A / B of the outer ceramic layer is equal to 1.0100. Is configured.
[0039]
On the other hand, condition No. In Nos. 2 and 3, the molar ratio A / B of the ceramics constituting the outer ceramic layer was reduced to 1.0070 and 1.0050. Therefore, the condition No. In the multilayer ceramic capacitors obtained under the conditions of Nos. 2 and 3, the temperature differences at which the rate of change of the shrinkage ratio is the maximum are 60 ° C. and 30 ° C., respectively. 1 is lower than that of the conventional example.
[0040]
Furthermore, the condition No. in which Mn was added at 0.2% by weight was used. Also in No. 4, since the temperature difference at which the rate of change in the shrinkage rate was the largest was 50 ° C., the incidence of structural defects was 0%.
[0041]
Therefore, it can be seen from the above results that when the temperature difference at which the rate of change of the shrinkage rate is the largest is 60 ° C. or less, more preferably 50 ° C. or less, the structural defect occurrence rate can be significantly reduced.
[0042]
Condition No. In No. 5, a large amount of SiO 2 as a sintering member was added to the ceramic green sheets constituting the outer ceramic layer, and the shrinkage starting temperature of the outer ceramic layer was lowered to 1100 ° C. However, in this case, the shrinkage rate of the outer ceramic layer after firing was lower than that of the ceramic layer of the internal electrode laminated portion, and thus the structural defect occurrence rate was as high as 4%. That is, the condition No. In FIG. 5, since the outer ceramic layer had a lower shrinkage start temperature of 1100 ° C. than that of the internal electrode laminated portion, as shown in FIG. It was big. Therefore, the structural defect occurrence rate was as high as 4%.
[0043]
Condition No. When the outer ceramic layer of No. 6 was formed, the shrinkage after firing of the outer ceramic layer was too small as 81% by increasing the amount of the binder resin, and the structural defect occurrence rate was significantly increased to 6%.
[0044]
That is, from the results in Table 1, the difference in temperature at which the rate of change of the shrinkage rate of the ceramic layer and the outer ceramic layer of the internal electrode laminated portion at the time of firing is maximized is set to 60 ° C. or less, more preferably 50 ° C. or less. It can be seen that the structural defect occurrence rate can be effectively reduced. Further, it can be seen that the method of controlling the molar ratio A / B and the method of adding a Mn oxide as described above are effective in reducing the temperature difference at which the rate of change of the shrinkage rate becomes maximum.
[0045]
Therefore, the condition No. As is clear from the comparison of Nos. 2 to 6, it is difficult to reduce the structural defect occurrence rate only by controlling the shrinkage onset temperature, and the temperature difference at which the rate of change of the shrinkage rate is the largest is 60 ° C or less. It can be seen that by setting the temperature to preferably 50 ° C. or less, the difference in shrinkage rate after firing can be reduced, and the occurrence rate of structural defects can be reduced.
[0046]
Condition No. In No. 4, since the Mn oxide was added in an amount of 0.1 mol% to the ceramic green sheets of the internal electrode laminated portion and in an amount of 0.2 mol% to the ceramic green sheets forming the outer ceramic layer, the rate of change in the shrinkage was the largest. Is reduced to 50 ° C., thereby reducing the structural defect occurrence rate to 0%. That is, preferably, the condition No. According to the present invention, by adding a relatively large amount of an additive such as Mn oxide, which can lower the temperature at which the rate of change of the shrinkage is maximized, to the outer ceramic layer side, the rate of change of the shrinkage is maximized according to the present invention. The temperature difference can be easily adjusted to 60 ° C or less, more preferably 50 ° C or less.
[0047]
In the above embodiment, a method of manufacturing a multilayer ceramic capacitor has been described. However, the present invention relates to an internal electrode laminated portion in which internal electrodes are laminated via ceramic layers, and an outer ceramic layer above and below the internal electrode laminated portion. Can be generally applied to a method for manufacturing a multilayer ceramic electronic component in which is disposed. That is, the present invention can be applied to a method for manufacturing various multilayer ceramic electronic components such as a multilayer substrate and a multilayer ceramic inductor.
[0048]
【The invention's effect】
In the method for manufacturing a multilayer ceramic electronic component according to the present invention, the temperature at which the rate of change of the shrinkage rate at the time of firing the outer ceramic layer is maximized and the firing at the time when the internal electrode of the ceramic layer of the internal electrode laminated portion is formed. Since the difference from the temperature at which the rate of change of the shrinkage of the ceramic becomes maximum is 60 ° C. or less, more preferably 50 ° C. or less, it is possible to effectively suppress the occurrence of structural defects after firing, and The non-defective rate of electronic components can be increased.
[0049]
In the present invention, when the molar ratio A / B in the outer ceramic layer is lower than the molar ratio A / B of the composition constituting the ceramic layer of the internal electrode laminated portion, the internal ratio during firing is thereby reduced. Easily set the difference between the temperature at which the rate of change of the shrinkage rate of the ceramic layer constituting the electrode laminated portion is the maximum and the temperature at which the rate of change of the shrinkage rate during firing of the outer ceramic layer is the maximum at 60 ° C. or less. can do.
[0050]
Further, although not particularly limited, used for the multilayer ceramic electronic component, for example, when a barium titanate-based ceramic is used, the A site is a titanium ion site, the B site is a barium ion site, and titanium ion and barium are used. By controlling the molar ratio of ions as described above, the temperature difference at which the rate of change of the shrinkage rate of the ceramic layer of the internal electrode laminated portion becomes the maximum and the temperature difference at which the rate of change of the shrinkage rate of the outer ceramic layer becomes the maximum are obtained. The temperature can be easily reduced to 60 ° C. or lower.
[0051]
Also, when the outer ceramic layer contains a larger amount of Mn oxide than the ceramic layer of the internal electrode laminated portion, the change rate of the shrinkage rate during firing of the ceramic layer of the internal electrode laminated portion is thereby maximized. The difference between the predetermined temperature and the temperature at which the rate of change of the shrinkage rate during firing of the outer ceramic layer is maximized can be easily reduced to 60 ° C. or less.
[Brief description of the drawings]
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view showing a shrinkage ratio curve and a molar ratio A / B of a ceramic green sheet of an outer ceramic layer mother in a firing step of a ceramic green sheet of a mother ceramic layer of an internal electrode laminated portion in an embodiment of the present invention. The figure which shows the shrinkage rate curve at the time of baking, the shrinkage rate curve of the ceramic green sheet of the mother for outer layer ceramic layers in which the glass component was increased, and the temperature change in a baking process.
FIG. 2 is a front sectional view for explaining an unfired ceramic laminate prepared in an example.
FIG. 3 is a front sectional view schematically showing a multilayer ceramic capacitor obtained in an example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Ceramic laminated body 2-5 ... Internal electrode 6 ... Internal electrode laminated part 6a-6c ... Ceramic layer 7, 8 ... Outer ceramic layer 9, 10 ... External electrode 11 ... Multilayer ceramic capacitor

Claims (4)

複数の内部電極がセラミック層を介して重なり合っている内部電極積層部と、内部電極積層部の上方及び下方に配置された外層セラミック層とを有し、かつ前記外層セラミック層の焼成に際しての収縮率の変化率が最大となる温度を、前記内部電極積層部のセラミック層の内部電極が形成された状態での焼成に際しての収縮率の変化率が最大となる温度との差が60℃以下となるように構成した未焼成のセラミック積層体を用意する工程と、
前記セラミック積層体を焼成し、焼結体を得る工程と、
前記焼結体の外表面に、内部電極と電気的に接続される外部電極を形成する工程とを備える、積層セラミック電子部品の製造方法。
A plurality of internal electrodes overlap each other with a ceramic layer interposed therebetween, and an external ceramic layer disposed above and below the internal electrode laminated portion, and a shrinkage ratio during firing of the external ceramic layer The difference between the temperature at which the rate of change of the maximum becomes the maximum and the temperature at which the rate of change of the shrinkage at the time of firing in the state where the internal electrodes of the ceramic layers of the internal electrode laminated portion are formed is 60 ° C. or less is at most 60 ° C. A step of preparing an unfired ceramic laminate configured as described above,
Firing the ceramic laminate to obtain a sintered body,
Forming an external electrode electrically connected to an internal electrode on the outer surface of the sintered body.
前記内部電極積層部のセラミック層及び外層セラミック層が、AサイトとBサイトとを有するセラミックスを主体とする組成物からなり、各組成物におけるAサイトイオンのモル濃度をA、Bサイトイオンのモル濃度をBとしたときに、前記内部電極積層部におけるモル比A/Bに比べて、外層セラミック層におけるモル比A/Bが低くされている、請求項1に記載の積層セラミック電子部品の製造方法。The ceramic layer and the outer ceramic layer of the internal electrode laminated portion are composed of a composition mainly composed of a ceramic having an A site and a B site, and the molar concentration of A site ions in each composition is A, 2. The production of the multilayer ceramic electronic component according to claim 1, wherein when the concentration is B, the molar ratio A / B in the outer ceramic layer is lower than the molar ratio A / B in the internal electrode laminated portion. Method. 前記内部電極積層部のセラミック層及び前記外層セラミック層を構成する前記セラミックスが、チタン酸バリウム系セラミックスからなり、前記Aサイトがチタンイオンサイトであり、前記Bサイトがバリウムイオンサイトである、請求項2に記載の積層セラミック電子部品の製造方法。The ceramics constituting the ceramic layer and the outer ceramic layer of the internal electrode laminated portion are made of a barium titanate-based ceramic, the A site is a titanium ion site, and the B site is a barium ion site. 3. The method for manufacturing a multilayer ceramic electronic component according to item 2. 前記内部電極積層部のセラミック層に比べて、前記外層セラミック層においてMn酸化物が多く含有されている、請求項1〜3のいずれかに記載の積層セラミック電子部品の製造方法。The method for manufacturing a multilayer ceramic electronic component according to any one of claims 1 to 3, wherein the outer ceramic layer contains a larger amount of Mn oxide than the ceramic layer of the internal electrode laminated portion.
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