JP2004140229A - Semiconductor device and electronic apparatus incorporated therein - Google Patents

Semiconductor device and electronic apparatus incorporated therein Download PDF

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Publication number
JP2004140229A
JP2004140229A JP2002304476A JP2002304476A JP2004140229A JP 2004140229 A JP2004140229 A JP 2004140229A JP 2002304476 A JP2002304476 A JP 2002304476A JP 2002304476 A JP2002304476 A JP 2002304476A JP 2004140229 A JP2004140229 A JP 2004140229A
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Prior art keywords
back surface
sealing body
semiconductor chip
leads
resin sealing
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JP2002304476A
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JP3920753B2 (en
Inventor
Katsuhiko Funatsu
船津　勝彦
Kazuo Shimizu
清水　一男
Takeshi Otani
大谷　健
Takamitsu Kanazawa
金澤　孝光
Hitohisa Sato
佐藤　仁久
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Renesas Technology Corp
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Renesas Technology Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for improving the packaging property of a semiconductor device. <P>SOLUTION: The semiconductor device includes: a semiconductor chip which is provided with a plurality of electrodes on its main surface; a plurality of leads which are arranged along one side of the semiconductor chip and electrically connected to the plurality of electrodes of the semiconductor chip; a resin sealing body which seals the semiconductor chip and the plurality of leads; a plurality of terminals for external connection which are provided to the plurality leads respectively and exposed on the reverse surface of the resin sealing body; a supporter which is fixed to the reverse surface of the semiconductor chip and exposed on the reverse surface of the resin sealing body; and recessed parts extending over two flanks of the resin sealing body which are recessed parts provided on the reverse surface of the resin sealing body and positioned on the mutually opposite sides in the array direction of the plurality of leads across between the plurality of terminals for external connection and the supporter. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置及びそれを組み込んだ電子装置に関し、特に、ノンリード型半導体装置及びそれを組み込んだ電子装置に適用して有効な技術に関するものである。
【０００２】
【従来の技術】
樹脂封止型半導体装置は、その製造においてリードフレームが使用される。リードフレームは、金属板を精密プレスによる打ち抜きやエッチングによって所望のパターンに加工することで製造される。リードフレームは、半導体チップ（半導体素子）を固定するための支持体（タブ、ダイパッド等）や、この支持体の周囲に先端（内端）を臨ませる複数のリードを有し、支持体はリードフレームの枠部から延在する吊りリードによって支持されている。
【０００３】
このようなリードフレームを使用して樹脂封止型半導体装置を製造する場合、リードフレームのダイパッド上に半導体チップを固定すると共に、半導体チップの電極とリードの先端とをボンディングワイヤで電気的に接続し、その後、ボンディングワイヤ、半導体チップ及びリードの内端側を絶縁性の樹脂で封止して樹脂封止体を形成し、その後、リードフレームの不要な部分を切断除去すると共に、樹脂封止体から突出するリードやタブ吊りリードを切断する。
【０００４】
一方、リードフレームを用いて製造する樹脂封止型半導体装置の一つとして、リードフレームの片面側に片面モールドを行って樹脂封止体を形成し、樹脂封止体の互いに反対側に位置する主面及び裏面のうちの裏面に外部接続用端子としてリード又はリードの一部を露出させたノンリード型半導体装置が知られている。このノンリード型半導体装置としては、例えば、樹脂封止体の裏面の互いに反対側に位置する２つの辺側に夫々リードを配置したＳＯＮ（Ｓｍａｌｌ　Ｏｕｔｌｉｎｅ　Ｎｏｎ−Ｌｅａｄｅｄ　Ｐａｃｋａｇｅ）型や、樹脂封止体の裏面の４つの辺側に夫々リードを配置したＱＦＮ（Ｑｕａｄ　Ｆｌａｔ　Ｎｏｎ−Ｌｅａｄｅｄ　Ｐａｃｋａｇｅ）型が知られている。このようなノンリード型半導体装置は、樹脂封止体の側面からリードを突出させて所定の形状に折り曲げ成形したパッケージ構造、例えばＱＦＰ（Ｑｕａｄ　Ｆｌａｔｐａｃｋ　Ｐａｃｋａｇｅ）型やＳＯＰ（Ｓｍａｌｌ　Ｏｕｔ−ｌｉｎｅ　Ｐａｃｋａｇｅ）型の半導体装置と比較して小型化を図ることができる。
【０００５】
なお、ノンリード型半導体装置については、例えば特開２００１−３５９６１号公報（特許文献１）に記載されている。また、この特許文献１には、樹脂封止体の裏面に凹部を設け、異物に起因するノンリード型半導体装置の実装不良を抑制する技術も記載されている。
【０００６】
【特許文献１】
特開２００１−３５９６１号公報
【０００７】
【発明が解決しようとする課題】
ところで、樹脂封止型半導体装置の一つに、電力増幅回路や電源回路等のスイッチング素子に使用されるパワートランジスタ（電力用半導体装置）がある。このパワートランジスタにおいても様々なパッケージ構造のものが提案され、製品化されている。例えばＴＳＳＯＰ（Ｔｈｉｎ　Ｓｈｒｉｎｋ　Ｓｍａｌｌ　Ｏｕｔ−ｌｉｎｅ　Ｐａｃｋａｇｅ）型のパワートランジスタが製品化されている。また、近年、ノンリード型のパワートランジスタも製品化されている。
【０００８】
本発明者は、配線基板にノンリード型パワートランジスタを実装する電子装置について検討した結果、以下の問題点を見出した。
【０００９】
配線基板の主面を延在する配線は、配線の保護を目的に一般的に絶縁膜で覆われている。配線を絶縁膜で覆った部分は、配線の厚さに相当する分、配線を絶縁膜で覆わない部分よりも厚みが増す。ＴＳＳＯＰ型パワートランジスタの場合、樹脂封止体の側面から突出するリードの折り曲げ成形によって、配線基板の主面と樹脂封止体の裏面との間隔、即ちスタンドオフ高さを、配線が絶縁膜で覆われた部分の厚さよりも高くすることができるため、配線基板の主面のトランジスタ実装領域に、絶縁膜で配線を覆った部分が存在していても、この部分がトランジスタの実装時の障害物となることはない。従って、ＴＳＳＯＰ型パワートランジスタの場合は、配線基板の主面と樹脂封止体の裏面との間に、絶縁膜で覆われた配線を通すことができる。
【００１０】
ノンリード型パワートランジスタの場合、樹脂封止体の裏面からリードが突出する突出量が極わずかであり、ＴＳＳＯＰ型のようにリードの曲げ成形によってスタンドオフ高さを高くすることができないため、配線基板の主面のトランジスタ実装領域に、絶縁膜で配線を覆った部分が存在した場合、この部分がトランジスタの実装時の障害物となり、配線基板の電極パッドにリードが接続されないといった実装不良が発生し易くなる。従って、ノンリード型パワートランジスタの場合は、配線基板の主面と樹脂封止体の裏面との間に絶縁膜で覆われた配線を通すことができない。
【００１１】
一方、電子機器の小型化に伴い、電子機器に組み込まれる電子装置においても小型化が要求されている。電子装置の小型化を図るためには、配線基板の平面サイズを縮小する必要がある。配線基板の平面サイズを縮小するためには、配線基板の主面の配線密度を高める必要がある。しかしながら、リードレス型パワートランジスタの場合、前述したように、配線基板の主面と樹脂封止体の裏面との間に、絶縁膜で覆われた配線を通すことができないため、配線基板の主面のトランジスタ実装領域を避けて配線を引き回す必要があり、配線基板の主面の配線密度を高めることが困難である。従って、従来のノンリード型パワートランジスタを実装する場合には電子装置の小型化が困難であった。
【００１２】
本発明の目的は、配線基板の主面と半導体装置との間に配線を通すことが可能な技術を提供することにある。
【００１３】
本発明の他の目的は、電子装置の小型化を図ることが可能な技術を提供することにある。
【００１４】
本発明の前記並びにその他の目的と新規な特徴は、本明細書の記述及び添付図面によって明らかになるであろう。
【００１５】
【課題を解決するための手段】
本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、下記のとおりである。
（１）本発明の半導体装置は、互いに反対側に位置する主面及び裏面を有し、かつ前記主面に複数の電極が設けられた半導体チップと、
前記半導体チップの一辺に沿って配置され、かつ前記半導体チップの複数の電極に夫々電気的に接続された複数のリードと、
互いに反対側に位置する主面及び裏面を有し、かつ前記半導体チップ及び前記複数のリードを封止する樹脂封止体と、
前記複数のリードに夫々設けられ、かつ前記樹脂封止体の裏面から露出された複数の外部接続用端子と、
前記半導体チップの裏面に固定され、かつ前記樹脂封止体の裏面から露出された支持体と、
前記樹脂封止体の裏面に設けられた凹部であって、前記複数の外部接続用端子と前記支持体との間を横切り、かつ前記複数のリードの配列方向において互いに反対側に位置する前記樹脂封止体の２つの側面に亘って延在する凹部とを有する。
（２）本発明の電子装置は、主面に絶縁膜で覆われた配線を有する配線基板と、前記配線基板の主面に実装された半導体装置とを有し、
前記半導体装置は、互いに反対側に位置する主面及び裏面を有し、かつ前記主面に複数の電極が設けられた半導体チップと、
前記半導体チップの一辺に沿って配置され、かつ前記半導体チップの複数の電極に夫々電気的に接続された複数のリードと、
互いに反対側に位置する主面及び裏面を有し、かつ前記半導体チップ及び前記複数のリードを封止する樹脂封止体と、
前記複数のリードに夫々設けられ、かつ前記樹脂封止体の裏面から露出された複数の外部接続用端子と、
前記半導体チップの裏面に固定され、かつ前記樹脂封止体の裏面から露出された支持体と、
前記樹脂封止体の裏面に設けられた凹部であって、前記複数の外部接続用端子と前記支持体との間を横切り、かつ前記複数のリードの配列方向において互いに反対側に位置する前記樹脂封止体の２つの側面に亘って延在する凹部とを有し、前記配線基板の配線は、前記半導体装置の凹部の下を通って前記半導体装置を横切っている。
【００１６】
【発明の実施の形態】
以下、図面を参照して本発明の実施の形態を詳細に説明する。なお、発明の実施の形態を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。
【００１７】
本実施形態では、ノンリード型パワートランジスタ（半導体装置）に本発明を適用した例について説明する。
【００１８】
図１は、本実施形態のパワートランジスタの内部構造を示す模式的平面図であり、
図２（ａ）は、図１のａ−ａ線に沿う模式的断面図、図２（ｂ）は、図１のｂ−ｂ線に沿う模式的断面図であり、
図３は、図２（ａ）の一部を拡大した模式的要部断面図であり、
図４は、図１のパワートランジスタの模式的底面図である。
【００１９】
図１及び図２に示すように、本実施形態のパワートランジスタ１は、主に、半導体チップ２、複数のリード４、板状の支持体６、及び樹脂封止体１０等を有する構成になっている。
【００２０】
半導体チップ２は、その厚さ方向と直行する平面形状が方形状で形成されている。半導体チップ２は、その厚さ方向において互いに反対側に位置する主面及び裏面を有し、主面にはソース電極３ｓ及びゲート電極３ｇを含む複数の電極３が設けられ、裏面には電極３としてドレイン電極３ｄが設けられている。半導体チップ２の主面の複数の電極３は、半導体チップ２の一辺側にその一辺に沿って配置されている。
【００２１】
半導体チップ２は、例えば、単結晶シリコンからなる半導体基板を主体に構成されている。半導体基板の主面には、トランジスタ素子として、例えば縦型構造のＭＯＳＦＥＴ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）が形成されている。この縦型構造のＭＯＳＦＥＴは、大電力を得るため、微細な複数のトランジスタセルを並列に接続した構成になっている。
【００２２】
複数のリード４は、半導体チップ２の周囲に配置され、複数の電極３が配置された半導体チップ２の主面の一辺に沿って配置されている。複数のリード４は、ボンディングワイヤ９を介して、半導体チップ２の主面の複数の電極３と夫々電気的に接続されている。
【００２３】
半導体チップ２、複数のリード４、支持体６、複数のボンディングワイヤ９等は、樹脂封止体１０によって封止されている。樹脂封止体１０は、互いに反対側に位置する主面１０ｘ及び裏面１０ｙを有し、その厚さ方向と直交する平面形状が方形状で形成されている。樹脂封止体１０は低応力化を図る目的として、例えば、フェノール系硬化剤、シリコーンゴム及びフィラー等が添加されたエポキシ系の熱硬化性樹脂で形成されている。
【００２４】
支持体６の主面は、導電性の接着材８を介在して半導体チップ２の裏面のドレイン電極３ｄに固定され、電気的にかつ機械的に接続されている。支持体６の主面と反対側の裏面は樹脂封止体１０の裏面１０ｙから露出され、この支持体６には樹脂封止体１０の裏面１０ｙから露出された外部接続用端子７が設けられている。
【００２５】
複数のリード４の夫々には、樹脂封止体１０の裏面から露出された外部接続用端子５が設けられている。複数のリード４の夫々は、図３に示すように、支持体６よりも樹脂封止体１０の主面１０ｘ側に位置する第１の部分４ａと、この第１の部分４ａから樹脂封止体１０の裏面１０ｙ側に折れ曲がる第２の部分４ｂと、樹脂封止体１０の裏面１０ｙから露出し、かつ第２の部分４ｂから樹脂封止体１０の側面１０ｚに向かって延びる第３の部分４ｃとを有する構成になっている。外部接続用端子５は、リード４の第３の部分４ｃに設けられている。
【００２６】
ボンディングワイヤ９は、一端側が半導体チップ２の電極３に接続され、他端側がリード４の第１の部分４ａに接続されている。ボンディングワイヤ９としては、例えば金（Ａｕ）ワイヤを用いている。ボンディングワイヤ９の接続方法としては、例えば、熱圧着に超音波振動を併用したボールボンディング（ネイルヘッドボンディング）法を用いている。
【００２７】
図２乃至図４に示すように、樹脂封止体１０の裏面１０ｙには、その裏面１０ｙから厚さ方向に窪む凹部１１が設けられている。凹部１１は、複数のリード４の夫々の第３の部分４ｃ（外部接続用端子５）と支持体６（外部接続用端子７）との間を横切り、かつ複数のリード４の配列方向において互いに反対側に位置する樹脂封止体１０の２つの側面１０ｚ１に亘って延在している。また、凹部１１は、複数のリード４の夫々の第１の部分４ａの下を横切っている。
【００２８】
本実施形態のパワートランジスタ１は、その製造においてリードフレームが使用される。リードフレームは、図示していないが、枠部で囲まれた領域内に複数のリード４及び支持体６等を有し、複数のリード４は枠部に支持され、支持体６は枠部から延在する吊りリードによって支持されている。リードフレームは、例えばＣｕからなる金属板又はＣｕ系の合金からなる金属板にエッチング加工又はプレス加工を施して所定のリードパターンを形成した後、複数のリード４に折り曲げ加工を施すことによって形成される。
【００２９】
樹脂封止体１０は、大量生産に好適なトランスファ・モールディング法によって形成される。トランスファ・モールディング法は、ポット、ランナー、ゲート及びキャビティ等を有する成型金型を使用し、ポットからランナー、ゲートを通してキャビティの中に樹脂を注入して樹脂封止体を形成する技術である。従って、凹部１１は、成型金型の下型にキャビティの内部において凸部を設けることによって容易に形成することができる。なお、凹部１１は、樹脂封止体１０を形成した後、樹脂封止体１０の裏面１０ｙに切削加工又はエッチング加工を施して形成してもよい。
【００３０】
図５は、図１に示すパワートランジスタを組み込んだ電子装置の模式的要部平面図であり、
図６は、図５のｃ−ｃ線に沿う模式的断面図であり、
図７は、図５の配線基板の導体パターンを示す要部模式的平面図であり、
図８は、図５の配線基板の絶縁膜に形成された開口パターンを示す模式的要部平面図である。
【００３１】
図５に示すように、電子装置２０は、配線基板２１の主面に複数のパワートランジスタ１を実装した構成になっている。複数のパワートランジスタ１は、各々のリード４が同じ方向を向くように向きを揃えた状態で一直線状に配置されている。
【００３２】
複数のパワートランジスタ１は、配線基板２１の主面に設けられた複数の実装領域に夫々実装されている。各実装領域には、図７に示すように、ドレイン用電極パッド２３ｄ、ゲート用電極パッド２３ｇ及びソース用電極パッド２３ｓを含む複数の電極パッドが配置されている。ドレイン用電極パッド２３ｄは、半導体チップ２のドレイン電極３ｄに対応して配置され、ゲート用電極パッド２３ｇは、半導体チップ２のゲート電極３ｇと電気的に接続されたリード４の第３の部分４ｃ（外部接続用端子５）に対応して配置され、ソース用電極パッド２３ｓは、半導体チップ２のソース電極３ｓと電気的に接続されたリード４の第３の部分４ｃ（外部接続用端子５）に対応して配置されている。
【００３３】
配線基板２１の主面には、ドレイン配線２２ｄ、ゲート配線２２ｇ及びソース配線２２ｓを含む配線が設けられている。これらの配線（２２ｄ，２２ｇ，２２ｓ）は、実装領域の配列方向に沿って各実装領域を横切るように連続的に延在している。ドレイン配線２２ｄは、実装領域の配列方向と直行する方向においてドレイン用電極パッド２３ｄの外側に配置され、各実装領域のドレイン用電極パッド２３ｄと電気的に接続されている。ソース配線２２ｓは、実装領域の配列方向と直行する方向においてソース用電極パッド２３ｓの外側に配置され、各実装領域のソース用電極パッド２３ｓと電気的に接続されている。ゲート配線２２ｇは、ドレイン用電極パッド２３ｄとゲート用電極パッド２３ｇ及びソース用電極パッド２３ｓとの間に配置され、各実装領域のゲート用電極２３ｇと電気的に接続されている。
【００３４】
図６及び図８に示すように、配線（２２ｄ，２２ｇ，２２ｓ）は、これらの配線を保護するために、配線基板２１の主面に設けられた絶縁膜２４で覆われている。絶縁膜２４には開口部２５ａ及び２５ｂが設けられ、開口部２５ａによって電極パッド（２３ｇ，２３ｓ）が露出され、開口部２５ｂによってドレイン用電極パッド２３ｄが露出されている。本実施形態において、開口部２５ａは電極パッド（２３ｇ，２３ｓ）毎に設けられている。また、開口部２５ａは、電極パッド（２３ｇ，２３ｓ）の縁を覆うようにして形成されている。また、開口部２５ｂは、ドレイン用電極パッド２３ｄの縁を覆うようにして形成されている。
【００３５】
図６に示すように、パワートランジスタ１の支持体６（外部接続用端子７）は、導電性の接着材２６（例えば半田）を介在して配線基板２０のドレイン用電極パッド２３ｄに固定され、電気的にかつ機械的に接続されている。半導体チップ２のソース電極３ｓと電気的に接続されたリード４の第３の部分４ｃ（外部接続用端子５）は、導電性の接着材２６を介在して配線基板２１のソース用電極パッド２３ｓに固定され、電気的にかつ機械的に接続されている。図示していないが、半導体チップ２のゲート電極３ｇと電気的に接続されたリード４の第３の部分４ｃ（外部接続用端子５）は、導電性の接着材２６を介在して配線基板２１のゲート用電極パッド２３ｇに固定され、電気的にかつ機械的に接続されている。
【００３６】
図６に示すように、ゲート配線２２ｇは、絶縁膜２４で覆われている。絶縁膜２４でゲート配線２２ｇを覆った部分は、配線の厚さに相当する分、配線を絶縁膜で覆わない部分よりも厚みが増しているが、絶縁膜２４で覆われたゲート配線２２ｇは、パワートランジスタ１の樹脂封止体１０の裏面１０ｙに設けられた凹部１１の下を通って各パワートランジスタ１を横切っている。
【００３７】
このように、樹脂封止体１０の裏面１０ｙに、複数のリード４の夫々の第３の部分４ｃ（外部接続用端子５）と支持体６（外部接続用端子７）との間を横切り、かつ複数のリード４の配列方向において互いに反対側に位置する樹脂封止体１０の２つの側面１０ｚ１に亘って延在する凹部１１を設けることにより、ノンリード型パワートランジスタ１においても、配線基板２１の主面と樹脂封止体１０の裏面１０ｙとの間に、絶縁膜２４で覆われたゲート配線２２ｇを通すことができる。凹部１１の深さは、ゲート配線２２ｇを絶縁膜２４で覆った部分の高さに応じて設定する。
【００３８】
また、配線基板２１とノンリード型パワートランジスタ１との間にゲート配線２２ｇを通すことができるので、配線基板２１の主面の配線密度を高めることができる。この結果、配線基板２１の平面サイズを縮小することができるので、ノンリード型パワートランジスタ１を実装する電子装置２０の小型化を図ることができる。
【００３９】
複数のリード４は、支持体６よりも樹脂封止体１０の主面側に位置する第１の部分４ａと、第１の部分４ａから樹脂封止体１０の裏面側に折れ曲がる第２の部分４ｂと、樹脂封止体１０の裏面から露出し、かつ第２の部分４ｂから樹脂封止体１０の側面に向かって延びる第３の部分４ｃとを有し、凹部１１は、複数のリード４の夫々の第１の部分４ａの下を横切っている。このような構成にすることにより、パワートランジスタ１の平面サイズを大型化することなく、配線基板２１の主面と樹脂封止体１０の裏面１０ｙとの間に、絶縁膜２４で覆われたゲート配線２２ｇを通すことができる。
【００４０】
ボンディングワイヤ９は、一端側が半導体チップの電極３に接続され、他端側がリード４の第１の部分４ａに接続されている。このような構成にすることにより、ボンディングワイヤ９の長さを短くすることができるため、パワートランジスタ１の低オン抵抗化を図ることができる。
【００４１】
また、ボンディングワイヤ９のループ高さを低くすることができるため、パワートランジスタ１の薄型化を図ることができる。
【００４２】
パワートランジスタ１は、低オン抵抗化及び低熱抵抗化を図るため、半導体チップ２のドレイン電極３ｄが接続された支持体６を樹脂封止体１０の裏面１０ｙから露出させ、実装時において配線基板２１のドレイン用電極パッド２３ｄに支持体６を接続させる構造になっている。パワートランジスタ１の低オン抵抗化及び低熱抵抗化を図るためには、できるだけ支持体６とドレイン用電極パッド２３ｄとの接合面を大きくすることが望ましい。従って、このようなパッケージ構造の場合、配線基板２１の主面とパワートランジスタ１との間に、絶縁膜２４で覆われたゲート配線２２ｇを通すためのスペースが小さくなる。
【００４３】
しかしながら、本実施形態のように、リード４を、第１部分４ａ、第２の部分４ｂ及び第３の部分４ｃを有するリード形状にし、リード４の第３の部分４ｃの下を横切るように凹部１１を設けることにより、パワートランジスタ１の平面サイズを大型化することなく、配線基板２１の主面と樹脂封止体１０の裏面１０ｙとの間に、絶縁膜２４で覆われたゲート配線２２ｇを通すことができる。
【００４４】
なお、本実施形態では、配線基板２１の主面とパワートランジスタ１との間に、絶縁膜２４で覆われたゲート配線２２ｇを通す例について説明したが、ゲート配線２２ｇに代えてソース配線２２ｓ又はドレイン配線２２ｄを通してもよい。但し、ソース配線２２ｓを通す場合、電位差が大きいドレイン用電極パッド２３ｄとソース配線２２ｓとの距離が近づくため、両者間の絶縁耐圧を十分考慮して配置する必要がある。
【００４５】
また、本施形態では、電極パッドの縁を覆うように開口部（２５ａ，２５ｂ）を形成した例について説明したが、開口部は、図９（図５の配線基板の絶縁膜に形成された開口パターンの第１の変形例を示す要部模式的平面図）に示すように、開口端が電極パッド（２３ｄ，２３ｇ，２３ｓ）の外側に位置するように形成してもよい。
【００４６】
また、開口部２５ａは、図１０（図５の配線基板の絶縁膜に形成された開口パターンの第２の変形例を示す要部模式的平面図）に示すように、複数の電極パッド（２３ｓ，２３ｇ）を露出するように形成してもよい。
【００４７】
以上、本発明者によってなされた発明を、前記実施の形態に基づき具体的に説明したが、本発明は、前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは勿論である。
【００４８】
例えば、本発明は、主面にドレイン電極及びゲート電極が設けられ、裏面にソース電極が設けられた半導体チップを有するパワートランジスタ、及びそれを組み込んだ電子装置に適用できる。
【００４９】
また、本発明は、トランジスタ素子としてバイポーラトランジスタが内蔵された半導体チップを有するパワートランジスタ、及びそれを組み込んだ電子装置に適用できる。
【００５０】
また、本発明は、トランジスタ素子としてＩＧＢＴが内蔵された半導体チップを有するパワートランジスタ、及びそれを組み込んだ電子装置に適用できる。
【００５１】
【発明の効果】
本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記のとおりである。
【００５２】
本発明によれば、配線基板の主面と半導体装置との間に配線を通すことができる。
【００５３】
本発明によれば、電子装置の小型化を図ることができる。
【図面の簡単な説明】
【図１】本発明の一実施形態である半導体装置の内部構造を示す模式的平面図である。
【図２】（ａ）は図１のａ−ａ線に沿う模式的断面図であり、（ｂ）は図１のｂ−ｂ線に沿う模式的断面図である。
【図３】図２（ａ）の一部を拡大した模式的要部断面図である。
【図４】図１に示す半導体装置の模式的底面図である。
【図５】図１に示す半導体装置を組み込んだ電子装置の模式的要部平面図である。
【図６】図５のｃ−ｃ線に沿う模式的断面図である。
【図７】図５の配線基板の導体パターンを示す要部模式的平面図である。
【図８】図５の配線基板の保護膜に形成された開口パターンを示す要部模式的平面図である。
【図９】図５の配線基板の絶縁膜に形成された開口パターンの第１の変形例を示す要部模式的平面図である。
【図１０】図５の配線基板の絶縁膜に形成された開口パターンの第２の変形例を示す要部模式的平面図である。
【符号の説明】
１…パワートランジスタ（半導体装置）、２…半導体チップ、３…電極、３ｓ…ソース電極、３ｇ…ゲート電極、３ｄ…ドレイン電極、４…リード、５…外部接続用端子、６…支持体、７…外部接続用端子、８…接着材、９…ボンディングワイヤ、１０…樹脂封止体、１１…凹部、２０…電子装置、２１…配線基板、２２ｄ…ドレイン配線、２２ｇ…ゲート配線、２２ｓ…ソース配線、２３ｄ…ドレイン用電極パッド、２３ｇ…ゲート用電極パッド、２４…絶縁膜、２５ａ，２５ｂ…開口部。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and an electronic device incorporating the semiconductor device, and more particularly to a technology effective when applied to a non-lead type semiconductor device and an electronic device incorporating the semiconductor device.
[0002]
[Prior art]
A resin-encapsulated semiconductor device uses a lead frame in its manufacture. The lead frame is manufactured by processing a metal plate into a desired pattern by punching or etching with a precision press. The lead frame has a support (tab, die pad, etc.) for fixing a semiconductor chip (semiconductor element) and a plurality of leads that face the tip (inner end) around the support, and the support is a lead. It is supported by a suspension lead extending from the frame portion of the frame.
[0003]
When manufacturing a resin-encapsulated semiconductor device using such a lead frame, the semiconductor chip is fixed on the die pad of the lead frame, and the electrode of the semiconductor chip and the tip of the lead are electrically connected by a bonding wire. Thereafter, the inner ends of the bonding wires, the semiconductor chip and the leads are sealed with an insulating resin to form a resin sealing body, and then unnecessary portions of the lead frame are cut and removed, and the resin sealing is performed. Cut leads and tab suspension leads protruding from the body.
[0004]
On the other hand, as one of the resin-encapsulated semiconductor devices manufactured using a lead frame, a single-side mold is performed on one side of the lead frame to form a resin encapsulant, and the resin encapsulant is positioned on the opposite side of the resin encapsulant. A non-lead type semiconductor device is known in which a lead or a part of a lead is exposed as an external connection terminal on the back surface of the main surface and the back surface. As this non-lead type semiconductor device, for example, a SON (Small Outline Non-Leaded Package) type in which leads are arranged on two sides opposite to each other on the back side of the resin sealing body, or a resin sealing body is used. A QFN (Quad Flat Non-Leaded Package) type in which leads are arranged on the four sides of the back surface is known. Such a non-lead type semiconductor device has a package structure in which a lead protrudes from a side surface of a resin sealing body and is bent into a predetermined shape, such as a QFP (Quad Flat Pack Package) type or an SOP (Small Out-line Package) type. The size can be reduced as compared with a semiconductor device.
[0005]
The non-lead type semiconductor device is described in, for example, Japanese Patent Laid-Open No. 2001-35961 (Patent Document 1). Further, this Patent Document 1 also describes a technique of providing a recess on the back surface of the resin sealing body to suppress a mounting failure of a non-lead type semiconductor device due to foreign matter.
[0006]
[Patent Document 1]
Japanese Patent Laid-Open No. 2001-35961
[Problems to be solved by the invention]
By the way, one of the resin-encapsulated semiconductor devices is a power transistor (power semiconductor device) used for a switching element such as a power amplifier circuit or a power supply circuit. Various types of power transistors have been proposed and commercialized. For example, a power transistor of a TSSOP (Thin Shrink Small Out-line Package) type has been commercialized. In recent years, non-lead type power transistors have also been commercialized.
[0008]
As a result of studying an electronic device in which a non-lead type power transistor is mounted on a wiring board, the present inventor has found the following problems.
[0009]
A wiring extending on the main surface of the wiring board is generally covered with an insulating film for the purpose of protecting the wiring. The portion where the wiring is covered with the insulating film is thicker than the portion where the wiring is not covered with the insulating film by an amount corresponding to the thickness of the wiring. In the case of a TSSOP type power transistor, the distance between the main surface of the wiring board and the back surface of the resin sealing body, that is, the stand-off height is determined by bending the lead protruding from the side surface of the resin sealing body. Since the thickness of the covered part can be higher than that of the covered part, even if there is a part where the wiring is covered with an insulating film in the transistor mounting area on the main surface of the wiring board, this part is a failure during transistor mounting. It will not be a thing. Therefore, in the case of the TSSOP type power transistor, the wiring covered with the insulating film can be passed between the main surface of the wiring substrate and the back surface of the resin sealing body.
[0010]
In the case of a non-lead type power transistor, the amount of protrusion from which the lead protrudes from the back surface of the resin encapsulant is very small, and the standoff height cannot be increased by bending the lead as in the TSSOP type. If there is a part where the wiring is covered with an insulating film in the transistor mounting area on the main surface of this, this part becomes an obstacle when mounting the transistor, and mounting defects such as leads not being connected to the electrode pads on the wiring board occur. It becomes easy. Therefore, in the case of the non-lead type power transistor, the wiring covered with the insulating film cannot be passed between the main surface of the wiring substrate and the back surface of the resin sealing body.
[0011]
On the other hand, along with the downsizing of electronic devices, downsizing is also required in electronic devices incorporated in electronic devices. In order to reduce the size of the electronic device, it is necessary to reduce the planar size of the wiring board. In order to reduce the planar size of the wiring board, it is necessary to increase the wiring density of the main surface of the wiring board. However, in the case of a leadless type power transistor, as described above, the wiring covered with the insulating film cannot be passed between the main surface of the wiring substrate and the back surface of the resin sealing body. It is necessary to route the wiring while avoiding the transistor mounting region on the surface, and it is difficult to increase the wiring density on the main surface of the wiring substrate. Therefore, it is difficult to reduce the size of the electronic device when a conventional non-lead type power transistor is mounted.
[0012]
An object of the present invention is to provide a technique capable of passing wiring between a main surface of a wiring board and a semiconductor device.
[0013]
Another object of the present invention is to provide a technique capable of downsizing an electronic device.
[0014]
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
[0015]
[Means for Solving the Problems]
Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
(1) A semiconductor device of the present invention includes a semiconductor chip having a main surface and a back surface located on opposite sides, and a plurality of electrodes provided on the main surface;
A plurality of leads arranged along one side of the semiconductor chip and electrically connected to a plurality of electrodes of the semiconductor chip, and
A resin sealing body having a main surface and a back surface located on opposite sides, and sealing the semiconductor chip and the plurality of leads;
A plurality of external connection terminals respectively provided on the plurality of leads and exposed from the back surface of the resin sealing body;
A support body fixed to the back surface of the semiconductor chip and exposed from the back surface of the resin-encapsulated body;
The resin, which is a recess provided on the back surface of the resin sealing body, which crosses between the plurality of external connection terminals and the support and is located on the opposite side in the arrangement direction of the plurality of leads. And a recess extending over two side surfaces of the sealing body.
(2) The electronic device of the present invention has a wiring board having wiring covered with an insulating film on the main surface, and a semiconductor device mounted on the main surface of the wiring board,
The semiconductor device has a main surface and a back surface located on opposite sides, and a semiconductor chip provided with a plurality of electrodes on the main surface;
A plurality of leads arranged along one side of the semiconductor chip and electrically connected to a plurality of electrodes of the semiconductor chip, and
A resin sealing body having a main surface and a back surface located on opposite sides, and sealing the semiconductor chip and the plurality of leads;
A plurality of external connection terminals respectively provided on the plurality of leads and exposed from the back surface of the resin sealing body;
A support body fixed to the back surface of the semiconductor chip and exposed from the back surface of the resin-encapsulated body;
The resin, which is a recess provided on the back surface of the resin sealing body, which crosses between the plurality of external connection terminals and the support and is located on the opposite side in the arrangement direction of the plurality of leads. A recess extending over two side surfaces of the sealing body, and the wiring of the wiring board passes under the recess of the semiconductor device and crosses the semiconductor device.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment of the invention, and the repetitive description thereof is omitted.
[0017]
In the present embodiment, an example in which the present invention is applied to a non-read type power transistor (semiconductor device) will be described.
[0018]
FIG. 1 is a schematic plan view showing the internal structure of the power transistor of this embodiment.
2A is a schematic cross-sectional view taken along the line aa in FIG. 1, and FIG. 2B is a schematic cross-sectional view taken along the line bb in FIG.
FIG. 3 is a schematic cross-sectional view of an essential part in which a part of FIG.
FIG. 4 is a schematic bottom view of the power transistor of FIG.
[0019]
As shown in FIGS. 1 and 2, the power transistor 1 according to the present embodiment mainly includes a semiconductor chip 2, a plurality of leads 4, a plate-like support 6, a resin sealing body 10, and the like. ing.
[0020]
The semiconductor chip 2 is formed in a square shape in a plane shape perpendicular to the thickness direction. The semiconductor chip 2 has a main surface and a back surface that are opposite to each other in the thickness direction, and a plurality of electrodes 3 including a source electrode 3s and a gate electrode 3g are provided on the main surface, and an electrode 3 is provided on the back surface. A drain electrode 3d is provided. The plurality of electrodes 3 on the main surface of the semiconductor chip 2 are arranged on one side of the semiconductor chip 2 along the one side.
[0021]
The semiconductor chip 2 is mainly composed of, for example, a semiconductor substrate made of single crystal silicon. On the main surface of the semiconductor substrate, as a transistor element, for example, a vertical oxide MOSFET (Metal Oxide Field Effect Transistor) is formed. This vertical MOSFET has a structure in which a plurality of fine transistor cells are connected in parallel in order to obtain high power.
[0022]
The plurality of leads 4 are arranged around the semiconductor chip 2 and arranged along one side of the main surface of the semiconductor chip 2 on which the plurality of electrodes 3 are arranged. The plurality of leads 4 are electrically connected to the plurality of electrodes 3 on the main surface of the semiconductor chip 2 via bonding wires 9.
[0023]
The semiconductor chip 2, the plurality of leads 4, the support 6, the plurality of bonding wires 9, and the like are sealed with a resin sealing body 10. The resin sealing body 10 has a main surface 10x and a back surface 10y located on opposite sides, and a planar shape orthogonal to the thickness direction is formed in a square shape. For the purpose of reducing the stress, the resin sealing body 10 is formed of, for example, an epoxy thermosetting resin to which a phenolic curing agent, silicone rubber, filler, and the like are added.
[0024]
The main surface of the support 6 is fixed to the drain electrode 3d on the back surface of the semiconductor chip 2 via a conductive adhesive 8, and is electrically and mechanically connected. The back surface opposite to the main surface of the support body 6 is exposed from the back surface 10y of the resin sealing body 10, and the support body 6 is provided with an external connection terminal 7 exposed from the back surface 10y of the resin sealing body 10. ing.
[0025]
Each of the plurality of leads 4 is provided with an external connection terminal 5 exposed from the back surface of the resin sealing body 10. As shown in FIG. 3, each of the plurality of leads 4 includes a first portion 4 a located on the main surface 10 x side of the resin sealing body 10 with respect to the support body 6, and resin sealing from the first portion 4 a. A second portion 4b that bends to the back surface 10y side of the body 10, and a third portion that is exposed from the back surface 10y of the resin sealing body 10 and extends from the second portion 4b toward the side surface 10z of the resin sealing body 10. 4c. The external connection terminal 5 is provided in the third portion 4 c of the lead 4.
[0026]
The bonding wire 9 has one end connected to the electrode 3 of the semiconductor chip 2 and the other end connected to the first portion 4 a of the lead 4. For example, a gold (Au) wire is used as the bonding wire 9. As a method for connecting the bonding wires 9, for example, a ball bonding (nail head bonding) method using ultrasonic vibration in combination with thermocompression bonding is used.
[0027]
As shown in FIGS. 2 to 4, the back surface 10 y of the resin sealing body 10 is provided with a recess 11 that is recessed from the back surface 10 y in the thickness direction. The recess 11 crosses between the third portion 4c (external connection terminal 5) and the support 6 (external connection terminal 7) of each of the plurality of leads 4, and is mutually in the arrangement direction of the plurality of leads 4. It extends over the two side surfaces 10z1 of the resin sealing body 10 located on the opposite side. Further, the recess 11 crosses under the first portion 4 a of each of the plurality of leads 4.
[0028]
The power transistor 1 of this embodiment uses a lead frame in its manufacture. Although not shown, the lead frame has a plurality of leads 4 and a support 6 in a region surrounded by the frame, the plurality of leads 4 are supported by the frame, and the support 6 is separated from the frame. It is supported by extending suspension leads. The lead frame is formed by, for example, forming a predetermined lead pattern by etching or pressing a metal plate made of Cu or a metal plate made of a Cu-based alloy, and then bending the plurality of leads 4. The
[0029]
The resin sealing body 10 is formed by a transfer molding method suitable for mass production. The transfer molding method is a technique in which a molding die having a pot, a runner, a gate, a cavity, and the like is used, and a resin is injected from the pot into the cavity through the runner and the gate to form a resin sealing body. Therefore, the concave portion 11 can be easily formed by providing a convex portion in the cavity of the lower mold. In addition, after forming the resin sealing body 10, you may form the recessed part 11 by giving a cutting process or an etching process to the back surface 10y of the resin sealing body 10. FIG.
[0030]
FIG. 5 is a schematic plan view of an essential part of an electronic device incorporating the power transistor shown in FIG.
6 is a schematic cross-sectional view taken along the line cc of FIG.
FIG. 7 is a schematic plan view of an essential part showing a conductor pattern of the wiring board of FIG.
FIG. 8 is a schematic plan view of an essential part showing an opening pattern formed in the insulating film of the wiring board of FIG.
[0031]
As shown in FIG. 5, the electronic device 20 has a configuration in which a plurality of power transistors 1 are mounted on the main surface of a wiring board 21. The plurality of power transistors 1 are arranged in a straight line with their leads 4 oriented in the same direction.
[0032]
The plurality of power transistors 1 are respectively mounted on a plurality of mounting regions provided on the main surface of the wiring board 21. As shown in FIG. 7, a plurality of electrode pads including a drain electrode pad 23d, a gate electrode pad 23g, and a source electrode pad 23s are arranged in each mounting region. The drain electrode pad 23d is arranged corresponding to the drain electrode 3d of the semiconductor chip 2, and the gate electrode pad 23g is the third portion 4c of the lead 4 electrically connected to the gate electrode 3g of the semiconductor chip 2. The source electrode pad 23 s is arranged corresponding to (external connection terminal 5), and the third portion 4 c of the lead 4 electrically connected to the source electrode 3 s of the semiconductor chip 2 (external connection terminal 5). It is arranged corresponding to.
[0033]
On the main surface of the wiring substrate 21, wiring including a drain wiring 22d, a gate wiring 22g, and a source wiring 22s is provided. These wirings (22d, 22g, 22s) continuously extend so as to cross each mounting region along the arrangement direction of the mounting regions. The drain wiring 22d is disposed outside the drain electrode pad 23d in a direction orthogonal to the mounting region arrangement direction, and is electrically connected to the drain electrode pad 23d in each mounting region. The source wiring 22s is arranged outside the source electrode pad 23s in a direction perpendicular to the arrangement direction of the mounting region, and is electrically connected to the source electrode pad 23s in each mounting region. The gate wiring 22g is disposed between the drain electrode pad 23d, the gate electrode pad 23g, and the source electrode pad 23s, and is electrically connected to the gate electrode 23g in each mounting region.
[0034]
As shown in FIGS. 6 and 8, the wirings (22d, 22g, 22s) are covered with an insulating film 24 provided on the main surface of the wiring substrate 21 in order to protect these wirings. Openings 25a and 25b are provided in the insulating film 24, the electrode pads (23g, 23s) are exposed through the openings 25a, and the drain electrode pad 23d is exposed through the openings 25b. In the present embodiment, the opening 25a is provided for each electrode pad (23g, 23s). The opening 25a is formed so as to cover the edges of the electrode pads (23g, 23s). The opening 25b is formed so as to cover the edge of the drain electrode pad 23d.
[0035]
As shown in FIG. 6, the support 6 (external connection terminal 7) of the power transistor 1 is fixed to the drain electrode pad 23d of the wiring substrate 20 with a conductive adhesive 26 (for example, solder) interposed therebetween, Electrically and mechanically connected. The third portion 4c (external connection terminal 5) of the lead 4 electrically connected to the source electrode 3s of the semiconductor chip 2 is connected to the source electrode pad 23s of the wiring substrate 21 with a conductive adhesive 26 interposed therebetween. Fixed and electrically and mechanically connected. Although not shown, the third portion 4c (external connection terminal 5) of the lead 4 electrically connected to the gate electrode 3g of the semiconductor chip 2 is connected to the wiring substrate 21 with a conductive adhesive 26 interposed therebetween. The gate electrode pad 23g is fixed and electrically and mechanically connected.
[0036]
As shown in FIG. 6, the gate wiring 22 g is covered with an insulating film 24. The portion of the gate wiring 22g covered with the insulating film 24 is thicker than the portion where the wiring is not covered with the insulating film by an amount corresponding to the thickness of the wiring, but the gate wiring 22g covered with the insulating film 24 is The power transistors 1 are traversed under the recesses 11 provided on the back surface 10 y of the resin sealing body 10 of the power transistors 1.
[0037]
In this manner, the back surface 10y of the resin sealing body 10 crosses between the third portion 4c (external connection terminal 5) and the support 6 (external connection terminal 7) of each of the leads 4, Further, by providing the recess 11 extending over the two side surfaces 10z1 of the resin sealing body 10 located on the opposite sides in the arrangement direction of the plurality of leads 4, the non-lead type power transistor 1 also has the wiring substrate 21. Between the main surface and the back surface 10y of the resin sealing body 10, the gate wiring 22g covered with the insulating film 24 can be passed. The depth of the recess 11 is set according to the height of the portion where the gate wiring 22g is covered with the insulating film 24.
[0038]
Further, since the gate wiring 22g can be passed between the wiring substrate 21 and the non-read type power transistor 1, the wiring density of the main surface of the wiring substrate 21 can be increased. As a result, since the planar size of the wiring substrate 21 can be reduced, the electronic device 20 on which the non-lead type power transistor 1 is mounted can be downsized.
[0039]
The plurality of leads 4 includes a first portion 4a located on the main surface side of the resin sealing body 10 with respect to the support body 6, and a second portion bent from the first portion 4a to the back surface side of the resin sealing body 10. 4 b and a third portion 4 c that is exposed from the back surface of the resin sealing body 10 and extends from the second portion 4 b toward the side surface of the resin sealing body 10, and the recess 11 includes the plurality of leads 4. Across the first part 4a. With such a configuration, the gate covered with the insulating film 24 between the main surface of the wiring substrate 21 and the back surface 10y of the resin sealing body 10 without increasing the planar size of the power transistor 1. Wiring 22g can be passed.
[0040]
The bonding wire 9 has one end connected to the electrode 3 of the semiconductor chip and the other end connected to the first portion 4 a of the lead 4. With such a configuration, the length of the bonding wire 9 can be shortened, so that the on-resistance of the power transistor 1 can be reduced.
[0041]
In addition, since the loop height of the bonding wire 9 can be reduced, the power transistor 1 can be thinned.
[0042]
In order to reduce the on-resistance and the thermal resistance, the power transistor 1 exposes the support 6 to which the drain electrode 3d of the semiconductor chip 2 is connected from the back surface 10y of the resin sealing body 10, and at the time of mounting, the wiring substrate 21 The support 6 is connected to the drain electrode pad 23d. In order to reduce the on-resistance and the thermal resistance of the power transistor 1, it is desirable to enlarge the bonding surface between the support 6 and the drain electrode pad 23d as much as possible. Therefore, in the case of such a package structure, a space for passing the gate wiring 22g covered with the insulating film 24 between the main surface of the wiring substrate 21 and the power transistor 1 is reduced.
[0043]
However, as in the present embodiment, the lead 4 is formed into a lead shape having a first portion 4a, a second portion 4b, and a third portion 4c, and is recessed so as to cross under the third portion 4c of the lead 4. 11, the gate wiring 22g covered with the insulating film 24 is provided between the main surface of the wiring substrate 21 and the back surface 10y of the resin sealing body 10 without increasing the planar size of the power transistor 1. Can pass through.
[0044]
In the present embodiment, the example in which the gate wiring 22g covered with the insulating film 24 is passed between the main surface of the wiring substrate 21 and the power transistor 1, but the source wiring 22s or the gate wiring 22g is used instead of the gate wiring 22g. The drain wiring 22d may be passed through. However, when the source wiring 22s is passed, the distance between the drain electrode pad 23d having a large potential difference and the source wiring 22s becomes closer, and therefore, it is necessary to sufficiently dispose the wiring between the two.
[0045]
In the present embodiment, the example in which the openings (25a, 25b) are formed so as to cover the edges of the electrode pads has been described. However, the openings are formed in the insulating film of the wiring board in FIG. As shown in a schematic plan view of a main part showing a first modification of the opening pattern, the opening end may be formed outside the electrode pads (23d, 23g, 23s).
[0046]
Further, the opening 25a includes a plurality of electrode pads (23s) as shown in FIG. 10 (main part schematic plan view showing a second modification of the opening pattern formed in the insulating film of the wiring board of FIG. 5). , 23g) may be exposed.
[0047]
Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.
[0048]
For example, the present invention can be applied to a power transistor having a semiconductor chip in which a drain electrode and a gate electrode are provided on the main surface and a source electrode is provided on the back surface, and an electronic device incorporating the power transistor.
[0049]
Further, the present invention can be applied to a power transistor having a semiconductor chip in which a bipolar transistor is incorporated as a transistor element, and an electronic device incorporating the power transistor.
[0050]
Further, the present invention can be applied to a power transistor having a semiconductor chip in which an IGBT is incorporated as a transistor element, and an electronic device incorporating the power transistor.
[0051]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0052]
According to the present invention, wiring can be passed between the main surface of the wiring board and the semiconductor device.
[0053]
According to the present invention, the electronic device can be reduced in size.
[Brief description of the drawings]
FIG. 1 is a schematic plan view showing an internal structure of a semiconductor device according to an embodiment of the present invention.
2A is a schematic cross-sectional view taken along the line aa in FIG. 1, and FIG. 2B is a schematic cross-sectional view taken along the line bb in FIG. 1;
FIG. 3 is a schematic cross-sectional view of an essential part in which a part of FIG. 2 (a) is enlarged.
4 is a schematic bottom view of the semiconductor device shown in FIG. 1. FIG.
FIG. 5 is a schematic plan view of an essential part of an electronic device incorporating the semiconductor device shown in FIG. 1;
6 is a schematic cross-sectional view taken along the line cc of FIG.
7 is a schematic plan view of an essential part showing a conductor pattern of the wiring board of FIG. 5; FIG.
8 is a schematic plan view of a main part showing an opening pattern formed in a protective film of the wiring board shown in FIG. 5;
9 is a schematic plan view of an essential part showing a first modification of an opening pattern formed in an insulating film of the wiring board of FIG. 5; FIG.
10 is a schematic plan view of an essential part showing a second modification of the opening pattern formed in the insulating film of the wiring board of FIG. 5; FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Power transistor (semiconductor device), 2 ... Semiconductor chip, 3 ... Electrode, 3s ... Source electrode, 3g ... Gate electrode, 3d ... Drain electrode, 4 ... Lead, 5 ... External connection terminal, 6 ... Support, 7 DESCRIPTION OF SYMBOLS ... External connection terminal, 8 ... Adhesive material, 9 ... Bonding wire, 10 ... Resin sealing body, 11 ... Recessed part, 20 ... Electronic device, 21 ... Wiring board, 22d ... Drain wiring, 22g ... Gate wiring, 22s ... Source Wiring, 23d ... drain electrode pad, 23g ... gate electrode pad, 24 ... insulating film, 25a, 25b ... opening.

Claims (5)

互いに反対側に位置する主面及び裏面を有し、かつ前記主面に複数の電極が設けられた半導体チップと、
前記半導体チップの一辺に沿って配置され、かつ前記半導体チップの複数の電極に夫々電気的に接続された複数のリードと、
互いに反対側に位置する主面及び裏面を有し、かつ前記半導体チップ及び前記複数のリードを封止する樹脂封止体と、
前記複数のリードに夫々設けられ、かつ前記樹脂封止体の裏面から露出された複数の外部接続用端子と、
前記半導体チップの裏面に固定され、かつ前記樹脂封止体の裏面から露出された支持体と、
前記樹脂封止体の裏面に設けられた凹部であって、前記複数の外部接続用端子と前記支持体との間を横切り、かつ前記複数のリードの配列方向において互いに反対側に位置する前記樹脂封止体の２つの側面に亘って延在する凹部とを有することを特徴とする半導体装置。A semiconductor chip having a main surface and a back surface located on opposite sides, and a plurality of electrodes provided on the main surface;
A plurality of leads arranged along one side of the semiconductor chip and electrically connected to a plurality of electrodes of the semiconductor chip, and
A resin sealing body having a main surface and a back surface located on opposite sides, and sealing the semiconductor chip and the plurality of leads;
A plurality of external connection terminals respectively provided on the plurality of leads and exposed from the back surface of the resin sealing body;
A support body fixed to the back surface of the semiconductor chip and exposed from the back surface of the resin-encapsulated body;
The resin, which is a recess provided on the back surface of the resin sealing body, which crosses between the plurality of external connection terminals and the support and is located on the opposite side in the arrangement direction of the plurality of leads. A semiconductor device comprising: a recess extending over two side surfaces of the sealing body. 請求項１に記載の半導体装置において、
前記複数のリードは、前記支持体よりも前記樹脂封止体の主面側に位置する第１の部分と、前記第１の部分から前記樹脂封止体の裏面側に折れ曲がる第２の部分と、前記樹脂封止体の裏面から露出し、かつ前記第２の部分から前記樹脂封止体の側面に向かって延びる第３の部分とを有し、
前記凹部は、前記複数のリードの夫々の第１の部分の下を横切っていることを特徴とする半導体装置。The semiconductor device according to claim 1,
The plurality of leads include a first portion located on the main surface side of the resin sealing body with respect to the support, and a second portion bent from the first portion to the back surface side of the resin sealing body. And a third portion exposed from the back surface of the resin sealing body and extending from the second portion toward the side surface of the resin sealing body,
The semiconductor device according to claim 1, wherein the concave portion crosses under a first portion of each of the plurality of leads. 請求項１に記載の半導体装置において、
複数の電極は、ソース電極及びゲート電極を含み、
前記半導体チップは、その裏面にドレイン電極を更に有することを特徴とする半導体装置。The semiconductor device according to claim 1,
The plurality of electrodes includes a source electrode and a gate electrode,
The semiconductor device further comprises a drain electrode on the back surface thereof. 請求項１に記載の半導体装置において、
前記半導体チップの複数の電極は、ボンディングワイヤを介して前記複数のリードと夫々電気的に接続されていることを特徴とする半導体装置。The semiconductor device according to claim 1,
The plurality of electrodes of the semiconductor chip are electrically connected to the plurality of leads, respectively, through bonding wires. 主面に絶縁膜で覆われた配線を有する配線基板と、前記配線基板の主面に実装された半導体装置とを有する電子装置であって、
前記半導体装置は、互いに反対側に位置する主面及び裏面を有し、かつ前記主面に複数の電極が設けられた半導体チップと、
前記半導体チップの一辺に沿って配置され、かつ前記半導体チップの複数の電極に夫々電気的に接続された複数のリードと、
互いに反対側に位置する主面及び裏面を有し、かつ前記半導体チップ及び前記複数のリードを封止する樹脂封止体と、
前記複数のリードに夫々設けられ、かつ前記樹脂封止体の裏面から露出された複数の外部接続用端子と、
前記半導体チップの裏面に固定され、かつ前記樹脂封止体の裏面から露出された支持体と、
前記樹脂封止体の裏面に設けられた凹部であって、前記複数の外部接続用端子と前記支持体との間を横切り、かつ前記複数のリードの配列方向において互いに反対側に位置する前記樹脂封止体の２つの側面に亘って延在する凹部とを有し、前記配線基板の配線は、前記半導体装置の凹部の下を通って前記半導体装置を横切っていることを特徴とする電子装置。An electronic device having a wiring board having wiring covered with an insulating film on a main surface, and a semiconductor device mounted on the main surface of the wiring board,
The semiconductor device has a main surface and a back surface located on opposite sides, and a semiconductor chip provided with a plurality of electrodes on the main surface;
A plurality of leads arranged along one side of the semiconductor chip and electrically connected to a plurality of electrodes of the semiconductor chip, and
A resin sealing body having a main surface and a back surface located on opposite sides, and sealing the semiconductor chip and the plurality of leads;
A plurality of external connection terminals respectively provided on the plurality of leads and exposed from the back surface of the resin sealing body;
A support body fixed to the back surface of the semiconductor chip and exposed from the back surface of the resin-encapsulated body;
The resin, which is a recess provided on the back surface of the resin sealing body, which crosses between the plurality of external connection terminals and the support and is located on the opposite side in the arrangement direction of the plurality of leads. An electronic device having a recess extending over two side surfaces of the sealing body, wherein the wiring of the wiring board passes under the recess of the semiconductor device and crosses the semiconductor device .
JP2002304476A 2002-10-18 2002-10-18 Semiconductor device and electronic device incorporating the same Expired - Fee Related JP3920753B2 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006203048A (en) * 2005-01-21 2006-08-03 Matsushita Electric Ind Co Ltd Semiconductor chip
WO2012137333A1 (en) * 2011-04-07 2012-10-11 三菱電機株式会社 Molded module and electric power steering apparatus

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006203048A (en) * 2005-01-21 2006-08-03 Matsushita Electric Ind Co Ltd Semiconductor chip
WO2012137333A1 (en) * 2011-04-07 2012-10-11 三菱電機株式会社 Molded module and electric power steering apparatus
CN103402853A (en) * 2011-04-07 2013-11-20 三菱电机株式会社 Molded module and electric power steering apparatus
EP2695795A1 (en) 2011-04-07 2014-02-12 Mitsubishi Electric Corporation Molded module and electric power steering apparatus
JP5705306B2 (en) * 2011-04-07 2015-04-22 三菱電機株式会社 Mold module used as power section of electric power steering apparatus, and electric power steering apparatus
EP2695795A4 (en) * 2011-04-07 2015-07-08 Mitsubishi Electric Corp Molded module and electric power steering apparatus
US9123693B2 (en) 2011-04-07 2015-09-01 Mitsubishi Electric Corporation Mold module utilized as power unit of electric power steering apparatus and electric power steering apparatus
EP3536582A1 (en) * 2011-04-07 2019-09-11 Mitsubishi Electric Corporation Mold module and electric power steering apparatus

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