JP2003347700A - Wiring board - Google Patents

Wiring board

Info

Publication number
JP2003347700A
JP2003347700A JP2002155727A JP2002155727A JP2003347700A JP 2003347700 A JP2003347700 A JP 2003347700A JP 2002155727 A JP2002155727 A JP 2002155727A JP 2002155727 A JP2002155727 A JP 2002155727A JP 2003347700 A JP2003347700 A JP 2003347700A
Authority
JP
Japan
Prior art keywords
hole
insulating substrate
conductive
wiring board
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002155727A
Other languages
Japanese (ja)
Inventor
Kenzo Fujii
健三 藤井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Original Assignee
Renesas Semiconductor Manufacturing Co Ltd
Kansai Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Semiconductor Manufacturing Co Ltd, Kansai Nippon Electric Co Ltd filed Critical Renesas Semiconductor Manufacturing Co Ltd
Priority to JP2002155727A priority Critical patent/JP2003347700A/en
Publication of JP2003347700A publication Critical patent/JP2003347700A/en
Pending legal-status Critical Current

Links

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To prevent damage of electrical connection that occurs within a relatively short time in a case, in which electrically conductive patterns formed on both surfaces of an insulating substrate are electrically connected by an electrically conductive material that fills a tapered through hole. <P>SOLUTION: By making the diameter of a through hole 12 at the middle on its axial direction smaller than those of the openings 12a, 12b at both ends of the hole 12, the angle between the openings 12a, 12b of the through hole 12 and the insulating substrate 11 becomes an acute angle, thus forming an electrically conductive thin film 15 on the inner wall of the through hole 12 by dry plating. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は電子回路装置に用い
られる配線基板に関し、特に貫通孔を有する絶縁基板の
両面に形成した導電パターンを貫通孔に充填した導電部
材により電気的に接続した両面配線基板に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board used for an electronic circuit device, and more particularly to a double-sided wiring in which conductive patterns formed on both sides of an insulating substrate having a through hole are electrically connected by a conductive member filling the through hole. Regarding the substrate.

【0002】[0002]

【従来の技術】電子回路装置は絶縁基板上に導電パター
ンを形成した配線基板上に多数の電子部品をマウントし
各電子部品の電極を導電パターンによって電気的に接続
したもので、小型の電子回路装置では両面に導電パター
ンを形成した配線基板を用い、この配線基板の両面に電
子部品をマウントすることにより実装密度を向上させて
いる。
2. Description of the Related Art An electronic circuit device mounts a large number of electronic components on a wiring board having a conductive pattern formed on an insulating substrate and electrically connects electrodes of each electronic component by the conductive pattern. In the apparatus, a wiring board having conductive patterns formed on both sides is used, and electronic components are mounted on both sides of the wiring board to improve the mounting density.

【0003】この種配線基板のうち、絶縁基板の両面に
導電パターンを直接的に形成しこの両面の導電パターン
の要部を電気的に接続した配線基板の一例を図7から説
明する。図において、1は絶縁基板で、電子部品をマウ
ントする際の熱衝撃に耐える耐熱性を有する部材が用い
られ、小型、薄型さらには可撓性が要求されるものでは
樹脂ポリイミド樹脂やエポキシ樹脂、全芳香性ポリエス
テル樹脂(液晶ポリマ樹脂)などの樹脂フィルムが用い
られ、所定位置に貫通孔2が穿設されている。3は貫通
孔1の内壁を含む絶縁基板1の両面を被覆した導電薄
膜、4、5は導電薄膜3上に所定のパターンで積層形成
された導電パターンで、一部が貫通孔2の開口端と重合
している。6は貫通孔2内に充填された導電部材で、一
般的に導電パターン4、5と同一の材料からなり、導電
パターン4、5と同時に形成される。
An example of a wiring board of this type, in which conductive patterns are directly formed on both surfaces of an insulating substrate and the main parts of the conductive patterns on both surfaces are electrically connected, will be described with reference to FIG. In the figure, reference numeral 1 denotes an insulating substrate, which is made of a heat-resistant member that withstands a thermal shock when mounting an electronic component, and is a resin polyimide resin, an epoxy resin, A resin film such as a wholly aromatic polyester resin (liquid crystal polymer resin) is used, and a through hole 2 is formed at a predetermined position. Reference numeral 3 denotes a conductive thin film covering both surfaces of the insulating substrate 1 including the inner wall of the through hole 1, and 4 and 5 denote conductive patterns formed by laminating a predetermined pattern on the conductive thin film 3, and a part thereof is an opening end of the through hole 2. And polymerized. Reference numeral 6 denotes a conductive member filled in the through hole 2, which is generally made of the same material as the conductive patterns 4 and 5, and is formed simultaneously with the conductive patterns 4 and 5.

【0004】この配線基板7の製造方法の一例を以下に
説明する。先ず図8に示すように平坦な絶縁基板1の所
定部分に貫通孔2を穿設する。この穿孔作業は絶縁基板
の厚み、貫通孔2の径に応じてレーザ光やドリルが適宜
用いられる。次に図9に示すように貫通孔2の内面を含
む絶縁基板1の両面に蒸着、スパッタリングなどのドラ
イめっき処理をする。ドライめっき処理は方向性がある
ため、回転テーブル(図示せず)上に絶縁基板1を支持
し、回転する絶縁基板1に対して傾めにめっき処理する
ことにより貫通孔2の内周面にめっき層を形成すること
ができる。このめっき層を絶縁薄膜3として利用できる
が、必要に応じて絶縁基板1をパラジウムなどのめっき
触媒に浸漬し続いて無電解めっき液に浸漬することによ
りドライめっき層を無電解めっき層で覆いピンホールの
ない導電薄膜3を形成することができる。導電薄膜3は
貫通孔2の内面にも形成されるため絶縁基板1の両面の
導電薄膜3、3は電気的に接続される。
An example of a method for manufacturing the wiring board 7 will be described below. First, as shown in FIG. 8, a through hole 2 is formed in a predetermined portion of a flat insulating substrate 1. For this drilling operation, a laser beam or a drill is appropriately used according to the thickness of the insulating substrate and the diameter of the through hole 2. Next, as shown in FIG. 9, dry plating such as evaporation and sputtering is performed on both surfaces of the insulating substrate 1 including the inner surface of the through hole 2. Since the dry plating process has directionality, the insulating substrate 1 is supported on a rotating table (not shown), and the rotating insulating substrate 1 is plated at an angle to the inner peripheral surface of the through hole 2. A plating layer can be formed. This plating layer can be used as the insulating thin film 3. If necessary, the insulating substrate 1 is immersed in a plating catalyst such as palladium and then immersed in an electroless plating solution to cover the dry plating layer with the electroless plating layer. The conductive thin film 3 without holes can be formed. Since the conductive thin film 3 is also formed on the inner surface of the through hole 2, the conductive thin films 3 on both surfaces of the insulating substrate 1 are electrically connected.

【0005】このようにして全面に導電薄膜3を形成し
た絶縁基板1の表裏両面を図10に示すように感光性レ
ジスト膜7、8で覆い、前記貫通孔2を含む所定のパタ
ーン領域を露光して現像し所定パターンの窓明け部7
a、8aを形成する。さらに図11に示すように絶縁基
板1を電気めっきして前記窓明け部7a、8aに露呈し
た導電層3、3上に厚い導電パターン4、5を形成す
る。この後、感光性レジスト膜7、8を除去して導電薄
膜3を露呈させ、露呈した導電薄膜3をエッチング除去
し図7に示す配線基板7が完成する。
As shown in FIG. 10, both sides of the insulating substrate 1 on which the conductive thin film 3 is formed over the entire surface are covered with photosensitive resist films 7 and 8 as shown in FIG. And developed to form a predetermined pattern window opening 7
a and 8a are formed. Further, as shown in FIG. 11, the insulating substrate 1 is electroplated to form thick conductive patterns 4 and 5 on the conductive layers 3 and 3 exposed in the window openings 7a and 8a. Thereafter, the photosensitive resist films 7 and 8 are removed to expose the conductive thin film 3, and the exposed conductive thin film 3 is removed by etching to complete the wiring board 7 shown in FIG.

【0006】導電薄膜3や導電パターン4、5などのめ
っき金属として一般的に銅が用いられる。導電薄膜3は
厚みが0.05〜3μmに、導電薄膜3を含む導電パタ
ーン4、5の厚みは3〜50μmに設定される。この配
線基板6はめっきにより絶縁基板1上に直接的に導電パ
ターン4、5を形成できるため微細パターン化が可能
で、小型の電子回路装置用配線基板として好適である。
Copper is generally used as a plating metal for the conductive thin film 3 and the conductive patterns 4 and 5. The thickness of the conductive thin film 3 is set to 0.05 to 3 μm, and the thickness of the conductive patterns 4 and 5 including the conductive thin film 3 is set to 3 to 50 μm. The wiring substrate 6 can be formed into a fine pattern because the conductive patterns 4 and 5 can be formed directly on the insulating substrate 1 by plating, and is suitable as a small wiring substrate for electronic circuit devices.

【0007】この種配線基板は例えば特開昭60−26
3607号公報(先行技術1)、特開平2−14349
2号公報(先行技術2)、特開2001−7648号公
報(先行技術3)、特開2002−443752号公報
(先行技術4)などに開示されている。
This type of wiring board is disclosed in, for example, Japanese Patent Application Laid-Open No. 60-26.
No. 3607 (Prior Art 1), Japanese Patent Application Laid-Open No. 2-14349.
No. 2 (Prior Art 2), Japanese Patent Application Laid-Open No. 2001-7648 (Prior Art 3), and Japanese Patent Application Laid-Open No. 2002-443752 (Prior Art 4).

【0008】ところで貫通孔2を穿設するのに、先行技
術1ではドリルを用い、先行技術2ではレーザ光を用い
ているが、高密度実装用の配線基板では微細化した導電
パターンに対応するため貫通孔2も微細化する必要があ
り一般的にレーザ光により穿設される。
In the prior art 1, a drill is used to form the through hole 2, and in the prior art 2, laser light is used. However, a wiring board for high-density mounting corresponds to a fine conductive pattern. Therefore, the through hole 2 also needs to be miniaturized, and is generally formed by laser light.

【0009】[0009]

【発明が解決しようとする課題】しかしながらドライめ
っき処理による導電薄膜3は、貫通孔2の内周面には開
口部を通して傾斜してめっき層が形成されるため、貫通
孔2の開口径が絶縁基板1の厚みに比して小さいと貫通
孔2の軸方向中間部で導電薄膜3の厚みがばらつき図1
2に示すようにめっき層の不着部分9が形成されること
があった。
However, since the conductive thin film 3 formed by the dry plating process has a plating layer formed on the inner peripheral surface of the through hole 2 so as to be inclined through the opening, the opening diameter of the through hole 2 is insulated. If the thickness is smaller than the thickness of the substrate 1, the thickness of the conductive thin film 3 varies at the axially intermediate portion of the through hole 2.
As shown in FIG. 2, a non-adhered portion 9 of the plating layer was sometimes formed.

【0010】このように貫通孔2の軸方向中間の不着部
分9で絶縁基板1の素地が露呈すると、この部分は電気
めっき層が成長せず、図13に示すように導電部材6の
中間にボイド10が形成され、両面の導電薄膜3、3の
電気的接続が不安定となり、絶縁基板1の両面から局部
的に接続できたとしても温度サイクル試験により配線基
板7に熱膨張、熱伸縮を繰返しかけると、比較的短時間
で接続部にクラックを生じることがあった。上記クラッ
クは時間の経過とともに成長し電子回路装置がノイズを
発生したり不安定動作をするようになり、さらにクラッ
クが成長すると電子回路装置を不良にするという問題が
あった。
When the base of the insulating substrate 1 is exposed at the non-attached portion 9 in the axially intermediate portion of the through hole 2, the electroplating layer does not grow in this portion, and as shown in FIG. The voids 10 are formed, the electrical connection between the conductive thin films 3 on both surfaces becomes unstable, and even if local connection can be made from both surfaces of the insulating substrate 1, thermal expansion and thermal expansion and contraction of the wiring substrate 7 by the temperature cycle test are performed. When repeated, cracks were sometimes formed in the connection portion in a relatively short time. The cracks grow with the passage of time, causing the electronic circuit device to generate noise or perform unstable operation. Further, if the crack grows further, there is a problem that the electronic circuit device becomes defective.

【0011】このボイドやクラックは絶縁基板1の厚
く、貫通孔2の開口径が小さいほど発生し易く、導電パ
ターン4、5の微細化により顕著となるため解決が望ま
れていた。
These voids and cracks are more likely to occur as the insulating substrate 1 is thicker and the opening diameter of the through-hole 2 is smaller, and it becomes more conspicuous as the conductive patterns 4 and 5 become finer.

【0012】[0012]

【課題を解決するための手段】本発明は上記課題の解決
を目的として提案されたもので、所定位置に貫通孔を穿
設した絶縁基板の両面に前記貫通孔と重合する導電パタ
ーンを形成するとともに貫通孔内に充填した導電部材に
より両面の導電パターンを電気的に接続した配線基板に
おいて、上記貫通孔の径を絶縁基板の両面から軸方向中
間に向かって縮径させるとともに貫通孔の内壁を含む絶
縁基板素地上にドライめっき層を形成したことを特徴と
する配線基板を提供する。
SUMMARY OF THE INVENTION The present invention has been proposed for the purpose of solving the above-mentioned problems, and a conductive pattern is formed on both surfaces of an insulating substrate having a through hole formed at a predetermined position so as to overlap the through hole. In a wiring board in which conductive patterns on both sides are electrically connected by a conductive member filled in the through-hole, the diameter of the through-hole is reduced toward the middle in the axial direction from both sides of the insulating substrate, and the inner wall of the through-hole is reduced. Provided is a wiring board characterized in that a dry plating layer is formed on a substrate including the same.

【0013】[0013]

【発明の実施の形態】本発明による配線基板は絶縁基板
に穿設した貫通孔の径を絶縁基板の両面から軸方向中間
に向かって縮径させるとともに貫通孔の内壁を含む絶縁
基板素地上にドライめっき層を形成したことを特徴とす
るが、貫通孔をレーザ光により穿設し、この貫通孔内面
をドライめっき処理し、無電解めっきまたは電解めっき
による導電部材により貫通孔内を充填して、絶縁基板両
面の導電パターンを電気的に接続することができる。
BEST MODE FOR CARRYING OUT THE INVENTION A wiring board according to the present invention reduces the diameter of a through hole formed in an insulating substrate from both sides of the insulating substrate toward the center in the axial direction and places the through hole on the insulating substrate base including the inner wall of the through hole. It is characterized in that a dry plating layer is formed, but a through hole is drilled by laser light, the inner surface of this through hole is subjected to dry plating, and the inside of the through hole is filled with a conductive member by electroless plating or electrolytic plating. The conductive patterns on both surfaces of the insulating substrate can be electrically connected.

【0014】また貫通孔の両端周縁から内面に沿って軸
方向中間に向かう傾斜面のなす角を鈍角とすることによ
り、ドライめっき処理を効率良く行なうことができる。
Further, by making the angle formed by the inclined surface extending from the peripheral edges of both ends of the through hole toward the middle in the axial direction along the inner surface an obtuse angle, the dry plating process can be performed efficiently.

【0015】貫通孔の軸方向中間の縮径部の径は5μm
から2×(導電パターンの厚み)の範囲に設定すること
により貫通孔内を導電部材で確実に充填することができ
る。
The diameter of the reduced diameter portion in the axial direction of the through hole is 5 μm.
By setting the thickness in the range of 2 × (the thickness of the conductive pattern), the inside of the through hole can be reliably filled with the conductive member.

【0016】[0016]

【実施例】以下に本発明を適用した配線基板の一例を図
1から説明する。図において、11は耐熱性樹脂からな
る絶縁基板で、所定位置に貫通孔12を穿設している。
この貫通孔12の径は両端の開口部12a、12bから
軸方向中間部12cに向かって縮径させ、これにより軸
方向中間部12cの周壁は内方に突出している。13、
14は一部が貫通孔12の開口部12a、12bと重合
し絶縁基板11の両面に所定のパターンで形成された導
電パターンで、絶縁基板11上に被着された薄い導電薄
膜15a、15bと、この導電薄膜15a、15b上に
積層された導電膜16a、16bの積層構造となってい
る。貫通孔12の内壁には各導電薄膜15a、15bか
ら連続して延びる導電薄膜15cが被着され、この導電
薄膜15cによって両面の導電薄膜15a、15bは電
気的に接続されている。また導電薄膜15a、15bに
積層された導電膜16a、16bの一部は貫通孔12内
の導電薄膜15cに積層されロッド状の導電部材17と
なって貫通孔12内に充填されている。
FIG. 1 shows an example of a wiring board to which the present invention is applied. In the figure, reference numeral 11 denotes an insulating substrate made of a heat-resistant resin, and a through-hole 12 is formed at a predetermined position.
The diameter of the through hole 12 is reduced from the openings 12a and 12b at both ends toward the axial intermediate portion 12c, whereby the peripheral wall of the axial intermediate portion 12c protrudes inward. 13,
Reference numeral 14 denotes a conductive pattern partially overlapped with the openings 12a and 12b of the through hole 12 and formed in a predetermined pattern on both surfaces of the insulating substrate 11, and includes thin conductive thin films 15a and 15b applied on the insulating substrate 11. The conductive films 16a and 16b are laminated on the conductive thin films 15a and 15b. A conductive thin film 15c extending continuously from the conductive thin films 15a and 15b is applied to the inner wall of the through hole 12, and the conductive thin films 15a and 15b on both surfaces are electrically connected by the conductive thin film 15c. A part of the conductive films 16a and 16b stacked on the conductive thin films 15a and 15b is stacked on the conductive thin film 15c in the through hole 12 and becomes a rod-shaped conductive member 17 to fill the through hole 12.

【0017】本発明による配線基板18は貫通孔12の
径を絶縁基板11の両面から軸方向中間に向かって縮径
させるとともに貫通孔12の内壁を含む絶縁基板11素
地上にドライめっき層を形成したことを特徴とする。
In the wiring board 18 according to the present invention, the diameter of the through-hole 12 is reduced from both surfaces of the insulating substrate 11 toward the middle in the axial direction, and a dry plating layer is formed on the substrate 11 including the inner wall of the through-hole 12. It is characterized by having done.

【0018】蒸着法、スパッタ法などのドライめっき処
理により清浄化した絶縁基板11上に形成した導電薄膜
15は絶縁基板11に対する密着性が良好で、剥離しに
くいことが知られている。 図1に示すように貫通孔1
2は絶縁基板11の両面に開口した端部12a、12b
から軸方向中間部12cに向かって縮径させているた
め、その内壁12dは図2に示すように開口端12a、
12bから軸方向中間部12cまでの全面を外部から臨
むことができる。また絶縁基板11の一方の面の開口端
部12aから軸方向中間部12cを通り他の面の開口端
部12bに連続する沿面の屈曲部をいずれも鈍角とな
し、急激な角部をなくすことができる。そのためこの絶
縁基板11の両面にドライめっき処理により導電薄膜1
5a、15bを形成すると同時に貫通孔12の内壁にも
厚みむらのない導電薄膜15cを形成することができ
る。さらに導電部材17は、導電薄膜15c上を被覆す
る導電膜16を、貫通孔12の軸方向中間部12cの径
小側から開口端部12a,12bの径大側に向かって成
長させて形成されるため、開口径に対する軸長の比が大
きい貫通孔でもボイドを発生することなく確実に充填で
きる。これらの組み合わせにより、貫通孔12の内壁1
2dを含む絶縁基板11の全面に密着性が良好な導電薄
膜15を形成することかでき、導電薄膜15a、15
b、15cの各隣接角部に熱膨張、熱収縮による応力集
中を防止することができ、信頼性の高い配線基板を実現
できる。
It is known that a conductive thin film 15 formed on an insulating substrate 11 which has been cleaned by a dry plating process such as a vapor deposition method or a sputtering method has good adhesion to the insulating substrate 11 and is difficult to peel off. As shown in FIG.
2 are ends 12a and 12b opened on both sides of the insulating substrate 11.
, The inner wall 12d has an open end 12a, as shown in FIG.
The entire surface from 12b to the axial intermediate portion 12c can be viewed from the outside. In addition, any bent portion on the surface extending from the open end portion 12a on one surface of the insulating substrate 11 to the open end portion 12b on the other surface through the axial middle portion 12c is formed at an obtuse angle to eliminate sharp corner portions. Can be. Therefore, the conductive thin film 1 is formed on both surfaces of the insulating substrate 11 by dry plating.
The conductive thin film 15c having no thickness unevenness can be formed on the inner wall of the through hole 12 at the same time as the formation of 5a and 15b. Further, the conductive member 17 is formed by growing the conductive film 16 covering the conductive thin film 15c from the small diameter side of the axial middle portion 12c of the through hole 12 to the large diameter side of the opening end portions 12a and 12b. Therefore, even a through hole having a large ratio of the axial length to the opening diameter can be reliably filled without generating a void. By combining these, the inner wall 1 of the through hole 12 is formed.
The conductive thin film 15 having good adhesion can be formed on the entire surface of the insulating substrate 11 including 2d.
Stress concentration due to thermal expansion and thermal contraction at each of the adjacent corners of b and 15c can be prevented, and a highly reliable wiring board can be realized.

【0019】この配線基板18の製造方法を以下に説明
する。まず図3に示すように絶縁基板11を用意する。
この絶縁基板11はポリイミド樹脂、エポキシ樹脂、全
芳香性ポリエステル樹脂(液晶ポリマ樹脂)などの耐熱
性樹脂が一般的に用いられ、薄型あるいは可撓性が要求
されるものでは例えば厚さ25〜200μmのフィルム
状樹脂基板が用いられる。この絶縁基板11の所定部分
には貫通孔12が穿設される。この貫通孔12はレーザ
光を絶縁基板11の一方の面から照射して基板11の厚
みの1/2よりやや深く穿孔して開口端から内方に向か
って縮径する有底穴を形成した後、この穴と同軸に絶縁
基板11の他の面からレーザ光を照射して基板厚みの1
/2よりやや深く穿孔させると両面の穿孔穴は連通し、
軸方向中間部が縮径した貫通孔12が形成される。この
とき貫通孔12の軸方向中間部12cの内壁が鈍角とな
るように穿孔する。次に図4に示すように貫通孔12の
内面を含む絶縁基板11の両面にドライめっき処理して
導電薄膜15a、15bを形成する。スパッタ法により
めっき処理する場合、クロムやニッケルなど硬質金属を
下地層として0.03μm〜1μmの厚みに形成し、そ
の上に銅などの導電性が良好な軟質金属を積層すること
が望ましい。この処理は絶縁基板11の表面と同時に貫
通孔12内に行なわれるが、貫通孔12は開口両端12
a、12bから内壁全面を臨むことができ、開口端12
a、12bから軸方向中間部12cまでの全軸長の1/
2の内壁にめっき処理すればよい。そのため、導電パタ
ーンの狭小化に対応して貫通孔12の開口径を縮小して
もその内壁に確実にめっき処理できる。また絶縁基板1
1の両面と貫通孔12とは開口端12a、12bで鈍角
をなして接続し、開口端から内方に向かって縮径し、軸
方向中間部12cの内方に突出した内壁12dも断面が
鈍角をなして一端側から他端側へ連続しているため、貫
通孔12内に形成した導電薄膜15cは両面の導電薄膜
15a、15bの電気的接続を確実にできる。
A method for manufacturing the wiring board 18 will be described below. First, an insulating substrate 11 is prepared as shown in FIG.
The insulating substrate 11 is generally made of a heat-resistant resin such as a polyimide resin, an epoxy resin, a wholly aromatic polyester resin (liquid crystal polymer resin), and is required to be thin or flexible. Is used. A through hole 12 is formed in a predetermined portion of the insulating substrate 11. The through-hole 12 is irradiated with a laser beam from one surface of the insulating substrate 11 to form a hole with a bottom having a diameter slightly smaller than 厚 み of the thickness of the substrate 11 and inward from the opening end. Thereafter, a laser beam is irradiated from the other surface of the insulating substrate 11 coaxially with the hole to reduce the thickness of the substrate to one.
When drilling slightly deeper than / 2, the drilling holes on both sides are connected,
A through hole 12 having a reduced diameter in the axial middle portion is formed. At this time, the inner wall of the intermediate portion 12c in the axial direction of the through hole 12 is perforated so as to form an obtuse angle. Next, as shown in FIG. 4, both surfaces of the insulating substrate 11 including the inner surface of the through hole 12 are subjected to dry plating to form conductive thin films 15a and 15b. In the case of plating by a sputtering method, it is desirable to form a hard metal such as chromium or nickel as a base layer to a thickness of 0.03 μm to 1 μm, and to stack a soft metal having good conductivity such as copper thereon. This process is performed in the through hole 12 at the same time as the surface of the insulating substrate 11.
a, 12b, the entire inner wall can be viewed from the open end 12a.
a, 1/1 of the total axial length from the axially intermediate portion 12c to the intermediate portion 12c.
2 may be plated. Therefore, even if the opening diameter of the through hole 12 is reduced in accordance with the narrowing of the conductive pattern, the inner wall thereof can be reliably plated. Insulating substrate 1
1 and the through-hole 12 are connected at obtuse angles at the open ends 12a and 12b, the diameter is reduced inward from the open ends, and the cross section of the inner wall 12d protruding inward of the axial intermediate portion 12c is also formed. Since the conductive thin film 15c formed in the through-hole 12 forms an obtuse angle and is continuous from one end to the other end, electrical connection between the conductive thin films 15a and 15b on both surfaces can be ensured.

【0020】このようにして導電薄膜15を形成した
後、図示省略するが絶縁基板11をパラジウムなどを含
むめっき触媒に浸漬し、さらにこの絶縁基板11を無電
解めっき液に浸漬して絶縁基板11の全面にめっき金属
を厚み0.01μm〜1μm程度析出させ、導電薄膜1
5の全体の厚みを0.05μm〜3μmに形成する。こ
れによりドライめっき処理に要する時間を短縮し、ドラ
イめっき層のピンホールをなくし、後工程でのめっき処
理を良好にできる。次に図5に示すように絶縁基板11
の両面を感光性レジスト膜19、20で覆い、前記貫通
孔12を含む所定のパターン領域を露光して現像し所定
パターンの窓明け部19a、20aを形成する。この絶
縁基板11に対して図6に示すように電気めっきして前
記窓明け部19a、20aに露呈した導電薄膜15a、
15b上に電気めっきによる厚い導電層16a、16b
を形成する。このめっき金属は導電性が良好な銅が一般
的に用いられ、導電薄膜15を含む厚みが5〜30μm
となるように形成する。このめっきにより、貫通孔12
は導電部材17で充填される。この後、感光性レジスト
膜19、20を除去し露呈した導電薄膜をエッチング除
去して図1に示す導電パターン13、14を形成した配
線基板18が完成する。
After forming the conductive thin film 15 in this manner, although not shown, the insulating substrate 11 is immersed in a plating catalyst containing palladium or the like, and the insulating substrate 11 is further immersed in an electroless plating solution. The plating metal is deposited to a thickness of about 0.01 μm to 1 μm on the entire surface of the conductive thin film 1.
5 is formed to a thickness of 0.05 μm to 3 μm. As a result, the time required for the dry plating process can be reduced, pinholes in the dry plating layer can be eliminated, and the plating process in the subsequent step can be improved. Next, as shown in FIG.
Are covered with photosensitive resist films 19 and 20, and a predetermined pattern area including the through hole 12 is exposed and developed to form window openings 19a and 20a having a predetermined pattern. As shown in FIG. 6, the conductive thin film 15a exposed on the window openings 19a and 20a by electroplating the insulating substrate 11 as shown in FIG.
Thick conductive layers 16a, 16b by electroplating on 15b
To form As the plating metal, copper having good conductivity is generally used, and the thickness including the conductive thin film 15 is 5 to 30 μm.
It is formed so that By this plating, the through holes 12
Is filled with the conductive member 17. Thereafter, the photosensitive resist films 19 and 20 are removed, and the exposed conductive thin film is removed by etching to complete the wiring substrate 18 on which the conductive patterns 13 and 14 shown in FIG. 1 are formed.

【0021】本発明による配線基板18は貫通孔12の
内周を傾斜させ両端の開口径に比して軸方向中間部の径
を小径としたので、開口端部12a、12bから内壁1
2dを臨むことができ、しかも露呈した内壁12dの軸
方向長さが全長の1/2に短縮され、ドライめっきの際
に開口端から内壁12dの全面を臨むことができ、貫通
孔12内のドライめっき処理が容易である。また貫通孔
12の内壁12dへのドライめっき処理は開口端12
a、12bの開口径によって制限されるが、内壁12d
が傾斜しているためめっき投射面積が広く、めっき効率
を高めることができる。そのため、貫通孔12内壁のド
ライめっき層の厚みのばらつきがなく、処理時間を短縮
することができる。
In the wiring board 18 according to the present invention, the inner periphery of the through hole 12 is inclined so that the diameter of the middle portion in the axial direction is smaller than the diameter of the opening at both ends, so that the inner wall 1 extends from the opening ends 12a and 12b.
2d, and the exposed length of the inner wall 12d in the axial direction is reduced to の of the total length. In the case of dry plating, the entire surface of the inner wall 12d can be viewed from the opening end. Dry plating is easy. Dry plating on the inner wall 12d of the through hole 12 is performed at the opening end 12d.
a, 12b, but the inner wall 12d
Is inclined, so that the plating projection area is large and the plating efficiency can be increased. Therefore, there is no variation in the thickness of the dry plating layer on the inner wall of the through hole 12, and the processing time can be reduced.

【0022】また貫通孔12の内壁12dは絶縁基板1
1の一方の面から他の面へ、屈曲部が鈍角をなして連続
しているため、内壁12dの屈曲部でも導電薄膜15を
連続して形成することができる。そのため導電薄膜15
の不着部分が形成されず、両面の導電薄膜15a、15
bを確実に電気接続でき、熱膨張、熱収縮を繰返し受け
ても局所的な応力が発生せず、導電薄膜15、導電膜1
6、導電部材17にクラックを生じず、長期間安定した
電気的接続を保つことができ、信頼性の高い電子回路装
置を実現できる。
The inner wall 12d of the through hole 12 is
Since the bent portion is continuous from one surface to the other surface at an obtuse angle, the conductive thin film 15 can be formed continuously even at the bent portion of the inner wall 12d. Therefore, the conductive thin film 15
Is not formed, and the conductive thin films 15a, 15 on both surfaces are not formed.
b can be reliably connected electrically, and no local stress is generated even when the thermal expansion and the thermal contraction are repeatedly applied.
6. A stable electronic connection can be maintained for a long time without cracking in the conductive member 17, and a highly reliable electronic circuit device can be realized.

【0023】尚、本発明は上記実施例にのみ限定される
ことなく、例えば導電パターン13、14や貫通孔12
内に充填される導電部材17は電解めっきにより形成す
るだけでなく、無電解めっき単独または電解めっき単独
で形成でき、さらには無電解めっきや電解めっきのめっ
き条件を変えて多層に積層形成することもできる。また
貫通孔12の両端開口部と中間小径部のそれぞれの径の
比は絶縁基板11の厚み、沿面屈曲部の角度に応じて任
意に設定することができる。また貫通孔12の中間の内
壁12dの直径は5μmから導電パターンのめっき厚さ
の2倍の範囲で設定することが望ましい。また導電パタ
ーン13、14はクロム、ニッケル、銅だけでなく、電
気抵抗と硬度を考慮して適宜採用することができる。
It should be noted that the present invention is not limited to the above-described embodiment, but includes, for example, the conductive patterns 13 and 14 and the through holes 12.
The conductive member 17 to be filled therein can be formed not only by electrolytic plating but also by electroless plating alone or electrolytic plating alone, and furthermore, by multilayering by changing plating conditions of electroless plating and electrolytic plating. Can also. The ratio of the diameter of the opening at both ends of the through hole 12 to the diameter of the intermediate small-diameter portion can be arbitrarily set according to the thickness of the insulating substrate 11 and the angle of the creeping bent portion. It is desirable that the diameter of the inner wall 12d in the middle of the through hole 12 is set in the range of 5 μm to twice the plating thickness of the conductive pattern. The conductive patterns 13 and 14 can be appropriately adopted in consideration of not only chromium, nickel and copper but also electric resistance and hardness.

【0024】[0024]

【発明の効果】以上のように本発明によれば両面に形成
した導電パターンの電気的接続を長期間にわたって安定
させることのできる信頼性の高い配線基板を提供するこ
とができる。
As described above, according to the present invention, it is possible to provide a highly reliable wiring board capable of stabilizing the electrical connection of the conductive patterns formed on both surfaces for a long period of time.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明による配線基板の要部側断面図FIG. 1 is a sectional side view of a main part of a wiring board according to the present invention.

【図2】 図1配線基板に用いられる絶縁基板の貫通孔
を示す要部平面図
FIG. 2 is a main part plan view showing through holes of an insulating substrate used for the wiring substrate of FIG. 1;

【図3】 図1配線基板用絶縁基板の要部側断面図FIG. 3 is a sectional side view of a main part of the insulating substrate for a wiring board in FIG. 1;

【図4】 図3に示す絶縁基板に導電薄膜を形成した状
態を示す要部側断面図
FIG. 4 is a sectional side view showing a state where a conductive thin film is formed on the insulating substrate shown in FIG. 3;

【図5】 図4に示す絶縁基板上をレジスト膜で被覆
し、要部を窓明けした状態を示す要部側断面図
FIG. 5 is a sectional side view of a main part showing a state where the insulating substrate shown in FIG. 4 is covered with a resist film and the main part is opened;

【図6】 図5に示すレジスト膜の窓明け部分に電解め
っきによる導電膜を形成した状態を示す要部側断面図
FIG. 6 is a side sectional view of a main part showing a state where a conductive film is formed by electroplating in a window portion of the resist film shown in FIG. 5;

【図7】 本発明の前提となる従来の配線基板を示す要
部側断面図
FIG. 7 is a sectional side view of a main part showing a conventional wiring board which is a premise of the present invention.

【図8】 図7配線基板の製造方法を示す絶縁基板の要
部側断面図
8 is a cross-sectional view of a main part of an insulating substrate, illustrating a method of manufacturing a wiring substrate of FIG. 7;

【図9】 図8に示す絶縁基板上に導電薄膜を形成した
状態を示す要部側断面図
FIG. 9 is a side sectional view showing a state where a conductive thin film is formed on the insulating substrate shown in FIG. 8;

【図10】 図9に示す絶縁基板上をレジスト膜で被覆
し、窓明けした状態を示す要部側断面図
10 is a sectional side view of a main part showing a state in which the insulating substrate shown in FIG. 9 is covered with a resist film and a window is opened.

【図11】 図10に示すレジスト膜の窓明け部分に電
解めっきによる導電膜を形成した状態を示す要部側断面
11 is a side sectional view of a main part showing a state where a conductive film is formed by electroplating in a window portion of the resist film shown in FIG. 10;

【図12】 貫通孔内の導電薄膜に不着部分が形成され
た状態を示す絶縁基板の要部側断面図
FIG. 12 is a side cross-sectional view of a main part of an insulating substrate, showing a state where a non-adhesion portion is formed on a conductive thin film in a through hole.

【図13】 貫通孔内を充填する導電部材にボイドが形
成された状態を示す絶縁基板の要部側断面図
FIG. 13 is a side cross-sectional view of a main part of the insulating substrate, showing a state in which a void is formed in the conductive member filling the through hole;

【符号の説明】[Explanation of symbols]

11 絶縁基板 12 貫通孔 12a、12b 開口端部 12d 内壁 13、14 導電パターン 15、15a、15b、15c 導電薄膜 16、16a、16b 導電層 17 導電部材 18 配線基板 11 Insulating substrate 12 Through hole 12a, 12b Open end 12d inner wall 13, 14 conductive pattern 15, 15a, 15b, 15c conductive thin film 16, 16a, 16b conductive layer 17 conductive members 18 Wiring board

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 所定位置に貫通孔を穿設した絶縁基板の
両面に前記貫通孔と重合する導電パターンを形成すると
ともに貫通孔内に充填した導電部材により両面の導電パ
ターンを電気的に接続した配線基板において、上記貫通
孔の径を絶縁基板の両面から軸方向中間に向かって縮径
させるとともに貫通孔の内壁を含む絶縁基板素地上にド
ライめっき層を形成したことを特徴とする配線基板。
A conductive pattern overlapping with the through hole is formed on both surfaces of an insulating substrate having a through hole formed at a predetermined position, and the conductive patterns on both surfaces are electrically connected by a conductive member filled in the through hole. In a wiring board, a diameter of the through hole is reduced from both surfaces of the insulating substrate toward an intermediate portion in an axial direction, and a dry plating layer is formed on a base surface of the insulating substrate including an inner wall of the through hole.
【請求項2】 レーザ光により穿設された貫通孔内面が
ドライめっき処理され、無電解めっきまたは電解めっき
による導電部材により貫通孔内が充填されて、絶縁基板
両面の導電パターンが電気的に接続されたことを特徴と
する請求項1に記載の配線基板。
2. An inner surface of a through hole formed by a laser beam is subjected to a dry plating process, the inside of the through hole is filled with a conductive member formed by electroless plating or electrolytic plating, and conductive patterns on both surfaces of the insulating substrate are electrically connected. The wiring board according to claim 1, wherein
【請求項3】 貫通孔の両端から軸方向中間に向かう傾
斜面のなす角が鈍角であることを特徴とする請求項1に
記載の配線基板。
3. The wiring board according to claim 1, wherein the angle formed by the inclined surface extending from both ends of the through hole toward the middle in the axial direction is an obtuse angle.
【請求項4】 貫通孔の軸方向中間の縮径部の径を5μ
mから2×(導電パターンの厚み)の範囲に設定したこ
とを特徴とする請求項1に記載の配線基板。
4. The diameter of the reduced diameter portion in the axial direction of the through hole is 5 μm.
The wiring board according to claim 1, wherein the wiring board is set in a range of m to 2 x (thickness of the conductive pattern).
JP2002155727A 2002-05-29 2002-05-29 Wiring board Pending JP2003347700A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002155727A JP2003347700A (en) 2002-05-29 2002-05-29 Wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002155727A JP2003347700A (en) 2002-05-29 2002-05-29 Wiring board

Publications (1)

Publication Number Publication Date
JP2003347700A true JP2003347700A (en) 2003-12-05

Family

ID=29772186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002155727A Pending JP2003347700A (en) 2002-05-29 2002-05-29 Wiring board

Country Status (1)

Country Link
JP (1) JP2003347700A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100659509B1 (en) 2006-01-12 2006-12-20 삼성전기주식회사 Pcb terminal
CN101925266A (en) * 2009-06-09 2010-12-22 揖斐电株式会社 The manufacture method of printed circuit board (PCB) and printed circuit board (PCB)
JP2011210794A (en) * 2010-03-29 2011-10-20 Sumitomo Bakelite Co Ltd Insulating substrate, method of manufacturing the same, printed-wiring board, and semiconductor device
KR101077336B1 (en) * 2009-09-09 2011-10-26 삼성전기주식회사 Fabricating Method of Printed Circuit Board
JP2012099970A (en) * 2010-10-29 2012-05-24 Tdk Corp Laminated electronic component and manufacturing method therefor
KR101148545B1 (en) * 2009-06-09 2012-05-25 이비덴 가부시키가이샤 Double-sided circuit board and manufacturing method thereof
JP2012204662A (en) * 2011-03-25 2012-10-22 Furukawa Electric Co Ltd:The Wiring board and method for manufacturing the same, and semiconductor device
KR101343296B1 (en) 2012-11-02 2013-12-18 삼성전기주식회사 Method for manufacturing electric component and electric component
US8891245B2 (en) 2011-09-30 2014-11-18 Ibiden Co., Ltd. Printed wiring board
JP2018174189A (en) * 2017-03-31 2018-11-08 大日本印刷株式会社 Through-electrode substrate and manufacturing method therefor
CN111096088A (en) * 2017-09-22 2020-05-01 住友电气工业株式会社 Printed circuit board and method of manufacturing printed circuit board

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100659509B1 (en) 2006-01-12 2006-12-20 삼성전기주식회사 Pcb terminal
US8413324B2 (en) 2009-06-09 2013-04-09 Ibiden Co., Ltd. Method of manufacturing double-sided circuit board
CN101925266A (en) * 2009-06-09 2010-12-22 揖斐电株式会社 The manufacture method of printed circuit board (PCB) and printed circuit board (PCB)
JP2010287878A (en) * 2009-06-09 2010-12-24 Ibiden Co Ltd Method for manufacturing printed wiring board, and printed wiring board
US8925192B2 (en) 2009-06-09 2015-01-06 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
US8766106B2 (en) 2009-06-09 2014-07-01 Ibiden Co., Ltd. Double-sided circuit board and manufacturing method thereof
KR101148545B1 (en) * 2009-06-09 2012-05-25 이비덴 가부시키가이샤 Double-sided circuit board and manufacturing method thereof
US8698009B2 (en) 2009-06-09 2014-04-15 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
KR101077336B1 (en) * 2009-09-09 2011-10-26 삼성전기주식회사 Fabricating Method of Printed Circuit Board
JP2011210794A (en) * 2010-03-29 2011-10-20 Sumitomo Bakelite Co Ltd Insulating substrate, method of manufacturing the same, printed-wiring board, and semiconductor device
JP2012099970A (en) * 2010-10-29 2012-05-24 Tdk Corp Laminated electronic component and manufacturing method therefor
JP2012204662A (en) * 2011-03-25 2012-10-22 Furukawa Electric Co Ltd:The Wiring board and method for manufacturing the same, and semiconductor device
US8891245B2 (en) 2011-09-30 2014-11-18 Ibiden Co., Ltd. Printed wiring board
KR101343296B1 (en) 2012-11-02 2013-12-18 삼성전기주식회사 Method for manufacturing electric component and electric component
JP2018174189A (en) * 2017-03-31 2018-11-08 大日本印刷株式会社 Through-electrode substrate and manufacturing method therefor
CN111096088A (en) * 2017-09-22 2020-05-01 住友电气工业株式会社 Printed circuit board and method of manufacturing printed circuit board
US20200196445A1 (en) * 2017-09-22 2020-06-18 Sumitomo Electric Industries, Ltd. Printed circuit board and method of manufacturing a printed circuit board
US10980114B2 (en) * 2017-09-22 2021-04-13 Sumitomo Electric Industries, Ltd. Printed circuit board and method of manufacturing a printed circuit board
CN111096088B (en) * 2017-09-22 2023-04-18 住友电气工业株式会社 Printed circuit board and method of manufacturing printed circuit board

Similar Documents

Publication Publication Date Title
JP4564342B2 (en) Multilayer wiring board and manufacturing method thereof
WO2000003572A1 (en) Printed wiring board and method for producing the same
JPH06112630A (en) Method of forming circuit wiring pattern
US6674017B1 (en) Multilayer-wiring substrate and method for fabricating same
JPH1012677A (en) Manufacture of double-side wiring tape carrier for semiconductor device
JP4054269B2 (en) Electronic component manufacturing method and electronic component
JP2003347700A (en) Wiring board
JP2001053188A (en) Method for manufacturing multilayer wiring board
JPH0964493A (en) Wiring structure of circuit board and its formation
JP2004047836A (en) Printed board and its manufacturing method
JP2001156453A (en) Forming method for embedded via at printed wiring board
JP2002252436A (en) Double-sided laminate and its manufacturing method
JP2005197648A (en) Method for manufacturing a circuit board wired by electroplating
JP2003318501A (en) Wiring board
JP2000200975A (en) Manufacture of multilayer wiring substrate
JP2003142823A (en) Manufacturing method for both-sided flexible circuit board
JP2000124615A (en) Multilayer printed wiring board and its manufacture
JP2001144442A (en) Multilayer wiring board
KR100593211B1 (en) Method for manufacturing through hole electrode for wafer
JP2004288748A (en) Method of manufacturing wiring board
KR100468195B1 (en) A manufacturing process of multi-layer printed circuit board
JP2000151107A (en) Multilayer printed wiring board and manufacture thereof
JP2003273170A (en) Manufacturing method for both-side wiring tape carrier and tape carrier using the same
JP3205089B2 (en) Method for producing multilayer conductor film carrier
JP2000332417A (en) Via forming method for multilayer printed board