JP2003332588A - Semiconductor element - Google Patents
Semiconductor elementInfo
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- JP2003332588A JP2003332588A JP2002133977A JP2002133977A JP2003332588A JP 2003332588 A JP2003332588 A JP 2003332588A JP 2002133977 A JP2002133977 A JP 2002133977A JP 2002133977 A JP2002133977 A JP 2002133977A JP 2003332588 A JP2003332588 A JP 2003332588A
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- Prior art keywords
- region
- conductivity type
- active region
- breakdown voltage
- insulating film
- Prior art date
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、耐圧維持構造を備
えた半導体素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a breakdown voltage maintaining structure.
【０００２】[0002]
【従来の技術】一般に、ＰＮ接合が逆電圧を受けると
き、その接合部に電界集中を受けやすく破壊の原因とも
なる。ｐｎ接合の降伏は、空乏領域の最大電界Ｅｍａｘ
が臨界電界Ｅｃｒｉｔに達するときに起こるというのが
実験結果によく一致する一般的な理論である。この電界
集中を緩和させて一定印加電圧に対する最大電界Ｅｍａ
ｘを下げることにより、耐圧を向上することができる。2. Description of the Related Art In general, when a PN junction receives a reverse voltage, it is apt to receive an electric field concentration on the junction, which may cause destruction. The breakdown of the pn junction depends on the maximum electric field Emax of the depletion region.
Occurs when the critical electric field Ecrit is reached is a general theory that agrees well with experimental results. This electric field concentration is relieved to reduce the maximum electric field Ema for a constant applied voltage.
By lowering x, the breakdown voltage can be improved.
【０００３】図３０は従来技術の最も基本的な構造の半
導体素子１０１の平面図(a)とＢ−Ｂ断面図(b)である。
図３０に示すように従来例の半導体素子（ダイオード）
１０１は、Ｎ+型の半導体基板１と、半導体基板１上に
Ｎ-型でエピタキシャル成長により形成されたシリコン
層２とを備える。シリコン層２の表層中央部には活性領
域となるＰ+型領域３が不純物導入により形成され、シ
リコン層２の表層外周部にはＮ+型周縁領域４が不純物
導入により形成され、残存部がＮ-型領域５となる。さ
らに従来例の半導体素子１０１は、シリコン層２の表面
に形成されたシリコン酸化膜等の絶縁膜６と、絶縁膜６
に設けられた開口部を介してＰ+型領域３に接続する陽
極電極７と、半導体基板１の裏面に被着された陰極電極
８とを備えて構成される。陽極電極７、陰極電極８はア
ルミニウム等により構成される。FIG. 30 is a plan view (a) and a BB sectional view (b) of a semiconductor device 101 having the most basic structure of the prior art.
As shown in FIG. 30, a conventional semiconductor device (diode)
101 includes an N + type semiconductor substrate 1, and an N − type silicon layer 2 formed on the semiconductor substrate 1 by epitaxial growth. A P + type region 3 serving as an active region is formed by introducing impurities in the central portion of the surface layer of the silicon layer 2, and an N + type peripheral region 4 is formed by introducing impurities in the outer peripheral portion of the surface layer of the silicon layer 2. It becomes the N − type region 5. Furthermore, in the semiconductor element 101 of the conventional example, the insulating film 6 such as a silicon oxide film formed on the surface of the silicon layer 2 and the insulating film 6 are used.
An anode electrode 7 connected to the P + type region 3 through an opening provided in the cathode electrode 8 and a cathode electrode 8 deposited on the back surface of the semiconductor substrate 1. The anode electrode 7 and the cathode electrode 8 are made of aluminum or the like.
【０００４】電極７、８間に逆方向電圧が印加される
と、Ｐ+-Ｎ-接合面の両側に空乏層１０が広がる。Ｎ-型
領域５はＰ+型領域３に比較的して不純物濃度が低いた
め、この空乏層１０はＮ-側に大きく広がる。空乏層１
０の拡大は、高濃度領域により抑えられる。すなわち、
空乏層１０の横方向の拡大はＮ+型周縁領域４により、
縦方向の拡大は半導体基板１により抑えられる。Ｐ+-Ｎ
-接合部、特に円筒コーナー部１１に、急峻な電界集中
による最大電界Ｅｍａｘが生じ、より高い逆電圧を印加
すれば、降伏、ひいては破壊が起こり得る。図３０(a)
に示す球状コーナー部１２は最も高い電界が生じ、危険
な個所である。高耐圧に作製するためには、Ｎ-型領域
５を大きく低濃度にすることにより、空乏層１０を広範
囲に広げるための幅を確保する必要がある。空乏層１０
が広範囲に広がるようにすると、印加電圧を広範囲の電
界分布により負担し、最大電界の上昇を抑えることがで
きる。このように活性領域であるＰ+型領域３の縁から
Ｎ+型周縁領域４までの距離Ｗｓは主として耐圧維持の
ために必要となる。ここで、Ｗｓを耐圧維持領域幅と呼
ぶ。また、活性領域幅をＷｍ、Ｎ+型周縁領域４の幅を
Ｗｅとする。以上説明したことから分かるように、より
高耐圧にするために耐圧維持領域幅Ｗｓをより大きくす
ることが必要となる。現在、５００V系素子では耐圧維
持領域幅Ｗｓを５０〜１５０μｍ程度としており、一般
的にも、耐圧維持領域幅Ｗｓとして少なくとも５０μｍ
以上の幅を確保しなければならないといわれている。When a reverse voltage is applied between the electrodes 7 and 8, the depletion layer 10 spreads on both sides of the P + -N - junction surface. Since the N − type region 5 has a relatively low impurity concentration as compared with the P + type region 3, the depletion layer 10 spreads largely to the N − side. Depletion layer 1
The expansion of 0 is suppressed by the high density region. That is,
The lateral expansion of the depletion layer 10 is caused by the N + type peripheral region 4.
The expansion in the vertical direction is suppressed by the semiconductor substrate 1. P + -N
- joint, in particular the cylindrical corner portion 11, the maximum electric field Emax is caused by steep electric field concentration, by applying a higher reverse voltage breakdown can occur and destruction. Figure 30 (a)
The spherical corner portion 12 shown in is a dangerous place where the highest electric field is generated. In order to manufacture a high breakdown voltage, it is necessary to secure a width for widening the depletion layer 10 in a wide range by making the N − type region 5 large and low in concentration. Depletion layer 10
Is spread over a wide range, the applied voltage is borne by the wide range of electric field distribution, and the rise of the maximum electric field can be suppressed. Thus, the distance Ws from the edge of the P + type region 3 which is the active region to the N + type peripheral region 4 is mainly necessary for maintaining the breakdown voltage. Here, Ws is called the breakdown voltage maintaining region width. The width of the active region is Wm, and the width of the N + type peripheral region 4 is We. As can be seen from the above description, it is necessary to increase the breakdown voltage maintaining region width Ws in order to increase the breakdown voltage. At present, the withstand voltage maintaining region width Ws is set to about 50 to 150 μm in a 500 V element, and generally, the withstand voltage maintaining region width Ws is at least 50 μm.
It is said that the above range must be secured.
【０００５】更なる高耐圧化のため、上記半導体素子１
０１に一又は複数本のガードリング構造やＪＴＥ（Junc
tion-Termination -Extension）構造を設けることがし
ばしば行われる。図３１は、従来のガードリングを備え
た半導体素子１０２の平面図(a)及びＣ−Ｃ断面図(b)で
ある。図３２は従来のＪＴＥ構造を備えた半導体素子１
０３の平面図(a)及びＤ−Ｄ断面図(b)である。図３１に
示すように半導体素子（ダイオード）１０２では、ガー
ドリング１３を設けるために、半導体素子１０１に対し
てさらに幅Ｗｇが追加して必要となる。Ｗｇは現在５０
〜１００μｍ程度必要とされている。したがって、Ｗｇ
を加えた耐圧維持領域幅Ｗｓは１００μｍ以上必要とな
る。図３２に示すように半導体素子（ダイオード）１０
３では、ＪＴＥ構造として、Ｐ+型領域３の周辺(場合に
より底面にも)に接合するＰ-型領域１4を設けるため
に、半導体素子１０１に対してさらに幅Ｗｊが追加して
必要となる。Ｗｊも現在５０〜１００μｍ程度必要とさ
れている。したがって、Ｗｊを加えた耐圧維持領域幅Ｗ
ｓもやはり１００μｍ以上必要となる。In order to further increase the breakdown voltage, the above semiconductor device 1 is used.
01 or more guard ring structure or JTE (Junc
A tion-Termination-Extension) structure is often provided. FIG. 31 is a plan view (a) and a CC cross-sectional view (b) of a semiconductor device 102 including a conventional guard ring. FIG. 32 shows a semiconductor device 1 having a conventional JTE structure.
03 is a plan view (a) and a DD sectional view (b) of FIG. As shown in FIG. 31, in the semiconductor element (diode) 102, in order to provide the guard ring 13, a width Wg needs to be added to the semiconductor element 101. Wg is currently 50
Approximately 100 μm is required. Therefore, Wg
The withstand voltage maintaining region width Ws including 100 μm or more is required. As shown in FIG. 32, the semiconductor element (diode) 10
In No. 3, in order to provide the P − -type region 14 that is joined to the periphery of the P + -type region 3 (and also on the bottom surface in some cases) as the JTE structure, an additional width Wj is required for the semiconductor element 101. . Wj is also currently required to be about 50 to 100 μm. Therefore, the breakdown voltage maintaining region width W including Wj
s also needs to be 100 μm or more.
【０００６】一方、従来のパワーＭＯＳ素子やパワーＩ
ＧＢＴ素子には、パワーＭＯＳ素子にあってはＮ+型、
パワーＩＧＢＴ素子にあってはＰ+型の半導体基板上に
成膜されたＮ-エピタキシャル層の中央に活性セル領域
が形成され、その周囲にアルミ等からなるゲートパッド
を敷設する領域としてＰ+型領域が形成され、さらにそ
の周囲に間隔隔ててガードリングとしてのＰ+型領域が
形成され、さらにその周囲に一定幅のＮ-耐圧維持領域
が形成された構造のものがある。活性セル領域には多数
のＭＯＳセルが形成される。On the other hand, conventional power MOS devices and power I
The GBT element is an N + type in the power MOS element,
N In the power IGBT element has been formed on a semiconductor substrate of P + -type - active cell area in the middle of the epitaxial layer is formed, P + -type as a region for laying the gate pad made of aluminum or the like on the periphery There is a structure in which a region is formed, a P + type region as a guard ring is further formed around the region, and an N − breakdown voltage maintaining region of a constant width is further formed around the region. A large number of MOS cells are formed in the active cell region.
【０００７】[0007]
【発明が解決しようとする課題】以上の従来技術によれ
ば、耐圧維持領域幅Ｗｓが大きくなり、素子全体に対す
る活性領域の面積率が低下し素子の利用効率が低下する
という問題がある。特に、従来のパワーＭＯＳ素子やパ
ワーＩＧＢＴ素子にあっては、活性領域の周囲に耐圧維
持領域とは別にゲートアルミ線敷設領域を割り当てる必
要があるため、活性領域の面積率の低下は著しい。ま
た、素子の外形寸法を小さくしても一定の耐圧を得るた
めには、耐圧維持領域を縮小することはできない。その
ため、活性領域の面積率は素子の外形寸法が小さくなる
ほど低下する傾向にある。その傾向を知るために以下の
概算を行った。According to the above-mentioned conventional technique, there is a problem that the breakdown voltage maintaining region width Ws becomes large, the area ratio of the active region to the entire device is reduced, and the utilization efficiency of the device is reduced. In particular, in the conventional power MOS element or power IGBT element, since it is necessary to allocate a gate aluminum wire laying region around the active region in addition to the breakdown voltage maintaining region, the area ratio of the active region is significantly reduced. Further, even if the outer dimensions of the element are reduced, the breakdown voltage maintaining region cannot be reduced in order to obtain a constant breakdown voltage. Therefore, the area ratio of the active region tends to decrease as the outer dimension of the element decreases. In order to know the tendency, the following estimation was performed.
【０００８】図３３に示すように、実際の丸みＲ１，Ｒ
２を省略して正方形とし、近似計算した。Ｌは素子の一
辺の長さ、Ｗｍは活性領域幅、Ｗｓは耐圧維持領域幅、
ＷｅはＮ+型周縁領域幅である。図３４の表に示すよう
に、０．５〜１０（ｍｍ）の異なる１２通りのチップ外
形寸法に対して計算した。耐圧維持領域幅Ｗｓは耐圧レ
ベルにより一定の幅（ここでは０．１３（ｍｍ））が必
要となる。また、Ｎ+型周縁領域幅Ｗｅは素子分離・切
断のために一定の幅必要となり、現状０．０５（ｍｍ）
程度は必要となるので、０．０５（ｍｍ）とした。その
結果、活性領域幅Ｗｍは図３４の表に示すように変化す
る。これに伴って活性領域の周辺長（Ｗｍ×４）も図３
４の表に示すように変化する。チップ全体の面積をＳ、
活性領域の面積をＳ１、耐圧維持領域の面積をＳ２、Ｎ
+型周縁領域の面積をＳ３（Ｓ＝Ｓ1＋Ｓ２＋Ｓ３）とし
てそれぞれ算出してまとめると図３４の表に示す通りと
なる。さらに、素子全体に対する各領域の面積率Ｓ１／
Ｓ，Ｓ２／Ｓ，Ｓ３／Ｓを算出しまとめると、図３４の
表に示す通りとなる。また、素子外形寸法Ｌの変化に伴
う各面積率Ｓ１／Ｓ，Ｓ２／Ｓ，Ｓ３／Ｓの変化をグラ
フ化したものを図３５に示す。As shown in FIG. 33, the actual roundness R1, R
Approximate calculation was performed by omitting 2 to make a square. L is the length of one side of the element, Wm is the active region width, Ws is the breakdown voltage maintaining region width,
We is the N + type peripheral region width. As shown in the table of FIG. 34, calculation was performed for 12 different chip outer dimensions of 0.5 to 10 (mm). The withstand voltage maintaining region width Ws needs to have a constant width (here, 0.13 (mm)) depending on the withstand voltage level. Further, the N + type peripheral region width We needs a certain width for element isolation and cutting, and is currently 0.05 (mm).
Since the degree is necessary, it was set to 0.05 (mm). As a result, the active region width Wm changes as shown in the table of FIG. Along with this, the peripheral length (Wm × 4) of the active region is also shown in FIG.
4 as shown in the table. The area of the entire chip is S,
The area of the active region is S1, the area of the breakdown voltage maintaining region is S2, N
The area of the + type peripheral region is calculated as S3 (S = S1 + S2 + S3) and summarized, as shown in the table of FIG. Furthermore, the area ratio S1 / of each region with respect to the entire device
When S, S2 / S, S3 / S are calculated and summarized, the result is as shown in the table of FIG. Further, FIG. 35 shows a graph showing changes in the area ratios S1 / S, S2 / S, and S3 / S with changes in the element outer dimension L.
【０００９】図３４の表又は図３５のグラフから明らか
なように、素子外形寸法が小さくなるほど活性領域の占
有面積率Ｓ１／Ｓが減少し、耐圧維持領域の占有面積率
Ｓ２／Ｓ及びＮ+型周縁領域の占有面積率Ｓ３／Ｓは増
大して素子の利用効率が低下する。比較的大きな素子、
例えば素子外形寸法７ｍｍ以上では、その利用効率は９
０％以上と、さほど悪くないが、素子外形寸法１ｍｍ以
下では４１％以下となり、素子の小型化・微細化に伴っ
て耐圧維持領域の占有面積増大による活性領域の面積率
の低下は深刻な問題となる。以上の計算では、ガードリ
ング構造やＪＴＥ構造を備えない素子について計算した
が、さらなる高耐圧を確保するためにガードリング構造
やＪＴＥ構造を備えた場合、耐圧維持領域幅Ｗｓが上記
設定（０．１３（ｍｍ））より大きくなり、したがっ
て、耐圧維持領域の占有面積率Ｓ２／Ｓが大きくなる。
その結果、活性領域の面積率低下の問題が比較的大きな
素子外形寸法のものにまで及びこと、及び、より深刻と
なることは必至である。一方、図３４の表に示したよう
に活性領域の周辺長（Ｗｍ×４）の増加は、プレーナ構
造特有の円筒、球状等の曲面接合の増大に直結する。曲
面接合はエネルギー負荷の大きい危険な部分（弱い部
分）であるため、曲面接合の増大は素子の性能、信頼性
の低下を招き設計上の制約となる。しかも、活性領域の
周辺長（Ｗｍ×４）は素子外形寸法に依存するため、素
子外形寸法が異なるたびに異なる耐圧設計を強いられて
いた。As is clear from the table of FIG. 34 or the graph of FIG. 35, the occupation area ratio S1 / S of the active region decreases as the outer dimension of the element decreases, and the occupation area ratio S2 / S and N + of the breakdown voltage maintaining region decrease. The occupation area ratio S3 / S of the mold peripheral region increases and the utilization efficiency of the element decreases. Relatively large element,
For example, if the external dimensions of the element are 7 mm or more, the utilization efficiency is 9
Although it is not so bad as 0% or more, it becomes 41% or less when the outer dimension of the element is 1 mm or less, and the decrease in the area ratio of the active region due to the increase in the occupying area of the breakdown voltage maintaining region accompanying the miniaturization and miniaturization of the device is a serious problem. Becomes In the above calculation, an element having no guard ring structure or JTE structure was calculated. However, when a guard ring structure or a JTE structure is provided to secure a higher withstand voltage, the withstand voltage maintaining region width Ws is set to the above setting (0. 13 (mm)), and therefore the occupation area ratio S2 / S of the breakdown voltage maintaining region increases.
As a result, it is inevitable that the problem of reduction in the area ratio of the active region extends to a relatively large element outer dimension and becomes more serious. On the other hand, as shown in the table of FIG. 34, the increase in the peripheral length (Wm × 4) of the active region is directly connected to the increase in the curved surface joining such as the cylinder and the sphere, which is peculiar to the planar structure. Since the curved surface joint is a dangerous portion (weak portion) where the energy load is large, an increase in the curved surface joint causes a decrease in the performance and reliability of the device, which is a design constraint. Moreover, since the peripheral length (Wm × 4) of the active region depends on the outer dimensions of the element, different withstand voltage designs have been required each time the outer dimensions of the element differ.
【００１０】本発明は以上の従来技術における問題に鑑
みてなされたものであって、耐圧維持領域の増大、ひい
ては素子の大面積化を招くことなく高耐圧化を図ること
ができる構造の半導体素子を提供することを課題とす
る。また、耐圧を低下させること無く、素子全体に対す
る活性領域の占有する面積を拡大することができる構造
の半導体素子を提供することを課題とする。さらには耐
圧維持領域を有効利用することにより活性領域の占有す
る面積を拡大することができる構造の半導体素子を提供
することを課題とする。また、耐圧を低下させること無
く、素子外形寸法の変更に伴う曲面接合の増減を回避で
きる構造の半導体素子を提供することを課題とする。The present invention has been made in view of the above problems in the prior art, and is a semiconductor device having a structure capable of achieving a high breakdown voltage without increasing the breakdown voltage maintaining region and consequently increasing the area of the device. The challenge is to provide. Another object of the present invention is to provide a semiconductor device having a structure in which the area occupied by the active region with respect to the entire device can be increased without lowering the breakdown voltage. Another object is to provide a semiconductor device having a structure in which the area occupied by the active region can be expanded by effectively utilizing the breakdown voltage maintaining region. It is another object of the present invention to provide a semiconductor element having a structure capable of avoiding an increase or decrease in curved surface bonding due to a change in element outer dimension without lowering the breakdown voltage.
【００１１】[0011]
【課題を解決するための手段】以上の課題を解決するた
めの請求項１記載の発明は、例えば図１に示すように、
第一導電型の半導体素材２の表面へ反対導電型である第
二導電型の不純物を選択的に導入し、不純物活性化処理
を施すことより形成された第二導電型活性領域２１と、
前記半導体素材内の領域であって前記第二導電型活性領
域に接合する第一導電型領域２２と、前記表面上を所定
パターンで覆う絶縁膜２３と、前記表面の外周に連続す
る外周面を前記表面から所定の深さまで被覆する保護膜
２４，２５と、前記第一導電型領域側の第一電極２７
と、前記絶縁膜に設けられた開口部を介して前記第二導
電型活性領域に接続する第二電極２６とを備える半導体
素子において、前記第一導電型領域と前記第二導電型活
性領域とで構成されるＰＮ接合の一方の終端が前記絶縁
膜下の前記表面上に在り、他方の終端が前記保護膜下の
前記外周面上に在り、前記第一導電型領域が前記第二導
電型活性領域に包囲された範囲で前記表面に露出し、そ
の露出面が前記絶縁膜により覆われてなることを特徴と
する半導体素子である。The invention according to claim 1 for solving the above-mentioned problems is, for example, as shown in FIG.
A second-conductivity-type active region 21 formed by selectively introducing impurities of the second-conductivity-type opposite to the first-conductivity-type semiconductor material 2 and performing an impurity activation treatment;
A first conductivity type region 22 that is a region in the semiconductor material and is joined to the second conductivity type active region, an insulating film 23 that covers the surface with a predetermined pattern, and an outer peripheral surface that is continuous with the outer periphery of the surface. Protective films 24 and 25 covering the surface to a predetermined depth, and a first electrode 27 on the side of the first conductivity type region.
And a second electrode 26 connected to the second conductivity type active region through an opening provided in the insulating film, wherein the first conductivity type region and the second conductivity type active region are provided. One end of the PN junction formed on the surface under the insulating film, the other end on the outer peripheral surface under the protective film, and the first conductivity type region is the second conductivity type. The semiconductor element is exposed on the surface in a range surrounded by the active region, and the exposed surface is covered with the insulating film.
【００１２】前記第一導電型の半導体素材としては、Ｎ
+型又はＰ+型半導体基板上に積層したＮ-型半導体層
や、Ｎ型単結晶基板が好適に用いられるが、Ｐ型を用い
ても良い。前記第一電極はこれらの半導体基板の裏面に
付設すれば足りる。表面の外周に連続する外周面は、メ
サ溝、トレンチ溝、Ｕ字溝等により形成することがで
き、この外周面を被覆する保護膜としては、熱ＳｉＯ２
膜や、ガラス・パシベーション、ＴＥＯＳ酸化膜、Ｐｏ
ｌｙ−Ｓｉ等を用いることができる。請求項１記載の発
明において、第二導電型活性領域は活性化処理された不
純物活性領域である。また、同一ＰＮ接合の終端が絶縁
膜下の半導体素材表面上及び保護膜下の半導体素材外周
面上に在るように第二導電型活性領域が形成される。一
方、この第二導電型活性領域に包囲された範囲で第一導
電型領域が表面に露出し、且つ、その露出面が絶縁膜に
より覆われることで耐圧維持領域が構成される。すなわ
ち、上述した従来技術においては活性領域の周囲に耐圧
維持領域が形成されるのに対し、本発明においては耐圧
維持領域の周囲に活性領域が形成される。The first conductivity type semiconductor material is N
An N − type semiconductor layer laminated on a + type or P + type semiconductor substrate or an N type single crystal substrate is preferably used, but a P type may be used. It suffices if the first electrode is attached to the back surface of these semiconductor substrates. An outer peripheral surface continuous to the outer periphery of the surface can be formed by a mesa groove, a trench groove, a U-shaped groove, or the like.
Film, glass passivation, TEOS oxide film, Po
ly-Si or the like can be used. In the invention according to claim 1, the second conductivity type active region is an impurity active region which has been activated. Further, the second conductivity type active region is formed such that the ends of the same PN junction are on the surface of the semiconductor material under the insulating film and on the outer peripheral surface of the semiconductor material under the protective film. On the other hand, the first conductivity type region is exposed on the surface in the range surrounded by the second conductivity type active region, and the exposed surface is covered with the insulating film to form the breakdown voltage maintaining region. That is, in the above-mentioned conventional technique, the breakdown voltage maintaining region is formed around the active region, whereas in the present invention, the active region is formed around the breakdown voltage maintaining region.
【００１３】かかる構造の請求項１記載の発明によれ
ば、次のような利点がある（後のシミュレーションにお
いても説明する。）。
（１）電界相殺効果
第二導電型活性領域の内周面上の任意の一点から対岸の
内周面へ伸びる空乏層が、その対岸から逆向きに伸びて
くる空乏層と干渉し、その干渉領域で互いに逆方向の電
界ベクトル成分が打ち消し合って電界強度を低下させる
電界相殺効果が得られるのである。この電界相殺効果
は、第二導電型活性領域の内周面上の一点から対岸の内
周面への距離、すなわち、ＰＮ接合の対岸距離が比較的
大きい場合は得られないが、ＰＮ接合の対岸距離が小さ
いほど著しくなる。かかる電界相殺効果により、リング
状又は多数穴明き状の第二導電型活性領域の内周面下端
部に形成される曲面接合に生じる最大電界強度が低下す
るので、高耐圧の半導体素子がもたらされる。
（２）活性領域外周
第一導電型領域と第二導電型活性領域とからなるＰＮ接
合の外周部は平面接合となり、その終端は半導体素材外
周面を被覆する保護膜下に在るため、素子外周面での高
電界による不具合は阻止される。また本発明によると、
かかる外周接合終端の最大電界をも低下させることがで
きる場合がある。
（３）活性領域の占有面積拡大
本発明においては耐圧維持領域の周囲に活性領域が形成
されるので、耐圧維持領域の幅が従来と等しいとして見
積もっても、活性領域の占有面積率は従来に比較して大
きくなる。また、上記電界相殺効果を利用する場合、従
来ほど耐圧維持領域の幅を要しないため、さらに活性領
域の占有面積率は大きくなって、且つ、耐圧が向上す
る。
（４）曲面接合の不変性
本発明においては耐圧維持領域の周囲に活性領域が形成
されるので、素子の外形寸法の変更に伴い活性領域の面
積を拡大するためには活性領域の外周位置を変更すれば
よい。そのため、活性領域の内周、すなわち、耐圧維持
領域の外周を変更する必要はない。活性領域の内周（す
なわち、耐圧維持領域の外周）を変更する必要がないか
ら、活性領域の内周下端に形成される曲面接合の面積を
一定に保つことができる。According to the invention described in claim 1 having such a structure, there are the following advantages (which will be described in a later simulation). (1) Electric field cancellation effect A depletion layer extending from any one point on the inner surface of the second conductivity type active region to the inner surface of the opposite bank interferes with a depletion layer extending in the opposite direction from the opposite bank, and the interference occurs. The electric field vector components in opposite directions cancel each other out in the region, and an electric field canceling effect of reducing the electric field strength is obtained. This electric field canceling effect cannot be obtained when the distance from one point on the inner peripheral surface of the second conductivity type active region to the inner peripheral surface on the opposite bank, that is, when the opposite bank distance of the PN junction is relatively large. It becomes remarkable as the opposite bank distance is small. Due to the electric field offsetting effect, the maximum electric field strength generated in the curved surface junction formed at the lower end of the inner peripheral surface of the ring-shaped or multi-hole-shaped active region of the second conductivity type is lowered. Be done. (2) Outer periphery of active region The outer periphery of the PN junction consisting of the first conductivity type active region and the second conductivity type active region is a planar junction, and its end is under the protective film covering the outer peripheral surface of the semiconductor material. Problems due to the high electric field on the outer peripheral surface are prevented. Also according to the invention,
In some cases, the maximum electric field at the peripheral junction termination can be reduced. (3) Expansion of Occupied Area of Active Region In the present invention, since the active region is formed around the breakdown voltage maintaining region, even if it is estimated that the width of the breakdown voltage maintaining region is equal to the conventional one, the occupation area ratio of the active region is not It becomes large in comparison. Further, when utilizing the electric field canceling effect, the width of the breakdown voltage maintaining region is not required as much as in the conventional case, so that the occupied area ratio of the active region is further increased and the breakdown voltage is improved. (4) Invariance of curved surface junction In the present invention, the active region is formed around the breakdown voltage maintaining region. Therefore, in order to expand the area of the active region along with the change of the external dimensions of the element, the outer peripheral position of the active region is set. You can change it. Therefore, it is not necessary to change the inner circumference of the active region, that is, the outer circumference of the breakdown voltage maintaining region. Since it is not necessary to change the inner circumference of the active region (that is, the outer circumference of the breakdown voltage maintaining region), the area of the curved surface junction formed at the lower end of the inner circumference of the active region can be kept constant.
【００１４】以上の点に起因して本発明によれば、耐圧
維持領域の増大、ひいては素子の大面積化を招くことな
く高耐圧化を図ることができるばかりでなく、耐圧維持
領域を従来技術より縮小し素子の小面積化を図りつつ高
耐圧化を図ることも可能である。また本発明によれば、
耐圧を低下させること無く、素子全体に対する活性領域
の占有する面積を拡大することができる。また本発明に
よれば、耐圧を低下させること無く、素子外形寸法の変
更に伴う曲面接合の増減を回避できる。以上により、小
型、高耐圧、高信頼性の半導体素子を得ることが可能で
ある。Due to the above points, according to the present invention, not only can the breakdown voltage maintaining region be increased, but the breakdown voltage maintaining region can be increased without increasing the area of the element, and the breakdown voltage maintaining region can be formed by the conventional technique. It is also possible to further increase the breakdown voltage while reducing the area of the device. According to the invention,
The area occupied by the active region with respect to the entire device can be expanded without lowering the breakdown voltage. Further, according to the present invention, it is possible to avoid an increase or decrease in curved surface bonding due to a change in the external dimensions of the element without lowering the breakdown voltage. As described above, it is possible to obtain a semiconductor device having a small size, high breakdown voltage, and high reliability.
【００１５】請求項２記載の発明は、例えば図２に示す
ように、前記半導体素材の表面へ第一導電型の不純物を
選択的に導入することより、前記第一導電型領域より高
濃度の第一導電型高濃度領域２９が、前記第一導電型領
域２２に包囲された範囲で前記表面に露出して形成さ
れ、その露出面が前記絶縁膜２３に設けられた開口部を
介して前記第一電極３０と接続してなることを特徴とす
る請求項１に記載の半導体素子である。According to a second aspect of the present invention, for example, as shown in FIG. 2, by selectively introducing impurities of the first conductivity type into the surface of the semiconductor material, the concentration of the impurities is higher than that of the first conductivity type region. The first-conductivity-type high-concentration region 29 is formed so as to be exposed on the surface in a range surrounded by the first-conductivity-type region 22, and the exposed surface is formed through an opening provided in the insulating film 23. The semiconductor element according to claim 1, wherein the semiconductor element is connected to the first electrode 30.
【００１６】したがって請求項２記載の発明によれば、
第一電極及び第二電極が素子表面側に形成されるので、
裏面側から表面側への配線手段を要することなくプリン
ト回路基板等に実装することができる。Therefore, according to the invention of claim 2,
Since the first electrode and the second electrode are formed on the element surface side,
It can be mounted on a printed circuit board or the like without requiring wiring means from the back surface side to the front surface side.
【００１７】請求項３記載の発明は、例えば図３に示す
ように、前記第一導電型領域３３が前記第二導電型活性
領域３２に包囲された複数の部分で前記表面に露出して
なることを特徴とする請求項１に記載の半導体素子であ
る。According to a third aspect of the present invention, for example, as shown in FIG. 3, the first conductivity type region 33 is exposed on the surface at a plurality of portions surrounded by the second conductivity type active region 32. It is a semiconductor element of Claim 1 characterized by the above-mentioned.
【００１８】したがって請求項３記載の発明によれば、
第一導電型領域の半導体素材表面への露出部を複数とす
るので、ＰＮ接合の対岸距離を容易に小さくすることが
でき、その結果、前記電界相殺効果を高めることができ
る。また、第一導電型領域の半導体素材表面への露出部
を素子表面に均一に配置することにより、素子表面にお
いて広範且つ均一に電界相殺効果を利用した耐圧維持領
域を形成することができる。第一導電型領域の半導体素
材表面への露出部のパターンは、複数本の縞状パター
ン、散点パターンその他、中央の円形パターンとこれを
一重又は二重以上に囲む一又は複数のリング状パターン
などいずれのパターンであっても良い。Therefore, according to the invention of claim 3,
Since there are a plurality of exposed portions of the first conductivity type region on the surface of the semiconductor material, the opposite bank distance of the PN junction can be easily reduced, and as a result, the electric field cancellation effect can be enhanced. Further, by uniformly disposing the exposed portion of the first conductivity type region on the surface of the semiconductor material on the device surface, it is possible to form a breakdown voltage maintaining region that widely and uniformly utilizes the electric field cancellation effect on the device surface. The pattern of the exposed portion of the first conductivity type region on the surface of the semiconductor material is a plurality of striped patterns, scattered patterns, etc., a circular pattern in the center and one or more ring-shaped patterns that surround it in a single or double or more manner. Any pattern may be used.
【００１９】請求項４記載の発明は、例えば図５に示す
ように、前記第二導電型活性領域２１に包囲された範囲
内に、前記第二導電型活性領域２１の内周に沿って形成
された一又は二本以上のガードリング３６a,３６b,３６
cを有することを特徴とする請求項１又は請求項３に記
載の半導体素子である。According to a fourth aspect of the present invention, for example, as shown in FIG. 5, the second conductivity type active region 21 is surrounded by the second conductivity type active region 21 along the inner circumference thereof. One or more guard rings 36a, 36b, 36
The semiconductor device according to claim 1, wherein the semiconductor device has c.
【００２０】したがって請求項４記載の発明によれば、
ガードリングを備えたより高耐圧の耐圧維持構造が得ら
れる。請求項３を引用する請求項４の発明においては、
第一導電型領域の半導体素材表面への露出部毎に、ガー
ドリングを構成することも有効である。Therefore, according to the invention of claim 4,
A breakdown voltage maintaining structure having a higher breakdown voltage including a guard ring can be obtained. In the invention of claim 4 which cites claim 3,
It is also effective to configure a guard ring for each exposed portion of the first conductivity type region on the surface of the semiconductor material.
【００２１】請求項５記載の発明は、例えば図６に示す
ように、前記第二導電型活性領域が、比較的高濃度の第
二導電型高濃度領域２１と比較的低濃度の第二導電型低
濃度領域３８とから構成され、前記第二導電型低濃度領
域が前記第二導電型高濃度領域の少なくとも内周部に接
合し、前記第二導電型高濃度領域の内周に隣接して前記
表面にリング状に露出するように形成され、前記第二導
電型低濃度領域に包囲された範囲で前記第一導電型領域
３７が前記表面に露出してなることを特徴とする請求項
１又は請求項３に記載の半導体素子である。According to a fifth aspect of the present invention, for example, as shown in FIG. 6, the second conductivity type active region has a relatively high concentration second conductivity type high concentration region 21 and a relatively low concentration second conductivity type. And a second conductivity type low concentration region, the second conductivity type low concentration region is joined to at least the inner peripheral portion of the second conductivity type high concentration region, and is adjacent to the inner periphery of the second conductivity type high concentration region. 7. The first conductivity type region 37 is exposed to the surface in a range surrounded by the second conductivity type low concentration region so as to be exposed on the surface in a ring shape. The semiconductor device according to claim 1 or claim 3.
【００２２】したがって請求項５記載の発明によれば、
第二導電型低濃度領域によりＪＴＥ（Junction-Termina
tion -Extension）構造が構成される。すなわち、空乏
層が第二導電型低濃度領域内で拡張されて電界集中が緩
和され、一定印加電圧に対する最大電界Ｅｍａｘが下が
ることとなり、より高耐圧の耐圧維持構造が得られる。
請求項３を引用する請求項５の発明においては、第一導
電型領域の半導体素材表面への露出部毎に、第二導電型
低濃度領域によりなるＪＴＥ構造を構成することも有効
である。Therefore, according to the invention of claim 5,
JTE (Junction-Termina)
tion-Extension) structure is constructed. That is, the depletion layer is expanded in the second-conductivity-type low-concentration region, the electric field concentration is relaxed, the maximum electric field Emax for a constant applied voltage is lowered, and a breakdown voltage maintaining structure having a higher breakdown voltage is obtained.
In the invention of claim 5 which cites claim 3, it is also effective to configure a JTE structure including a second conductivity type low concentration region for each exposed portion of the first conductivity type region to the surface of the semiconductor material.
【００２３】請求項６記載の発明は、例えば図７に示す
ように、第一導電型の半導体素材２の表面へ反対導電型
である第二導電型の不純物を選択的に導入し、不純物活
性化処理を施すことより形成された第二導電型活性領域
３９と、前記半導体素材内の領域であって前記第二導電
型活性領域に接合する第一導電型領域４０と、前記表面
上を所定パターンで覆う絶縁膜２３と、前記表面の外周
に連続する外周面を前記表面から所定の深さまで被覆す
る保護膜２４と、前記第一導電型領域側の第一電極２７
と、前記絶縁膜に設けられた開口部を介して前記第二導
電型活性領域に接続する第二電極４４とを備える半導体
素子において、前記第一導電型領域と前記第二導電型活
性領域とで構成されるＰＮ接合の一方の終端が前記絶縁
膜下の前記表面上に在り、他方の終端が前記保護膜下の
前記外周面上に在り、前記第一導電型領域４０が前記第
二導電型活性領域３９に包囲された複数の部分で前記表
面に露出し、その各露出面上にゲート絶縁膜４２が敷設
され、該ゲート絶縁膜上にゲート電極４３が敷設されて
なるＭＩＳ素子を複数個備え、前記第一導電型領域は前
記第二導電型活性領域に包囲された他の部分で前記表面
に露出し、その露出面が前記絶縁膜２３bにより覆わ
れ、前記各ゲート電極と導通する外部接続用ゲート電極
パッド４５が前記他の部分を覆う前記絶縁膜２３ｂ上に
設けられてなることを特徴とする半導体素子である。According to a sixth aspect of the present invention, for example, as shown in FIG. 7, impurities of the second conductivity type having the opposite conductivity type are selectively introduced into the surface of the semiconductor material 2 of the first conductivity type to activate the impurities. A second conductivity type active region 39 formed by subjecting the semiconductor material to a heat treatment, a first conductivity type region 40 in the semiconductor material which is bonded to the second conductivity type active region, and a predetermined surface. An insulating film 23 that is covered with a pattern, a protective film 24 that covers the outer peripheral surface continuous to the outer periphery of the surface to a predetermined depth from the surface, and a first electrode 27 on the first conductivity type region side.
And a second electrode 44 connected to the second conductivity type active region through an opening provided in the insulating film, wherein a first conductivity type region and a second conductivity type active region are provided. One end of the PN junction formed on the surface under the insulating film, the other end on the outer peripheral surface under the protective film, and the first conductivity type region 40 has the second conductivity type. A plurality of MIS elements which are exposed on the surface at a plurality of portions surrounded by the mold active region 39, a gate insulating film 42 is laid on each exposed surface, and a gate electrode 43 is laid on the gate insulating film. The first conductivity type region is exposed to the surface at another portion surrounded by the second conductivity type active region, and the exposed surface is covered with the insulating film 23b and is electrically connected to each gate electrode. The external connection gate electrode pad 45 is different from the above. The semiconductor element is provided on the insulating film 23b that covers the portion.
【００２４】したがって請求項６記載の発明によれば、
第一導電型領域の半導体素材表面への露出部を覆う絶縁
膜上に外部接続用ゲート電極パッドを形成することがで
きる。すなわち、耐圧維持領域上にゲートパッドを配す
ることができる。耐圧維持領域上にゲートパッドを配す
ることができるので、耐圧維持領域の上部をゲートパッ
ド敷設領域として立体的に有効利用することにより、従
来技術に比較して、活性領域の占有する面積をゲートパ
ッド敷設領域分拡大することができる。Therefore, according to the invention of claim 6,
The external connection gate electrode pad can be formed on the insulating film covering the exposed portion of the first conductivity type region on the surface of the semiconductor material. That is, the gate pad can be arranged on the breakdown voltage maintaining region. Since the gate pad can be arranged on the breakdown voltage maintaining region, by effectively using the upper part of the breakdown voltage maintaining region as a gate pad laying region three-dimensionally, the area occupied by the active region can be reduced compared to the conventional technique. The pad laying area can be expanded.
【００２５】請求項７記載の発明は、例えば図８に示す
ように、第一導電型の半導体素材２の表面へ反対導電型
である第二導電型の不純物を選択的に導入することより
該半導体素材の表層外周部にリング状に形成された第二
導電型リング領域４６と、前記半導体素材の表面へ第二
導電型の不純物を選択的に導入し、不純物活性化処理を
施すことより前記第二導電型リング領域の内側に形成さ
れた第二導電型活性領域４７と、前記半導体素材内の領
域であって前記第二導電型リング領域及び前記第二導電
型活性領域の両者に接合し該両者間に介在する第一導電
型領域４８と、前記表面上を所定パターンで覆う絶縁膜
４９と、前記表面の外周に連続する外周面を前記表面か
ら所定の深さまで被覆する保護膜２４と、前記第一導電
型領域側の第一電極２７と、前記絶縁膜に設けられた開
口部を介して前記第二導電型活性領域に接続する第二電
極５０とを備え、前記第二導電型リング領域と前記第一
導電型領域とで構成されるＰＮ接合の一方の終端が前記
絶縁膜下の前記表面上に在り、他方の終端が前記保護膜
下の前記外周面上に在り、前記第二導電型リング領域及
び前記第一導電型領域の前記表面への露出面が前記絶縁
膜により覆われてなることを特徴とする半導体素子であ
る。According to a seventh aspect of the present invention, for example, as shown in FIG. 8, by selectively introducing impurities of the opposite conductivity type of the second conductivity type into the surface of the semiconductor material 2 of the first conductivity type. The second conductivity type ring region 46 formed in a ring shape on the outer peripheral portion of the surface of the semiconductor material and the impurity of the second conductivity type are selectively introduced into the surface of the semiconductor material, and the impurity activation treatment is performed to thereby A second conductivity type active region 47 formed inside the second conductivity type ring region and a region in the semiconductor material that is bonded to both the second conductivity type ring region and the second conductivity type active region. A first conductivity type region 48 interposed therebetween, an insulating film 49 that covers the surface with a predetermined pattern, and a protective film 24 that covers an outer peripheral surface continuous to the outer periphery of the surface to a predetermined depth from the surface. , The first electrode on the side of the first conductivity type region 27 and a second electrode 50 connected to the second-conductivity-type active region through an opening provided in the insulating film, and composed of the second-conductivity-type ring region and the first-conductivity-type region. One end of the PN junction located on the surface under the insulating film and the other end on the outer peripheral surface under the protective film, the second conductivity type ring region and the first conductivity type region. The semiconductor element is characterized in that the surface exposed to the surface of is covered with the insulating film.
【００２６】請求項７記載の発明においては、上述した
従来技術と同様に活性領域の周囲に耐圧維持領域が形成
されるが、請求項１記載の発明と同様に、第二導電型リ
ング領域の内周面上の任意の一点から伸びる空乏層と、
その対岸の第二導電型活性領域外周面上の一点とから伸
びる空乏層とが干渉し、互いに逆向きの電界ベクトル成
分が打ち消し合って電界強度を低下させる電界相殺効果
が得られる。この電界相殺効果を利用した第二導電型リ
ング領域と第二導電型活性領域とに挟まれる第一導電型
領域の露出面直下部は、極めて狭小にすることができる
ので、活性領域周囲の耐圧維持のための領域を従来技術
に比較して狭小とすることができ、活性領域の占有面積
を十分に取って、高耐圧を維持、向上することができ
る。また、耐圧を維持しつつ素子の小面積化も可能であ
る。According to the invention of claim 7, the breakdown voltage maintaining region is formed around the active region as in the prior art described above. However, as in the invention of claim 1, the second conductivity type ring region is formed. A depletion layer extending from any one point on the inner peripheral surface,
The depletion layer extending from one point on the outer peripheral surface of the second conductivity type active region on the opposite bank interferes with the depletion layer, and electric field vector components in opposite directions cancel each other out to obtain an electric field canceling effect of lowering the electric field strength. The area directly below the exposed surface of the first-conductivity-type area sandwiched between the second-conductivity-type ring area and the second-conductivity-type active area that utilizes this electric field canceling effect can be extremely narrowed, so that the breakdown voltage around the active area is reduced. The region for maintaining can be made narrower than that of the conventional technique, and the area occupied by the active region can be sufficiently taken to maintain or improve the high breakdown voltage. Further, it is possible to reduce the area of the element while maintaining the breakdown voltage.
【００２７】[0027]
【発明の実施の形態】以下に本発明の一実施形態につき
図面を参照して説明する。以下は本発明の一実施形態で
あって本発明を限定するものではない。BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. The following is one embodiment of the present invention and does not limit the present invention.
【００２８】〔第１の実施形態〕まず、本発明の第１の
実施形態につき、図１を参照して説明する。図１(a)は
本発明の第１の実施形態の半導体素子のシリコン表面以
下を示す平面図、(b)はD1-D1断面図である。なお、本実
施形態はダイオードへの適用例である。また、本実施形
態においては、Ｐ型活性領域２１が前記第二導電型活性
領域に対応し、Ｎ型領域２２が前記第一導電型領域に対
応する。First Embodiment First, a first embodiment of the present invention will be described with reference to FIG. FIG. 1A is a plan view showing the silicon surface and below of a semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a D1-D1 sectional view. Note that this embodiment is an example of application to a diode. Further, in this embodiment, the P-type active region 21 corresponds to the second conductivity-type active region, and the N-type region 22 corresponds to the first conductivity-type region.
【００２９】本実施形態の半導体素子１１１は、概ね次
のようにして作製される。まず、Ｎ+型の半導体基板１
上にＮ-型でエピタキシャル成長によりシリコン層２が
形成される。シリコン層２上にシリコン酸化膜が成膜さ
れ、エッチングにより所定の開口パターンが形成され
る。そのシリコン酸化膜をマスクとして選択的な拡散又
はイオン注入によりシリコン層２の表層外周部に不純物
を導入し、後に活性化処理を行ってＰ型活性領域２１を
得る。Ｐ型活性領域２１と残存部のＮ-型領域２２とに
よりＰＮ接合が構成される。当初、Ｐ型活性領域２１は
外周及び内周において曲面接合を有するプレーナ型接合
を形成するが、後に、素子外周に沿ってシリコン層２及
び半導体基板１を切断するか、又は、素子外周に沿って
シリコン層２に溝を形成することによって外周部の曲面
接合は削除され、平面接合が外周面に露出する。図１に
示すように外周面は、保護膜２４又は２５によって被覆
される。保護膜２４はトレンチ溝に施したものであり、
保護膜２５はメサ溝に施したものであり、便宜上同一図
面に示したが、実際にはいずれか一方が選択される。マ
スクに用いたシリコン酸化膜は通常そのまま残される。
シリコン酸化膜の上からアルミ層が敷設され前記第二電
極としての陽極電極２６が形成される。半導体基板１の
裏面にもアルミ層が被着し陰極電極２７が形成される。The semiconductor element 111 of this embodiment is manufactured as follows. First, the N + type semiconductor substrate 1
A silicon layer 2 of N - type is epitaxially grown thereon. A silicon oxide film is formed on the silicon layer 2, and a predetermined opening pattern is formed by etching. Using the silicon oxide film as a mask, impurities are introduced into the outer peripheral portion of the surface of the silicon layer 2 by selective diffusion or ion implantation, and activation treatment is performed later to obtain the P-type active region 21. The P-type active region 21 and the remaining N − -type region 22 form a PN junction. Initially, the P-type active region 21 forms a planar-type junction having curved junctions on the outer and inner peripheries, but later, the silicon layer 2 and the semiconductor substrate 1 are cut along the outer periphery of the element, or along the outer periphery of the element. By forming a groove in the silicon layer 2 as a result, the curved surface joint at the outer peripheral portion is eliminated and the planar joint is exposed on the outer peripheral surface. As shown in FIG. 1, the outer peripheral surface is covered with a protective film 24 or 25. The protective film 24 is applied to the trench groove,
Although the protective film 25 is provided in the mesa groove and is shown in the same drawing for convenience, either one is actually selected. The silicon oxide film used for the mask is usually left as it is.
An aluminum layer is laid on the silicon oxide film to form an anode electrode 26 as the second electrode. An aluminum layer is also deposited on the back surface of the semiconductor substrate 1 to form the cathode electrode 27.
【００３０】図１(b)に示すように本実施形態の半導体
素子１１１は、Ｎ+型の半導体基板１と、半導体基板１
上にＮ-型でエピタキシャル成長により形成されたシリ
コン層２とを備える。シリコン層２の表層外周部には活
性領域となるＰ型活性領域２１が構成される。さらに本
実施形態の半導体素子１１１は、シリコン層２表面上を
所定パターンで覆うシリコン酸化膜２３と、シリコン層
２表面の外周に連続する外周面を前記表面から所定の深
さまで被覆する保護膜２４又は２５とを備える。Ｐ型活
性領域２１とＮ-型領域２２とによるＰＮ接合の一方の
終端６１がシリコン酸化膜２３下の表面上に在り、他方
の終端６２が保護膜下の外周面上に在る。外周面上に存
在する前記他方の終端６２は外周一周に亘って保護膜下
の外周面上に存在する。Ｐ型活性領域２１の外周部は外
周面に露出し、保護膜２４又は２５によって被覆され
る。保護膜２４又は２５は、少なくとも外周面上の接合
終端６２より深い位置まで施され、この接合終端６２を
被覆保護する。図１(a)に示すようにＰ型活性領域２１
はリング状に形成される。Ｐ型活性領域２１の外周は四
角に丸みのついた正方形状で、Ｐ型活性領域２１の内周
はほぼ円形である。Ｐ型活性領域２１の内周の内側でＮ
-型領域２２がシリコン層２表面に露出する。Ｎ-型領域
２２のシリコン層２表面への露出面はシリコン酸化膜２
３により覆われる。Ｐ型活性領域２１の外周の外側に保
護膜２４又は２５が被着されている。As shown in FIG. 1B, the semiconductor element 111 of this embodiment includes an N + type semiconductor substrate 1 and a semiconductor substrate 1.
And an N − -type silicon layer 2 formed by epitaxial growth thereon. A P-type active region 21 serving as an active region is formed on the outer peripheral portion of the surface layer of the silicon layer 2. Further, in the semiconductor device 111 of the present embodiment, the silicon oxide film 23 that covers the surface of the silicon layer 2 with a predetermined pattern, and the protective film 24 that covers the outer peripheral surface continuous to the outer periphery of the surface of the silicon layer 2 to a predetermined depth from the surface. Or 25. One end 61 of the PN junction formed by the P type active region 21 and the N − type region 22 is on the surface under the silicon oxide film 23, and the other end 62 is on the outer peripheral surface under the protective film. The other end 62 existing on the outer peripheral surface exists on the outer peripheral surface under the protective film over the entire circumference. The outer peripheral portion of the P-type active region 21 is exposed on the outer peripheral surface and is covered with the protective film 24 or 25. The protective film 24 or 25 is applied at least to a position deeper than the joint end 62 on the outer peripheral surface to cover and protect the joint end 62. As shown in FIG. 1A, the P-type active region 21
Is formed in a ring shape. The outer periphery of the P-type active region 21 has a square shape with rounded squares, and the inner periphery of the P-type active region 21 is substantially circular. N inside the inner periphery of the P-type active region 21
The -type region 22 is exposed on the surface of the silicon layer 2. The exposed surface of the N − type region 22 on the surface of the silicon layer 2 is the silicon oxide film 2
Covered by 3. A protective film 24 or 25 is deposited on the outer periphery of the P-type active region 21.
【００３１】図１(b)に示すようにＮ-型領域２２は、Ｐ
型活性領域２１の内周部および底部に接合する。この内
周部から底部にかけては曲面接合が構成される。この曲
面接合のうち、内周下端のコーナー部２８が、最大電界
の生じる部分となる。シリコン酸化膜２３の開口部を介
して陽極電極２６がＰ型活性領域２１に接合する。Ｎ-
型領域２２側の電極である陰極電極２７は、半導体基板
１の裏面に被着して形成される。As shown in FIG. 1B, the N -- type region 22 has a P
It is bonded to the inner peripheral portion and the bottom portion of the mold active region 21. A curved surface joint is formed from the inner peripheral portion to the bottom portion. In this curved surface joint, the corner portion 28 at the lower end of the inner circumference is a portion where the maximum electric field is generated. The anode electrode 26 is bonded to the P-type active region 21 through the opening of the silicon oxide film 23. N -
The cathode electrode 27, which is an electrode on the mold region 22 side, is formed by being adhered to the back surface of the semiconductor substrate 1.
【００３２】以上の構成の半導体素子１１１によれば、
耐圧維持領域を増大させることなく、高耐圧化を図り、
比較的大面積の活性領域を確保することができるなどの
効果がある。その詳細は後続のシミュレーションの開示
において説明する。According to the semiconductor element 111 having the above structure,
A high breakdown voltage is achieved without increasing the breakdown voltage maintaining area,
There is an effect that a relatively large active area can be secured. The details will be described in the subsequent simulation disclosure.
【００３３】また、Ｐ型活性領域２１の内周を円形とす
ることで、内周下部の接合曲面を電界の局所集中の受け
にくい均一な円筒面とすることができる。仮にＰ型活性
領域２１の内周を四角に丸みのついた正方形状にする
と、直線部分が生じるため内周下部の円筒面は直線状の
軸を有した円筒面と円弧上の軸を有した円筒面とで構成
される。従来の外周部に曲面接合が存在する構造では、
素子をチップにダイシングする場合には通常、矩形にカ
ットするので、曲面接合部を平面視円形状に構成すると
その外側の周縁部に無駄が生じやすく面積効率が低下す
る。しかし本発明によれば、曲面接合が外周部に存在せ
ず内周部に存在するので面積効率を損なうことなく曲面
接合部を平面視円形状に構成することができる。Further, by making the inner circumference of the P-type active region 21 circular, the junction curved surface at the lower part of the inner circumference can be made a uniform cylindrical surface which is less susceptible to local concentration of the electric field. If the inner periphery of the P-type active region 21 is formed in a square shape with rounded squares, a straight line portion is formed, so that the cylindrical surface at the lower portion of the inner periphery has a cylindrical surface having a linear axis and an arc-shaped axis. And a cylindrical surface. In the conventional structure with curved joints on the outer periphery,
When an element is diced into chips, it is usually cut into a rectangular shape. Therefore, if the curved surface joint portion is formed into a circular shape in plan view, the outer peripheral edge portion is likely to be wasted, and the area efficiency is reduced. However, according to the present invention, since the curved surface joint does not exist in the outer peripheral portion but in the inner peripheral portion, it is possible to configure the curved surface joint portion in a circular shape in plan view without impairing the area efficiency.
【００３４】〔第２の実施形態〕次に、本発明の第２の
実施形態につき、図２を参照して説明する。図２(a)は
本発明の第２の実施形態の半導体素子のシリコン表面以
下を示す平面図、(b)はD2-D2断面図である。[Second Embodiment] Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 2A is a plan view showing the silicon surface and below of the semiconductor device according to the second embodiment of the present invention, and FIG. 2B is a D2-D2 sectional view.
【００３５】本実施形態の半導体素子１１２は第１の実
施形態と同様の、半導体基板１と、シリコン層２と、シ
リコン層２中に作り込まれたＰ型活性領域２１及びＮ-
型領域２２と、外周面に施された保護膜２４と、表面に
敷設されたシリコン酸化膜２３と、半導体基板１の裏面
に被着する陰極電極２７とを有する。一方、本実施形態
の半導体素子１１２は、素子中央にＮ+型領域２９及び
表面側陰極電極３０が設けられている点で第１の実施形
態とは異なる。The semiconductor element 112 of this embodiment is similar to the semiconductor element 112 of the first embodiment, that is, the semiconductor substrate 1, the silicon layer 2, and the P-type active regions 21 and N − formed in the silicon layer 2.
It has a mold region 22, a protective film 24 provided on the outer peripheral surface, a silicon oxide film 23 laid on the front surface, and a cathode electrode 27 deposited on the back surface of the semiconductor substrate 1. On the other hand, the semiconductor device 112 of this embodiment is different from that of the first embodiment in that the N + type region 29 and the surface side cathode electrode 30 are provided in the center of the device.
【００３６】シリコン層２の表層中央部に不純物を選択
的に導入することよりＮ+型領域２９がＮ-型領域２２に
包囲されて形成される。Ｎ+型領域２９のシリコン層２
表面への露出面にはシリコン酸化膜２３に設けられた開
口部を介して表面側陰極電極３０が接続する。シリコン
酸化膜２３の開口部を介してＰ型活性領域２１に接合す
る陽極電極３１は、第１の実施形態の陽極電極２６とは
異なり、中央に開口部を有する。この開口部内において
表面側陰極電極３０は敷設される。陽極電極２６のエッ
ジと表面側陰極電極３０のエッジとは間隔を隔てる。パ
ッケージングの際には、その間隔に絶縁性の封止剤が充
填されて、陽極電極２６と表面側陰極電極３０との絶縁
性が高められる。By selectively introducing impurities into the central portion of the surface layer of the silicon layer 2, the N + type region 29 is formed so as to be surrounded by the N − type region 22. Silicon layer 2 of N + type region 29
The front surface side cathode electrode 30 is connected to the exposed surface through the opening provided in the silicon oxide film 23. The anode electrode 31 joined to the P-type active region 21 through the opening of the silicon oxide film 23 has an opening at the center unlike the anode electrode 26 of the first embodiment. The front side cathode electrode 30 is laid in this opening. The edge of the anode electrode 26 and the edge of the front surface side cathode electrode 30 are separated from each other. At the time of packaging, an insulating sealant is filled in the space to enhance the insulation between the anode electrode 26 and the front-side cathode electrode 30.
【００３７】〔第３の実施形態〕次に、本発明の第３の
実施形態につき、図３及び図４を参照して説明する。図
３(a)は本発明の第３の実施形態の半導体素子のシリコ
ン表面パターンを示す平面図、(b)は他のシリコン表面
パターンを示す平面図である。図４は図３(a)におけるD
3-D3断面図である。[Third Embodiment] Next, a third embodiment of the present invention will be described with reference to FIGS. FIG. 3A is a plan view showing a silicon surface pattern of a semiconductor device according to a third embodiment of the present invention, and FIG. 3B is a plan view showing another silicon surface pattern. Fig. 4 shows D in Fig. 3 (a)
It is a 3-D3 sectional view.
【００３８】本実施形態の半導体素子１１３は第１の実
施形態と同様の、半導体基板１と、シリコン層２と、外
周面に施された保護膜２４と、半導体基板１の裏面に被
着する陰極電極２７とを有する。一方、本実施形態の半
導体素子１１３は、Ｐ型活性領域３２、Ｎ-型領域３
３、シリコン酸化膜３４、及び陽極電極３５の形状が第
１の実施形態とは異なる。図４に示すように本実施形態
の半導体素子１１３は、Ｎ-型領域３３がＰ型活性領域
３２に包囲された複数の部分でシリコン表面に露出して
なるものである。The semiconductor element 113 of the present embodiment is deposited on the back surface of the semiconductor substrate 1 and the semiconductor substrate 1, the silicon layer 2, the protective film 24 provided on the outer peripheral surface, as in the first embodiment. And a cathode electrode 27. On the other hand, the semiconductor element 113 according to the present embodiment has the P-type active region 32 and the N − -type region 3.
3, the shapes of the silicon oxide film 34 and the anode electrode 35 are different from those of the first embodiment. As shown in FIG. 4, in the semiconductor element 113 of this embodiment, the N − type region 33 is exposed on the silicon surface at a plurality of portions surrounded by the P type active region 32.
【００３９】散点状のマスクパターンを用いてＰ型不純
物を導入することによりＰ型活性領域３２を形成する。
その結果、図３(a)に示すように、散点的に位置するＰ
型活性領域３２に包囲された複数の部分でＮ-型領域３
３がシリコン表面にほぼ円形状で露出する。図３(a)に
示すパターンに代えて、図３(b)に示す縞状パターンと
しても良い。図４に示すように、Ｎ-型領域３３のシリ
コン表面への露出面はシリコン酸化膜３４により覆われ
る。シリコン酸化膜３４上に敷設される陽極電極３５
は、シリコン酸化膜３４に設けられた開口部を介してＰ
型活性領域３２に接合する。A P-type active region 32 is formed by introducing a P-type impurity using a dotted mask pattern.
As a result, as shown in FIG.
A plurality of portions surrounded by the mold active region 32 are N − -type regions 3
3 is exposed on the silicon surface in a substantially circular shape. Instead of the pattern shown in FIG. 3A, the striped pattern shown in FIG. 3B may be used. As shown in FIG. 4, the exposed surface of the N − type region 33 on the silicon surface is covered with the silicon oxide film 34. Anode electrode 35 laid on the silicon oxide film 34
Is P through the opening provided in the silicon oxide film 34.
Join to the mold active region 32.
【００４０】〔第４の実施形態〕次に、本発明の第４の
実施形態につき、図５を参照して説明する。図５(a)は
本発明の第４の実施形態の半導体素子のシリコン表面以
下を示す平面図、(b)はD4-D4断面図である。[Fourth Embodiment] Next, a fourth embodiment of the present invention will be described with reference to FIG. FIG. 5A is a plan view showing the silicon surface and below of the semiconductor device according to the fourth embodiment of the present invention, and FIG. 5B is a D4-D4 sectional view.
【００４１】本実施形態の半導体素子１１４は第１の実
施形態と同様の、半導体基板１と、シリコン層２と、リ
ング状のＰ型活性領域２１と、シリコン酸化膜２３と、
外周面に施された保護膜２４と、陽極電極２６と、半導
体基板１の裏面に被着する陰極電極２７とを有する。一
方、本実施形態の半導体素子１１４は第１の実施形態と
は異なり、1本構成のガードリング３６a又は２本構成の
ガードリング３６b,３６cを有する。1本構成のガードリ
ング３６aは図５(a)(b)の左半身に描いたように構成さ
れる。２本構成のガードリング３６b,３６cは図５(a)
(b)の右半身に描いたように構成される。The semiconductor element 114 of this embodiment is the same as that of the first embodiment, including the semiconductor substrate 1, the silicon layer 2, the ring-shaped P-type active region 21, the silicon oxide film 23, and the like.
It has a protective film 24 provided on the outer peripheral surface, an anode electrode 26, and a cathode electrode 27 adhered to the back surface of the semiconductor substrate 1. On the other hand, unlike the first embodiment, the semiconductor element 114 of the present embodiment has the guard ring 36a having one configuration or the guard rings 36b and 36c having two configurations. The single guard ring 36a is constructed as depicted in the left half of the body of FIGS. 5 (a) and 5 (b). The two guard rings 36b and 36c are shown in FIG. 5 (a).
It is constructed as depicted in the right half of (b).
【００４２】図５(a)に示すように、中央に円形状にＮ-
型領域３７が露出し、この外側に隣接してガードリング
３６a、又は２本構成のうちの内周のガードリング３６b
が形成される。その外側には再びＮ-型領域３７がリン
グ状に露出する。1本構成の場合、その外側にＰ型活性
領域２１が形成される。2本構成の場合、Ｎ-型領域３７
がリング状の露出部の外側に外周のガードリング３６c
が形成される。ガードリングを3本以上とする場合は、
Ｎ-型領域３７のリング状の露出パターンとガードリン
グパターンが繰り返される。最外周のガードリングの外
側にＮ-型領域３７のリング状の露出パターンが形成さ
れ、さらにその外側にＰ型活性領域２１が形成される。[0042] As shown in FIG. 5 (a), the central circular N -
The mold region 37 is exposed and adjacent to the outside thereof is the guard ring 36a or the guard ring 36b of the inner periphery of the two-piece structure.
Is formed. The N − -type region 37 is again exposed to the outside in a ring shape. In the case of a single structure, the P-type active region 21 is formed on the outside thereof. In the case of two lines, the N − type region 37
Is the outer guard ring 36c on the outside of the ring-shaped exposed part
Is formed. When using three or more guard rings,
The ring-shaped exposed pattern and the guard ring pattern of the N − type region 37 are repeated. A ring-shaped exposed pattern of the N − type region 37 is formed on the outer side of the outermost guard ring, and a P type active region 21 is further formed on the outer side thereof.
【００４３】〔第５の実施形態〕次に、本発明の第５の
実施形態につき、図６を参照して説明する。図６(a)は
本発明の第５の実施形態の半導体素子のシリコン表面以
下を示す平面図、(b)はD5-D5断面図である。[Fifth Embodiment] Next, a fifth embodiment of the present invention will be described with reference to FIG. FIG. 6A is a plan view showing the silicon surface and below of a semiconductor device according to a fifth embodiment of the present invention, and FIG. 6B is a D5-D5 cross-sectional view.
【００４４】本実施形態の半導体素子１１５は第１の実
施形態と同様の、半導体基板１と、シリコン層２と、シ
リコン層２中に作り込まれたリング状のＰ型活性領域２
１及びＮ-型領域２２と、シリコン酸化膜２３と、外周
面に施された保護膜２４と、陽極電極２６と、半導体基
板１の裏面に被着する陰極電極２７とを有する。一方、
本実施形態の半導体素子１１５は第１の実施形態とは異
なり、Ｐ型活性領域が比較的高濃度であるＰ型活性領域
２１と比較的低濃度であるＰ-型領域３８とから構成さ
れる。Ｐ-型領域３８によりＪＴＥ構造が構成される。The semiconductor element 115 of this embodiment is similar to that of the first embodiment in that the semiconductor substrate 1, the silicon layer 2, and the ring-shaped P-type active region 2 formed in the silicon layer 2 are formed.
It has a 1 and N − type region 22, a silicon oxide film 23, a protective film 24 provided on the outer peripheral surface, an anode electrode 26, and a cathode electrode 27 attached to the back surface of the semiconductor substrate 1. on the other hand,
Unlike the first embodiment, the semiconductor element 115 of this embodiment is composed of a P-type active region 21 having a relatively high concentration of P-type active regions and a P − -type region 38 having a relatively low concentration. . The P − type region 38 constitutes the JTE structure.
【００４５】図６(a)に示すように、Ｐ-型領域３８はＰ
型活性領域２１の少なくとも内周部に接合し、Ｐ型活性
領域２１の内周に隣接してシリコン表面にリング状に露
出するように形成される。Ｐ-型領域３８に包囲された
範囲でＮ-型領域２２がシリコン表面に露出する。Ｐ-型
領域３８は、少なくとも電界集中しやすいＰ型活性領域
２１内周下端コーナー部にまで接合する。Ｐ-型領域３
８をＰ型活性領域２１の底部にも接合するように形成し
ても良い。As shown in FIG. 6 (a), the P -- type region 38 has P
It is formed so as to be bonded to at least the inner periphery of the type active region 21 and adjacent to the inner periphery of the P type active region 21 so as to be exposed in a ring shape on the silicon surface. The N − type region 22 is exposed to the silicon surface in the range surrounded by the P − type region 38. The P − type region 38 is joined at least to the lower end corner portion of the inner periphery of the P type active region 21 where the electric field is easily concentrated. P - type region 3
8 may be formed so as to be joined also to the bottom of the P-type active region 21.
【００４６】〔第６の実施形態〕次に、本発明の第６の
実施形態につき、図７を参照して説明する。図７(a)は
本発明の第６の実施形態の半導体素子を示す平面図、
(b)はD6-D6断面図である。[Sixth Embodiment] Next, a sixth embodiment of the present invention will be described with reference to FIG. FIG. 7A is a plan view showing a semiconductor device according to a sixth embodiment of the present invention,
(b) is a D6-D6 sectional view.
【００４７】本実施形態の半導体素子１１６は第１の実
施形態と同様の、半導体基板１と、シリコン層２と、シ
リコン酸化膜２３（２３a，２３b）と、外周面に施され
た保護膜２４と、半導体基板１の裏面に被着する陰極電
極２７とを有する。一方、本実施形態の半導体素子１１
６は第１の実施形態とは異なり、Ｐ+型活性領域３９内
にＭＯＳセル群が構成される。The semiconductor element 116 of this embodiment is similar to the first embodiment in that the semiconductor substrate 1, the silicon layer 2, the silicon oxide film 23 (23a, 23b), and the protective film 24 provided on the outer peripheral surface are formed. And a cathode electrode 27 attached to the back surface of the semiconductor substrate 1. On the other hand, the semiconductor device 11 of the present embodiment
6 differs from the first embodiment in that a MOS cell group is formed in the P + type active region 39.
【００４８】図７(b)に示すように、Ｐ+型活性領域３９
に包囲されてＮ-型領域４０がシリコン表面へセル数に
相当する多数の部分で露出することによりチャネル部が
セル数分形成される。チャネル部近傍のＰ+型活性領域
３９内にＮ+型領域４１が形成されてソース／エミッタ
部となる。チャネル部上にゲート酸化膜４２が形成さ
れ、さらにゲート酸化膜４２上にゲートポリシリコン４
３が形成されて、ＭＯＳ構造を成す。Ｐ+型活性領域３
９は素子中央部で開口部を形成する。その開口部内で、
Ｎ-型領域４０がシリコン表面に露出し、その露出面が
シリコン酸化膜２３ｂにより覆われる。素子中央のシリ
コン酸化膜２３ｂ上にはゲート電極パッド４５が設けら
れる。このゲート電極パッド４５は、ＭＯＳセル群の各
ゲート電極と図示しない配線により導通がとられてい
る。素子中央のシリコン酸化膜２３ｂ下のシリコン層に
Ｐ+型領域４３を設けても良い。ソース／エミッタ電極
４４は素子中央を除く領域に敷設され、ゲート電極パッ
ド４５との隔絶がとられている。なお、本実施形態の半
導体素子１１６は、半導体基板１をＮ+型とする場合に
あってはパワーＭＯＳ素子、半導体基板１をＰ+型とす
る場合にあってはパワーＩＧＢＴ素子への適用例であ
る。As shown in FIG. 7B, the P + type active region 39 is formed.
The N − -type region 40 is surrounded by and exposed at the silicon surface in a large number of cells corresponding to the number of cells, so that the channel portions are formed by the number of cells. An N + type region 41 is formed in the P + type active region 39 near the channel portion to serve as a source / emitter portion. A gate oxide film 42 is formed on the channel portion, and a gate polysilicon 4 is formed on the gate oxide film 42.
3 is formed to form a MOS structure. P + type active region 3
Reference numeral 9 forms an opening in the central portion of the element. Within that opening,
The N − type region 40 is exposed on the silicon surface, and the exposed surface is covered with the silicon oxide film 23b. A gate electrode pad 45 is provided on the silicon oxide film 23b at the center of the device. The gate electrode pad 45 is electrically connected to each gate electrode of the MOS cell group by a wiring (not shown). The P + type region 43 may be provided in the silicon layer below the silicon oxide film 23b at the center of the device. The source / emitter electrode 44 is laid in a region other than the center of the element and isolated from the gate electrode pad 45. The semiconductor device 116 of this embodiment, application of the semiconductor substrate 1 power MOS device in a case where the N + -type, there the semiconductor substrate 1 in the case of the P + type to the power IGBT element Example Is.
【００４９】本実施形態によれば、素子中央に配された
耐圧維持領域上に外部接続用のゲート電極パッド４５が
設けられるので、面積利用効率が良く、セル領域の拡
大、素子の小面積化に寄与できる。According to the present embodiment, since the gate electrode pad 45 for external connection is provided on the breakdown voltage maintaining region arranged in the center of the device, the area utilization efficiency is good, the cell region is expanded, and the device area is reduced. Can contribute to.
【００５０】〔第７の実施形態〕次に、本発明の第７の
実施形態につき、図８を参照して説明する。図８(a)は
本発明の第７の実施形態の半導体素子のシリコン表面以
下を示す平面図、(b)はD7-D7断面図である。[Seventh Embodiment] Next, a seventh embodiment of the present invention will be described with reference to FIG. FIG. 8A is a plan view showing the silicon surface and below of the semiconductor device according to the seventh embodiment of the present invention, and FIG. 8B is a D7-D7 sectional view.
【００５１】本実施形態の半導体素子１１７は第１の実
施形態と同様の、半導体基板１と、シリコン層２と、外
周面に施された保護膜２４と、半導体基板１の裏面に被
着する陰極電極２７とを有する。一方、本実施形態の半
導体素子１１７は第１の実施形態とは異なり、シリコン
表層外周部にＰ型リング領域４６を備え、Ｎ-型領域４
８を介してＰ型リング領域４６の内側にＰ型活性領域４
７が形成されている。The semiconductor element 117 of this embodiment is the same as that of the first embodiment, and is deposited on the semiconductor substrate 1, the silicon layer 2, the protective film 24 provided on the outer peripheral surface, and the back surface of the semiconductor substrate 1. And a cathode electrode 27. On the other hand, unlike the first embodiment, the semiconductor element 117 of the present embodiment is provided with the P-type ring region 46 in the outer peripheral portion of the silicon surface layer, and the N − -type region 4 is provided.
P-type active region 4 inside P-type ring region 46 via
7 are formed.
【００５２】図８(a)に示すように、四角に丸みの付い
た正方形形状のＰ型活性領域４７が素子中央に形成さ
れ、その外周に隣接してＮ-型領域４８がリング状に露
出し、Ｎ-型領域４８のリング状の露出面に隣接してＰ
型リング領域４６が形成される。図８(b)に示すよう
に、Ｐ型リング領域４６の外周部は外周面に露出し、且
つ、保護膜２４によって被覆保護される。Ｐ型リング領
域４６の表面及びＮ-型領域４８のリング状の露出面
は、シリコン酸化膜４９に覆われる。Ｐ型リング領域４
６とＮ-型領域４８とによるＰＮ接合の一方の終端はシ
リコン酸化膜４９下のシリコン表面上に在り、他方の終
端は保護膜２４下の外周面上に在る。陽極電極５０はシ
リコン酸化膜４９上から積層され、シリコン酸化膜４９
に設けられた開口部を介してＰ型活性領域４７に接合す
る。As shown in FIG. 8 (a), a square P-type active region 47 with rounded squares is formed in the center of the element, and an N -- type region 48 is exposed in a ring shape adjacent to the outer periphery thereof. P adjacent to the ring-shaped exposed surface of the N − type region 48.
A mold ring region 46 is formed. As shown in FIG. 8B, the outer peripheral portion of the P-type ring region 46 is exposed on the outer peripheral surface and is covered and protected by the protective film 24. The surface of the P type ring region 46 and the ring-shaped exposed surface of the N − type region 48 are covered with the silicon oxide film 49. P-type ring area 4
One end of the PN junction formed by 6 and the N − type region 48 is on the silicon surface under the silicon oxide film 49, and the other end is on the outer peripheral surface under the protective film 24. The anode electrode 50 is stacked on the silicon oxide film 49,
It is bonded to the P-type active region 47 through the opening provided in the.
【００５３】本実施形態によれば、Ｐ型リング領域４６
の内周面から伸びる空乏層と、Ｐ型活性領域４７の外周
面から伸びる空乏層との干渉により電界相殺効果が得ら
れるので、Ｐ型活性領域４７の外周下端部のコーナーに
おける最大電界強度を低下させることができ、耐圧を維
持・向上することができる。また、高耐圧を実現しつ
つ、Ｐ型活性領域４７の周囲の耐圧維持領域幅を狭くす
ることができるので、活性領域の面積率増大、素子の小
面積化が可能となる。According to this embodiment, the P-type ring region 46 is provided.
The interference between the depletion layer extending from the inner peripheral surface of the P-type active region 47 and the depletion layer extending from the outer peripheral surface of the P-type active region 47 provides an electric field canceling effect. It can be lowered, and the breakdown voltage can be maintained and improved. Further, since the breakdown voltage maintaining region width around the P-type active region 47 can be narrowed while realizing a high breakdown voltage, the area ratio of the active region can be increased and the element area can be reduced.
【００５４】〔シミュレーション〕本発明に該当する構
造につきシミュレーションを行った。以下にその内容を
開示する。以下の内容はシミュレーション１とシミュレ
ーション２とからなる。[Simulation] The structure corresponding to the present invention was simulated. The contents will be disclosed below. The following contents consist of simulation 1 and simulation 2.
【００５５】まず、シミュレーション１につき説明す
る。シミュレーション１は素子外形寸法の変化に伴う各
領域の面積率とその従来比等の概算である。First, the simulation 1 will be described. Simulation 1 is an approximate calculation of the area ratio of each region and the conventional ratio thereof according to the change of the external dimensions of the element.
【００５６】図９の平面図に示すように、実際の丸みを
省略して各領域の境を正方形として近似計算した。Ｌは
素子の一辺の長さ、Ｗｍは活性領域幅、Ｗｓは耐圧維持
領域幅、Ｗｅは周縁領域幅である。なお、上記従来例の
概算結果と比較するため、活性領域幅Ｗｍは素子中心に
対して両側合計の幅とし、耐圧維持領域幅Ｗｓは素子中
心に対して片側の幅とした。図１０の表に示すように、
０．５〜１０（ｍｍ）の異なる１２通りのチップ外形寸
法に対して計算した。耐圧維持領域幅Ｗｓは上述の従来
例と同様に０．１３（ｍｍ）とする。また、周縁領域幅
Ｗｅも上述の従来例と同様に０．０５（ｍｍ）とする。
その結果、活性領域幅Ｗｍは素子外形寸法の変化に伴い
図１０の表に示すように変化する。しかし、プレーナ型
ＰＮ接合（曲面接合）の長さ（内周長）は、素子外形寸
法が変化しても一定の８×Ｗｓである。したがって、素
子外形寸法の変化に伴う設計的制約が少ない。チップ全
体の面積をＳ、活性領域の面積をＳ１、耐圧維持領域の
面積をＳ２、周縁領域の面積をＳ３（Ｓ＝Ｓ1＋Ｓ２＋
Ｓ３）としてそれぞれ算出してまとめると図１０の表に
示す通りとなる。さらに、素子全体に対する各領域の面
積率Ｓ１／Ｓ，Ｓ２／Ｓ，Ｓ３／Ｓを算出しまとめる
と、図１０の表に示す通りとなる。また、素子外形寸法
Ｌの変化に伴う各面積率Ｓ１／Ｓ，Ｓ２／Ｓ，Ｓ３／Ｓ
の変化をグラフ化したものを図１１に示す。As shown in the plan view of FIG. 9, the actual roundness was omitted, and the boundary between the regions was approximated to a square for the calculation. L is the length of one side of the element, Wm is the active region width, Ws is the breakdown voltage maintaining region width, and We is the peripheral region width. For comparison with the estimation result of the conventional example, the active region width Wm is the total width on both sides with respect to the element center, and the breakdown voltage maintaining region width Ws is one width with respect to the element center. As shown in the table of FIG.
Calculation was performed for 12 different chip outer dimensions of 0.5 to 10 (mm). The breakdown voltage maintaining region width Ws is set to 0.13 (mm) as in the conventional example described above. Further, the peripheral region width We is also set to 0.05 (mm) as in the above-mentioned conventional example.
As a result, the active region width Wm changes as shown in the table of FIG. However, the length (inner peripheral length) of the planar PN junction (curved surface junction) is 8 × Ws which is constant even if the external dimensions of the element change. Therefore, there are few design restrictions associated with changes in the external dimensions of the element. The area of the entire chip is S, the area of the active region is S1, the area of the breakdown voltage maintaining region is S2, and the area of the peripheral region is S3 (S = S1 + S2 +
S3) is calculated and summarized as shown in the table of FIG. Further, the area ratios S1 / S, S2 / S, S3 / S of the respective regions with respect to the entire element are calculated and summarized as shown in the table of FIG. In addition, the area ratios S1 / S, S2 / S, S3 / S due to changes in the element external dimension L
FIG. 11 shows a graph of the change in the above.
【００５７】さらに、本発明例の活性領域の面積率をＳ
１ｎ／Ｓ、耐圧維持領域の面積率をＳ２ｎ／Ｓとし、従
来例の活性領域の面積率をＳ１o／Ｓ、耐圧維持領域の
面積率をＳ２o／Ｓとしてまとめ、図１２の表に示すと
ともに、それらの素子外形寸法Ｌの変化に対するグラフ
を図１３に示す。Further, the area ratio of the active region of the present invention is S
1n / S, the area ratio of the breakdown voltage maintaining region is S2n / S, the area ratio of the conventional active region is S1o / S, and the area ratio of the breakdown voltage maintaining region is S2o / S, which is shown in the table of FIG. FIG. 13 shows a graph with respect to changes in the external dimensions L of these elements.
【００５８】さらに、活性領域の面積率について本発明
例の従来例に対する比（以下、「活性領域面積向上率」
という。）をＳ１：本/従とし、耐圧維持領域の面積率
について本発明例の従来例に対する比（以下、「耐圧維
持領域面積低下率」という。）をＳ２：本/従として算
出し図１２の表に示すとともに、それらの素子外形寸法
Ｌの変化に対するグラフを図１４に示す。Further, the ratio of the area of the active region to that of the conventional example of the present invention (hereinafter referred to as "active region area improvement rate")
Say. ) Is defined as S1: book / slave, and the ratio of the area of the breakdown voltage maintaining region to the conventional example (hereinafter, referred to as “breakdown voltage maintaining region area reduction rate”) is calculated as S2: book / slave. In addition to the table, FIG. 14 shows a graph with respect to changes in the element external dimension L.
【００５９】図１３のグラフを参照すれば明らかなよう
に、本発明例の活性領域の面積率が従来例のそれより大
幅に向上していることが認められる。本発明例、従来例
ともに素子外形寸法Ｌが減少するほど、活性領域の面積
率が減少するが、従来例より本発明例の方が活性領域の
面積率が高レベルに残存する。活性領域の面積率向上に
相反する当然の結果として、本発明例の耐圧維持領域の
面積率が従来例のそれに比較して低レベルに抑えられて
いることが認められる。As is apparent from the graph of FIG. 13, it is recognized that the area ratio of the active region of the present invention is much higher than that of the conventional example. In both the present invention example and the conventional example, the area ratio of the active region decreases as the element outer dimension L decreases, but the active region area ratio of the present invention example remains higher than that of the conventional example. As a natural result which is contrary to the improvement of the area ratio of the active region, it is recognized that the area ratio of the breakdown voltage maintaining region of the example of the present invention is suppressed to a low level as compared with that of the conventional example.
【００６０】図１４のグラフを参照すれば明らかなよう
に、本発明例の活性領域面積向上率は、常に１倍を超
え、素子外形寸法が減少するほど著しく向上しているこ
とが認められる。また、本発明例の耐圧維持領域面積低
下率は、常に１倍を下回ることが認められる。As is apparent from the graph of FIG. 14, the active region area improvement rate of the example of the present invention always exceeds 1 times, and it is recognized that the active area area improvement rate is remarkably improved as the outer dimension of the element is reduced. It is also recognized that the breakdown voltage maintaining region area reduction rate of the example of the present invention is always less than 1 time.
【００６１】なお、図１５に示すようにメサ型素子にお
いては、素子外周面を形成する際の等方性エッチングに
より表面寸法の減少が深刻な場合がある。すなわち、ス
クライブ部６３に加え、メサ消失分６４が表面寸法の減
少に影響する。そこで、周縁領域幅Ｗｅをスクライブ部
５０（μｍ）にメサ消失分５０（μｍ）を加えた１００
（μｍ）とした場合と、周縁領域幅Ｗｅをスクライブ部
５０（μｍ）にメサ消失分１００（μｍ）を加えた１５
０（μｍ）とした場合につき同様に概算した。その計算
結果を図１６及び図１７に示す。通常、ウエットエッチ
ングにおいては、メサ消失分を大きくとも溝深さＤの２
倍とすれば充分である。このように周縁領域幅Ｗｅが拡
幅してしまう技術手段を採択した場合でも、本発明によ
る活性領域面積率向上の効果を得ることは十分可能であ
る（図１７参照）。As shown in FIG. 15, in the mesa type element, there is a case where the surface dimension is seriously reduced due to isotropic etching when forming the element outer peripheral surface. That is, in addition to the scribe portion 63, the mesa loss 64 affects the reduction of the surface dimension. Therefore, the peripheral region width We is 100, which is obtained by adding 50 (μm) of mesa disappearance to the scribe portion 50 (μm).
(Μm) and the peripheral region width We was added to the scribe portion 50 (μm) by 100 (μm) for the disappearance of the mesa 15
Similar estimations were made for the case of 0 (μm). The calculation results are shown in FIGS. 16 and 17. Usually, in wet etching, even if the mesa loss is large, the groove depth D is 2
Doubling is enough. Even if such a technical means that the peripheral region width We is widened is adopted, the effect of improving the active region area ratio according to the present invention can be sufficiently obtained (see FIG. 17).
【００６２】以上のシミュレーション１では、従来例と
本発明例とにおいて耐圧維持領域幅を等しくして計算し
た。本発明によれば、従来例と等しい耐圧維持領域幅で
も耐圧の向上が期待できるとともに（具体的手段及び設
計値により異なる）、耐圧維持領域幅を狭くすることに
より最大電界強度を低下させる効果があることは次のシ
ミュレーション２により明らかである。また、耐圧維持
領域幅の狭小化は活性領域面積率の向上や素子の小面積
化を意味する。In the above simulation 1, the breakdown voltage maintaining region widths of the conventional example and the present invention example were made equal. According to the present invention, the breakdown voltage can be expected to be improved even with the width of the breakdown voltage maintaining region equal to that of the conventional example (depending on the specific means and the design value), and the effect of lowering the maximum electric field strength can be obtained by narrowing the breakdown voltage maintaining region width. It is clear from Simulation 2 below. Further, narrowing the breakdown voltage maintaining region width means improving the active region area ratio and reducing the element area.
【００６３】次に、シミュレーション２につき説明す
る。シミュレーション２は異なる耐圧維持領域幅Ｗｓの
素子につき、電界強度等を算出したものである。Next, the simulation 2 will be described. Simulation 2 is for calculating the electric field strength and the like for elements having different withstand voltage maintaining region widths Ws.
【００６４】シミュレーション２の対象とした構造（以
下、「本発明例」という。）は図１８及び図１９に示さ
れる。図１８は本発明例の計算対象部分断面図であり、
上記実施形態の対応する部分と同一の符号を付すが、半
導体基板１はシリコン基板、電極２６はアルミニウムと
している。図１８において、シリコン表面の左端を原点
として、原点から右に正の横軸をＸ軸、下に正の縦軸を
Ｙ軸（深さ方向の軸）とする。図１９はＸ＝０．１（μ
ｍ）におけるＹ：０〜４６（μｍ）の範囲の不純物濃度
の片対数グラフである。図１９に示すように、耐圧維持
領域幅Ｗｓ＝３,６，１１，２１，３１（μｍ）の５種
の異なる構造につき計算した。縦方向の不純物濃度分布
は共通である。図１８に示すように、ＰＮ接合の内端コ
ーナー部２８の深さはＹ＝５．６８（μｍ）、接合深さ
はＹ＝６（μｍ）、エピタキシャル層厚すなわち半導体
基板１表面までの深さはＹ＝２１（μｍ）、半導体基板
１裏面までの深さはＹ＝２５（μｍ）である。活性領域
幅Ｗｍは１５（μｍ）、片側で７．５（μｍ）である。
印加逆電圧は１８０（Ｖ）である。The structure targeted for the simulation 2 (hereinafter referred to as "the present invention example") is shown in FIGS. FIG. 18 is a partial cross-sectional view of the calculation target of the example of the present invention,
The same reference numerals as those of the corresponding portions in the above-described embodiment are given, but the semiconductor substrate 1 is a silicon substrate and the electrode 26 is aluminum. In FIG. 18, the left end of the silicon surface is the origin, the positive horizontal axis is the X axis to the right of the origin, and the positive vertical axis is the Y axis (the depth direction axis). In FIG. 19, X = 0.1 (μ
3 is a semi-logarithmic graph of the impurity concentration in the range of Y: 0 to 46 (μm) in (m). As shown in FIG. 19, calculation was performed for five different structures with breakdown voltage maintaining region widths Ws = 3, 6, 11, 21, 31 (μm). The impurity concentration distribution in the vertical direction is common. As shown in FIG. 18, the depth of the inner end corner portion 28 of the PN junction is Y = 5.68 (μm), the junction depth is Y = 6 (μm), the epitaxial layer thickness, that is, the depth to the surface of the semiconductor substrate 1. The depth is Y = 21 (μm), and the depth to the back surface of the semiconductor substrate 1 is Y = 25 (μm). The active region width Wm is 15 (μm) and 7.5 (μm) on one side.
The applied reverse voltage is 180 (V).
【００６５】以下にシミュレーション２の結果を開示す
る。
シリコン中の縦方向電界強度分布
まず、本発明例の縦方向の電界強度分布シミュレーショ
ン結果を示す。図２０は、耐圧維持領域幅Ｗｓ＝３,
６，１１，２１，３１（μｍ）とした各本発明例につい
てのＸ＝０におけるＹ：０〜２５の範囲（Ｙ０−Ｙ０'
線上）における電界強度曲線である。最大電界強度はＰ
型領域２１内の接合付近に生じ、小さい順にＷｓ＝３,
６，１１,２１，３１の場合となった。その最大電界強
度の値を図２３(a)の表に、Ｗｓの変化に対するグラフ
を図２３(b)に示す。図２１は、耐圧維持領域幅Ｗｓ＝
３,６，１１，２１，３１（μｍ）とした各本発明例に
ついてのＸ＝３．６におけるＹ：０〜２５の範囲（Ｙ１
−Ｙ１'線上）における電界強度曲線である。最大電界
強度はＰ型領域２１の内端コーナー部２８に生じ、小さ
い順にＷｓ＝３,６，１１,２１，３１の場合となった。
その最大電界強度の値を図２３(a)の表に、Ｗｓの変化
に対するグラフを図２３(b)に示す。図２２は、耐圧維
持領域幅Ｗｓ＝３,６，１１，２１，３１（μｍ）とし
た各本発明例についてのＸ＝３．６におけるＹ：０〜２
５の範囲（Ｙ２−Ｙ２'線上）における電界強度曲線で
ある。最大電界強度は小さい順にＷｓ＝３,６，１１,２
１，３１の場合となった。その最大電界強度の値を図２
３(a)の表に、Ｗｓの変化に対するグラフを図２３(b)に
示す。The results of the simulation 2 will be disclosed below. Vertical Electric Field Strength Distribution in Silicon First, a vertical electric field strength distribution simulation result of the example of the present invention will be shown. FIG. 20 shows the breakdown voltage maintaining region width Ws = 3,
The range of Y: 0 to 25 at X = 0 (Y0-Y0 ') for each example of the present invention of 6, 11, 21, 31 (μm)
It is an electric field strength curve on the line. Maximum electric field strength is P
It occurs near the junction in the mold region 21, and Ws = 3, in ascending order.
It became the case of 6,11,21,31. The value of the maximum electric field strength is shown in the table of FIG. 23 (a), and the graph with respect to the change of Ws is shown in FIG. 23 (b). FIG. 21 shows the breakdown voltage maintaining region width Ws =
The range of Y: 0 to 25 at X = 3.6 (Y1 for each example of the present invention set to 3, 6, 11, 21, 31 (μm))
It is an electric field intensity curve in (-Y1 'line). The maximum electric field intensity was generated in the inner end corner portion 28 of the P-type region 21, and Ws = 3, 6, 11, 21, 31 in ascending order.
The value of the maximum electric field strength is shown in the table of FIG. 23 (a), and the graph with respect to the change of Ws is shown in FIG. 23 (b). FIG. 22 shows Y = 0 to 2 at X = 3.6 for each example of the present invention in which the breakdown voltage maintaining region width Ws = 3, 6, 11, 21, 31 (μm).
It is an electric field intensity curve in the range of 5 (on the Y2-Y2 'line). Ws = 3,6,11,2 in descending order of maximum electric field strength
This was the case of 1,31. The value of the maximum electric field strength is shown in FIG.
In the table of 3 (a), a graph for changes in Ws is shown in FIG. 23 (b).
【００６６】電界強度２次元分布図
図２４は、耐圧維持領域幅Ｗｓ＝３,６，１１，２１，
３１（μｍ）とした各本発明例についての電界強度２次
元分布図である。(a)はＷｓ＝３１の場合、(b)はＷｓ＝
２１の場合、(c)はＷｓ＝１１の場合、(d)はＷｓ＝６の
場合、(e)はＷｓ＝３の場合である。図中、縞状の線は
等電界強度線である。Electric field strength two-dimensional distribution chart FIG. 24 shows breakdown voltage maintaining region width Ws = 3, 6, 11, 21,
FIG. 3 is a two-dimensional electric field intensity distribution chart for each example of the present invention with 31 (μm). When (a) is Ws = 31, (b) is Ws =
In the case of 21, (c) is the case of Ws = 11, (d) is the case of Ws = 6, and (e) is the case of Ws = 3. In the figure, the striped lines are equal field strength lines.
【００６７】酸化膜直下の電位
図２５は、耐圧維持領域幅Ｗｓ＝３,６，１１，２１，
３１（μｍ）とした各本発明例についてのＹ＝０．０５
におけるＸ：０〜４３の範囲（Ｘ１−Ｘ１'線上）にお
ける電位分布曲線である。陽極電極２６に−１８０
（Ｖ）の電圧が印加され、図２５においてＷｓ＝３の場
合はピーク値−１６８（Ｖ）となる。陽極電極２６の電
位を基準の０（Ｖ）とすると、−１８０（Ｖ）と−１６
８（Ｖ）との差の絶対値、すなわち１２（Ｖ）がＷｓ＝
３（μｍ）の場合の素子中央酸化膜直下（深さ０．０５
μｍ）の電位となる。同様にしてＷｓ＝６，１１，２
１，３１（μｍ）の場合についても電位を求め、まとめ
て図２６(a)の表に示す。Ｗｓの変化に対する素子中央
酸化膜直下（深さ０．０５μｍ）の電位の変化を表すグ
ラフを図２６(b)に示す。また、素子中央酸化膜直下
（深さ０．０５μｍ）の電位と１８０（Ｖ）との差（相
殺電位）の値を図２６(a)の表に示し、Ｗｓの変化に対
する相殺電位の変化を表すグラフを図２６(b)に示す。The potential just below the oxide film is shown in FIG. 25. The breakdown voltage maintaining region width Ws = 3, 6, 11, 21,
Y = 0.05 for each example of the present invention with 31 (μm)
Is a potential distribution curve in the range of X: 0 to 43 (on the X1-X1 ′ line) in FIG. -180 for the anode electrode 26
When a voltage of (V) is applied and Ws = 3 in FIG. 25, the peak value is -168 (V). Assuming that the potential of the anode electrode 26 is 0 (V) as a reference, -180 (V) and -16
The absolute value of the difference from 8 (V), that is, 12 (V) is Ws =
In the case of 3 (μm), directly under the central oxide film of the element (depth 0.05
(μm). Similarly, Ws = 6,11,2
In the case of 1, 31 (μm) as well, the potentials were obtained and are collectively shown in the table of FIG. FIG. 26 (b) is a graph showing changes in the potential just below the central oxide film of the element (depth: 0.05 μm) with respect to changes in Ws. In addition, the value of the difference (offset potential) between the potential just under the element central oxide film (depth of 0.05 μm) and 180 (V) is shown in the table of FIG. 26 (a), and the change of the offset potential with respect to the change of Ws is shown. The graph shown is shown in FIG.
【００６８】シリコン中の横方向Ｘ成分電界分布
次に、本発明例の横方向のＸ成分電界分布シミュレーシ
ョン結果を示す。Ｘ成分電界とは、電界ベクトルのＸ方
向成分をいう。図２７(a)は、耐圧維持領域幅Ｗｓ＝３,
６，１１，２１，３１（μｍ）とした各本発明例につい
てのＹ＝０におけるＸ：０〜４３の範囲（Ｘ０−Ｘ０'
線上）におけるＸ成分電界分布曲線である。最大電界強
度は、小さい順にＷｓ＝３,６，１１,２１，３１の場合
となった。その最大電界強度の値を図２９(a)の表に、
Ｗｓの変化に対するグラフを図２９(b)に示す。図２７
(b)は、耐圧維持領域幅Ｗｓ＝３,６，１１，２１，３１
（μｍ）とした各本発明例についてのＹ＝０.０５にお
けるＸ：０〜４３の範囲（Ｘ１−Ｘ１'線上）における
Ｘ成分電界分布曲線である。最大電界強度は、小さい順
にＷｓ＝３,６，１１,２１，３１の場合となった。その
最大電界強度の値を図２９(a)の表に、Ｗｓの変化に対
するグラフを図２９(b)に示す。Lateral X-Component Electric Field Distribution in Silicon Next, the results of the lateral X-component electric field distribution simulation of the present invention are shown. The X component electric field refers to the X direction component of the electric field vector. FIG. 27A shows a breakdown voltage maintaining region width Ws = 3,
The range of X: 0 to 43 at Y = 0 (X0-X0 'for each of the present invention examples of 6, 11, 21, 31 (μm))
It is an X component electric field distribution curve (on the line). The maximum electric field strength was Ws = 3, 6, 11, 21, 31 in ascending order. The value of the maximum electric field strength is shown in the table of FIG.
A graph with respect to changes in Ws is shown in FIG. FIG. 27
(b) shows breakdown voltage maintaining region width Ws = 3, 6, 11, 21, 31
(Μm) is an X component electric field distribution curve in the range of X: 0 to 43 (on the X1-X1 ′ line) at Y = 0.05 for each example of the present invention. The maximum electric field strength was Ws = 3, 6, 11, 21, 31 in ascending order. The value of the maximum electric field strength is shown in the table of FIG. 29 (a), and the graph with respect to the change of Ws is shown in FIG. 29 (b).
【００６９】図２８(a)は、耐圧維持領域幅Ｗｓ＝３,
６，１１，２１，３１（μｍ）とした各本発明例につい
てのＹ＝５．６８におけるＸ：０〜４３の範囲（Ｘ２−
Ｘ２'線上）におけるＸ成分電界分布曲線である。最大
電界強度は、小さい順にＷｓ＝３,６，１１,２１，３１
の場合となった。その最大電界強度の値を図２９(a)の
表に、Ｗｓの変化に対するグラフを図２９(b)に示す。
図２８(b)は、耐圧維持領域幅Ｗｓ＝３,６，１１，２
１，３１（μｍ）とした各本発明例についてのＹ＝６に
おけるＸ：０〜４３の範囲（Ｘ３−Ｘ３'線上）におけ
るＸ成分電界分布曲線である。最大電界強度は、小さい
順にＷｓ＝３,６，１１,２１，３１の場合となった。そ
の最大電界強度の値を図２９(a)の表に、Ｗｓの変化に
対するグラフを図２９(b)に示す。FIG. 28A shows the breakdown voltage maintaining region width Ws = 3,
The range of X: 0 to 43 at Y = 5.68 (X2−6,11,21,31 (μm))
It is an X component electric field distribution curve in (on X2 'line). The maximum electric field strength is Ws = 3, 6, 11, 21, 31 in ascending order.
That was the case. The value of the maximum electric field strength is shown in the table of FIG. 29 (a), and the graph with respect to the change of Ws is shown in FIG. 29 (b).
FIG. 28B shows the breakdown voltage maintaining region width Ws = 3, 6, 11, and 2.
It is an X component electric field distribution curve in the range of X: 0-43 (on the X3-X3 'line) in Y = 6 about 1,31 (micrometer) each of this invention example. The maximum electric field strength was Ws = 3, 6, 11, 21, 31 in ascending order. The value of the maximum electric field strength is shown in the table of FIG. 29 (a), and the graph with respect to the change of Ws is shown in FIG. 29 (b).
【００７０】次に、以上のシミュレーション２の結果を
受けて考察し本発明の技術的意義をより明らかにする。Next, the technical significance of the present invention will be made clearer by considering the results of the above simulation 2.
【００７１】（１）電界相殺効果
まず、素子中央の耐圧維持領域における電界相殺効果に
つき考察する。図２２のグラフによれば、耐圧維持領域
幅Ｗｓが減少するに従って素子中央の電界強度が低下す
ることがわかる。図２３の表及びグラフに示されるよう
に、最大電界強度は耐圧維持領域幅Ｗｓが減少するに従
って低下する。図２２のグラフを参照すれば、最大電界
強度の低下に従って全体的に電界強度分布が低下し、Ｗ
ｓ＝３（μｍ）あっては全体として０（Ｖ/ｃｍ）とな
る。シリコン表面の電界強度も次第に低下しＷｓ＝３
（μｍ）あっては０（Ｖ/ｃｍ）となる。図２１のグラ
フによれば、Ｐ型活性領域２１の内端コーナー部２８に
生じる最大電界がＷｓの減少に従って低下する。(1) Electric Field Canceling Effect First, the electric field canceling effect in the breakdown voltage maintaining region in the center of the element will be considered. From the graph of FIG. 22, it can be seen that the electric field strength at the center of the element decreases as the breakdown voltage maintaining region width Ws decreases. As shown in the table and graph of FIG. 23, the maximum electric field strength decreases as the breakdown voltage maintaining region width Ws decreases. Referring to the graph of FIG. 22, the electric field strength distribution generally decreases as the maximum electric field strength decreases, and
When s = 3 (μm), it becomes 0 (V / cm) as a whole. The electric field strength on the silicon surface also gradually decreases and Ws = 3
(Μm), it becomes 0 (V / cm). According to the graph of FIG. 21, the maximum electric field generated at the inner end corner portion 28 of the P-type active region 21 decreases as Ws decreases.
【００７２】以上の電界強度の低下の原因は、図２４の
電界強度２次元分布図を参照して考察するとわかりやす
い。図２４(a)（Ｗｓ＝３１）においては、対岸同士の
空乏層はほとんど重なっていない。図２４(b)（Ｗｓ＝
２１）においては、対岸同士の空乏層は確実に重なって
干渉し合う。このとき、右側の接合内端から伸びる空乏
層中の電界ベクトルの方向と左側の接合内端から伸びる
空乏層中の電界ベクトルの方向とが逆であるため、干渉
して電界を弱め合う（電界相殺効果）。そのために、素
子中央及びＰ型活性領域２１の内端コーナー部２８の電
界強度が低下したのである。図２４(c)（Ｗｓ＝１１）
→(d)（Ｗｓ＝６）→(e)（Ｗｓ＝３）となるに従って、
干渉が強まる結果、電界相殺効果は高まり、電界強度が
低下するものである。The cause of the above-mentioned decrease in electric field strength can be easily understood by considering with reference to the electric field strength two-dimensional distribution chart of FIG. In FIG. 24A (Ws = 31), the depletion layers on the opposite banks do not substantially overlap. Figure 24 (b) (Ws =
In 21), the depletion layers on the opposite banks certainly overlap and interfere with each other. At this time, the direction of the electric field vector in the depletion layer extending from the inner edge of the junction on the right side is opposite to the direction of the electric field vector in the depletion layer extending from the inner edge of the left side junction, so they interfere and weaken the electric field (electric field Offset effect). As a result, the electric field strength at the center of the device and at the inner corner 28 of the P-type active region 21 is lowered. Figure 24 (c) (Ws = 11)
→ (d) (Ws = 6) → (e) (Ws = 3)
As a result of stronger interference, the electric field canceling effect is enhanced and the electric field strength is reduced.
【００７３】（２）活性領域外周の平面接合における最
大電界強度の低下
次に、活性領域外周の平面接合における電界強度の低下
につき考察する。図２０のグラフによれば、耐圧維持領
域幅Ｗｓが減少するに従って活性領域外周の平面接合に
おける最大電界強度が低下することがわかる。図２３の
表及びグラフにも示されるように、最大電界強度は耐圧
維持領域幅Ｗｓが減少するに従って低下する。(2) Reduction of Maximum Electric Field Strength in Planar Junction on Outer Edge of Active Region Next, consideration will be given to reduction of electric field strength in plane junction on the outer circumference of active region. From the graph of FIG. 20, it can be seen that the maximum electric field strength at the planar junction around the outer periphery of the active region decreases as the width Ws of breakdown voltage maintaining region decreases. As shown in the table and graph of FIG. 23, the maximum electric field strength decreases as the breakdown voltage maintaining region width Ws decreases.
【００７４】以上の最大電界強度の低下の原因は、図２
０のグラフに加え図２４の電界強度２次元分布図を参照
して考察するとわかりやすい。図２４(a)（Ｗｓ＝３
１）→(b)（Ｗｓ＝２１）→(c)（Ｗｓ＝１１）→(d)
（Ｗｓ＝６）→(e)（Ｗｓ＝３）となるに従って、空乏
層の最下端が下降するのがわかる。空乏層は際限無く拡
大するのではなく、不純物の高濃度領域に達するとその
拡大は抑止される。この高濃度領域は半導体基板１及び
半導体基板１付近のエピタキシャル層の最下層である。
エピタキシャル層の最下層の高濃度領域（以下「オート
ドーピング層」という。）は、エピタキシャル成長中、
及びその後の高温熱処理中に半導体基板１の不純物が拡
散しエピタキシャル層に進出することにより形成され
る。本シミュレーションにおいては半導体基板１とエピ
タキシャル層の界面は深さＹ＝２１（μｍ）である。本
シミュレーションによれば、活性領域外周の平面接合に
おける最大電界強度の低下に影響を与える程度のオート
ドーピング層（以下「実効オートドーピング層」とい
う。）は、深さＹ＝２０（μｍ）程度から始まり、半導
体基板界面までの１（μｍ）程度の厚みである。Ｗｓ＝
３１では定かでないが、Ｗｓ＝２１では、空乏層最下端
は実効オートドーピング層に達し、最大電界強度が低下
する。実効オートドーピング層に到達した空乏層は、そ
の拡大が抑止される。その結果、実効オートドーピング
層及びその付近の比較的下層のエピタキシャル層中にお
ける電界強度が高まる。比較的下層のエピタキシャル層
中の電界強度が高まる結果、接合付近の電界強度が反対
に低下する。図２０のグラフを参照すると、Ｗｓ＝１
１，６，３においては明らかにそのような現象により電
界強度は略台形状に分布することがわかる。接合付近の
電界強度が低下する結果、最大電界強度が低下する。The cause of the decrease in the maximum electric field strength is as shown in FIG.
In addition to the graph of 0, it is easy to understand by referring to the electric field intensity two-dimensional distribution chart of FIG. Figure 24 (a) (Ws = 3
1) → (b) (Ws = 21) → (c) (Ws = 11) → (d)
It can be seen that the lowermost end of the depletion layer descends as (Ws = 6) → (e) (Ws = 3). The depletion layer does not expand indefinitely, but its expansion is suppressed when reaching a high impurity concentration region. This high-concentration region is the bottom layer of the semiconductor substrate 1 and the epitaxial layer near the semiconductor substrate 1.
The high-concentration region (hereinafter referred to as “autodoping layer”) at the bottom of the epitaxial layer is
Then, during the high temperature heat treatment thereafter, the impurities of the semiconductor substrate 1 are diffused and penetrate into the epitaxial layer to be formed. In this simulation, the interface between the semiconductor substrate 1 and the epitaxial layer has a depth Y = 21 (μm). According to this simulation, the auto-doping layer (hereinafter referred to as “effective auto-doping layer”) to the extent that it affects the reduction of the maximum electric field strength in the planar junction around the active region has a depth Y = about 20 (μm). The thickness is about 1 (μm) from the beginning to the interface of the semiconductor substrate. Ws =
Although it is not clear in 31, when Ws = 21, the lowermost end of the depletion layer reaches the effective autodoping layer, and the maximum electric field strength decreases. The expansion of the depletion layer reaching the effective autodoping layer is suppressed. As a result, the electric field strength in the effective autodoping layer and in the relatively lower epitaxial layer in the vicinity thereof is increased. As a result of the increase in the electric field strength in the lower epitaxial layer, the electric field strength near the junction is decreased. Referring to the graph of FIG. 20, Ws = 1
It is apparent that in Nos. 1, 6 and 3, the electric field strength is distributed in a substantially trapezoidal shape due to such a phenomenon. As a result of the decrease in the electric field strength near the junction, the maximum electric field strength decreases.
【００７５】（３）まとめ
実際の設計においては、以上のシミュレーションを参考
にし、電界相殺効果とオートドーピング層による効果を
実効あらしめるようにすることが好ましい。(3) Summary In the actual design, it is preferable to refer to the above simulations so that the electric field canceling effect and the effect of the autodoping layer are effectively exhibited.
【００７６】[0076]
【発明の効果】上述したように請求項１記載の発明によ
れば、耐圧維持領域の増大、ひいては素子の大面積化を
招くことなく高耐圧化を図ることができるばかりでな
く、耐圧維持領域を従来技術より縮小し素子の小面積化
を図りつつ高耐圧化を図ることも可能であるという効果
がある。また、耐圧を低下させること無く、素子全体に
対する活性領域の占有する面積を拡大することができる
という効果がある。また、耐圧を低下させること無く、
素子外形寸法の変更に伴う曲面接合の増減を回避できる
という効果がある。As described above, according to the first aspect of the invention, not only the breakdown voltage maintaining region can be increased, but the breakdown voltage maintaining region can be increased without increasing the area of the device. There is an effect that it is possible to achieve higher breakdown voltage while reducing the size of the device as compared with the prior art to reduce the area of the device. Further, there is an effect that the area occupied by the active region with respect to the entire element can be expanded without lowering the breakdown voltage. Also, without lowering the breakdown voltage,
There is an effect that it is possible to avoid an increase or decrease in curved surface joint due to a change in the outer dimension of the element.
【００７７】上述したように請求項２記載の発明によれ
ば、第一電極及び第二電極が素子表面側に形成されるの
で、裏面側から表面側への配線手段を要することなくプ
リント回路基板等に実装することができるという効果が
ある。As described above, according to the second aspect of the present invention, the first electrode and the second electrode are formed on the front surface side of the element, so that the printed circuit board does not require wiring means from the back surface side to the front surface side. And so on.
【００７８】上述したように請求項３記載の発明によれ
ば、第一導電型領域の半導体素材表面への露出部を複数
とするので、ＰＮ接合の対岸距離を容易に小さくするこ
とができ、その結果、前記電界相殺効果を高めることが
できるという効果がある。また、第一導電型領域の半導
体素材表面への露出部を素子表面に均一に配置すること
により、素子表面において広範且つ均一に電界相殺効果
を利用した耐圧維持領域を形成することができるという
効果がある。。As described above, according to the third aspect of the invention, since the first conductivity type region has a plurality of exposed portions on the surface of the semiconductor material, the opposite bank distance of the PN junction can be easily reduced. As a result, there is an effect that the electric field offsetting effect can be enhanced. Further, by uniformly disposing the exposed portion of the first conductivity type region on the surface of the semiconductor material on the device surface, it is possible to form a breakdown voltage maintaining region that widely and uniformly utilizes the electric field cancellation effect on the device surface. There is. .
【００７９】上述したように請求項４記載の発明によれ
ば、ガードリングを備えたより高耐圧の耐圧維持構造が
得られるという効果がある。As described above, according to the invention described in claim 4, there is an effect that a breakdown voltage maintaining structure having a higher breakdown voltage including a guard ring can be obtained.
【００８０】上述したように請求項５記載の発明によれ
ば、第二導電型低濃度領域によりＪＴＥ（Junction-Ter
mination -Extension）構造が構成され、空乏層が第二
導電型低濃度領域内で拡張されて電界集中が緩和され、
一定印加電圧に対する最大電界Ｅｍａｘが下がることと
なり、より高耐圧の耐圧維持構造が得られるという効果
がある。As described above, according to the fifth aspect of the invention, the JTE (Junction-Ter) is formed by the second conductivity type low concentration region.
mination-Extension) structure is formed, the depletion layer is expanded in the second conductivity type low-concentration region, and the electric field concentration is relaxed.
The maximum electric field Emax with respect to a constant applied voltage is lowered, and there is an effect that a breakdown voltage maintaining structure having a higher breakdown voltage can be obtained.
【００８１】上述したように請求項６記載の発明によれ
ば、耐圧維持領域上にゲートパッドを配することができ
るので、耐圧維持領域の上部をゲートパッド敷設領域と
して立体的に有効利用することにより、従来技術に比較
して、活性領域の占有する面積をゲートパッド敷設領域
分拡大することができるという効果がある。As described above, according to the invention of claim 6, since the gate pad can be arranged on the breakdown voltage maintaining region, the upper part of the breakdown voltage maintaining region can be effectively used three-dimensionally as the gate pad laying region. As a result, there is an effect that the area occupied by the active region can be expanded by the amount of the gate pad laying region as compared with the conventional technique.
【００８２】上述したように請求項７記載の発明によれ
ば次の効果がある。第二導電型リング領域の内周面上の
任意の一点から伸びる空乏層と、その対岸の第二導電型
活性領域外周面上の一点とから伸びる空乏層とが干渉
し、互いに逆向きの電界ベクトル成分が打ち消し合って
電界強度を低下させる電界相殺効果が得られる。この電
界相殺効果を利用した第二導電型リング領域と第二導電
型活性領域とに挟まれる第一導電型領域の露出面直下部
は、極めて狭小にすることができるので、活性領域周囲
の耐圧維持のための領域を従来技術に比較して狭小とす
ることができ、活性領域の占有面積を十分に取って、高
耐圧を維持、向上することができる。また、耐圧を維持
しつつ素子の小面積化も可能である。As described above, the invention according to claim 7 has the following effects. The depletion layer extending from any one point on the inner peripheral surface of the second conductivity type ring region interferes with the depletion layer extending from one point on the outer peripheral surface of the second conductivity type active region on the opposite shore, and electric fields in opposite directions to each other. An electric field canceling effect is obtained in which the vector components cancel each other out to reduce the electric field strength. The area directly below the exposed surface of the first-conductivity-type area sandwiched between the second-conductivity-type ring area and the second-conductivity-type active area that utilizes this electric field canceling effect can be extremely narrowed, so that the breakdown voltage around the active area is reduced. The region for maintaining can be made narrower than that of the conventional technique, and the area occupied by the active region can be sufficiently taken to maintain or improve the high breakdown voltage. Further, it is possible to reduce the area of the element while maintaining the breakdown voltage.
【図１】(a)は本発明の第１の実施形態の半導体素子の
シリコン表面以下を示す平面図、(b)はD1-D1断面図であ
る。FIG. 1A is a plan view showing a silicon surface and below of a semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a D1-D1 sectional view.
【図２】(a)は本発明の第２の実施形態の半導体素子の
シリコン表面以下を示す平面図、(b)はD2-D2断面図であ
る。2A is a plan view showing the silicon surface and below of a semiconductor device according to a second embodiment of the present invention, and FIG. 2B is a D2-D2 sectional view.
【図３】(a)は本発明の第３の実施形態の半導体素子の
シリコン表面パターンを示す平面図、(b)は他のシリコ
ン表面パターンを示す平面図である。3A is a plan view showing a silicon surface pattern of a semiconductor device according to a third embodiment of the present invention, and FIG. 3B is a plan view showing another silicon surface pattern.
【図４】図３(a)におけるD3-D3断面図である。FIG. 4 is a sectional view taken along line D3-D3 in FIG.
【図５】(a)は本発明の第４の実施形態の半導体素子の
シリコン表面以下を示す平面図、(b)はD4-D4断面図であ
る。FIG. 5A is a plan view showing a silicon surface and below of a semiconductor device according to a fourth embodiment of the present invention, and FIG. 5B is a D4-D4 cross-sectional view.
【図６】(a)は本発明の第５の実施形態の半導体素子の
シリコン表面以下を示す平面図、(b)はD5-D5断面図であ
る。FIG. 6 (a) is a plan view showing the silicon surface and below of a semiconductor device according to a fifth embodiment of the present invention, and FIG. 6 (b) is a D5-D5 sectional view.
【図７】(a)は本発明の第６の実施形態の半導体素子を
示す平面図、(b)はD6-D6断面図である。7A is a plan view showing a semiconductor device according to a sixth embodiment of the present invention, and FIG. 7B is a sectional view taken along line D6-D6.
【図８】(a)は本発明の第７の実施形態の半導体素子の
シリコン表面以下を示す平面図、(b)はD7-D7断面図であ
る。FIG. 8A is a plan view showing the silicon surface and below of a semiconductor device according to a seventh embodiment of the present invention, and FIG. 8B is a sectional view taken along line D7-D7.
【図９】本発明例シミュレーション１のための平面図で
ある。FIG. 9 is a plan view for an example simulation 1 of the present invention.
【図１０】本発明例シミュレーション１における表計算
に供された表である。FIG. 10 is a table provided for a table calculation in the simulation example 1 of the present invention.
【図１１】本発明例シミュレーション１において得られ
た、素子外形寸法Ｌの変化に伴う各面積率Ｓ１／Ｓ，Ｓ
２／Ｓ，Ｓ３／Ｓの変化を表すグラフである。FIG. 11 shows the area ratios S1 / S, S according to changes in the element external dimension L obtained in the simulation example 1 of the present invention.
It is a graph showing change of 2 / S and S3 / S.
【図１２】本発明例シミュレーション１におけて従来比
を算出する表計算に供された表である。FIG. 12 is a table provided for a table calculation for calculating a conventional ratio in the simulation 1 of the present invention.
【図１３】本発明例シミュレーション１において得られ
た、素子外形寸法Ｌの変化に伴う各面積率の変化を表す
グラフである。本発明例の活性領域の面積率をＳ１ｎ／
Ｓ、耐圧維持領域の面積率をＳ２ｎ／Ｓとし、従来例の
活性領域の面積率をＳ１o／Ｓ、耐圧維持領域の面積率
をＳ２o／Ｓとしている。FIG. 13 is a graph showing a change in each area ratio with a change in the element external dimension L, which is obtained in the simulation example 1 of the present invention. The area ratio of the active region of the example of the present invention is S1n /
S, the area ratio of the breakdown voltage maintaining region is S2n / S, the area ratio of the conventional active region is S1o / S, and the area ratio of the breakdown voltage maintaining region is S2o / S.
【図１４】本発明例シミュレーション１において得られ
た、素子外形寸法Ｌの変化に伴う各面積率の向上率の変
化を表すグラフである。活性領域の面積率について本発
明例の従来例に対する比（「活性領域面積向上率」とい
う。）をＳ１：本/従とし、耐圧維持領域の面積率につ
いて本発明例の従来例に対する比（「耐圧維持領域面積
低下率」という。）をＳ２：本/従としている。FIG. 14 is a graph showing the change in the improvement rate of each area ratio with the change in the element external dimension L, which is obtained in the simulation example 1 of the present invention. Regarding the area ratio of the active region, the ratio of the present invention example to the conventional example (referred to as “active region area improvement ratio”) is S1: book / subordinate, and the area ratio of the breakdown voltage maintaining region is the ratio (“ "The breakdown voltage maintaining area reduction rate") is defined as S2: book / subordinate.
【図１５】本発明例シミュレーション１におけるメサ型
素子の断面図である。FIG. 15 is a cross-sectional view of a mesa-type element in the simulation example 1 of the present invention.
【図１６】本発明例シミュレーション１におけるメサ型
素子についての表計算に供された表である。FIG. 16 is a table provided for a table calculation for a mesa element in the simulation example 1 of the present invention.
【図１７】(a)は本発明例シミュレーション１における
メサ型素子についての従来比を算出する表計算に供され
た表であり、(b)はそれをグラフ化したものである。17 (a) is a table provided for a table calculation for calculating a conventional ratio for a mesa element in the simulation example 1 of the present invention, and FIG. 17 (b) is a graph thereof.
【図１８】本発明例シミュレーション２における計算対
象部分断面図である。本図においてＸ−Ｙ座標が定義さ
れる。なお、本図から図２９まではシミュレーション２
の参照用である。FIG. 18 is a partial cross-sectional view of a calculation target in the simulation 2 of the present invention. In this figure, XY coordinates are defined. In addition, from this figure to FIG. 29, the simulation 2
For reference.
【図１９】Ｘ＝０．１（μｍ）におけるＹ：０〜４６
（μｍ）の範囲の不純物濃度の片対数グラフである。FIG. 19: Y: 0 to 46 at X = 0.1 (μm)
It is a semi-logarithmic graph of the impurity concentration in the range of (μm).
【図２０】耐圧維持領域幅Ｗｓ＝３,６，１１，２１，
３１（μｍ）とした各本発明例についてのＸ＝０におけ
るＹ：０〜２５の範囲（Ｙ０−Ｙ０'線上）における電
界強度曲線である。FIG. 20 shows breakdown voltage maintaining region width Ws = 3, 6, 11, 21,
It is an electric field intensity curve in the range of Y: 0 to 25 (on the Y0-Y0 'line) at X = 0 for each example of the present invention set to 31 (μm).
【図２１】耐圧維持領域幅Ｗｓ＝３,６，１１，２１，
３１（μｍ）とした各本発明例についてのＸ＝３．６に
おけるＹ：０〜２５の範囲（Ｙ１−Ｙ１'線上）におけ
る電界強度曲線である。FIG. 21 shows breakdown voltage maintaining region width Ws = 3, 6, 11, 21,
It is an electric field intensity curve in the range of Y: 0 to 25 (on the Y1-Y1 'line) at X = 3.6 for each example of the present invention with 31 (μm).
【図２２】耐圧維持領域幅Ｗｓ＝３,６，１１，２１，
３１（μｍ）とした各本発明例についてのＸ＝３．６に
おけるＹ：０〜２５の範囲（Ｙ２−Ｙ２'線上）におけ
る電界強度曲線である。FIG. 22 shows breakdown voltage maintaining region width Ws = 3, 6, 11, 21,
It is an electric field intensity curve in the range of Y: 0 to 25 (on the Y2-Y2 'line) at X = 3.6 for each example of the present invention with 31 (μm).
【図２３】(a)は図２０,２１，２２のグラフにおける最
大値をまとめた表であり、(b)は(a)の表をグラフ化した
ものである。23A is a table summarizing the maximum values in the graphs of FIGS. 20, 21, and 22, and FIG. 23B is a graph of the table of FIG.
【図２４】耐圧維持領域幅Ｗｓ＝３,６，１１，２１，
３１（μｍ）とした各本発明例についての電界強度２次
元分布図である。24 is a breakdown voltage maintaining region width Ws = 3, 6, 11, 21,
FIG. 3 is a two-dimensional electric field intensity distribution chart for each example of the present invention with 31 (μm).
【図２５】耐圧維持領域幅Ｗｓ＝３,６，１１，２１，
３１（μｍ）とした各本発明例についてのＹ＝０．０５
におけるＸ：０〜４３の範囲（Ｘ１−Ｘ１'線上）にお
ける電位分布曲線である。FIG. 25 shows breakdown voltage maintaining region width Ws = 3, 6, 11, 21,
Y = 0.05 for each example of the present invention with 31 (μm)
Is a potential distribution curve in the range of X: 0 to 43 (on the X1-X1 ′ line) in FIG.
【図２６】本発明例シミュレーション２における酸化膜
直下の電位の評価に供される表(a)及びグラフ(b)であ
る。FIG. 26 is a table (a) and a graph (b) used for evaluation of the potential just below the oxide film in the simulation 2 of the present invention.
【図２７】(a)は、耐圧維持領域幅Ｗｓ＝３,６，１１，
２１，３１（μｍ）とした各本発明例についてのＹ＝０
におけるＸ：０〜４３の範囲（Ｘ０−Ｘ０'線上）にお
けるＸ成分電界分布曲線である。(b)は、耐圧維持領域
幅Ｗｓ＝３,６，１１，２１，３１（μｍ）とした各本
発明例についてのＹ＝０.０５におけるＸ：０〜４３の
範囲（Ｘ１−Ｘ１'線上）におけるＸ成分電界分布曲線
である。FIG. 27 (a) is a breakdown voltage maintaining region width Ws = 3, 6, 11,
Y = 0 for each example of the present invention with 21, 31 (μm)
3 is an X component electric field distribution curve in the range of X: 0 to 43 (on the X0-X0 ′ line) in FIG. (b) is a range of X: 0 to 43 (Y1-X1 'line on Y = 0.05 in each of the examples of the present invention in which breakdown voltage maintaining region width Ws = 3, 6, 11, 21, 31 (μm)). 3) is an X component electric field distribution curve in FIG.
【図２８】(a)は、耐圧維持領域幅Ｗｓ＝３,６，１１，
２１，３１（μｍ）とした各本発明例についてのＹ＝
５．６８におけるＸ：０〜４３の範囲（Ｘ２−Ｘ２'線
上）におけるＸ成分電界分布曲線である。(b)は、耐圧
維持領域幅Ｗｓ＝３,６，１１，２１，３１（μｍ）と
した各本発明例についてのＹ＝６におけるＸ：０〜４３
の範囲（Ｘ３−Ｘ３'線上）におけるＸ成分電界分布曲
線である。FIG. 28 (a) is a breakdown voltage maintaining region width Ws = 3, 6, 11,
Y = 21, 31 (μm) for each example of the present invention
It is an X component electric field distribution curve in the range of X: 0 to 43 in 5.68 (on the X2-X2 ′ line). (b) shows X: 0 to 43 at Y = 6 for each example of the present invention in which the breakdown voltage maintaining region width Ws = 3, 6, 11, 21, 31 (μm).
3 is an X component electric field distribution curve in the range (on the line X3-X3 ').
【図２９】(a)はシリコン中の各深さにおける横方向Ｘ
成分電界分布の最大電界強度の値をまとめた表であり、
(b)は(a)の表をグラフ化したものである。FIG. 29 (a) is a horizontal direction X at each depth in silicon.
It is a table summarizing the values of the maximum electric field strength of the component electric field distribution,
(b) is a graph of the table of (a).
【図３０】従来の最も基本的な構造の半導体素子１０１
の平面図(a)とＢ−Ｂ断面図(b)である。FIG. 30 is a conventional semiconductor device 101 having the most basic structure.
3A is a plan view (a) and a BB sectional view (b).
【図３１】従来のガードリングを備えた半導体素子１０
２の平面図(a)及びＣ−Ｃ断面図(b)である。FIG. 31 is a semiconductor device 10 including a conventional guard ring.
2 is a plan view (a) and a sectional view taken along line CC of FIG.
【図３２】従来のＪＴＥ構造を備えた半導体素子１０３
の平面図(a)及びＤ−Ｄ断面図(b)である。FIG. 32 is a semiconductor device 103 having a conventional JTE structure.
3A is a plan view (a) and a DD cross-sectional view (b) of FIG.
【図３３】従来例を対象として各面積率概算のための平
面図である。FIG. 33 is a plan view for estimating the area ratios of a conventional example.
【図３４】従来例を対象として各面積率概算における表
計算に供された表である。FIG. 34 is a table provided for a table calculation in each area ratio approximation targeting a conventional example.
【図３５】従来例を対象として各面積率概算において得
られた、素子外形寸法Ｌの変化に伴う各面積率Ｓ１／
Ｓ，Ｓ２／Ｓ，Ｓ３／Ｓの変化を表すグラフである。FIG. 35 is an area ratio S1 / associated with a change in the external dimension L of the element, which is obtained in the area ratio estimation for the conventional example.
It is a graph showing change of S, S2 / S, and S3 / S.
１…半導体基板 ２…半導体層（エピタキシャル層）
２１…Ｐ型活性領域 ２２…Ｎ-型領域 ２３…シリコ
ン酸化膜 ２４,２５…保護膜 ２６…陽極電極
２７…陰極電極1 ... Semiconductor substrate 2 ... Semiconductor layer (epitaxial layer)
21 ... P-type active region 22 ... N - type region 23 ... Silicon oxide film 24, 25 ... Protective film 26 ... Anode electrode 27 ... Cathode electrode
Claims (7)
電型である第二導電型の不純物を選択的に導入し、不純
物活性化処理を施すことより形成された第二導電型活性
領域と、前記半導体素材内の領域であって前記第二導電
型活性領域に接合する第一導電型領域と、前記表面上を
所定パターンで覆う絶縁膜と、前記表面の外周に連続す
る外周面を前記表面から所定の深さまで被覆する保護膜
と、前記第一導電型領域側の第一電極と、前記絶縁膜に
設けられた開口部を介して前記第二導電型活性領域に接
続する第二電極とを備える半導体素子において、前記第
一導電型領域と前記第二導電型活性領域とで構成される
ＰＮ接合の一方の終端が前記絶縁膜下の前記表面上に在
り、他方の終端が前記保護膜下の前記外周面上に在り、
前記第一導電型領域が前記第二導電型活性領域に包囲さ
れた範囲で前記表面に露出し、その露出面が前記絶縁膜
により覆われてなることを特徴とする半導体素子。1. An active region of the second conductivity type formed by selectively introducing impurities of the second conductivity type of the opposite conductivity type into the surface of a semiconductor material of the first conductivity type and performing an impurity activation treatment. A first conductivity type region which is a region in the semiconductor material and is bonded to the second conductivity type active region, an insulating film which covers the surface with a predetermined pattern, and an outer peripheral surface which is continuous with the outer periphery of the surface. A protective film covering the surface to a predetermined depth, a first electrode on the first conductivity type region side, and a second electrode connected to the second conductivity type active region through an opening provided in the insulating film. In a semiconductor device including an electrode, one end of a PN junction composed of the first conductivity type region and the second conductivity type active region is present on the surface under the insulating film, and the other end thereof is On the outer peripheral surface under the protective film,
A semiconductor device, wherein the first conductivity type region is exposed to the surface in a range surrounded by the second conductivity type active region, and the exposed surface is covered with the insulating film.
純物を選択的に導入することより、前記第一導電型領域
より高濃度の第一導電型高濃度領域が、前記第一導電型
領域に包囲された範囲で前記表面に露出して形成され、
その露出面が前記絶縁膜に設けられた開口部を介して前
記第一電極と接続してなることを特徴とする請求項１に
記載の半導体素子。2. A first-conductivity-type high-concentration region having a higher concentration than that of the first-conductivity-type region is obtained by selectively introducing impurities of the first-conductivity-type into the surface of the semiconductor material. Exposed on the surface in a region surrounded by a region,
The semiconductor element according to claim 1, wherein the exposed surface is connected to the first electrode through an opening provided in the insulating film.
性領域に包囲された複数の部分で前記表面に露出してな
ることを特徴とする請求項１に記載の半導体素子。3. The semiconductor device according to claim 1, wherein the first conductivity type region is exposed at the surface at a plurality of portions surrounded by the second conductivity type active region.
囲内に、前記第二導電型活性領域の内周に沿って形成さ
れた一又は二本以上のガードリングを有することを特徴
とする請求項１又は請求項３に記載の半導体素子。4. One or two or more guard rings formed along the inner circumference of the second conductivity type active region in a range surrounded by the second conductivity type active region. The semiconductor element according to claim 1 or claim 3.
度の第二導電型高濃度領域と比較的低濃度の第二導電型
低濃度領域とから構成され、前記第二導電型低濃度領域
が前記第二導電型高濃度領域の少なくとも内周部に接合
し、前記第二導電型高濃度領域の内周に隣接して前記表
面にリング状に露出するように形成され、前記第二導電
型低濃度領域に包囲された範囲で前記第一導電型領域が
前記表面に露出してなることを特徴とする請求項１又は
請求項３に記載の半導体素子。5. The second conductivity type active region is composed of a second conductivity type high concentration region having a relatively high concentration and a second conductivity type low concentration region having a relatively low concentration, and the second conductivity type low concentration region. The concentration region is bonded to at least the inner peripheral portion of the second conductivity type high concentration region, is formed so as to be adjacent to the inner periphery of the second conductivity type high concentration region and exposed in a ring shape on the surface, 4. The semiconductor element according to claim 1, wherein the first conductivity type region is exposed on the surface in a range surrounded by the second conductivity type low concentration region.
電型である第二導電型の不純物を選択的に導入し、不純
物活性化処理を施すことより形成された第二導電型活性
領域と、前記半導体素材内の領域であって前記第二導電
型活性領域に接合する第一導電型領域と、前記表面上を
所定パターンで覆う絶縁膜と、前記表面の外周に連続す
る外周面を前記表面から所定の深さまで被覆する保護膜
と、前記第一導電型領域側の第一電極と、前記絶縁膜に
設けられた開口部を介して前記第二導電型活性領域に接
続する第二電極とを備える半導体素子において、前記第
一導電型領域と前記第二導電型活性領域とで構成される
ＰＮ接合の一方の終端が前記絶縁膜下の前記表面上に在
り、他方の終端が前記保護膜下の前記外周面上に在り、
前記第一導電型領域が前記第二導電型活性領域に包囲さ
れた複数の部分で前記表面に露出し、その各露出面上に
ゲート絶縁膜が敷設され、該ゲート絶縁膜上にゲート電
極が敷設されてなるＭＩＳ素子を複数個備え、前記第一
導電型領域は前記第二導電型活性領域に包囲された他の
部分で前記表面に露出し、その露出面が前記絶縁膜によ
り覆われ、前記各ゲート電極と導通する外部接続用ゲー
ト電極パッドが前記他の部分を覆う前記絶縁膜上に設け
られてなることを特徴とする半導体素子。6. A second-conductivity-type active region formed by selectively introducing impurities of a second-conductivity type of opposite conductivity type into the surface of a first-conductivity-type semiconductor material and performing impurity activation treatment. A first conductivity type region which is a region in the semiconductor material and is bonded to the second conductivity type active region, an insulating film which covers the surface with a predetermined pattern, and an outer peripheral surface which is continuous with the outer periphery of the surface. A protective film covering the surface to a predetermined depth, a first electrode on the first conductivity type region side, and a second electrode connected to the second conductivity type active region through an opening provided in the insulating film. In a semiconductor device including an electrode, one end of a PN junction composed of the first conductivity type region and the second conductivity type active region is present on the surface under the insulating film, and the other end thereof is On the outer peripheral surface under the protective film,
The first conductivity type region is exposed on the surface at a plurality of portions surrounded by the second conductivity type active region, a gate insulating film is laid on each exposed surface, and a gate electrode is formed on the gate insulating film. A plurality of MIS elements that are laid, the first conductivity type region is exposed to the surface at another portion surrounded by the second conductivity type active region, and the exposed surface is covered with the insulating film, A semiconductor element, wherein an external connection gate electrode pad that is electrically connected to each of the gate electrodes is provided on the insulating film that covers the other portion.
電型である第二導電型の不純物を選択的に導入すること
より該半導体素材の表層外周部にリング状に形成された
第二導電型リング領域と、前記半導体素材の表面へ第二
導電型の不純物を選択的に導入し、不純物活性化処理を
施すことより前記第二導電型リング領域の内側に形成さ
れた第二導電型活性領域と、前記半導体素材内の領域で
あって前記第二導電型リング領域及び前記第二導電型活
性領域の両者に接合し該両者間に介在する第一導電型領
域と、前記表面上を所定パターンで覆う絶縁膜と、前記
表面の外周に連続する外周面を前記表面から所定の深さ
まで被覆する保護膜と、前記第一導電型領域側の第一電
極と、前記絶縁膜に設けられた開口部を介して前記第二
導電型活性領域に接続する第二電極とを備え、前記第二
導電型リング領域と前記第一導電型領域とで構成される
ＰＮ接合の一方の終端が前記絶縁膜下の前記表面上に在
り、他方の終端が前記保護膜下の前記外周面上に在り、
前記第二導電型リング領域及び前記第一導電型領域の前
記表面への露出面が前記絶縁膜により覆われてなること
を特徴とする半導体素子。7. A ring-shaped second material formed on the outer peripheral portion of the surface of the semiconductor material by selectively introducing impurities of the opposite conductivity type of the second conductivity type into the surface of the semiconductor material of the first conductivity type. A second conductivity type ring region and a second conductivity type formed inside the second conductivity type ring region by selectively introducing impurities of the second conductivity type into the surface of the semiconductor material and performing an impurity activation treatment. An active region, a region in the semiconductor material, a first conductivity type region which is joined to both the second conductivity type ring region and the second conductivity type active region and is interposed between the two, and the surface. An insulating film provided with a predetermined pattern, a protective film covering the outer peripheral surface continuous to the outer periphery of the surface to a predetermined depth from the surface, a first electrode on the side of the first conductivity type region, and provided on the insulating film Connected to the second conductivity type active region through the opening. A second electrode connected to the second conductive type ring region, one end of a PN junction formed of the second conductive type ring region and the first conductive type region is present on the surface under the insulating film, and the other end is On the outer peripheral surface under the protective film,
A semiconductor element, wherein exposed surfaces of the second conductivity type ring region and the first conductivity type region to the surface are covered with the insulating film.
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| JP2005311208A (en) * | 2004-04-23 | 2005-11-04 | Sharp Corp | Solid-state imaging element, manufacturing method therefor, and electronic information apparatus |
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| JP2010258327A (en) * | 2009-04-28 | 2010-11-11 | Fuji Electric Systems Co Ltd | Vertical gallium nitride semiconductor device having reverse withstand voltage |
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| JP2017168579A (en) * | 2016-03-15 | 2017-09-21 | 三菱電機株式会社 | Semiconductor device |
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