JP2003318315A - Transistor bare chip mounting wiring substrate and its manufacturing method - Google Patents

Transistor bare chip mounting wiring substrate and its manufacturing method

Info

Publication number
JP2003318315A
JP2003318315A JP2002123274A JP2002123274A JP2003318315A JP 2003318315 A JP2003318315 A JP 2003318315A JP 2002123274 A JP2002123274 A JP 2002123274A JP 2002123274 A JP2002123274 A JP 2002123274A JP 2003318315 A JP2003318315 A JP 2003318315A
Authority
JP
Japan
Prior art keywords
wiring board
plate
transistor bare
shaped conductive
bare chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002123274A
Other languages
Japanese (ja)
Inventor
Hiroaki Takahashi
宏明 高橋
Hiroshi Tsutsumi
寛 堤
Shoji Hara
昇司 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Furukawa Electric Co Ltd
Original Assignee
Furukawa Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furukawa Electric Co Ltd filed Critical Furukawa Electric Co Ltd
Priority to JP2002123274A priority Critical patent/JP2003318315A/en
Publication of JP2003318315A publication Critical patent/JP2003318315A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/852—Applying energy for connecting
    • H01L2224/85201—Compression bonding
    • H01L2224/85205—Ultrasonic bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transistor bare chip mounting wiring substrate which reduces heating loss and improves a heat sink and to provide a method for manufacturing the transistor bare chip mounting wiring substrate which can reduce a cost and can improve productivity. <P>SOLUTION: A plurality of transistor bare chips 3 are mounted along the end of the wiring substrate 11, the collector electrodes of the plurality of the chips 3 are connected to the one end of a plate-like conductive member 7 via a conductive passage 2a, emitter electrodes 5 are connected directly to the plate-like conductive members 8, and the other end of the member 7 constitutes the external connection terminal of the wiring substrate 11. The members 7, 8 are formed by press-cutting a punching member integrated with a plurality of the members 7, 8. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は自動車等に用いられ
るトランジスタベアチップ実装配線基板、特に発熱の大
きなパワーモジュール構造に好適なトランジスタベアチ
ップ実装配線基板およびその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor bare chip mounting wiring board used in automobiles and the like, and more particularly to a transistor bare chip mounting wiring board suitable for a power module structure which generates a large amount of heat and a manufacturing method thereof.

【０００２】[0002]

【従来の技術】自動車においては、部品の搭載スペース
に限界があることから、部品の実装密度を上げるため
に、搭載部品の小型化のニーズが高まっている。そのた
め、例えば、アクチュエータやランプなどの制御用ドラ
イバについては、メカニカルなリレーからバイポーラト
ランジスタや電界効果トランジスタといった半導体スイ
ッチへの置き換えが進んでいる。このような半導体スイ
ッチとしては樹脂モールドパッケージされたものが普及
しているが、更なる小型化を図る目的で、配線基板上に
ベアチップ実装することも行われている。例えば、トラ
ンジスタなどの標準的な樹脂モールドパッケージである
ＴＯ−２２０タイプでは、樹脂モールドの外形が約１０
ｍｍ×１０ｍｍであるのに対し、トランジスタベアチッ
プは５ｍｍ×５ｍｍ程度であり、トランジスタベアチッ
プ実装を採用することで、投影面積を４分の１にするこ
とができる。2. Description of the Related Art In automobiles, since there is a limit to the mounting space for components, there is an increasing need for miniaturization of the mounted components in order to increase the mounting density of the components. For this reason, for example, for control drivers such as actuators and lamps, replacement of mechanical relays with semiconductor switches such as bipolar transistors and field effect transistors is in progress. As such a semiconductor switch, a resin-molded package is widely used, but a bare chip is also mounted on a wiring substrate for the purpose of further miniaturization. For example, the TO-220 type, which is a standard resin mold package for transistors and the like, has a resin mold outline of about 10
The size of the transistor bare chip is about 5 mm × 5 mm, while the size of the transistor bare chip is about 5 mm × 5 mm. By adopting the transistor bare chip mounting, the projected area can be reduced to ¼.

【０００３】このトランジスタベアチップ実装における
配線方式としては、一般的にワイヤーボンディングが採
用されている。例えば図５に示すように、コレクタ電極
が下面に形成されたトランジスタベアチップ３（バイポ
ーラトランジスタの場合）を配線基板１の導電路２ａ上
に搭載する。その後、トランジスタチップ３上のベース
電極４（制御電極）とエミッタ電極５（電流通路電極）
を、配線基板１上の導電路２ｂ、２ｃに、数十μｍ程度
の径の金属線（アルミ、銅、金など）からなるボンディ
ングワイヤー６を一本ずつ超音波金属接合して、電気的
に接続する。Wire bonding is generally adopted as a wiring system for mounting the transistor bare chip. For example, as shown in FIG. 5, a transistor bare chip 3 (in the case of a bipolar transistor) having a collector electrode formed on the lower surface is mounted on the conductive path 2 a of the wiring board 1. After that, the base electrode 4 (control electrode) and the emitter electrode 5 (current passage electrode) on the transistor chip 3
Is electrically connected to the conductive paths 2b, 2c on the wiring board 1 by ultrasonic metal bonding one by one with a bonding wire 6 made of a metal wire (aluminum, copper, gold, etc.) having a diameter of about several tens of μm. Connecting.

【０００４】また、配線基板１から外部への電気接続を
行うために、配線基板１の端部の導電路２ａには板状導
電部材７の端部がハンダ付けなどにより接続される。通
常、板状導電部材７は、複数の板状導電部材７が一体に
形成された打ち抜き部材（いわゆるリードフレーム）を
ハンダ付けなどにより配線基板１に金属接合した後、不
要部分をプレスカットして形成する。配線基板１に接続
された板状導電部材７の配線基板１と反対側の端部は、
別の配線基板にハンダ付けされたり、コネクタのオス端
子となる。In order to electrically connect the wiring board 1 to the outside, the end of the plate-shaped conductive member 7 is connected to the conductive path 2a at the end of the wiring board 1 by soldering or the like. Usually, the plate-shaped conductive member 7 is formed by punching a plurality of plate-shaped conductive members 7 integrally formed (so-called lead frame) on the wiring board 1 by metal bonding, and then press-cutting unnecessary portions. Form. The end of the plate-shaped conductive member 7 connected to the wiring board 1 on the opposite side of the wiring board 1 is
Soldered to another wiring board or used as a male terminal of a connector.

【０００５】[0005]

【発明が解決しようとする課題】ところで、半導体スイ
ッチの性能の指標としてオン抵抗がある。半導体スイッ
チの損失はそこに流れる電流値の二乗とオン抵抗の積で
表される。したがって、小型の半導体スイッチに大きな
電流を流す場合には、通電による発熱を極力抑えるため
に、オン抵抗の低減が特に重要となる。On-resistance is an index of the performance of semiconductor switches. The loss of a semiconductor switch is represented by the product of the square of the current value flowing through it and the on-resistance. Therefore, when a large current is passed through a small semiconductor switch, it is particularly important to reduce the ON resistance in order to suppress heat generation due to energization as much as possible.

【０００６】オン抵抗は電流が流れる経路の抵抗値の和
となるが、現在は半導体スイッチチップについては数十
ｍΩ程度まで低オン抵抗化が進み、その結果、数〜数十
ｍΩの配線抵抗が無視できなくなっている。したがっ
て、ワイヤーボンディング方式にて配線を行う場合に
は、ワイヤーの径を太くしたり、ワイヤーの本数を増や
したりしている。The on-resistance is the sum of the resistance values of the paths through which the current flows. Currently, the on-resistance of semiconductor switch chips has been reduced to about several tens of mΩ, resulting in a wiring resistance of several to several tens of mΩ. It cannot be ignored. Therefore, when wiring is performed by the wire bonding method, the diameter of the wire is increased or the number of wires is increased.

【０００７】しかしながら、ワイヤーの太径化は、ボン
ディング時に半導体スイッチチップの機械的損傷を招く
可能性があるために限界があるという問題があった。ま
た、ワイヤー本数を多くすると、組立て作業時間の増大
を招くことになるという問題があった。However, there is a problem that there is a limit to the increase in the diameter of the wire because it may cause mechanical damage to the semiconductor switch chip during bonding. Further, there is a problem that increasing the number of wires leads to an increase in assembly work time.

【０００８】また、半導体スイッチチップの発熱による
損傷を防ぐためには、半導体スイッチチップを実装した
配線基板の放熱性が良いことが望まれる。実装した配線
基板の放熱性を向上させるためには、発熱部である半導
体スイッチチップから外気の空気までの熱抵抗を小さく
すれば良いが、ボンディングワイヤーはその細さから熱
抵抗が大きく、放熱効果がほとんど得られないという問
題があった。そこで、ボンディングワイヤー以外で接続
された回路からの放熱に依存することになるが、これで
も充分な放熱を得られない場合には、ヒートシンクなど
の放熱手段が必要となり、コストアップの要因となる。In order to prevent damage to the semiconductor switch chip due to heat generation, it is desired that the wiring board on which the semiconductor switch chip is mounted has good heat dissipation. In order to improve the heat dissipation of the mounted wiring board, it is sufficient to reduce the heat resistance from the semiconductor switch chip, which is the heat generating part, to the air of the outside air, but the bonding wire has a large heat resistance due to its thinness There was a problem that was hardly obtained. Therefore, although it depends on the heat radiation from the circuit connected by means other than the bonding wire, if sufficient heat radiation is still not obtained, a heat radiation means such as a heat sink is required, which causes a cost increase.

【０００９】本発明は、半導体スイッチチップとしてト
ランジスタベアチップを用いて、発熱損失を低減させ、
また、放熱性を向上させたトランジスタベアチップ実装
配線基板およびその製造方法を提供することを目的とす
る。The present invention uses a transistor bare chip as a semiconductor switch chip to reduce heat loss,
Another object is to provide a transistor bare chip mounting wiring board having improved heat dissipation and a method for manufacturing the same.

【００１０】[0010]

【課題を解決するための手段】本発明は上記目的を達成
するためになされたもので、請求項１に記載の発明は、
複数のトランジスタベアチップが配線基板の端部に沿っ
て搭載され、前記複数のトランジスタベアチップのそれ
ぞれの二つの電流通路電極は直接にあるいは前記配線基
板の導電路を介して板状導電部材の一端部に接続され、
前記二つの電流通路電極の少なくとも一方の電極に接続
された前記板状導電部材の他端部は前記配線基板の外部
接続端子を構成していることを特徴とするトランジスタ
ベアチップ実装配線基板である。The present invention has been made to achieve the above object, and the invention described in claim 1 is
A plurality of transistor bare chips are mounted along the end of the wiring board, and the two current path electrodes of each of the plurality of transistor bare chips are directly or through the conductive paths of the wiring board to one end of the plate-shaped conductive member. Connected,
The transistor bare chip mounting wiring board is characterized in that the other end of the plate-shaped conductive member connected to at least one of the two current passage electrodes constitutes an external connection terminal of the wiring board.

【００１１】ここで、トランジスタベアチップの二つの
電流通路電極とは、バイポーラトランジスタにおいては
エミッタ電極とコレクタ電極を意味し、電界効果トラン
ジスタにおいてはソース電極とドレイン電極を意味す
る。Here, the two current path electrodes of the transistor bare chip mean an emitter electrode and a collector electrode in a bipolar transistor and a source electrode and a drain electrode in a field effect transistor.

【００１２】また、請求項２に記載の発明は、請求項１
に記載の発明において、前記複数のトランジスタベアチ
ップは対向する二面のそれぞれに電流通路電極を有し、
前記電流通路電極は前記トランジスタベアチップを挟む
ように設けられた一対の板状導電部材の一端部に接続さ
れていることを特徴とするトランジスタベアチップ実装
配線基板である。The invention described in claim 2 is the same as claim 1.
In the invention described in, the plurality of transistor bare chips each have a current passage electrode on each of two opposing surfaces,
The transistor bare chip mounting wiring board is characterized in that the current path electrode is connected to one end of a pair of plate-shaped conductive members provided so as to sandwich the transistor bare chip.

【００１３】また、請求項３に記載の発明は、トランジ
スタベアチップ実装配線基板の製造方法であって、複数
の板状導電部材が一体化した打ち抜き部材を配線基板の
導電路または前記配線基板に搭載された複数のトランジ
スタベアチップの電流通路電極に接続し、次いで前記打
ち抜き部材をプレスカットして個別の板状導電部材を形
成することを特徴とするものである。According to a third aspect of the invention, there is provided a method for manufacturing a transistor bare chip mounted wiring board, wherein a punching member having a plurality of plate-shaped conductive members integrated with each other is mounted on a conductive path of the wiring board or the wiring board. It is characterized in that individual plate-shaped conductive members are formed by connecting to the current path electrodes of a plurality of transistor bare chips that have been formed and then press cutting the punching member.

【００１４】さらに、請求項４に記載の発明は、トラン
ジスタベアチップ実装配線基板の製造方法であって、複
数の板状導電部材が一体化した第１の打ち抜き部材を配
線基板に接続し、次いで、前記第１の打ち抜き部材上に
複数のトランジスタベアチップを一方の電流通路電極が
接続するように搭載し、次いで、複数の板状導電部材が
一体化した第２の打ち抜き部材を前記複数のトランジス
タベアチップを挟むように他方の電流通路電極に接続
し、その後、前記第１および第２の打ち抜き部材をプレ
スカットして個別の板状導電部材を形成することを特徴
とするものである。Further, a fourth aspect of the present invention is a method for manufacturing a transistor bare chip mounting wiring board, wherein a first punching member in which a plurality of plate-shaped conductive members are integrated is connected to the wiring board, and then, A plurality of transistor bare chips are mounted on the first punching member so that one current path electrode is connected, and then a second punching member integrated with a plurality of plate-shaped conductive members is mounted on the plurality of transistor bare chips. It is characterized in that it is connected to the other current path electrode so as to sandwich it, and then the first and second punching members are press-cut to form individual plate-shaped conductive members.

【００１５】請求項１に記載の発明によれば、トランジ
スタベアチップの制御電極（ゲート電極あるいはベース
電極）に比して大きな電流が流れる二つの電流通路電極
が直接にあるいは前記配線基板の導電路を介して板状導
電部材の一端部に接続している。したがって、従来のよ
うに電流通路電極に接続する導電部材として細いボンデ
ィングワイヤーを用いた場合に比して、導電部材の断面
積が大きくなり、電気抵抗が低下して発熱損失が低減
し、また、導電部材の表面積も大きくなるため、放熱性
が向上する。さらに、二つの電流通路電極の少なくとも
一方の電極に接続された板状導電部材の他端部は、配線
基板の外部接続端子となっているため、この板状導電部
材を通して配線基板外に放熱することができる。According to the first aspect of the present invention, the two current passage electrodes through which a larger current flows than the control electrode (gate electrode or base electrode) of the transistor bare chip directly or through the conductive path of the wiring board. It is connected to one end of the plate-shaped conductive member through. Therefore, as compared with the case where a thin bonding wire is used as the conductive member connected to the current path electrode as in the prior art, the cross-sectional area of the conductive member is increased, the electric resistance is reduced and the heat generation loss is reduced, and Since the surface area of the conductive member is also increased, heat dissipation is improved. Furthermore, since the other end of the plate-shaped conductive member connected to at least one of the two current path electrodes serves as an external connection terminal of the wiring board, heat is radiated to the outside of the wiring board through this plate-shaped conductive member. be able to.

【００１６】また、請求項２に記載の発明によれば、ト
ランジスタベアチップの対向する二面に設けられた電流
通路電極は一対の板状導電部材の一端部に直接接続して
いるため、発熱損失が一層低減し、放熱性が一層向上す
る。Further, according to the second aspect of the present invention, since the current passage electrodes provided on the two opposing surfaces of the transistor bare chip are directly connected to one end of the pair of plate-shaped conductive members, heat loss is generated. Is further reduced, and heat dissipation is further improved.

【００１７】また、請求項３に記載の発明によれば、複
数の板状導電部材が一体化した打ち抜き部材を配線基板
の導電路または前記配線基板に搭載された複数のトラン
ジスタベアチップの電流通路電極に接続し、次いで前記
打ち抜き部材をプレスカットして個別の板状導電部材を
形成するため、多数の板状導電部材を効率よく接続する
ことができる。According to the third aspect of the present invention, the punching member in which a plurality of plate-shaped conductive members are integrated is a conductive path of a wiring board or a current path electrode of a plurality of transistor bare chips mounted on the wiring board. Since the individual punched members are press-cut to form individual plate-shaped conductive members, a large number of plate-shaped conductive members can be efficiently connected.

【００１８】さらに、請求項４に記載の発明によれば、
第１の打ち抜き部材を配線基板に接続し、次いで、前記
第１の打ち抜き部材上に複数のトランジスタベアチップ
を搭載し、次いで、第２の打ち抜き部材を前記複数のト
ランジスタベアチップを挟むように他方の電流通路電極
に接続し、その後、前記第１および第２の打ち抜き部材
を一括してプレスカットし、個別の板状導電部材を形成
するため、多数の板状導電部材をトランジスタベアチッ
プを挟むように効率よく接続することができる。Further, according to the invention of claim 4,
The first punching member is connected to the wiring board, then a plurality of transistor bare chips are mounted on the first punching member, and then the second punching member is provided with the other current so as to sandwich the plurality of transistor bare chips. Since the individual plate-shaped conductive members are formed by press-cutting the first and second punching members collectively by connecting to the passage electrodes, it is possible to efficiently sandwich the transistor bare chips with a large number of plate-shaped conductive members. Can connect well.

【００１９】[0019]

【発明の実施の形態】以下、図面に基づいて本発明の実
施の形態を詳細に説明する。図１は一実施形態の部分斜
視図である。図１において、図５に関して説明した部分
と同部分は同符号で指示している。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a partial perspective view of one embodiment. In FIG. 1, the same parts as those described with reference to FIG. 5 are designated by the same reference numerals.

【００２０】図１において、配線基板１は、表面に導電
路２ａ、２ｂ、２ｃにより導電回路が形成されたプリン
ト基板である。配線基板１の端部に沿って、複数のトラ
ンジスタベアチップ３が一列に導電路２ａ上に搭載され
ている。また、配線基板１の端部にそって、複数の板状
導電部材７が配線基板１の外側に延びるように並行に設
けられ、前記板状導電部材７の一端部は導電路２ａに接
続し、他端部は配線基板１の外部接続端子を構成してい
る。In FIG. 1, a wiring board 1 is a printed circuit board having a conductive circuit formed on its surface by conductive paths 2a, 2b, 2c. A plurality of transistor bare chips 3 are mounted in a line on the conductive path 2a along the end of the wiring board 1. A plurality of plate-shaped conductive members 7 are provided in parallel along the end of the wiring board 1 so as to extend to the outside of the wiring board 1, and one end of the plate-shaped conductive member 7 is connected to the conductive path 2a. The other end constitutes an external connection terminal of the wiring board 1.

【００２１】トランジスタベアチップ３はバイポーラト
ランジスタベアチップであって、その下面にはコレクタ
電極（図示されず）が形成されており、上面にはベース
電極４とエミッタ電極５が形成されている。このトラン
ジスタベアチップ３はコレクタ電極側を配線基板１に向
けて、導電路２ａ上にはんだ付けなどの金属接合により
ダイボンディングされ、電気的に接続されるとともに、
前記配線基板１に機械的に固着されている。トランジス
タベアチップ３のコレクタ電極は、導電路２ａを介して
板状導電部材７の一端部に電気的に接続している。ま
た、エミッタ電極５には板状導電部材８の一端部が接続
しており、板状導電部材８の他端部は導電路２ｃに接続
している。なお、ベース電極４は従来どおりボンディン
グワイヤー６で導電路２ｂに接続している。The transistor bare chip 3 is a bipolar transistor bare chip, and a collector electrode (not shown) is formed on the lower surface thereof, and a base electrode 4 and an emitter electrode 5 are formed on the upper surface thereof. The transistor bare chip 3 is die-bonded on the conductive path 2a by metal joining such as soldering so that the collector electrode side faces the wiring board 1 and is electrically connected.
It is mechanically fixed to the wiring board 1. The collector electrode of the transistor bare chip 3 is electrically connected to one end of the plate-shaped conductive member 7 via the conductive path 2a. Further, one end of the plate-shaped conductive member 8 is connected to the emitter electrode 5, and the other end of the plate-shaped conductive member 8 is connected to the conductive path 2c. The base electrode 4 is connected to the conductive path 2b by the bonding wire 6 as in the conventional case.

【００２２】本実施形態が従来例と異なる特徴的なこと
は、ベース電極４に比較して大電流が流れるコレクタ電
極とエミッタ電極５に板状導電部材７および８が接続し
ていることである。A characteristic of this embodiment different from the conventional example is that the plate-shaped conductive members 7 and 8 are connected to the collector electrode and the emitter electrode 5 through which a large current flows as compared with the base electrode 4. .

【００２３】上記トランジスタベアチップ実装配線基板
は、以下のような手順で製造される。 １）先ず、図２（ａ）に示すように、トランジスタベア
チップ３をコレクタ電極側を配線基板１に向けて導電路
２ａにはんだ付けなどの金属接合により電気的に接続す
るとともに、前記配線基板１に機械的に固着する。 ２）また、図２（ｂ）に示すように、複数の板状導電部
材７と板状導電部材８を交互に並行になるように配列し
て一体化した打ち抜き部材９（リードフレームと称され
る）を用意する。なお、板状導電部材８には、端部がト
ランジスタベアチップ３の厚さ分だけ高くなるように段
差部８ａが設けられている。 ３）次いで、図２（ｃ）に示すように、打ち抜き部材９
を配線基板１上に搭載する。この際、あらかじめ配線基
板１の導電路２ａの板状導電部材７が接続する部分上
と、トランジスタベアチップ３のエミッタ電極５上にデ
ィスペンサを用いて適量のクリームはんだを塗布してお
く。そうして、打ち抜き部材９を配線基板１上に搭載
し、板状導電部材７の端部が導電路２ａ上に、板状導電
部材８の端部がトランジスタベアチップ３上側のエミッ
タ電極５上に、板状導電部材８の他の部分が導電路２ｃ
上に位置するようにする。その後、打ち抜き部材９を搭
載した配線基板１をリフロー炉により加熱し、リフロー
はんだ付けして、板状導電部材７、８の電気的、機械的
接続を行う。 ４）次いで、打ち抜き部材９をプレスカットし、板状導
電部材７、８を分離して、図１に示す状態にする。 ５）最後に、ベース電極４と導電路２ｂをボンディング
ワイヤー６で接続する。The transistor bare chip mounting wiring board is manufactured by the following procedure. 1) First, as shown in FIG. 2 (a), the transistor bare chip 3 is electrically connected to the conductive path 2a with the collector electrode side facing the wiring board 1 by metal bonding such as soldering, and the wiring board 1 is also connected. Mechanically stick to. 2) Further, as shown in FIG. 2B, a punching member 9 (referred to as a lead frame) in which a plurality of plate-shaped conductive members 7 and plate-shaped conductive members 8 are alternately arranged in parallel and integrated with each other. Prepare). The plate-shaped conductive member 8 is provided with a stepped portion 8a so that its end portion is raised by the thickness of the transistor bare chip 3. 3) Next, as shown in FIG. 2C, the punching member 9
Are mounted on the wiring board 1. At this time, an appropriate amount of cream solder is applied in advance on the portion of the conductive path 2a of the wiring board 1 to which the plate-shaped conductive member 7 is connected and on the emitter electrode 5 of the transistor bare chip 3 using a dispenser. Then, the punching member 9 is mounted on the wiring substrate 1, the end of the plate-shaped conductive member 7 is on the conductive path 2a, and the end of the plate-shaped conductive member 8 is on the emitter electrode 5 above the transistor bare chip 3. , The other part of the plate-shaped conductive member 8 is the conductive path 2c.
To be on top. After that, the wiring board 1 on which the punching member 9 is mounted is heated by a reflow furnace and reflow soldering is performed to electrically and mechanically connect the plate-shaped conductive members 7 and 8. 4) Next, the punching member 9 is press-cut to separate the plate-shaped conductive members 7 and 8 into the state shown in FIG. 5) Finally, the base electrode 4 and the conductive path 2b are connected by the bonding wire 6.

【００２４】本実施形態では、打ち抜き部材９は複数の
板状導電部材７と板状導電部材８が一体化しているた
め、多数の板状導電部材７と板状導電部材８を効率よく
配線基板１上に接続することができる。また、トランジ
スタベアチップ３は配線基板１の端部に沿って一列に配
置されているため、打ち抜き部材９の形状は複数の板状
導電部材７と板状導電部材８が交互に並行に配列する簡
単なパターンになり、打ち抜きに用いる金型構造も簡単
になる。さらに、トランジスタベアチップ３のエミッタ
電極５には板状導電部材８が接続しているため、従来の
ようにボンディングワイヤーが接続している場合に比し
て、接続導体の断面積が大きくなり、低抵抗化して発熱
損失が低減し、放熱性が向上する。In the present embodiment, since the punching member 9 is formed by integrating a plurality of plate-shaped conductive members 7 and plate-shaped conductive members 8, a large number of plate-shaped conductive members 7 and plate-shaped conductive members 8 can be efficiently connected to the wiring board. Can be connected on one. Further, since the transistor bare chips 3 are arranged in a line along the end portion of the wiring board 1, the punching member 9 has a simple shape in which a plurality of plate-shaped conductive members 7 and plate-shaped conductive members 8 are alternately arranged in parallel. The pattern becomes simple and the die structure used for punching becomes simple. Further, since the plate-shaped conductive member 8 is connected to the emitter electrode 5 of the transistor bare chip 3, the cross-sectional area of the connection conductor is large and low compared to the case where a bonding wire is connected as in the conventional case. Resistance is reduced to reduce heat loss and heat dissipation is improved.

【００２５】次に、他の実施形態について説明する。図
３は他の実施形態の部分斜視図である。本実施形態で
は、トランジスタベアチップ３は板状導電部材７上に直
接載置され、板状導電部材７を介して配線基板１に搭載
されている。その他の構造は前記実施例と同様である。Next, another embodiment will be described. FIG. 3 is a partial perspective view of another embodiment. In this embodiment, the transistor bare chip 3 is directly mounted on the plate-shaped conductive member 7 and mounted on the wiring board 1 via the plate-shaped conductive member 7. The other structure is the same as that of the above-mentioned embodiment.

【００２６】上記トランジスタベアチップ実装配線基板
は、以下のような手順で製造される。 １）先ず、図４（ａ）に示すように、複数の板状導電部
材７を並行になるように配列して一体化した打ち抜き部
材１０を配線基板１上に搭載し、電気的に接続する。な
お、打ち抜き部材１０と配線基板１の電気的接続箇所に
は、あらかじめ印刷あるいはディスペンサでクリームは
んだを塗布しておく。 ２）次いで、図４（ｂ）に示すように、板状導電部材７
の端部上にトランジスタベアチップ３を搭載する。な
お、板状導電部材７のトランジスタベアチップ３の搭載
箇所にあらかじめ印刷あるいはディスペンサでクリーム
はんだを塗布しておく。 ３）次いで、図４（ｃ）に示すように、複数の板状導電
部材８を並行になるように配列して一体化した打ち抜き
部材１１を配線基板１とトランジスタベアチップ３上に
搭載する。なお、打ち抜き部材１１と配線基板１の電気
的接続箇所と、トランジスタベアチップ３のエミッタ電
極５上には、あらかじめ印刷あるいはディスペンサでク
リームはんだを塗布しておく。The transistor bare chip mounting wiring board is manufactured by the following procedure. 1) First, as shown in FIG. 4A, a punching member 10 in which a plurality of plate-shaped conductive members 7 are arranged in parallel and integrated with each other is mounted on the wiring board 1 and electrically connected. . It should be noted that cream solder is applied in advance to the electrical connection between the punching member 10 and the wiring board 1 by printing or dispenser. 2) Next, as shown in FIG. 4B, the plate-shaped conductive member 7
The transistor bare chip 3 is mounted on the end of the. It should be noted that cream solder is applied in advance to the place where the transistor bare chip 3 is mounted on the plate-shaped conductive member 7 by printing or using a dispenser. 3) Next, as shown in FIG. 4C, a punching member 11 in which a plurality of plate-shaped conductive members 8 are arranged in parallel and integrated is mounted on the wiring substrate 1 and the transistor bare chip 3. It should be noted that cream solder is applied in advance to the electrical connection between the punching member 11 and the wiring board 1 and the emitter electrode 5 of the transistor bare chip 3 by printing or dispenser.

【００２７】打ち抜き部材１１には、板状導電部材８の
トランジスタベアチップ３のエミッタ電極５と接続する
端部がトランジスタベアチップ３と打ち抜き部材１１の
合わせた厚さ分だけ高くなるように段差部８ａが設けら
れている。また、打ち抜き部材１１には、板状導電部材
８、８を連結する連鎖部１１ａの板状導電部材８、８間
が打ち抜き部材１０（板状導電部材７）の厚さ分だけ高
くなるように段差部１１ｂが設けられている。そうし
て、打ち抜き部材１１は、板状導電部材８の端部がトラ
ンジスタベアチップ３上側のエミッタ電極５上に位置
し、連鎖部１１ａの段差１１ｂが板状導電部材７を跨ぐ
ように、配線基板１に搭載される。The punching member 11 has a stepped portion 8a so that the end of the plate-shaped conductive member 8 connected to the emitter electrode 5 of the transistor bare chip 3 is raised by the combined thickness of the transistor bare chip 3 and the punching member 11. It is provided. Further, in the punching member 11, the space between the plate-shaped conductive members 8 and 8 of the chain portion 11a connecting the plate-shaped conductive members 8 and 8 is increased by the thickness of the punching member 10 (the plate-shaped conductive member 7). A step portion 11b is provided. Then, the punching member 11 is arranged such that the end of the plate-shaped conductive member 8 is located on the emitter electrode 5 above the transistor bare chip 3 and the step 11b of the chain portion 11a straddles the plate-shaped conductive member 7. It is installed in 1.

【００２８】４）次いで、打ち抜き部材１０、１１を搭
載した配線基板１をリフロー炉により加熱し、リフロー
はんだ付けし、打ち抜き部材１０、１１とトランジスタ
ベアチップ３および配線基板１を電気的、機械的に接続
する。 ５）次いで、打ち抜き部材１０、１１を一括してプレス
カットし、板状導電部材７、８を分離して、図３に示す
状態にする。 ６）最後に、ベース電極４と導電路２ｂをボンディング
ワイヤー６で接続する。4) Next, the wiring board 1 on which the punching members 10 and 11 are mounted is heated in a reflow furnace and reflow soldered to electrically and mechanically connect the punching members 10 and 11, the transistor bare chip 3 and the wiring board 1. Connecting. 5) Next, the punching members 10 and 11 are collectively press-cut to separate the plate-shaped conductive members 7 and 8 into the state shown in FIG. 6) Finally, the base electrode 4 and the conductive path 2b are connected by the bonding wire 6.

【００２９】本実施形態では、トランジスタベアチップ
３が板状導電部材７の上に載置され、コレクタ電極が板
状導電部材７に直接接続しているため、（コレクタ電極
が導電路２ａを介して板状導電部材７に接続している）
前記実施形態よりも一層低抵抗化し、放熱性も一層向上
する。In the present embodiment, since the transistor bare chip 3 is placed on the plate-shaped conductive member 7 and the collector electrode is directly connected to the plate-shaped conductive member 7, (the collector electrode is connected via the conductive path 2a). (Connected to the plate-shaped conductive member 7)
The resistance is further reduced and the heat dissipation is further improved as compared with the above embodiment.

【００３０】以上、本発明の実施形態について説明をし
たが、本発明は上記実施形態に限られることはなく、た
とえば上記実施形態はバイポーラトランジスタのエミッ
タ電極とコレクタ電極について述べたが、電界効果トラ
ンジスタのソース電極とドレイン電極にしてもよい。ま
た、ベース電極（電界効果トランジスタではゲート電
極）をボンディングワイヤーの代わりに板状導電部材に
接続してよい。さらに、トランジスタベアチップや打ち
抜き部材（リードフレーム）の配線基板への接合方法
も、リフローはんだ付けに限定されることはない。Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. For example, the above embodiments have described the emitter electrode and the collector electrode of the bipolar transistor. Alternatively, the source electrode and the drain electrode may be used. Further, the base electrode (gate electrode in the field effect transistor) may be connected to the plate-shaped conductive member instead of the bonding wire. Furthermore, the method of joining the transistor bare chip and the punching member (lead frame) to the wiring board is not limited to reflow soldering.

【００３１】[0031]

【発明の効果】以上説明したように、本発明によれば次
のような優れた効果が得られる。即ち、コレクタ（ドレ
イン）電極だけでなくエミッタ（ソース）電極も板状導
電部材に接続することで、従来のワイヤーボンディング
に接続した場合に比べて、大きな負荷電流の流れる経路
（コレクタ、エミッタ間）の線路抵抗を小さくすること
ができるので、発熱損失を低減することが可能となる。
また、負荷電流の流れる経路の断面積および表面積を板
状導電部材の部分で大きくすることができるので、放熱
性を向上させることができる。また、本発明の配線基板
の製造方法によれば、複数のトランジスタチップについ
て、エミッタ（ソース）電極とコレクタ（ドレイン）電
極を同時に一括して導電部材に接続することができるた
め、加工工数低減によりコストダウンを図ることができ
るとともに、生産性を向上させることができる。As described above, according to the present invention, the following excellent effects can be obtained. That is, by connecting not only the collector (drain) electrode but also the emitter (source) electrode to the plate-shaped conductive member, a path (between the collector and the emitter) through which a large load current flows as compared with the case where the conventional wire bonding is connected. Since the line resistance can be reduced, it is possible to reduce the heat generation loss.
Moreover, since the cross-sectional area and the surface area of the path through which the load current flows can be increased in the portion of the plate-shaped conductive member, heat dissipation can be improved. Further, according to the method of manufacturing a wiring board of the present invention, the emitter (source) electrode and the collector (drain) electrode can be simultaneously connected to the conductive member for a plurality of transistor chips at the same time. The cost can be reduced and the productivity can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明に係るトランジスタベアチップ実装配線
基板の一実施形態の部分斜視図である。FIG. 1 is a partial perspective view of an embodiment of a transistor bare chip mounting wiring board according to the present invention.

【図２】本発明に係るトランジスタベアチップ実装配線
基板の製造方法の一実施形態を説明する説明図である。FIG. 2 is an explanatory diagram illustrating an embodiment of a method for manufacturing a transistor bare chip mounting wiring board according to the present invention.

【図３】本発明に係るトランジスタベアチップ実装配線
基板の他の実施形態の部分斜視図である。FIG. 3 is a partial perspective view of another embodiment of a transistor bare chip mounting wiring board according to the present invention.

【図４】本発明に係るトランジスタベアチップ実装配線
基板の製造方法の他の実施形態を説明する説明図であ
る。FIG. 4 is an explanatory view illustrating another embodiment of the method for manufacturing a transistor bare chip mounting wiring board according to the present invention.

【図５】従来のトランジスタベアチップ実装配線基板の
一例の部分斜視図である。FIG. 5 is a partial perspective view of an example of a conventional transistor bare chip mounting wiring board.

【符号の説明】[Explanation of symbols]

１ 配線基板 ２ａ、２ｂ、２ｃ 導電路 ３ トランジスタベアチップ ４ ベース電極 ５ エミッタ電極 ６ ボンディングワイヤー ７、８ 板状導電部材 ８ａ、１１ｂ 段差部 ９、１０、１１ 打ち抜き部材 １１ａ 連鎖部 1 wiring board 2a, 2b, 2c Conductive path 3 transistor bare chip 4 Base electrode 5 Emitter electrode 6 Bonding wire 7, 8 Plate-shaped conductive member 8a, 11b Step portion 9, 10, 11 punching member 11a Chain part

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 複数のトランジスタベアチップが配線基
板の端部に沿って搭載され、前記複数のトランジスタベ
アチップのそれぞれの二つの電流通路電極は直接にある
いは前記配線基板の導電路を介して板状導電部材の一端
部に接続され、前記二つの電流通路電極の少なくとも一
方の電極に接続された前記板状導電部材の他端部は前記
配線基板の外部接続端子を構成していることを特徴とす
るトランジスタベアチップ実装配線基板。1. A plurality of transistor bare chips are mounted along an end of a wiring board, and two current path electrodes of each of the plurality of transistor bare chips are directly or via a conductive path of the wiring board. The other end of the plate-shaped conductive member connected to one end of the member and connected to at least one electrode of the two current passage electrodes constitutes an external connection terminal of the wiring board. Transistor bare chip mounting wiring board. 【請求項２】 前記複数のトランジスタベアチップは対
向する二面のそれぞれに電流通路電極を有し、前記電流
通路電極は前記トランジスタベアチップを挟むように設
けられた一対の板状導電部材の一端部に接続されている
ことを特徴とする請求項１に記載のトランジスタベアチ
ップ実装配線基板。2. The plurality of transistor bare chips each have a current passage electrode on each of two opposing surfaces, and the current passage electrodes are provided at one end of a pair of plate-like conductive members provided so as to sandwich the transistor bare chip. The transistor bare chip mounting wiring board according to claim 1, which is connected. 【請求項３】 複数の板状導電部材が一体化した打ち抜
き部材を配線基板の導電路または前記配線基板に搭載さ
れた複数のトランジスタベアチップの電流通路電極に接
続し、次いで前記打ち抜き部材をプレスカットして個別
の板状導電部材を形成することを特徴とするトランジス
タベアチップ実装配線基板の製造方法。3. A punching member in which a plurality of plate-shaped conductive members are integrated is connected to a conductive path of a wiring board or a current path electrode of a plurality of transistor bare chips mounted on the wiring board, and then the punching member is press-cut. A method of manufacturing a transistor bare chip mounting wiring board, characterized in that a separate plate-shaped conductive member is formed. 【請求項４】 複数の板状導電部材が一体化した第１の
打ち抜き部材を配線基板に接続し、次いで、前記第１の
打ち抜き部材上に複数のトランジスタベアチップを一方
の電流通路電極が接続するように搭載し、次いで、複数
の板状導電部材が一体化した第２の打ち抜き部材を前記
複数のトランジスタベアチップを挟むように他方の電流
通路電極に接続し、その後、前記第１および第２の打ち
抜き部材をプレスカットして個別の板状導電部材を形成
することを特徴とするトランジスタベアチップ実装配線
基板の製造方法。4. A first punching member in which a plurality of plate-shaped conductive members are integrated is connected to a wiring substrate, and then a plurality of transistor bare chips are connected to one current path electrode on the first punching member. Then, a second punching member in which a plurality of plate-shaped conductive members are integrated is connected to the other current path electrode so as to sandwich the plurality of transistor bare chips, and then the first and second A method for manufacturing a transistor bare chip mounted wiring board, characterized in that a punched member is press-cut to form individual plate-shaped conductive members.
JP2002123274A 2002-04-25 2002-04-25 Transistor bare chip mounting wiring substrate and its manufacturing method Pending JP2003318315A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002123274A JP2003318315A (en) 2002-04-25 2002-04-25 Transistor bare chip mounting wiring substrate and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002123274A JP2003318315A (en) 2002-04-25 2002-04-25 Transistor bare chip mounting wiring substrate and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2003318315A true JP2003318315A (en) 2003-11-07

Family

ID=29538612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002123274A Pending JP2003318315A (en) 2002-04-25 2002-04-25 Transistor bare chip mounting wiring substrate and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2003318315A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008124176A (en) * 2006-11-10 2008-05-29 Mitsubishi Electric Corp Power semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008124176A (en) * 2006-11-10 2008-05-29 Mitsubishi Electric Corp Power semiconductor device

Similar Documents

Publication Publication Date Title
JP4634497B2 (en) Power semiconductor module
US9391006B2 (en) Semiconductor device and method of manufacturing semiconductor device
US9035453B2 (en) Semiconductor device
US7443014B2 (en) Electronic module and method of assembling the same
KR101388328B1 (en) Lead frame based, over-molded semiconductor package with integrated through hole technology(tht) heat spreader pin(s) and associated method of manufacturing
US9468087B1 (en) Power module with improved cooling and method for making
JP4651153B2 (en) Semiconductor device
JP2009534869A (en) Semiconductor die package including multiple die and common node structure
JP3390661B2 (en) Power module
JP2003197862A (en) Power module and its assembling method
JP2010034350A (en) Semiconductor device
JP7055151B2 (en) Semiconductor module
JP2001036001A (en) Power semiconductor module
JP2005174955A (en) Semiconductor module
JP2005051109A (en) Power semiconductor module
JP4797492B2 (en) Semiconductor device
JPH08274228A (en) Semiconductor mounting board, power semiconductor device and electronic circuit device
JP2018116960A (en) Power semiconductor device
JP5682511B2 (en) Semiconductor module
JP2012238737A (en) Semiconductor module and manufacturing method therefor
JP2003318315A (en) Transistor bare chip mounting wiring substrate and its manufacturing method
CN115579346B (en) Connection structure, packaging structure and manufacturing process of power module
JP2002026246A (en) Semiconductor device
JP4810898B2 (en) Semiconductor device
JP2004048084A (en) Semiconductor power module