JP2003318116A - Susceptor and semiconductor wafer manufacturing method - Google Patents
Susceptor and semiconductor wafer manufacturing methodInfo
- Publication number
- JP2003318116A JP2003318116A JP2002124056A JP2002124056A JP2003318116A JP 2003318116 A JP2003318116 A JP 2003318116A JP 2002124056 A JP2002124056 A JP 2002124056A JP 2002124056 A JP2002124056 A JP 2002124056A JP 2003318116 A JP2003318116 A JP 2003318116A
- Authority
- JP
- Japan
- Prior art keywords
- susceptor
- substrate
- semiconductor substrate
- main
- recessed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Chemical Vapour Deposition (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、サセプタおよび半
導体ウェーハの製造方法に関する。TECHNICAL FIELD The present invention relates to a method for manufacturing a susceptor and a semiconductor wafer.
【０００２】[0002]
【従来の技術】従来から、サセプタにより支持させた半
導体基板（以下、基板と略称することがある。）を加熱
装置により成長温度に加熱するとともに、基板の主表面
上にガス供給装置により原料ガスを供給することによっ
て、該基板の主表面上に薄膜を気相成長して半導体ウェ
ーハを製造する方法が知られている。2. Description of the Related Art Conventionally, a semiconductor substrate supported by a susceptor (hereinafter, may be abbreviated as a substrate) is heated to a growth temperature by a heating device, and a source gas is supplied on a main surface of the substrate by a gas supply device. Is known to produce a semiconductor wafer by vapor-depositing a thin film on the main surface of the substrate.
【０００３】このような製造方法に用いられる気相成長
装置には、いわゆる枚葉式の気相成長装置あるいはバレ
ル型（シリンダー型）気相成長装置等のように、基板を
主表面側と主裏面側との双方から加熱しつつ気相成長を
行うタイプ（以下、タイプ１）のもの（主裏面側からの
加熱はサセプタを介して行う）と、いわゆるパンケーキ
型の気相成長装置等のように、サセプタを介して基板を
主裏面側からのみ加熱しつつ気相成長を行うタイプ（以
下、タイプ２）のものとがある。The vapor phase growth apparatus used in such a manufacturing method is a so-called single-wafer type vapor phase growth apparatus or a barrel type (cylinder type) vapor phase growth apparatus. A type (hereinafter referred to as a type 1) of performing vapor phase growth while heating from both the back side (main heating from the back side is performed via a susceptor), a so-called pancake type vapor phase growth apparatus, etc. As described above, there is a type (hereinafter, type 2) of performing vapor phase growth while heating the substrate only from the main back surface side through the susceptor.
【０００４】このうち、タイプ２の場合、図６に示すよ
うに、基板Ｗを支持するサセプタ１０１の下側に加熱装
置（例えば、高周波誘導加熱コイル）１０２が配され、
該加熱装置１０２により、サセプタ１０１を介して基板
Ｗを主裏面側から加熱する。このため、気相成長の際に
は、基板Ｗの下部が上部に比べて大きく熱膨張するの
で、図６に示すように、基板Ｗが中心部ほど下側に凸と
なるように反り返る。従って、このように反り返った状
態時にも基板Ｗにサセプタ１０１を好適にフィットさせ
て、サセプタ１０１から基板Ｗへの熱伝導量を面内で均
一にするために、図６に示すように、サセプタ１０１の
座ぐり１０３は、周縁部から中心に向かうほど大きく凹
む凹曲面形状に窪まされている。Among them, in the case of type 2, as shown in FIG. 6, a heating device (for example, high frequency induction heating coil) 102 is arranged below the susceptor 101 supporting the substrate W,
The substrate W is heated from the main back surface side via the susceptor 101 by the heating device 102. Therefore, during vapor phase growth, the lower portion of the substrate W thermally expands more than the upper portion, and as shown in FIG. 6, the substrate W warps back so that the central portion is convex downward. Therefore, even in such a warped state, the susceptor 101 is appropriately fitted to the substrate W so that the amount of heat conduction from the susceptor 101 to the substrate W is uniform in the plane, as shown in FIG. The counterbore 103 of 101 is recessed into a concave curved surface shape that is largely recessed from the peripheral portion toward the center.
【０００５】他方、タイプ１の場合、例えば図５に示す
ように、サセプタ１１１に対し主表面側と主裏面側との
双方に加熱装置１１２（例えばハロゲンランプ）を配
し、これら加熱装置１１２により、基板Ｗを主表面側と
主裏面側との双方から加熱する。このため、基板Ｗは、
表裏方向において殆ど熱分布を生じないので、気相成長
の際にも殆どフラットに維持される。従って、タイプ１
の場合のサセプタ１１１の座ぐり１１３は、図５に示す
ように平面に形成されている。On the other hand, in the case of type 1, for example, as shown in FIG. 5, heating devices 112 (for example, halogen lamps) are arranged on both the main front surface side and the main back surface side of the susceptor 111, and these heating devices 112 are used. The substrate W is heated from both the main front surface side and the main back surface side. Therefore, the substrate W is
Since almost no heat distribution is generated in the front-back direction, it is maintained almost flat during vapor phase growth. Therefore, type 1
In the case of, the spot facing 113 of the susceptor 111 is formed in a plane as shown in FIG.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、上記タ
イプ１の場合、基板Ｗの主裏面が、平面である座ぐり１
１３の底面に接触状態となるため、該主裏面に座ぐり１
１３の底面との接触跡が形成されて、基板Ｗの外観に影
響を及ぼすことがある。このことは、特に、基板Ｗの主
裏面にも鏡面研磨処理が施されている場合（両面ミラー
の基板を用いる場合）に問題となる。However, in the case of the above type 1, the counterbore 1 in which the main back surface of the substrate W is a flat surface.
Since it comes into contact with the bottom surface of 13, the counterbore 1
Traces of contact with the bottom surface of 13 may be formed, which may affect the appearance of the substrate W. This becomes a problem particularly when the main back surface of the substrate W is also mirror-polished (when a double-sided mirror substrate is used).
【０００７】この発明は、上記のような問題点を解決す
るためになされたもので、半導体基板を主表面側からと
主裏面側からとの双方から加熱して気相成長を行う場合
に、基板の主裏面に接触跡が形成されてしまうことを防
止可能なサセプタおよび半導体ウェーハの製造方法を提
供することを目的とする。The present invention has been made in order to solve the above problems, and when vapor-phase growth is performed by heating a semiconductor substrate from both the main surface side and the main back surface side, An object of the present invention is to provide a susceptor capable of preventing a contact mark from being formed on the main back surface of a substrate and a method for manufacturing a semiconductor wafer.
【０００８】[0008]
【課題を解決するための手段】上記課題を解決するた
め、本発明のサセプタは、半導体基板を主表面側からと
主裏面側からとの双方から加熱して行う気相成長の際に
該半導体基板を支持するサセプタにおいて、当該サセプ
タに対し半導体基板を位置決めさせるための座ぐりを有
し、該座ぐりの底面が、前記加熱の際における半導体基
板の撓み形状よりも窪まされていることを特徴としてい
る。In order to solve the above problems, the susceptor of the present invention uses a semiconductor substrate for vapor phase growth by heating the semiconductor substrate from both the main surface side and the main back surface side. In the susceptor supporting the substrate, it has a counterbore for positioning the semiconductor substrate with respect to the susceptor, the bottom face of the counterbore is recessed from the bent shape of the semiconductor substrate during the heating. There is.
【０００９】より具体的には、座ぐりの底面は、例え
ば、周縁部から中心に向かうほど次第に窪まされている
ことが好ましい一例である。More specifically, one example is preferable in which the bottom face of the counterbore is gradually recessed from the peripheral portion toward the center.
【００１０】或いは、座ぐりの底面の一部は、周縁部か
ら中心に向かうほど次第に窪む傾斜面状部となっている
とともに、該底面のうちで該傾斜面状部よりも中央寄り
の部位は、該傾斜面状部の最深部以上の深さに設定され
ていることも好ましい一例である。Alternatively, a part of the bottom surface of the counterbore is an inclined surface portion which is gradually recessed from the peripheral portion toward the center, and a portion of the bottom surface closer to the center than the inclined surface portion is formed. It is also a preferable example that the depth is set to be equal to or more than the deepest portion of the inclined surface portion.
【００１１】或いは、座ぐりは、半導体基板を支持する
外周側部分と、該外周側部分の内側に該外周側部分より
も窪んだ状態に形成された内周側部分とを有する二段構
成をなすことも好ましい一例である。また、この場合
に、内周側部分の底面と半導体基板との最大距離が、半
導体基板を加熱しないで支持した状態で０．４ｍｍ以下
となるように、該内周側部分の底面が窪まされているこ
とが好ましい。Alternatively, the counterbore has a two-stage structure having an outer peripheral side portion for supporting the semiconductor substrate and an inner peripheral side portion formed inside the outer peripheral side portion so as to be recessed from the outer peripheral side portion. That is also a preferable example. In this case, the bottom surface of the inner peripheral side portion is recessed so that the maximum distance between the bottom surface of the inner peripheral side portion and the semiconductor substrate is 0.4 mm or less when the semiconductor substrate is supported without being heated. Preferably.
【００１２】本発明のサセプタによれば、座ぐりの底面
が、気相成長の加熱の際における基板の撓み形状よりも
窪まされているので、基板を主表面側からと主裏面側か
らとの双方から加熱して気相成長を行う場合に、基板
が、加熱によりその中心部が座ぐりに近づく方向に僅か
に撓んだとしても、基板の主裏面と座ぐり底面とを非接
触状態に維持することができる。よって、基板の主裏面
に、座ぐり底面との接触跡が形成されてしまうことを好
適に防止できる。しかし、座ぐりと基板との間隔があま
りにも大きいと、該間隔に気相成長の際に用いる水素が
大量に侵入してしまう結果、該水素により基板の主裏面
がエッチングされてしまい、該主裏面に形成されている
微少なキズが目立つようになってしまうことがある。従
って、座ぐりが有する窪みは大きければ良い（座ぐりが
単に深ければ良い）というものではない。このような事
情に対し、座ぐりの底面が周縁部から中心に向かうほど
次第に窪まされているサセプタ、或いは、傾斜面状部を
有するサセプタとすれば、基板との接触を防止しつつ
も、周縁部における基板と座ぐりとの間隔を狭くするこ
とができる。よって、該間隔への水素の侵入を抑制でき
る結果、該水素による基板主裏面のエッチングも抑制で
きるので、該主裏面に微少なキズが形成されていても、
このキズが目立つようになってしまうことを防止でき
る。According to the susceptor of the present invention, since the bottom surface of the spot facing is recessed more than the bent shape of the substrate during heating in vapor phase growth, the substrate is viewed from both the main surface side and the main back surface side. When performing vapor phase growth by heating from above, the main back surface of the substrate and the bottom surface of the spot facing are kept in non-contact with each other even if the substrate is slightly bent in the direction of approaching the spot facing due to heating. can do. Therefore, it is possible to preferably prevent the formation of a contact mark with the counterbore bottom surface on the main back surface of the substrate. However, if the gap between the spot facing and the substrate is too large, a large amount of hydrogen used for vapor phase infiltration enters the gap, and as a result, the main back surface of the substrate is etched by the hydrogen, and the main back surface is etched. The small scratches formed on the surface may become noticeable. Therefore, it is not necessary that the recess of the counterbore be large (if the counterbore is simply deep). Against such a situation, a susceptor in which the bottom face of the counterbore is gradually recessed from the peripheral portion toward the center or a susceptor having an inclined surface portion prevents the peripheral portion from contacting with the substrate. The distance between the substrate and the spot facing can be narrowed. Therefore, as a result of suppressing the invasion of hydrogen into the space, it is possible to suppress the etching of the main back surface of the substrate due to the hydrogen, so that even if a minute flaw is formed on the main back surface,
It is possible to prevent the scratches from becoming conspicuous.
【００１３】また、特に、二段構成をなす座ぐりにおい
て、内周側部分の底面と半導体基板との最大距離が、半
導体基板を加熱しないで支持した状態で０．４ｍｍ以下
となるように、該内周側部分の底面が窪まされている場
合、基板と座ぐりとの間隔を全面において狭くすること
ができる。よって、該間隔への水素の侵入をより一層抑
制できる。従って、基板の主裏面に形成されている微少
なキズが目立つようになってしまうことをより好適に防
止できる。Further, in particular, in a spot facing having a two-stage structure, the maximum distance between the bottom surface of the inner peripheral side portion and the semiconductor substrate is 0.4 mm or less when the semiconductor substrate is supported without being heated. When the bottom surface of the inner peripheral side portion is recessed, the distance between the substrate and the spot facing can be narrowed over the entire surface. Therefore, the penetration of hydrogen into the space can be further suppressed. Therefore, it is possible to more preferably prevent the minute scratches formed on the main back surface of the substrate from becoming conspicuous.
【００１４】ところで、サセプタは、例えば、グラファ
イトからなる本体部の表面にＳｉＣ（炭化珪素）をコー
ティングすることにより構成されている。そして、本体
部にＳｉＣをコーティングする際には、本体部を高温に
加熱する。本体部は、この加熱により大きく反り返る
が、この反り返り量の予測は困難であるため該反り返り
量を加熱量により制御することは極めて困難である。勿
論、反り返り量は、本体部が大寸法であるほど大きいた
め、直径の大きなサセプタであるほど平坦に形成するこ
とが困難であるという問題もある。このような事情に対
し、本発明のサセプタによれば、座ぐり底面（の少なく
とも一部）を、周縁部から中心に向かうほど基板から遠
ざかる曲面状に窪んだ状態に形成すればよいため、座ぐ
りを平坦に形成する必要がある場合よりもサセプタの製
造が容易となり、例えば直径３００ｍｍの半導体ウェー
ハを支持するサセプタのように、比較的大寸法のサセプ
タであっても好適に製造することが可能となる。By the way, the susceptor is formed by coating the surface of the main body made of graphite with SiC (silicon carbide), for example. Then, when the body portion is coated with SiC, the body portion is heated to a high temperature. The main body part is largely warped by this heating, but since it is difficult to predict the amount of warping, it is extremely difficult to control the amount of warping by the amount of heating. Of course, since the amount of warpage increases as the size of the main body increases, there is a problem that it is difficult to form the susceptor with a larger diameter so as to be flat. In view of such a situation, according to the susceptor of the present invention, it is sufficient that the bottom surface (at least a part of) of the spot facing is formed in a curved shape that is more distant from the substrate toward the center from the peripheral portion. The susceptor is easier to manufacture than the case where it is necessary to form the flat face, and it is possible to favorably manufacture even a relatively large susceptor such as a susceptor supporting a semiconductor wafer having a diameter of 300 mm. Becomes
【００１５】また、本発明のサセプタは、半導体基板を
支持する主表面に対し裏面が、該裏面の中心部ほど窪む
ように、反り返った全体姿勢をなす盤状に形成されてい
ることこと、換言すれば、半導体基板を支持する主表面
の中心部ほど突出するように反り返った全体姿勢をなす
盤状に形成されている場合にも適用することができる。
この場合、サセプタが、反り返った全体姿勢に形成され
ていても良いので、つまり、全体姿勢が平板状となるよ
うに形成する必要がないので、平板状に形成する必要が
ある場合よりもサセプタの製造が容易となり、例えば直
径３００ｍｍの半導体ウェーハを支持するサセプタのよ
うに、比較的大寸法のサセプタであっても好適に製造す
ることが可能となる。In addition, the susceptor of the present invention is formed in a plate shape in which the back surface with respect to the main surface supporting the semiconductor substrate is in a warped overall posture such that the back surface is recessed toward the central portion of the back surface. For example, the present invention can also be applied to the case where the main surface supporting the semiconductor substrate is formed in a disk shape in which the central position of the main surface is curved so as to project.
In this case, the susceptor may be formed in a warped overall posture, that is, it is not necessary to form the overall posture to be a flat plate shape. Manufacturing is facilitated, and even a susceptor having a relatively large size such as a susceptor supporting a semiconductor wafer having a diameter of 300 mm can be favorably manufactured.
【００１６】また、本発明の半導体ウェーハの製造方法
は、両面が鏡面研磨処理された半導体基板の主表面上に
薄膜を気相成長させて半導体ウェーハを製造する半導体
ウェーハの製造方法において、本発明のサセプタにより
支持させた半導体基板を、主表面側と該サセプタを介し
て主裏面側との双方から加熱しながら、該半導体基板の
主表面上に薄膜を気相成長させることを特徴としてい
る。The semiconductor wafer manufacturing method of the present invention is a semiconductor wafer manufacturing method of vapor-depositing a thin film on a main surface of a semiconductor substrate whose both surfaces are mirror-polished to manufacture a semiconductor wafer. While heating the semiconductor substrate supported by the susceptor from both the main surface side and the main back surface side via the susceptor, a thin film is vapor-phase grown on the main surface of the semiconductor substrate.
【００１７】また、本発明の半導体ウェーハの製造方法
は、半導体基板を位置決めさせるための座ぐりを有し、
気相成長の加熱の際における半導体基板の撓み形状より
も前記座ぐりの底面が窪まされたサセプタにより、両面
が鏡面研磨処理された半導体基板を支持し、該半導体基
板を、主表面側と該サセプタを介して主裏面側との双方
から加熱しながら、該半導体基板の主表面上に薄膜を気
相成長させて半導体ウェーハを製造することを特徴とし
ている。The semiconductor wafer manufacturing method of the present invention has a spot facing for positioning the semiconductor substrate,
A semiconductor substrate whose both surfaces are mirror-polished is supported by a susceptor in which the bottom surface of the counterbore is recessed rather than the bending shape of the semiconductor substrate during heating in vapor deposition, and the semiconductor substrate is supported on the main surface side and the susceptor. A semiconductor wafer is manufactured by vapor-depositing a thin film on the main surface of the semiconductor substrate while heating from both of the main back surface side through.
【００１８】本発明の半導体ウェーハの製造方法によれ
ば、本発明のサセプタにより基板を支持して、或いは、
気相成長の加熱の際における半導体基板の撓み形状より
も座ぐりの底面が窪まされたサセプタにより基板を支持
して、気相成長を行うので、基板を主表面側からと主裏
面側からとの双方から加熱する場合にも、基板の主裏面
に接触跡を形成することなく、両面が鏡面研磨処理され
た基板の主表面上に薄膜を気相成長させて半導体ウェー
ハを製造することができる。According to the method of manufacturing a semiconductor wafer of the present invention, the substrate is supported by the susceptor of the present invention, or
Since the substrate is supported by the susceptor in which the bottom surface of the counterbore is recessed rather than the bent shape of the semiconductor substrate during heating in vapor phase growth, and vapor phase growth is performed, the substrate is separated from the main surface side and the main back surface side. Even when heating from both sides, a semiconductor wafer can be manufactured by vapor-depositing a thin film on the main surface of a substrate whose both surfaces are mirror-polished, without forming contact marks on the main back surface of the substrate.
【００１９】[0019]
【発明の実施の形態】以下、図面を参照して、本発明に
係る実施の形態について説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.
【００２０】〔第１の実施の形態〕先ず、サセプタの構
成について説明する。図１に示す本実施の形態のサセプ
タ１は、基板Ｗを主表面側からと主裏面側からとの双方
から加熱して行う気相成長の際に該基板Ｗを支持するも
のである。このサセプタ１は、例えば平板な円盤状に概
略構成されている。サセプタ１は、基板Ｗの支持状態
で、該基板Ｗを当該サセプタ１に対し位置決めさせるた
めの座ぐり２を、上面に有している。この座ぐり２は、
基板Ｗの直径よりも内径が若干大きく設定された平面視
円形の凹部である。ただし、本実施形態のサセプタ１の
座ぐり２は、基板Ｗを支持する円環状の外周側部分２１
と、該外周側部分２１の内側に該外周側部分２１よりも
窪んだ状態に形成された平面視円形の内周側部分２２と
を有する二段構成をなしている。このうち、外周側部分
２１は、基板Ｗの周縁部あるいは面取部を好適に支持可
能となるように、例えば平面に形成されている。他方、
内周側部分２２の底面２２ａは、例えば、周縁部から中
心に向かうほど次第に深くなるよう凹曲面状に窪まされ
ている。ただし、該内周側部分２２の底面２２ａの窪み
形状は、気相成長の加熱の際における基板Ｗの撓み形状
よりも深く設定されている。すなわち、座ぐり２の底面
は、気相成長の加熱の際における基板Ｗの撓み形状より
も窪まされている。なお、基板Ｗを加熱しないでサセプ
タ１により支持した状態における座ぐり２の内周側部分
２２の底面２２ａと基板Ｗの主裏面との最大距離Ｄは、
例えば０．４ｍｍ以下に設定されている。このようなサ
セプタ１は、例えば、グラファイトからなる本体部の表
面にＳｉＣ（炭化珪素）をコーティングすることにより
構成されている。[First Embodiment] First, the structure of a susceptor will be described. The susceptor 1 of the present embodiment shown in FIG. 1 supports the substrate W during vapor phase growth performed by heating the substrate W from both the main surface side and the main back surface side. The susceptor 1 is generally configured in a flat disc shape, for example. The susceptor 1 has a counterbore 2 on its upper surface for positioning the substrate W with respect to the susceptor 1 while the substrate W is being supported. This spot facing 2
The concave portion is circular in plan view and has an inner diameter set to be slightly larger than the diameter of the substrate W. However, the counterbore 2 of the susceptor 1 of the present embodiment has an annular outer peripheral side portion 21 that supports the substrate W.
And an inner peripheral side portion 22 having a circular shape in plan view, which is formed inside the outer peripheral side portion 21 so as to be recessed from the outer peripheral side portion 21. Of these, the outer peripheral portion 21 is formed, for example, in a flat surface so that the peripheral portion or the chamfered portion of the substrate W can be favorably supported. On the other hand,
The bottom surface 22a of the inner peripheral side portion 22 is, for example, recessed into a concave curved surface so that the bottom surface 22a becomes gradually deeper from the peripheral portion toward the center. However, the hollow shape of the bottom surface 22a of the inner peripheral side portion 22 is set deeper than the bent shape of the substrate W during heating in vapor phase growth. That is, the bottom surface of the spot facing 2 is recessed more than the bent shape of the substrate W during heating in vapor phase growth. The maximum distance D between the bottom surface 22a of the inner peripheral side portion 22 of the spot facing 2 and the main back surface of the substrate W when the substrate W is supported by the susceptor 1 without being heated is
For example, it is set to 0.4 mm or less. Such a susceptor 1 is formed by coating the surface of a main body made of graphite with SiC (silicon carbide), for example.
【００２１】次に、半導体ウェーハの製造装置の構成に
ついて説明する。図２に示すように、半導体ウェーハの
製造装置１０は、基板Ｗ（例えばシリコン単結晶基板）
の主表面上に薄膜（例えばシリコン単結晶薄膜）を気相
成長させるための装置であり、反応容器１１と、この反
応容器１１内に配された上記サセプタ１と、このサセプ
タ１を気相成長の際に回転駆動させる駆動装置（図示
略）と、サセプタ１の上下に配され反応容器１１内を加
熱するための加熱装置１３（例えばハロゲンランプ）等
を備えて概略構成されている。反応容器１１内には、矢
印Ａ方向に沿ってガス（原料ガスおよびキャリアガスを
含む気相成長用ガス）が導入され、反応容器１１内から
は、矢印Ｂ方向に沿って排気されるようになっている。Next, the structure of the semiconductor wafer manufacturing apparatus will be described. As shown in FIG. 2, the semiconductor wafer manufacturing apparatus 10 includes a substrate W (for example, a silicon single crystal substrate).
Is a device for vapor-phase growing a thin film (for example, a silicon single crystal thin film) on the main surface of the reaction vessel 11, the susceptor 1 arranged in the reaction vessel 11, and the susceptor 1 In this case, a driving device (not shown) for rotating and driving, a heating device 13 (for example, a halogen lamp) arranged above and below the susceptor 1 for heating the inside of the reaction container 11, and the like are schematically configured. Gas (gas for vapor phase growth containing a source gas and a carrier gas) is introduced into the reaction vessel 11 along the direction of arrow A, and is exhausted from inside the reaction vessel 11 along the direction of arrow B. Has become.
【００２２】次に、半導体ウェーハの製造方法について
説明する。先ず、基板Ｗを支持したサセプタ１を反応容
器１１内に配し、このサセプタ１を回転させながら、加
熱装置１３により反応容器１１内の基板Ｗを加熱すると
ともに、反応容器１１内にガスを導入することで、該ガ
スを基板Ｗの主表面上に供給して、該基板Ｗの主表面上
に薄膜を気相成長させ、半導体ウェーハを製造すること
ができる。なお、気相成長の際の基板Ｗの加熱は、該基
板Ｗの主表面側とサセプタ１を介して該基板Ｗの主裏面
側との双方から行う。また、基板Ｗとしては、例えば、
両面が鏡面研磨処理されたもの（両面ミラーの基板）を
用いる。Next, a method of manufacturing a semiconductor wafer will be described. First, the susceptor 1 supporting the substrate W is placed in the reaction container 11, and while rotating the susceptor 1, the heating device 13 heats the substrate W in the reaction container 11 and introduces gas into the reaction container 11. By doing so, the gas can be supplied onto the main surface of the substrate W, and a thin film can be vapor-phase grown on the main surface of the substrate W to manufacture a semiconductor wafer. The heating of the substrate W during vapor phase growth is performed from both the main front surface side of the substrate W and the main back surface side of the substrate W via the susceptor 1. Further, as the substrate W, for example,
A mirror-polished surface (double-sided mirror substrate) is used.
【００２３】ところで、気相成長の際には、基板Ｗが、
加熱によりその中心部が座ぐり２の内周側部分２２の底
面２２ａに近づく方向に僅かに撓むことがある。これに
対し、本実施形態のサセプタ１は、座ぐり２の内周側部
分２２の底面（座ぐり底面）２２ａが、気相成長の加熱
の際における基板Ｗの撓み形状よりも窪まされているの
で、このように加熱によって基板Ｗが撓んだとしても、
基板Ｗの主裏面が底面２２ａに接触してしまうことを防
止できる。よって、基板Ｗの主裏面に座ぐり２との接触
跡が形成されてしまうことを好適に防止できる。しか
も、座ぐり２の内周側部分２２の底面２２ａが、周縁部
から中心に向かうほど次第に窪まされているため、該周
縁部における基板Ｗと底面２２ａとの間隔を中心部より
も狭くすることができる。よって、該底面２２ａと基板
Ｗとの非接触状態を保ちつつも、該間隔への水素（キャ
リアガスとして用いる）の侵入を抑制できる。この結
果、該水素による基板Ｗ主裏面のエッチングも抑制でき
るので、該主裏面に微少なキズが形成されていたとして
も、このキズが目立つようになってしまうことを防止で
きる。従って、両面ミラーの基板Ｗを用いて半導体ウェ
ーハを製造する場合にも、該基板Ｗの主裏面に底面２２
ａとの接触跡を形成してしまうことを防止できる。な
お、基板Ｗの主裏面に形成されている微少なキズは、研
磨工程にて形成される研磨キズであると考えられ、水素
エッチングにより目立つようになると考えられる。By the way, during the vapor phase growth, the substrate W is
The center of the spot facing 2 may slightly bend toward the bottom surface 22a of the inner peripheral side portion 22 due to heating. On the other hand, in the susceptor 1 of the present embodiment, the bottom surface (counterbore bottom surface) 22a of the inner peripheral side portion 22 of the counterbore 2 is recessed more than the bent shape of the substrate W during heating in vapor phase growth. Therefore, even if the substrate W is bent by heating in this way,
It is possible to prevent the main back surface of the substrate W from coming into contact with the bottom surface 22a. Therefore, it is possible to preferably prevent the contact mark with the counterbore 2 from being formed on the main back surface of the substrate W. Moreover, since the bottom surface 22a of the inner peripheral side portion 22 of the spot facing 2 is gradually recessed from the peripheral edge portion toward the center, the distance between the substrate W and the bottom surface 22a at the peripheral edge portion should be narrower than that in the central portion. You can Therefore, it is possible to suppress the invasion of hydrogen (used as a carrier gas) into the space while maintaining the non-contact state between the bottom surface 22a and the substrate W. As a result, etching of the main back surface of the substrate W due to the hydrogen can also be suppressed, so that even if minute scratches are formed on the main back surface, it is possible to prevent these scratches from becoming conspicuous. Therefore, even when a semiconductor wafer is manufactured using the double-sided mirror substrate W, the bottom surface 22 is formed on the main back surface of the substrate W.
It is possible to prevent the formation of contact marks with a. It is considered that the minute scratches formed on the main back surface of the substrate W are polishing scratches formed in the polishing step, and become conspicuous by hydrogen etching.
【００２４】次に、本実施形態の好適な実施例を説明す
る。
＜実施例＞本発明者は、直径３００ｍｍの基板を支持可
能で、基板Ｗを加熱しないで支持した状態における基板
Ｗの主裏面と座ぐり２の内周側部分２２の底面２２ａと
の最大距離が０．４ｍｍとなるように構成した本実施の
形態のサセプタ１と、該最大距離が０．３５ｍｍとなる
ように構成したサセプタ１とを各々作成した。そして、
これらサセプタ１を各々用いて、両面ミラーの基板Ｗと
してのシリコン単結晶基板の主表面上に、水素雰囲気中
１１３０℃で、薄膜としてのシリコン単結晶薄膜を気相
成長させて、半導体ウェーハとしてのシリコンエピタキ
シャルウェーハを製造した。この製造したシリコンエピ
タキシャルウェーハの主裏面を外観検査すると、前記最
大距離が０．４ｍｍのサセプタ１を用いた場合と、同
０．３５ｍｍのサセプタ１を用いた場合で、ともに目立
つキズは発見されなかった。Next, a preferred example of this embodiment will be described. <Example> The present inventor can support a substrate having a diameter of 300 mm, and the maximum distance between the main back surface of the substrate W and the bottom surface 22a of the inner peripheral side portion 22 of the spot facing 2 in a state where the substrate W is supported without being heated. And the susceptor 1 of the present embodiment configured to have a maximum distance of 0.4 mm and the susceptor 1 having a maximum distance of 0.35 mm, respectively. And
Each of these susceptors 1 is used to vapor-deposit a silicon single crystal thin film as a thin film on a main surface of a silicon single crystal substrate as a double-sided mirror substrate W at 1130 ° C. in a hydrogen atmosphere to obtain a semiconductor wafer. A silicon epitaxial wafer was manufactured. Visual inspection of the main back surface of the manufactured silicon epitaxial wafer revealed no conspicuous scratches when using the susceptor 1 having the maximum distance of 0.4 mm and when using the susceptor 1 having the maximum distance of 0.35 mm. It was
【００２５】＜比較例＞また、本発明者は、比較例とし
て、前記最大距離が０．４５ｍｍである他は上記の実施
例と同様のサセプタと、前記最大距離が０．７ｍｍであ
る他は上記の実施例と同様のサセプタとを各々作成し、
これらサセプタを用いて、上記の実施例と同様の条件で
半導体ウェーハ（つまりシリコンエピタキシャルウェー
ハ）を製造した。この製造したシリコンエピタキシャル
ウェーハの主裏面を外観検査すると、前記最大距離が
０．４５ｍｍのサセプタを用いた場合には、目立つキズ
が発見された。また、前記最大距離が０．７ｍｍのサセ
プタを用いた場合には、目立つキズがより多く発見され
た。<Comparative Example> Further, as a comparative example, the present inventor has the same susceptor as that of the above-described embodiment except that the maximum distance is 0.45 mm, and that the maximum distance is 0.7 mm. Create a susceptor similar to the above example,
Using these susceptors, semiconductor wafers (that is, silicon epitaxial wafers) were manufactured under the same conditions as those in the above-mentioned examples. When the main surface of the manufactured silicon epitaxial wafer was visually inspected, conspicuous scratches were found when a susceptor having a maximum distance of 0.45 mm was used. Further, when the susceptor having the maximum distance of 0.7 mm was used, more noticeable scratches were found.
【００２６】このような実施例と比較例との検討から明
らかなように、本実施の形態のサセプタ１は、基板Ｗを
加熱しないで支持した状態における基板Ｗの主裏面と座
ぐり２の内周側部分２２の底面２２ａとの最大距離が
０．４ｍｍ以下となるように構成すれば、該底面２２ａ
と基板Ｗとの間隔への水素の侵入を抑制でき、該水素に
よる基板主裏面のエッチングも抑制できる。よって、基
板Ｗの主裏面に元々微少なキズが形成されていても、こ
のキズが半導体ウェーハの製造後において目立つように
なってしまうことを防止できる。As is clear from the examination of such Examples and Comparative Examples, the susceptor 1 of the present embodiment includes the main back surface of the substrate W and the spot facing 2 in a state where the substrate W is supported without being heated. If the maximum distance from the bottom surface 22a of the peripheral side portion 22 is 0.4 mm or less, the bottom surface 22a
Hydrogen can be prevented from entering the space between the substrate W and the substrate W, and etching of the main and rear surfaces of the substrate due to the hydrogen can also be suppressed. Therefore, even if a minute flaw is originally formed on the main back surface of the substrate W, it is possible to prevent the flaw from becoming conspicuous after the manufacture of the semiconductor wafer.
【００２７】以上のような実施の形態によれば、座ぐり
２の底面２２ａが、気相成長の加熱の際における基板Ｗ
の撓み形状よりも窪まされているので、基板Ｗが、加熱
によりその中心部が座ぐり２に近づく方向に僅かに撓ん
だとしても、基板Ｗの主裏面と座ぐり２の底面２２ａと
を非接触状態に維持することができる。よって、基板Ｗ
の主裏面に接触跡が形成されてしまうことを好適に防止
できる。しかも、座ぐり２の底面２２ａが周縁部から中
心に向かうほど次第に窪まされているため、周縁部にお
ける基板Ｗと座ぐり２との間隔を狭くすることができ
る。よって、該間隔への水素の侵入を抑制できる結果、
該水素による基板主裏面のエッチングも抑制できるの
で、該主裏面に微少なキズが形成されていても、このキ
ズが目立つようになってしまうことを防止できる。ま
た、特に、内周側部分２２の底面２２ａと基板Ｗとの最
大距離が、基板Ｗを加熱しないで支持した状態で０．４
ｍｍ以下となるように、該底面２２ａが窪まされている
ので、基板Ｗと座ぐり２との間隔への水素の侵入を確実
に抑制できる。According to the above-described embodiment, the bottom surface 22a of the spot facing 2 is the substrate W during heating in vapor phase growth.
Since the substrate W is slightly dented in the direction in which the central portion thereof approaches the spot facing 2 due to heating, the main back surface of the substrate W and the bottom face 22a of the spot facing 2 are formed. It can be maintained in a non-contact state. Therefore, the substrate W
It is possible to preferably prevent a contact mark from being formed on the main back surface of the. Moreover, since the bottom surface 22a of the spot facing 2 is gradually recessed from the peripheral portion toward the center, the interval between the substrate W and the spot facing 2 at the peripheral portion can be narrowed. Therefore, as a result of being able to suppress the penetration of hydrogen into the interval,
Since the etching of the main back surface of the substrate due to the hydrogen can be suppressed, even if a minute flaw is formed on the main back surface, it is possible to prevent the flaw from becoming conspicuous. Further, in particular, the maximum distance between the bottom surface 22a of the inner peripheral side portion 22 and the substrate W is 0.4 when the substrate W is supported without being heated.
Since the bottom surface 22a is recessed so as to be less than or equal to mm, it is possible to reliably suppress the entry of hydrogen into the space between the substrate W and the spot facing 2.
【００２８】なお、上記の第１の実施の形態では、座ぐ
り２の底面２２ａが、周縁部から中心に向かうほど凹曲
面状に次第に窪まされている（ドーム状に窪まされてい
る）例について説明したが、本発明はこれに限らず、座
ぐり２の底面が、気相成長の加熱の際における基板Ｗの
撓み形状よりも窪まされていれば、その他の如何なる形
状であっても、基板Ｗの主裏面と座ぐり２の底面２２ａ
とを非接触状態に維持することができるので、基板Ｗの
主裏面に接触跡が形成されることを防止できる。具体的
には、例えば、座ぐりの底面が、倒立円錐状（ただし、
上面に比べて高さが極めて小さい）に窪まされていても
良い。或いは、座ぐりの底面が、倒立円錐台状に窪まさ
れていても良い。すなわち、座ぐりの底面の一部は、周
縁部から中心に向かうほど次第に窪む傾斜面状部（例え
ば、倒立円錐台状の窪みにおける側周面に相当）となっ
ているとともに、該底面のうちで該傾斜面状部よりも中
央寄りの部位（例えば、倒立円錐台状の窪みにおける平
面部に相当）は、該傾斜面状部の最深部以上の深さ（窪
みが倒立円錐台状の場合、傾斜面状部の最深部と等しい
深さ）に設定されていても良い。また、例えば、上記の
ような二段構成の座ぐりの場合などは、座ぐり２の底面
２２ａが、気相成長の加熱の際における基板Ｗの撓み形
状よりも窪まされていれば、該底面２２ａが平面に形成
されていても良い。ただし、この場合、周縁部における
底面２２ａと基板Ｗとの間隔が大きくなるため、基板Ｗ
がエッチングされやすくなる上、底面２２ａが平面であ
るため、サセプタが大寸法の場合、該サセプタを製造し
難い。また、例えば、上記のような二段構成の座ぐりの
場合などは、座ぐり２の底面２２ａが、***していても
良い。ただし、この場合も、周縁部における底面２２ａ
と基板Ｗとの間隔が大きくなるため、基板Ｗがエッチン
グされやすくなる上、基板周縁部の温度が中心部に比べ
て低くなるのでスリップが発生しやすくなる。In the first embodiment described above, the bottom surface 22a of the spot facing 2 is gradually recessed into a concave curved surface (dome-shaped recess) from the peripheral edge toward the center. However, the present invention is not limited to this, and any other shape may be used as long as the bottom surface of the spot facing 2 is recessed from the bent shape of the substrate W during heating in vapor phase growth. Main back surface of W and bottom surface 22a of counterbore 2
Since and can be maintained in a non-contact state, it is possible to prevent a contact mark from being formed on the main back surface of the substrate W. Specifically, for example, the bottom face of the spot facing is an inverted cone (however,
The height may be extremely smaller than that of the upper surface). Alternatively, the bottom surface of the spot facing may be recessed in an inverted truncated cone shape. That is, a part of the bottom surface of the counterbore is an inclined surface portion (for example, corresponding to a side peripheral surface of an inverted truncated cone-shaped recess) that gradually becomes recessed from the peripheral portion toward the center. At a portion closer to the center than the inclined surface portion (e.g., a flat surface portion in the inverted truncated cone-shaped recess), the depth is equal to or more than the deepest portion of the inclined planar portion (when the recess is an inverted truncated cone shape). , The same depth as the deepest part of the inclined surface portion). Further, for example, in the case of the above-described two-step counterbore, if the bottom surface 22a of the counterbore 2 is recessed from the bent shape of the substrate W at the time of heating in the vapor phase growth, the bottom surface 22a. May be formed flat. However, in this case, since the distance between the bottom surface 22a and the substrate W at the peripheral portion becomes large, the substrate W
Is easily etched, and the bottom surface 22a is a flat surface. Therefore, when the susceptor has a large size, it is difficult to manufacture the susceptor. Further, for example, in the case of the above-described two-stage counterbore, the bottom surface 22a of the counterbore 2 may be raised. However, also in this case, the bottom surface 22a at the peripheral portion
Since the distance between the substrate W and the substrate W becomes large, the substrate W is easily etched, and the temperature of the peripheral portion of the substrate becomes lower than that of the central portion, so that slip easily occurs.
【００２９】〔第２の実施の形態〕第２の実施の形態で
は、上記第１の実施の形態と同様の構成要素には同一の
符号を付し、その説明を省略する。図３に示す第２の実
施の形態のサセプタ３０は、直線に引かれた仮想線Ｌと
の比較から分かるように、基板Ｗを支持する主表面３１
に対し裏面３２が、該裏面３２の中心部ほど窪むように
反り返った全体姿勢をなす盤状に形成されている。この
サセプタ３０の主表面３１には、上記の第１の実施の形
態と同様の座ぐり２が形成されている。この第２の実施
の形態によれば、サセプタ３０が、反り返った全体姿勢
に形成されていても良い。つまり、全体姿勢が平板状と
なるように形成する必要がない。よって、平板状に形成
する必要がある場合よりもサセプタ３０の製造が容易と
なり、例えば直径３００ｍｍの半導体ウェーハを支持す
るサセプタのように、比較的大寸法のサセプタであって
も好適に製造することが可能となる。[Second Embodiment] In the second embodiment, the same components as those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. The susceptor 30 of the second embodiment shown in FIG. 3 has a main surface 31 that supports the substrate W, as can be seen from a comparison with a virtual line L drawn in a straight line.
On the other hand, the back surface 32 is formed in the shape of a board that is in an overall posture in which the back surface 32 is warped so as to be recessed toward the center thereof. On the main surface 31 of the susceptor 30, the spot facing 2 similar to that of the above-described first embodiment is formed. According to the second embodiment, the susceptor 30 may be formed in a warped overall posture. That is, it is not necessary to form the entire posture to be flat. Therefore, it becomes easier to manufacture the susceptor 30 than when it is necessary to form a flat plate, and it is preferable to appropriately manufacture a susceptor having a relatively large size such as a susceptor supporting a semiconductor wafer having a diameter of 300 mm. Is possible.
【００３０】なお、上記の各実施の形態では、座ぐり２
が二段構成をなす例について説明したが、これに限ら
ず、例えば、図４に示すサセプタ４０のように、座ぐり
２が一段であっても良い。図４に示す例の場合、座ぐり
２は、その底面２ａが基板Ｗに対し円状に線接触状態と
なって該基板Ｗを支持する。In each of the above embodiments, the spot facing 2
However, the present invention is not limited to this, and the counterbore 2 may have a single stage, such as the susceptor 40 shown in FIG. In the case of the example shown in FIG. 4, the counterbore 2 has the bottom surface 2 a thereof circularly in line contact with the substrate W to support the substrate W.
【００３１】[0031]
【発明の効果】本発明のサセプタによれば、座ぐりの底
面が、気相成長の加熱の際における基板の撓み形状より
も窪まされているので、基板が、加熱によりその中心部
が座ぐりに近づく方向に僅かに撓んだとしても、基板の
主裏面と座ぐり底面とを非接触状態に維持することがで
きる。よって、基板の主裏面に、座ぐり底面との接触跡
が形成されてしまうことを好適に防止できる。また、本
発明の半導体ウェーハの製造方法によれば、基板の主裏
面に接触跡を形成することなく、両面が鏡面研磨処理さ
れた基板の主表面上に薄膜を気相成長させて半導体ウェ
ーハを製造することができる。According to the susceptor of the present invention, since the bottom surface of the counterbore is recessed more than the bent shape of the substrate at the time of heating in the vapor phase growth, the center of the substrate is counterbored by heating. The main back surface of the substrate and the counterbore bottom surface can be maintained in a non-contact state even if they are slightly bent in the approaching direction. Therefore, it is possible to preferably prevent the formation of a contact mark with the counterbore bottom surface on the main back surface of the substrate. Further, according to the method for producing a semiconductor wafer of the present invention, a semiconductor wafer is obtained by vapor-depositing a thin film on the main surface of a substrate whose both surfaces are mirror-polished without forming a contact mark on the main back surface of the substrate. It can be manufactured.
【図面の簡単な説明】[Brief description of drawings]
【図１】第１の実施の形態のサセプタを示す模式的な正
面断面図である。FIG. 1 is a schematic front sectional view showing a susceptor according to a first embodiment.
【図２】半導体ウェーハの製造装置を示す模式的な正面
断面図である。FIG. 2 is a schematic front sectional view showing a semiconductor wafer manufacturing apparatus.
【図３】第２の実施の形態のサセプタを示す模式的な正
面断面図である。FIG. 3 is a schematic front cross-sectional view showing a susceptor according to a second embodiment.
【図４】座ぐりが一段の例を示す模式的な正面図であ
る。FIG. 4 is a schematic front view showing an example in which the spot facing is one step.
【図５】従来の気相成長装置（タイプ１）を示す模式的
な正面断面図である。FIG. 5 is a schematic front sectional view showing a conventional vapor phase growth apparatus (type 1).
【図６】従来の気相成長装置（タイプ２）を示す模式的
な正面断面図である。FIG. 6 is a schematic front sectional view showing a conventional vapor phase growth apparatus (type 2).
１ サセプタ ２ 座ぐり ２１ 外周側部分 ２２ 内周側部分 ２２ａ 内周側部分の底面（座ぐり底面） ３０ サセプタ ４０ サセプタ Ｗ 半導体基板 Ｄ 最大距離 1 susceptor 2 spot facing 21 Outer peripheral part 22 Inner peripheral part 22a Inner peripheral side bottom surface (counterbore bottom surface) 30 susceptor 40 susceptor W semiconductor substrate D maximum distance
Claims (8)
らとの双方から加熱して行う気相成長の際に該半導体基
板を支持するサセプタにおいて、当該サセプタに対し半
導体基板を位置決めさせるための座ぐりを有し、該座ぐ
りの底面が、前記加熱の際における半導体基板の撓み形
状よりも窪まされていることを特徴とするサセプタ。1. A susceptor for supporting a semiconductor substrate during vapor phase growth performed by heating the semiconductor substrate from both the main surface side and the main back surface side, for positioning the semiconductor substrate with respect to the susceptor. 2. The susceptor having a counterbore, wherein the bottom surface of the counterbore is recessed more than the bent shape of the semiconductor substrate during the heating.
向かうほど次第に窪まされていることを特徴とする請求
項１に記載のサセプタ。2. The susceptor according to claim 1, wherein the bottom surface of the counterbore is gradually recessed from the peripheral portion toward the center.
中心に向かうほど次第に窪む傾斜面状部となっていると
ともに、該底面のうちで該傾斜面状部よりも中央寄りの
部位は、該傾斜面状部の最深部以上の深さに設定されて
いることを特徴とする請求項１に記載のサセプタ。3. A part of the bottom surface of the counterbore is an inclined surface portion that is gradually recessed from the peripheral portion toward the center, and a portion of the bottom surface that is closer to the center than the inclined surface portion. Is set to a depth equal to or greater than the deepest part of the inclined surface-like part.
周側部分と、該外周側部分の内側に該外周側部分よりも
窪んだ状態に形成された内周側部分とを有する二段構成
をなすことを特徴とする請求項１または２に記載のサセ
プタ。4. The counterbore has a two-stage structure having an outer peripheral side portion for supporting a semiconductor substrate and an inner peripheral side portion formed inside the outer peripheral side portion in a state of being recessed from the outer peripheral side portion. The susceptor according to claim 1 or 2, wherein the susceptor is formed.
最大距離が、半導体基板を加熱しないで支持した状態で
０．４ｍｍ以下となるように、該内周側部分の底面が窪
まされていることを特徴とする請求項４に記載のサセプ
タ。5. The bottom surface of the inner peripheral portion is recessed so that the maximum distance between the bottom surface of the inner peripheral portion and the semiconductor substrate is 0.4 mm or less when the semiconductor substrate is supported without being heated. The susceptor according to claim 4, wherein:
主表面に対し裏面が、該裏面の中心部ほど窪むように、
反り返った全体姿勢をなす盤状に形成されていることを
特徴とする請求項１に記載のサセプタ。6. The main surface of the susceptor supporting a semiconductor substrate, the back surface of the susceptor is recessed toward the center of the back surface,
The susceptor according to claim 1, wherein the susceptor is formed in a disc-like shape that has a warped overall posture.
主表面上に薄膜を気相成長させて半導体ウェーハを製造
する半導体ウェーハの製造方法において、請求項１〜６
の何れかに記載のサセプタにより支持させた半導体基板
を、主表面側と該サセプタを介して主裏面側との双方か
ら加熱しながら、該半導体基板の主表面上に薄膜を気相
成長させることを特徴とする半導体ウェーハの製造方
法。7. A method for producing a semiconductor wafer, comprising producing a semiconductor wafer by vapor-depositing a thin film on a main surface of a semiconductor substrate, both surfaces of which are mirror-polished.
While vapor-depositing a thin film on the main surface of the semiconductor substrate while heating the semiconductor substrate supported by the susceptor according to any one of 1 to 3, from both the main surface side and the main back surface side through the susceptor. And a method for manufacturing a semiconductor wafer.
りを有し、気相成長の加熱の際における半導体基板の撓
み形状よりも前記座ぐりの底面が窪まされたサセプタに
より、両面が鏡面研磨処理された半導体基板を支持し、
該半導体基板を、主表面側と該サセプタを介して主裏面
側との双方から加熱しながら、該半導体基板の主表面上
に薄膜を気相成長させて半導体ウェーハを製造すること
を特徴とする半導体ウェーハの製造方法。8. A susceptor having a spot facing for positioning the semiconductor substrate, the bottom surface of which is recessed more than the bent shape of the semiconductor substrate during heating in vapor phase growth, is mirror-polished on both sides. Supporting the semiconductor substrate,
A semiconductor wafer is manufactured by vapor-depositing a thin film on the main surface of the semiconductor substrate while heating the semiconductor substrate from both the main surface side and the main back surface side via the susceptor. Manufacturing method of semiconductor wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002124056A JP4003527B2 (en) | 2002-04-25 | 2002-04-25 | Susceptor and semiconductor wafer manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002124056A JP4003527B2 (en) | 2002-04-25 | 2002-04-25 | Susceptor and semiconductor wafer manufacturing method |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007120829A Division JP4665935B2 (en) | 2007-05-01 | 2007-05-01 | Manufacturing method of semiconductor wafer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003318116A true JP2003318116A (en) | 2003-11-07 |
| JP4003527B2 JP4003527B2 (en) | 2007-11-07 |
Family
ID=29539173
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002124056A Expired - Fee Related JP4003527B2 (en) | 2002-04-25 | 2002-04-25 | Susceptor and semiconductor wafer manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4003527B2 (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2005081298A1 (en) * | 2004-02-25 | 2008-01-17 | 日鉱金属株式会社 | Vapor phase growth equipment |
| JP2008186940A (en) * | 2007-01-29 | 2008-08-14 | Dainippon Screen Mfg Co Ltd | Susceptor for heat treatment and heat treatment apparatus |
| JP2008205234A (en) * | 2007-02-21 | 2008-09-04 | Tokyo Electron Ltd | Method of obtaining height of chuck top and program recording medium in which the method is recorded |
| JP2009032946A (en) * | 2007-07-27 | 2009-02-12 | Shin Etsu Handotai Co Ltd | Vapor phase growth system and vapor-phase growth method |
| JP2009513027A (en) * | 2005-10-24 | 2009-03-26 | アプライド マテリアルズ インコーポレイテッド | Semiconductor processing chamber |
| WO2009084154A1 (en) * | 2007-12-28 | 2009-07-09 | Shin-Etsu Handotai Co., Ltd. | Susceptor for epitaxial growth |
| JP2010147080A (en) * | 2008-12-16 | 2010-07-01 | Shin Etsu Handotai Co Ltd | Susceptor for vapor deposition, vapor deposition apparatus, and manufacturing method of epitaxial wafer |
| JP2010530645A (en) * | 2007-06-19 | 2010-09-09 | エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド | Susceptor to improve throughput and reduce wafer damage |
| JP2010225646A (en) * | 2009-03-19 | 2010-10-07 | Dainippon Screen Mfg Co Ltd | Susceptor for heat treatment and heat treatment apparatus |
| JP2011193011A (en) * | 2011-04-28 | 2011-09-29 | Dainippon Screen Mfg Co Ltd | Susceptor for heat treatment and heat treatment apparatus |
| JP2012129405A (en) * | 2010-12-16 | 2012-07-05 | Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 | Susceptor |
| KR200471994Y1 (en) * | 2012-12-21 | 2014-03-31 | 주식회사 테스 | Substrate treatment apparatus |
| WO2016002815A1 (en) * | 2014-06-30 | 2016-01-07 | イビデン株式会社 | Method for producing ceramic member and supporting tool |
| JP2021106181A (en) * | 2019-12-26 | 2021-07-26 | 株式会社Sumco | Vapor phase growth apparatus |
| JP7326119B2 (en) | 2019-11-07 | 2023-08-15 | 株式会社アルバック | Substrate stage and vacuum processing equipment |
-
2002
- 2002-04-25 JP JP2002124056A patent/JP4003527B2/en not_active Expired - Fee Related
Cited By (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2005081298A1 (en) * | 2004-02-25 | 2008-01-17 | 日鉱金属株式会社 | Vapor phase growth equipment |
| KR101322217B1 (en) | 2004-02-25 | 2013-10-25 | 닛코킨조쿠 가부시키가이샤 | Epitaxially growing equipment |
| US7670434B2 (en) | 2004-02-25 | 2010-03-02 | Nippon Mining & Metals Co., Ltd. | Vapor phase growth apparatus |
| JP4647595B2 (en) * | 2004-02-25 | 2011-03-09 | Ｊｘ日鉱日石金属株式会社 | Vapor growth equipment |
| JP2009513027A (en) * | 2005-10-24 | 2009-03-26 | アプライド マテリアルズ インコーポレイテッド | Semiconductor processing chamber |
| JP2008186940A (en) * | 2007-01-29 | 2008-08-14 | Dainippon Screen Mfg Co Ltd | Susceptor for heat treatment and heat treatment apparatus |
| JP2008205234A (en) * | 2007-02-21 | 2008-09-04 | Tokyo Electron Ltd | Method of obtaining height of chuck top and program recording medium in which the method is recorded |
| JP4695106B2 (en) * | 2007-02-21 | 2011-06-08 | 東京エレクトロン株式会社 | Method for determining height of chuck top and program recording medium recording this method |
| JP2013093582A (en) * | 2007-06-19 | 2013-05-16 | Memc Electron Materials Inc | Susceptor for improving throughput and reducing wafer damage |
| JP2010530645A (en) * | 2007-06-19 | 2010-09-09 | エムイーエムシー・エレクトロニック・マテリアルズ・インコーポレイテッド | Susceptor to improve throughput and reduce wafer damage |
| JP2009032946A (en) * | 2007-07-27 | 2009-02-12 | Shin Etsu Handotai Co Ltd | Vapor phase growth system and vapor-phase growth method |
| US20110073037A1 (en) * | 2007-12-28 | 2011-03-31 | Shin-Etsu Handotai Co., Ltd. | Epitaxial growth susceptor |
| WO2009084154A1 (en) * | 2007-12-28 | 2009-07-09 | Shin-Etsu Handotai Co., Ltd. | Susceptor for epitaxial growth |
| TWI419255B (en) * | 2007-12-28 | 2013-12-11 | Shinetsu Handotai Kk | Epitaxial growth |
| JP4661982B2 (en) * | 2007-12-28 | 2011-03-30 | 信越半導体株式会社 | Epitaxial growth susceptor |
| JP2010147080A (en) * | 2008-12-16 | 2010-07-01 | Shin Etsu Handotai Co Ltd | Susceptor for vapor deposition, vapor deposition apparatus, and manufacturing method of epitaxial wafer |
| JP2010225646A (en) * | 2009-03-19 | 2010-10-07 | Dainippon Screen Mfg Co Ltd | Susceptor for heat treatment and heat treatment apparatus |
| JP2012129405A (en) * | 2010-12-16 | 2012-07-05 | Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 | Susceptor |
| JP2011193011A (en) * | 2011-04-28 | 2011-09-29 | Dainippon Screen Mfg Co Ltd | Susceptor for heat treatment and heat treatment apparatus |
| KR200471994Y1 (en) * | 2012-12-21 | 2014-03-31 | 주식회사 테스 | Substrate treatment apparatus |
| WO2016002815A1 (en) * | 2014-06-30 | 2016-01-07 | イビデン株式会社 | Method for producing ceramic member and supporting tool |
| JP2016011243A (en) * | 2014-06-30 | 2016-01-21 | イビデン株式会社 | Method for producing ceramic member, and supporting tool |
| JP7326119B2 (en) | 2019-11-07 | 2023-08-15 | 株式会社アルバック | Substrate stage and vacuum processing equipment |
| JP2021106181A (en) * | 2019-12-26 | 2021-07-26 | 株式会社Sumco | Vapor phase growth apparatus |
| JP7279630B2 (en) | 2019-12-26 | 2023-05-23 | 株式会社Sumco | Vapor deposition equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4003527B2 (en) | 2007-11-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100527672B1 (en) | Suscepter and apparatus for depositing included the same | |
| JP4669476B2 (en) | Holder for supporting wafers during semiconductor manufacturing | |
| JP4003527B2 (en) | Susceptor and semiconductor wafer manufacturing method | |
| KR20170122277A (en) | Susceptor, epitaxial growth device, and epitaxial wafer | |
| JPH0758041A (en) | Susceptor | |
| WO2016174859A1 (en) | Susceptor and epitaxial growth device | |
| JP2004319623A (en) | Susceptor and vapor phase growing apparatus | |
| JPH02186622A (en) | Susceptor | |
| JP2010034476A (en) | Method of manufacturing epitaxial wafer and holder of wafer used for the same | |
| JP2011176213A (en) | Susceptor for supporting semiconductor substrate for vapor phase epitaxy, and device and method of manufacturing epitaxial wafer | |
| TW201335414A (en) | Graphite disc, reaction chamber having the same and heating method for substrate | |
| WO2005034219A1 (en) | Production method for silicon epitaxial wafer, and silicon epitaxial wafer | |
| JP2003100855A (en) | Silicon single crystalline wafer processing apparatus, and method of manufacturing silicon single crystalline wafer and silicon epitaxial wafer | |
| JP4599816B2 (en) | Manufacturing method of silicon epitaxial wafer | |
| JP2004119859A (en) | Susceptor, and device and method for manufacturing semiconductor wafer | |
| JPH1087394A (en) | Susceptor for vapor phase growth device | |
| JP2017076652A (en) | Substrate mounting table and vapor phase growth apparatus | |
| JP2010147080A (en) | Susceptor for vapor deposition, vapor deposition apparatus, and manufacturing method of epitaxial wafer | |
| JP4665935B2 (en) | Manufacturing method of semiconductor wafer | |
| JP2017199745A (en) | Susceptor | |
| JP2009071210A (en) | Susceptor and epitaxial growth system | |
| JP2003289045A (en) | Suscepter, and device for manufacturing epitaxial wafer and method for manufacturing epitaxial wafer | |
| JP2004200436A (en) | Susceptor and its manufacturing method | |
| JP7233361B2 (en) | Susceptor, epitaxial substrate manufacturing method, and epitaxial substrate | |
| JP2000269150A (en) | Semiconductor wafer heating tool and semiconductor wafer heater using the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20040727 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060228 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060501 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20070227 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070501 |
|
| A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20070515 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20070619 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20070704 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20070731 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20070813 |
|
| R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 Ref document number: 4003527 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100831 Year of fee payment: 3 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100831 Year of fee payment: 3 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100831 Year of fee payment: 3 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110831 Year of fee payment: 4 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110831 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120831 Year of fee payment: 5 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120831 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130831 Year of fee payment: 6 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |