JP2003297918A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereofInfo
- Publication number
- JP2003297918A JP2003297918A JP2002094351A JP2002094351A JP2003297918A JP 2003297918 A JP2003297918 A JP 2003297918A JP 2002094351 A JP2002094351 A JP 2002094351A JP 2002094351 A JP2002094351 A JP 2002094351A JP 2003297918 A JP2003297918 A JP 2003297918A
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- insulating film
- wiring
- film
- semiconductor device
- wirings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置および
その製造技術に関し、特に、銅を主成分とする主導体膜
を含む配線を有する半導体装置に適用して有効な技術に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to a technique effectively applied to a semiconductor device having a wiring including a main conductor film containing copper as a main component.
【０００２】[0002]
【従来の技術】埋込配線構造は、絶縁膜に形成された配
線溝や孔などのような配線開口部内に、ダマシン（Dama
scene）技術（シングルダマシン（Single-Damascene）
技術およびデュアルダマシン（Dual-Damascene）技術）
と称する配線形成技術によって、配線材料を埋め込むこ
とで形成される。しかし、主配線材料が銅（Ｃｕ）の場
合、銅がアルミニウム（Ａｌ）などのような金属と比較
して絶縁膜中に拡散されやすいことから、その銅からな
る埋込配線が絶縁膜と直接接しないように、埋込配線の
表面（底面および側面）を薄いバリア金属膜で覆うこと
により、埋込配線中の銅が絶縁膜中に拡散するのを抑制
または防止するようにしている。また、配線開口部が形
成された絶縁膜の上面上に、例えば窒化シリコン膜など
からなる配線キャップ用バリア絶縁膜を形成して埋込配
線の上面を覆うことにより、埋込配線中の銅が埋込配線
の上面から絶縁膜中に拡散するのを抑制または防止する
ようにしている。2. Description of the Related Art A buried wiring structure has a damascene (Damascene) structure inside a wiring opening such as a wiring groove or a hole formed in an insulating film.
scene) Technology (Single-Damascene)
Technology and Dual-Damascene technology)
It is formed by embedding a wiring material by a wiring forming technique called. However, when the main wiring material is copper (Cu), copper is more likely to diffuse into the insulating film than a metal such as aluminum (Al), so that the embedded wiring made of copper directly contacts the insulating film. By covering the surface (bottom surface and side surface) of the embedded wiring with a thin barrier metal film so as not to contact with each other, diffusion of copper in the embedded wiring into the insulating film is suppressed or prevented. Further, by forming a wiring cap barrier insulating film made of, for example, a silicon nitride film on the upper surface of the insulating film in which the wiring opening is formed and covering the upper surface of the embedded wiring, the copper in the embedded wiring is removed. It is intended to suppress or prevent the diffusion from the upper surface of the embedded wiring into the insulating film.
【０００３】近年、このような埋込配線の間隔は、半導
体装置の高集積化に伴い、減少してきている。これによ
り、配線間の寄生容量が増大して信号遅延が生じ、隣接
配線との間にクロストークが発生する。このため、配線
間の寄生容量を低減することが望まれる。配線間の寄生
容量を低減するために、配線間絶縁膜として低誘電率材
料が使用される。また、例えば特開２００１−８５５１
９号公報には、配線を逆テーパ形状に形成し、この配線
間の空間にエアギャップが形成されるように層間絶縁膜
を形成する技術が開示されている。このエアギャップに
より、配線間容量の低減を図っている。In recent years, such an interval between the buried wirings has been reduced with the high integration of semiconductor devices. As a result, the parasitic capacitance between the wirings increases and signal delay occurs, causing crosstalk with the adjacent wirings. Therefore, it is desired to reduce the parasitic capacitance between wirings. In order to reduce the parasitic capacitance between the wirings, a low dielectric constant material is used as the inter-wiring insulating film. In addition, for example, Japanese Patent Laid-Open No. 2001-8551
Japanese Unexamined Patent Publication 9 discloses a technique in which wiring is formed in an inversely tapered shape and an interlayer insulating film is formed so that an air gap is formed in the space between the wirings. This air gap is intended to reduce the capacitance between wirings.
【０００４】[0004]
【発明が解決しようとする課題】ところが、本発明者の
検討結果によれば、上記銅を主導体層とする埋込み配線
技術においては、以下の課題があることを見い出した。However, according to the results of the study by the present inventor, it has been found that the buried wiring technique using copper as the main conductor layer has the following problems.
【０００５】銅を配線材料に用いた場合、ＴＤＤＢ（Ti
me Dependence on Dielectric Breakdown）寿命が、他
の金属材料（例えばアルミニウムやタングステン）に比
べて著しく短いという問題がある。その上、配線ピッチ
の微細化が進み、実効電界強度が増加する傾向にあるこ
とに加え、近年は配線容量を低減する観点などから酸化
シリコンよりも誘電率の低い絶縁材料を配線間の絶縁膜
として使用する方向にあるが、誘電率の低い絶縁膜は一
般的に絶縁耐圧も低いことから、ＴＤＤＢ寿命の確保が
益々困難になる状況にある。When copper is used as the wiring material, TDDB (Ti
There is a problem that the life of me Dependence on Dielectric Breakdown) is remarkably shorter than that of other metal materials (for example, aluminum and tungsten). In addition, as the wiring pitch becomes finer and the effective electric field strength tends to increase, in recent years, from the viewpoint of reducing the wiring capacitance, an insulating material having a lower dielectric constant than silicon oxide is used as the insulating film between the wirings. However, since an insulating film having a low dielectric constant generally has a low withstand voltage, it is more and more difficult to secure the TDDB life.
【０００６】ＴＤＤＢ寿命の劣化は、一般に配線材料に
適用された銅が周辺に拡散し、これが配線間の絶縁破壊
耐圧を低下させると考えられている。上記特開２００１
−８５５１９号公報では、バリア金属膜およびバリア絶
縁膜については全く考慮されていない。このため、層間
絶縁膜のエアギャップにより配線間容量は低減しても、
配線材料として使用されている銅が層間絶縁膜中に拡散
し、ＴＤＤＢ寿命が低減してしまう。また、配線に逆テ
ーパを持たせることによりエアギャップを形成している
ため、配線の上端部に電界が集中し、ＴＤＤＢ寿命が更
に低減してしまう。The deterioration of the TDDB life is generally considered to be that copper applied to the wiring material diffuses to the periphery, which lowers the dielectric breakdown voltage between the wirings. The above-mentioned JP 2001
In Japanese Patent No. 85519, no consideration is given to the barrier metal film and the barrier insulating film. Therefore, even if the inter-wiring capacitance is reduced by the air gap of the interlayer insulating film,
Copper used as a wiring material diffuses into the interlayer insulating film, which shortens the TDDB life. In addition, since the air gap is formed by giving the wire a reverse taper, the electric field is concentrated on the upper end portion of the wire, and the TDDB life is further reduced.
【０００７】本発明の目的は、銅を主導体層とする配線
間の絶縁破壊耐性を向上させることができる半導体装置
およびその製造方法を提供することにある。An object of the present invention is to provide a semiconductor device capable of improving dielectric breakdown resistance between wirings having copper as a main conductor layer and a method for manufacturing the same.
【０００８】本発明の他の目的は、銅を主導体層とする
配線間の容量を低減できる半導体装置およびその製造方
法を提供することにある。Another object of the present invention is to provide a semiconductor device capable of reducing the capacitance between wirings having copper as a main conductor layer and a method for manufacturing the same.
【０００９】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
【００１０】[0010]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
次のとおりである。Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.
【００１１】本発明の半導体装置は、半導体基板、半導
体基板上に形成された第１の絶縁膜、第１の絶縁膜上に
形成され銅を主成分として含む配線、配線の上面および
側面上と第１の絶縁膜上とに形成され銅の拡散を抑制ま
たは防止する機能を有する第２の絶縁膜、および第２の
絶縁膜上に形成され第２の絶縁膜の誘電率より低い誘電
率を有する第３の絶縁膜を具備するものである。A semiconductor device according to the present invention includes a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a wiring formed on the first insulating film and containing copper as a main component, an upper surface and a side surface of the wiring, and A second insulating film formed on the first insulating film and having a function of suppressing or preventing the diffusion of copper, and a dielectric constant lower than that of the second insulating film formed on the second insulating film. The third insulating film has.
【００１２】本発明の半導体装置の製造方法は、半導体
基板を準備する工程、半導体基板上に第１の絶縁膜を形
成する工程、第１の絶縁膜上に銅を主成分として含む配
線を形成する工程、銅の拡散を抑制または防止する機能
を有する第２の絶縁膜をその材料で配線間が満たされな
いように配線の上面および側面上と第１の絶縁膜上とに
形成する工程、第２の絶縁膜の誘電率より低い誘電率を
有する第３の絶縁膜を第２の絶縁膜上に形成する工程を
有するものである。A method of manufacturing a semiconductor device according to the present invention comprises a step of preparing a semiconductor substrate, a step of forming a first insulating film on the semiconductor substrate, and a wiring containing copper as a main component on the first insulating film. A step of forming a second insulating film having a function of suppressing or preventing the diffusion of copper on the upper surface and side surfaces of the wiring and on the first insulating film so that the material does not fill the space between the wirings. The method has a step of forming a third insulating film having a dielectric constant lower than that of the second insulating film on the second insulating film.
【００１３】[0013]
【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて詳細に説明する。なお、実施の形態を説明す
るための全図において、同一の機能を有する部材には同
一の符号を付し、その繰り返しの説明は省略する。ま
た、以下の実施の形態では、特に必要なとき以外は同一
または同様な部分の説明を原則として繰り返さない。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, members having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.
【００１４】（実施の形態１）まず、本発明者らによっ
て検討された上記銅を主導体層とした埋込み配線間にお
けるＴＤＤＢ寿命の劣化原因について説明する。なお、
ＴＤＤＢ（Time Dependence on Dielectric Breakdow
n）寿命とは、絶縁破壊の時間的依存性を客観的に計る
尺度であって、所定の温度（例えば１４０℃）の測定条
件下で電極間に比較的高い電圧を加え、電圧印加から絶
縁破壊までの時間を印加電界に対してプロットしたグラ
フを作成し、このグラフから実際の使用電界強度（例え
ば０．２ＭＶ／ｃｍ）に外挿して求めた時間（寿命）を
いう。(Embodiment 1) First, the cause of deterioration of the TDDB life between embedded wirings using copper as the main conductor layer, which has been studied by the present inventors, will be described. In addition,
TDDB (Time Dependence on Dielectric Breakdow
n) Life is a measure to objectively measure the time dependence of dielectric breakdown, and a relatively high voltage is applied between the electrodes under the measurement condition of a predetermined temperature (for example, 140 ° C.) to isolate it from voltage application. The time (lifetime) obtained by extrapolating the graph to the applied electric field and plotting the time to breakdown and extrapolating from this graph to the actual field strength used (for example, 0.2 MV / cm).
【００１５】ＴＤＤＢ寿命の劣化は、一般に配線材料に
適用された銅が周辺に拡散し、これが配線間の絶縁破壊
耐圧を低下させると考えられている。しかし、本発明者
らによる検討結果によれば銅の拡散現象は、次のような
要因が支配的である。すなわち、第１は、隣接配線間の
絶縁膜中を拡散する銅は、原子状の銅よりも、酸化銅
（ＣｕＯ）あるいは銅シリサイドから供給されるイオン
化銅が配線間の電位でドリフトし拡散する要因が支配的
である。第２は、銅の拡散経路は銅配線が形成された絶
縁膜と配線キャップ膜との界面が支配的である。そし
て、これらのことから、ＴＤＤＢ寿命の劣化が、次のよ
うなメカニズムによるものであることが分かった。The deterioration of the TDDB life is generally considered to be that copper applied to the wiring material diffuses to the periphery, which lowers the dielectric breakdown voltage between the wirings. However, according to the examination results by the present inventors, the following factors dominate the copper diffusion phenomenon. That is, first, as for copper diffused in the insulating film between adjacent wirings, ionized copper supplied from copper oxide (CuO) or copper silicide drifts and diffuses at the potential between the wirings rather than atomic copper. Factors dominate. Second, the diffusion path of copper is dominated by the interface between the insulating film on which the copper wiring is formed and the wiring cap film. From these, it was found that the deterioration of the TDDB life was due to the following mechanism.
【００１６】すなわち、銅を主導体膜とする埋込み配線
の表面には、ＣＭＰ後の表面プロセスにより酸化銅（Ｃ
ｕＯ）が形成されたり、また、キャップ膜（窒化シリコ
ン膜）の形成の際に銅シリサイド（Ｃｕ化合物）が形成
されたりする。このような酸化銅あるいは銅シリサイド
は、純粋な銅と比較してイオン化され易い。このように
してイオン化された銅は配線間の電界によりドリフトさ
れ、配線間の絶縁膜に拡散される。一方、上記埋込み配
線を形成する絶縁膜（酸化シリコン膜）とキャップ膜
（窒化シリコン膜）との界面は、ＣＭＰダメージ、有機
物またはダングリングボンドが多く形成され、不連続で
あり、密着性にも乏しい。このようなダングリングボン
ドの存在は、上記銅イオンの拡散を助長する作用を有
し、銅イオンは界面に沿ってドリフトされ拡散する。す
なわち、配線間の前記界面にリークパスが形成される。
リークパスを流れるリーク電流は、長時間のリーク作用
と電流による熱ストレスも加わり、その後、加速度的に
電流値が増加して絶縁破壊に至る（ＴＤＤＢ寿命の低
下）。なお、このようなＴＤＤＢ寿命の劣化原因につい
ては、本願発明者による特願平１１−２２６８７６号、
特願２０００−１０４０１５号または特願２０００−３
００８５３号に開示がある。That is, the surface of the buried wiring whose main conductor film is copper is copper oxide (C
uO) is formed, or copper silicide (Cu compound) is formed when the cap film (silicon nitride film) is formed. Such copper oxide or copper silicide is more likely to be ionized than pure copper. The copper thus ionized is drifted by the electric field between the wirings and diffused into the insulating film between the wirings. On the other hand, the interface between the insulating film (silicon oxide film) and the cap film (silicon nitride film) forming the above-mentioned embedded wiring is discontinuous because of many CMP damages, organic substances or dangling bonds. poor. The presence of such dangling bonds has an action of promoting diffusion of the copper ions, and the copper ions are drifted and diffused along the interface. That is, a leak path is formed at the interface between the wirings.
The leak current flowing through the leak path is subjected to a long-term leak action and a thermal stress due to the current, and then the current value is accelerated to cause dielectric breakdown (decrease in TDDB life). Regarding the cause of such deterioration of the TDDB life, Japanese Patent Application No. 11-226876 by the present inventor,
Japanese Patent Application No. 2000-104015 or Japanese Patent Application 2000-3
It is disclosed in No. 00853.
【００１７】そこで、本実施の形態においては、上記リ
ークパスとして作用する界面であるＣＭＰ面（ＣＭＰで
研磨された面）を同層配線間からなくして、ＴＤＤＢ特
性を改善させることを検討した。更に、配線間の寄生容
量を低減させることも検討した。Therefore, in the present embodiment, it was studied to eliminate the CMP surface (surface polished by CMP), which is the interface acting as the leak path, from between the wirings in the same layer to improve the TDDB characteristics. Further, reduction of parasitic capacitance between wirings was also examined.
【００１８】本実施の形態の半導体装置およびその製造
工程を図面を参照して説明する。図１は、本発明の一実
施の形態である半導体装置、例えばＣＭＩＳＦＥＴ（Co
mplementary Metal Insulator Semiconductor Field Ef
fect Transistor）、の製造工程中の要部平面図であ
り、図２は図１のＡ−Ａ断面図である。The semiconductor device of the present embodiment and the manufacturing process thereof will be described with reference to the drawings. FIG. 1 shows a semiconductor device according to an embodiment of the present invention, for example, CMISFET (Co
mplementary Metal Insulator Semiconductor Field Ef
FIG. 2 is a cross-sectional view taken along the line AA of FIG. 1 during the manufacturing process of the (fect transistor).
【００１９】図１および図２に示すように、例えば１〜
１０Ωｃｍ程度の比抵抗を有するｐ型の単結晶シリコン
などからなるウエハまたは半導体基板１は、その主面に
素子分離領域２が形成されている。素子分離領域２は酸
化シリコンなどからなり、例えばＳＴＩ（Shallow Tren
ch Isolation）法またはＬＯＣＯＳ（Local Oxidizatio
n of Silicon ）法などにより形成される。As shown in FIGS. 1 and 2, for example, 1 to
A wafer or semiconductor substrate 1 made of p-type single crystal silicon or the like having a specific resistance of about 10 Ωcm has an element isolation region 2 formed on its main surface. The element isolation region 2 is made of silicon oxide or the like, and for example, STI (Shallow Tren
ch Isolation) method or LOCOS (Local Oxidizatio)
n of Silicon) method or the like.
【００２０】半導体基板１には、その主面から所定の深
さに渡ってｐ型ウエル３およびｎ型ウエル４が形成され
ている。ｐ型ウエル３は、例えばホウ素などの不純物を
イオン注入することなどによって形成され、ｎ型ウエル
４は、例えばリンなどの不純物をイオン注入することな
どによって形成される。A p-type well 3 and an n-type well 4 are formed on the semiconductor substrate 1 over a predetermined depth from the main surface thereof. The p-type well 3 is formed, for example, by ion-implanting impurities such as boron, and the n-type well 4 is formed, for example, by ion-implanting impurities such as phosphorus.
【００２１】ｐ型ウエル３の領域では、素子分離領域２
で囲まれた活性領域に、ｎチャネル型のＭＩＳＦＥＴ５
が形成されている。また、ｎ型ウエル４の領域では、素
子分離領域２で囲まれた活性領域に、ｐチャネル型のＭ
ＩＳＦＥＴ６が形成されている。ｎ型ＭＩＳＦＥＴ５お
よびｐ型ＭＩＳＦＥＴ６のゲート絶縁膜７は、例えば薄
い酸化シリコン膜などからなり、例えば熱酸化法などに
よって形成される。In the region of the p-type well 3, the element isolation region 2
In the active region surrounded by, n-channel type MISFET5
Are formed. In the region of the n-type well 4, a p-channel type M is formed in the active region surrounded by the element isolation region 2.
ISFET 6 is formed. The gate insulating film 7 of the n-type MISFET 5 and the p-type MISFET 6 is made of, for example, a thin silicon oxide film, and is formed by, for example, a thermal oxidation method.
【００２２】ｎ型ＭＩＳＦＥＴ５およびｐ型ＭＩＳＦＥ
Ｔ６のゲート電極８は、例えば、低抵抗の多結晶シリコ
ン膜上にチタンシリサイド（ＴｉＳｉx）層またはコバ
ルトシリサイド（ＣｏＳｉx）層を積層することにより
形成されている。ゲート電極８の側壁上には、例えば酸
化シリコンなどからなる側壁スペーサまたはサイドウォ
ール９が形成されている。N-type MISFET 5 and p-type MISFE
The gate electrode 8 of T6 is formed, for example, by stacking a titanium silicide (TiSi x ) layer or a cobalt silicide (CoSi x ) layer on a low resistance polycrystalline silicon film. Sidewall spacers or sidewalls 9 made of, for example, silicon oxide are formed on the sidewalls of the gate electrode 8.
【００２３】ｎ型ＭＩＳＦＥＴ５のソースおよびドレイ
ン領域は、ｎ-型の半導体領域１０ａと、それより不純
物濃度が高いｎ+型の半導体領域１０ｂとを有するＬＤ
Ｄ（Lightly Doped Drain）構造を備えている。ｎ-型の
半導体領域１０ａは、例えば、サイドウォール９の形成
前に、ｐ型ウエル３のゲート電極８の両側の領域にリン
などの不純物をイオン注入することにより形成される。
ｎ+型の半導体領域１０ｂは、例えば、サイドウォール
９の形成後に、ｐ型ウエル３のゲート電極８およびサイ
ドウォール９の両側の領域にリンなどの不純物をイオン
注入することにより形成される。The source and drain regions of the n - type MISFET 5 have an LD having an n -- type semiconductor region 10a and an n + -type semiconductor region 10b having a higher impurity concentration.
It has a D (Lightly Doped Drain) structure. The n − type semiconductor region 10 a is formed, for example, by ion-implanting impurities such as phosphorus into regions of the p type well 3 on both sides of the gate electrode 8 before forming the sidewall 9.
The n + type semiconductor region 10b is formed, for example, by ion-implanting impurities such as phosphorus into regions on both sides of the gate electrode 8 and the sidewall 9 of the p-type well 3 after forming the sidewall 9.
【００２４】ｐ型ＭＩＳＦＥＴ６のソースおよびドレイ
ン領域は、ｐ-型の半導体領域１１ａと、それより不純
物濃度が高いｐ+型の半導体領域１１ｂとを有するＬＤ
Ｄ構造を備えている。ｐ-型の半導体領域１１ａは、例
えば、サイドウォール９の形成前に、ｎ型ウエル４のゲ
ート電極８の両側の領域にホウ素などの不純物をイオン
注入することにより形成される。ｐ+型の半導体領域１
１ｂは、例えば、サイドウォール９の形成後に、ｎ型ウ
エル４のゲート電極８およびサイドウォール９の両側の
領域にホウ素などの不純物をイオン注入することにより
形成される。また、ｎ+型半導体領域１０ｂおよびｐ+型
の半導体領域１１ｂの上面の一部には、例えばチタンシ
リサイド層またはコバルトシリサイド層などのようなシ
リサイド層が形成されている。The source and drain regions of the p-type MISFET 6 are LDs each having a p - type semiconductor region 11a and ap + type semiconductor region 11b having a higher impurity concentration.
It has a D structure. The p − type semiconductor region 11a is formed, for example, by ion-implanting impurities such as boron into regions on both sides of the gate electrode 8 of the n-type well 4 before forming the sidewall 9. p + type semiconductor region 1
1b is formed, for example, by ion-implanting impurities such as boron into regions of the n-type well 4 on both sides of the gate electrode 8 and the sidewall 9 after the sidewall 9 is formed. Further, a silicide layer such as a titanium silicide layer or a cobalt silicide layer is formed on a part of the upper surfaces of the n + type semiconductor region 10b and the p + type semiconductor region 11b.
【００２５】このような半導体基板１上には、ゲート電
極８およびサイドウォール９を覆うように、絶縁膜１２
が形成されている。絶縁膜１２は、ゲート電極８間の狭
いスペースを埋め込み可能なリフロー性の高い絶縁膜、
例えばＢＰＳＧ（Boron-doped Phospho Silicate Glas
s）膜などからなる。絶縁膜１２には、コンタクトホー
ル１３が形成されている。コンタクトホール１３の底部
では、半導体基板１の主面の一部、例えばｎ+型の半導
体領域１０ｂおよびｐ+型の半導体領域１１ｂの一部、
やゲート電極８の一部などが露出されている。An insulating film 12 is formed on the semiconductor substrate 1 so as to cover the gate electrodes 8 and the sidewalls 9.
Are formed. The insulating film 12 is a highly reflowable insulating film that can fill a narrow space between the gate electrodes 8.
For example, BPSG (Boron-doped Phospho Silicate Glas
s) Consists of a film. A contact hole 13 is formed in the insulating film 12. At the bottom of the contact hole 13, a part of the main surface of the semiconductor substrate 1, for example, a part of the n + type semiconductor region 10b and a part of the p + type semiconductor region 11b,
Part of the gate electrode 8 and the like are exposed.
【００２６】このコンタクトホール１３内には、タング
ステン（Ｗ）などからなるプラグ１４が形成されてい
る。プラグ１４は、例えば、コンタクトホール１３の内
部を含む絶縁膜１２上にバリア膜として例えば窒化チタ
ン膜１４ａを形成した後、タングステン膜をＣＶＤ（Ch
emical Vapor Deposition）法によって窒化チタン膜１
４ａ上にコンタクトホール１３を埋めるように形成し、
絶縁膜１２上の不要なタングステン膜および窒化チタン
膜１４ａをＣＭＰ（Chemical Mechanical Polishing）
法またはエッチバック法などによって除去することによ
り形成される。A plug 14 made of tungsten (W) or the like is formed in the contact hole 13. For the plug 14, for example, after forming a titanium nitride film 14a as a barrier film on the insulating film 12 including the inside of the contact hole 13, a tungsten film is formed by CVD (Ch
Titanium nitride film 1 by emical vapor deposition method
4a is formed so as to fill the contact hole 13,
The unnecessary tungsten film and titanium nitride film 14a on the insulating film 12 are CMP (Chemical Mechanical Polishing)
It is formed by removing it by the etching method or the etch back method.
【００２７】プラグ１４が埋め込まれた絶縁膜１２上に
は、例えばタングステンなどからなる第１層配線１５が
形成されている。第１層配線１５は、プラグ１４を介し
てｎ型ＭＩＳＦＥＴ５およびｐ型ＭＩＳＦＥＴ６のソー
ス・ドレイン用の半導体領域１０ｂおよび１１ｂやゲー
ト電極８と電気的に接続されている。第１層配線１５
は、タングステンに限定されず種々変更可能であり、例
えばアルミニウム（Ａｌ）またはアルミニウム合金など
の単体膜あるいはこれらの単体膜の上下層の少なくとも
一方にチタン（Ｔｉ）や窒化チタン（ＴｉＮ）などのよ
うな金属膜を形成した積層金属膜としても良い。A first layer wiring 15 made of, for example, tungsten is formed on the insulating film 12 in which the plug 14 is embedded. The first layer wiring 15 is electrically connected via the plug 14 to the source / drain semiconductor regions 10b and 11b of the n-type MISFET 5 and the p-type MISFET 6 and the gate electrode 8. First layer wiring 15
Is not limited to tungsten, but can be variously changed. For example, titanium (Ti), titanium nitride (TiN), etc. can be used as a simple substance film of aluminum (Al) or an aluminum alloy or at least one of upper and lower layers of these simple substance films. It may be a laminated metal film having a different metal film formed thereon.
【００２８】また、絶縁膜１２上には、第１層配線１５
を覆うように、絶縁膜１６が形成されている。絶縁膜１
６は、例えば有機ポリマーまたは有機シリカガラスなど
のような低誘電率材料（いわゆるＬｏｗ−Ｋ絶縁膜、Ｌ
ｏｗ−Ｋ材料）からなる。なお、低誘電率な絶縁膜（Ｌ
ｏｗ−Ｋ絶縁膜）とは、パッシベーション膜に含まれる
酸化シリコン膜（たとえばＴＥＯＳ（Tetraethoxysilan
e）酸化膜）の誘電率よりも低い誘電率を有する絶縁膜
を例示できる。一般的には、ＴＥＯＳ酸化膜の比誘電率
ε＝４．１〜４．２程度以下を低誘電率な絶縁膜と言
う。The first layer wiring 15 is formed on the insulating film 12.
An insulating film 16 is formed so as to cover the. Insulation film 1
6 is a low dielectric constant material such as organic polymer or organic silica glass (so-called Low-K insulating film, L
ow-K material). In addition, a low dielectric constant insulating film (L
An ow-K insulating film is a silicon oxide film (for example, TEOS (Tetraethoxysilan) included in the passivation film.
e) An insulating film having a dielectric constant lower than that of (oxide film) can be exemplified. In general, a TEOS oxide film having a relative dielectric constant ε of about 4.1 to 4.2 or less is called a low dielectric constant insulating film.
【００２９】上記低誘電率材料としての有機ポリマーに
は、例えばＳｉＬＫ（米The Dow Chemical Co製、比誘
電率＝２．７、耐熱温度＝４９０℃以上、絶縁破壊耐圧
＝４．０〜５．０ＭＶ／Ｖｍ）またはポリアリルエーテ
ル（ＰＡＥ）系材料のＦＬＡＲＥ（米Honeywell Electr
onic Materials製、比誘電率＝２．８、耐熱温度＝４０
０℃以上）がある。このＰＡＥ系材料は、基本性能が高
く、機械的強度、熱的安定性および低コスト性に優れる
という特徴を有している。上記低誘電率材料としての有
機シリカガラス（ＳｉＯＣ系材料）には、例えばＨＳＧ
−Ｒ７（日立化成工業製、比誘電率＝２．８、耐熱温度
＝６５０℃）、Ｂｌａｃｋ Ｄｉａｍｏｎｄ（米Applied
Materials，Inc製、比誘電率＝３．０〜２．４、耐熱
温度＝４５０℃）またはｐ−ＭＴＥＳ（日立開発製、比
誘電率＝３．２）がある。この他のＳｉＯＣ系材料に
は、例えばＣＯＲＡＬ（米Novellus Systems,Inc製、比
誘電率＝２．７〜２．４、耐熱温度＝５００℃）、Ａｕ
ｒｏｒａ２．７（日本エー・エス・エム社製、比誘電率
＝２．７、耐熱温度＝４５０℃）がある。Examples of the organic polymer as the low dielectric constant material include SiLK (manufactured by The Dow Chemical Co, USA, relative permittivity = 2.7, heat resistance temperature = 490 ° C. or higher, dielectric breakdown voltage = 4.0 to 5. 0 MV / Vm) or polyallyl ether (PAE) based FLARE (Honeywell Electr
Made by onic Materials, relative permittivity = 2.8, heat resistant temperature = 40
0 ° C or higher). This PAE-based material is characterized by high basic performance and excellent mechanical strength, thermal stability, and low cost. The organic silica glass (SiOC-based material) as the low dielectric constant material is, for example, HSG.
-R7 (manufactured by Hitachi Chemical Co., Ltd., relative permittivity = 2.8, heat resistance temperature = 650 ° C.), Black Diamond (Applied in the US)
Materials, Inc., relative permittivity = 3.0 to 2.4, heat resistance temperature = 450 ° C.) or p-MTES (Hitachi development, relative permittivity = 3.2). Other SiOC materials include, for example, CORAL (manufactured by Novellus Systems, Inc. in the US, relative dielectric constant = 2.7 to 2.4, heat resistance temperature = 500 ° C.), Au.
rora2.7 (manufactured by Nippon ASM Co., Ltd., relative dielectric constant = 2.7, heat resistance temperature = 450 ° C.).
【００３０】また、絶縁膜１６の低誘電率材料には、例
えばＦＳＧ（ＳｉＯＦ系材料）、ＨＳＱ（hydrogen sil
sesquioxane）系材料、ＭＳＱ（methyl silsesquioxan
e）系材料、ポーラスＨＳＱ系材料、ポーラスＭＳＱ材
料またはポーラス有機系材料を用いることもできる。上
記ＨＳＱ系材料には、例えばＯＣＤ Ｔ−１２（東京応
化工業製、比誘電率＝３．４〜２．９、耐熱温度＝４５
０℃）、ＦＯｘ（米DowCorning Corp．製、比誘電率＝
２．９）またはＯＣＬ Ｔ−３２（東京応化工業製、比
誘電率＝２．５、耐熱温度＝４５０℃）などがある。上
記ＭＳＱ系材料には、例えばＯＣＤ Ｔ−９（東京応化
工業製、比誘電率＝２．７、耐熱温度＝６００℃）、Ｌ
ＫＤ−Ｔ２００（ＪＳＲ製、比誘電率＝２．７〜２．
５、耐熱温度＝４５０℃）、ＨＯＳＰ（米Honeywell El
ectronic Materials製、比誘電率＝２．５、耐熱温度＝
５５０℃）、ＨＳＧ−ＲＺ２５（日立化成工業製、比誘
電率＝２．５、耐熱温度＝６５０℃）、ＯＣＬ Ｔ−３
１（東京応化工業製、比誘電率＝２．３、耐熱温度＝５
００℃）またはＬＫＤ−Ｔ４００（ＪＳＲ製、比誘電率
＝２．２〜２、耐熱温度＝４５０℃）などがある。上記
ポーラスＨＳＱ系材料には、例えばＸＬＫ（米Dow Corn
ing Corp．製、比誘電率＝２．５〜２）、ＯＣＬＴ−７
２（東京応化工業製、比誘電率＝２．２〜１．９、耐熱
温度＝４５０℃）、Ｎａｎｏｇｌａｓｓ（米Honeywell
Electronic Materials製、比誘電率＝２．２〜１．８、
耐熱温度＝５００℃以上）またはＭｅｓｏＥＬＫ（米Ai
r Productsand Chemicals,Inc、比誘電率＝２以下）が
ある。上記ポーラスＭＳＱ系材料には、例えばＨＳＧ−
６２１１Ｘ（日立化成工業製、比誘電率＝２．４、耐熱
温度＝６５０℃）、ＡＬＣＡＰ−Ｓ（旭化成工業製、比
誘電率＝２．３〜１．８、耐熱温度＝４５０℃）、ＯＣ
Ｌ Ｔ−７７（東京応化工業製、比誘電率＝２．２〜
１．９、耐熱温度＝６００℃）、ＨＳＧ−６２１０Ｘ
（日立化成工業製、比誘電率＝２．１、耐熱温度＝６５
０℃）またはｓｉｌｉｃａ ａｅｒｏｇｅｌ（神戸製鋼
所製、比誘電率１．４〜１．１）などがある。上記ポー
ラス有機系材料には、例えばＰｏｌｙＥＬＫ（米Air Pr
oductsand Chemicals,Inc、比誘電率＝２以下、耐熱温
度＝４９０℃）などがある。上記ＳｉＯＣ系材料、Ｓｉ
ＯＦ系材料は、例えばＣＶＤ法によって形成されてい
る。例えば上記Ｂｌａｃｋ Ｄｉａｍｏｎｄは、トリメ
チルシランと酸素との混合ガスを用いたＣＶＤ法などに
よって形成される。また、上記ｐ−ＭＴＥＳは、例えば
メチルトリエトキシシランとＮ 2Ｏとの混合ガスを用い
たＣＶＤ法などによって形成される。それ以外の上記低
誘電率の絶縁材料は、例えば塗布法で形成されている。Examples of the low dielectric constant material of the insulating film 16 include
For example, FSG (SiOF based material), HSQ (hydrogen sil
sesquioxane) material, MSQ (methyl silsesquioxan)
e) -based materials, porous HSQ-based materials, porous MSQ materials
Materials or porous organic materials can also be used. Up
The HSQ-based material includes, for example, OCD T-12 (Tokyo
Made by Kako Kogyo Co., Ltd., relative dielectric constant = 3.4 to 2.9, heat resistance temperature = 45
0 ° C.), FOx (manufactured by Dow Corning Corp., US, relative permittivity =
2.9) or OCL T-32 (manufactured by Tokyo Ohka Kogyo, ratio
Dielectric constant = 2.5, heat resistant temperature = 450 ° C.) and the like. Up
Note that MSQ materials include, for example, OCD T-9 (Tokyo Oka
Industrial, relative permittivity = 2.7, heat resistant temperature = 600 ° C), L
KD-T200 (manufactured by JSR, relative dielectric constant = 2.7 to 2.
5, heat-resistant temperature = 450 ℃, HOSP (Honeywell El
Made by ectronic Materials, relative permittivity = 2.5, heat resistance =
550 ° C), HSG-RZ25 (manufactured by Hitachi Chemical Co., Ltd.
Electric constant = 2.5, heat resistance temperature = 650 ° C.), OCL T-3
1 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 2.3, heat resistance temperature = 5)
00 ° C) or LKD-T400 (made by JSR, relative permittivity
= 2.2-2, heat resistant temperature = 450 ° C.) and the like. the above
For porous HSQ materials, for example, XLK (US Dow Corn
ing Corp. Made, relative permittivity = 2.5 to 2), OCLT-7
2 (manufactured by Tokyo Ohka Kogyo, relative permittivity = 2.2 to 1.9, heat resistance
Temperature = 450 ℃, Nanoglass (Honeywell, USA)
Made by Electronic Materials, relative permittivity = 2.2-1.8,
Heat-resistant temperature = 500 ° C or higher) or MesoELK (US Ai)
r Productsand Chemicals, Inc, relative dielectric constant = 2 or less)
is there. Examples of the porous MSQ-based material include HSG-
6211X (manufactured by Hitachi Chemical Co., Ltd., relative permittivity = 2.4, heat resistance)
Temperature = 650 ° C.), ALCAP-S (Made by Asahi Kasei, ratio
Dielectric constant = 2.3 to 1.8, heat resistance temperature = 450 ° C.), OC
LT-77 (manufactured by Tokyo Ohka Kogyo, relative permittivity = 2.2
1.9, heat resistant temperature = 600 ° C.), HSG-6210X
(Hitachi Chemical Co., Ltd., relative permittivity = 2.1, heat resistance temperature = 65
0 ℃) or silica aerogel (Kobe Steel)
Manufactured, relative permittivity 1.4 to 1.1). Above Po
For example, PolyELK (US Air Pr
oductsand Chemicals, Inc, relative permittivity = 2 or less, heat resistant temperature
Degree = 490 ° C.). Said SiOC material, Si
The OF-based material is formed by, for example, the CVD method.
It For example, the above Black Diamond
For CVD method using mixed gas of chillsilane and oxygen
Therefore, it is formed. Moreover, the p-MTES is, for example,
Methyltriethoxysilane and N 2Using mixed gas with O
It is formed by a CVD method or the like. Other than the above
The dielectric material having a dielectric constant is formed by, for example, a coating method.
【００３１】このようなＬｏｗ−Ｋ材料からなる絶縁膜
１６上には、Ｌｏｗ−Ｋキャップ用の絶縁膜１７が形成
されている。この絶縁膜１７は、例えば二酸化シリコン
（ＳｉＯ2）に代表される酸化シリコン（ＳｉＯx）膜か
らなり、例えばＣＭＰ処理時における絶縁膜１６の機械
的強度の確保、表面保護および耐湿性の確保などのよう
な機能を有している。絶縁膜１７の厚さは、絶縁膜１６
よりも相対的に薄く、例えば２５ｎｍ〜１００ｎｍ程度
である。ただし、絶縁膜１７は、酸化シリコン膜に限定
されるものではなく種々変更可能である。絶縁膜１７と
して、例えば窒化シリコン（ＳｉxＮy）膜、炭化シリコ
ン（ＳｉＣ）膜または炭窒化シリコン（ＳｉＣＮ）膜を
用いても良い。これら窒化シリコン膜、炭化シリコン膜
または炭窒化シリコン膜は、例えばプラズマＣＶＤ法に
よって形成することができる。プラズマＣＶＤ法で形成
された炭化シリコン膜としては、例えばＢＬＯｋ（ＡＭ
ＡＴ社製、比誘電率＝４．３）がある。その形成に際し
ては、例えばトリメチルシランとヘリウム（または
Ｎ2、ＮＨ3）との混合ガスを用いる。このような絶縁膜
１６および１７には、第１層配線１５の一部が露出する
ビアまたはスルーホール１８が形成されている。このス
ルーホール１８内には、例えばタングステンなどからな
るプラグ１９が埋め込まれている。An insulating film 17 for a Low-K cap is formed on the insulating film 16 made of such a Low-K material. The insulating film 17 is made of, for example, a silicon oxide (SiO x ) film typified by silicon dioxide (SiO 2 ). For example, the mechanical strength of the insulating film 16 during CMP processing, surface protection, and moisture resistance are ensured. It has the following functions. The thickness of the insulating film 17 is
It is relatively thinner than the above, for example, about 25 nm to 100 nm. However, the insulating film 17 is not limited to the silicon oxide film and can be variously modified. As the insulating film 17, for example, a silicon nitride (Si x N y ) film, a silicon carbide (SiC) film or a silicon carbonitride (SiCN) film may be used. These silicon nitride film, silicon carbide film or silicon carbonitride film can be formed by, for example, a plasma CVD method. The silicon carbide film formed by the plasma CVD method is, for example, BLOk (AM
There is a dielectric constant = 4.3) manufactured by AT company. At the time of formation, a mixed gas of trimethylsilane and helium (or N 2 , NH 3 ) is used, for example. Vias or through holes 18 through which a part of the first layer wiring 15 is exposed are formed in such insulating films 16 and 17. A plug 19 made of, for example, tungsten is embedded in the through hole 18.
【００３２】図３〜５は、図２に続く半導体装置の製造
工程中における要部断面図を示している。なお、理解を
簡単にするために、図３〜５では、図２の絶縁膜１７よ
り下の構造に対応する部分は図示を省略している。3 to 5 are sectional views of the essential part in the manufacturing process of the semiconductor device, following FIG. Note that, for easy understanding, in FIGS. 3 to 5, portions corresponding to the structure below the insulating film 17 in FIG. 2 are not shown.
【００３３】まず、本実施の形態においては、図３に示
されるように、プラグ１９が埋め込まれた絶縁膜１７上
に絶縁膜２０をプラズマＣＶＤ法などによって形成す
る。絶縁膜２０は、例えばプラズマＣＶＤ法によって形
成された窒化シリコン膜からなり、その厚さは、例えば
２５ｎｍ〜５０ｎｍ程度である。絶縁膜２０の他の材料
として、例えばプラズマＣＶＤ法で形成された炭化シリ
コン膜、プラズマＣＶＤ法で形成されたＳｉＣＮ膜また
はプラズマＣＶＤ法で形成された酸窒化シリコン（Ｓｉ
ＯＮ）膜の単体膜を用いても良い。これらの膜を用いた
場合、窒化シリコン膜に比べて誘電率を大幅に下げるこ
とができるので、配線容量を低減することができ、半導
体装置の動作速度を向上させることができる。プラズマ
ＣＶＤ法で形成された炭化シリコン膜には、例えば上記
ＢＬＯｋ（ＡＭＡＴ社製）がある。また、ＳｉＣＮ膜の
成膜に際しては、例えばヘリウム（Ｈｅ）と、アンモニ
ア（ＮＨ3）と、トリメチルシラン（３ＭＳ）との混合
ガスが用いられる。また、プラズマＣＶＤ法で形成され
た酸窒化シリコン膜としては、例えばＰＥ−ＴＭＳ（Ｃ
ａｎｏｎ製、誘電率＝３．９）があり、その形成に際し
ては、例えばトリメトキシシラン（ＴＭＳ）ガスと酸化
窒素（Ｎ2Ｏ）ガスとの混合ガスが用いられる。First, in the present embodiment, as shown in FIG. 3, the insulating film 20 is formed on the insulating film 17 in which the plug 19 is embedded by the plasma CVD method or the like. The insulating film 20 is made of, for example, a silicon nitride film formed by a plasma CVD method, and its thickness is, for example, about 25 nm to 50 nm. As another material of the insulating film 20, for example, a silicon carbide film formed by a plasma CVD method, a SiCN film formed by a plasma CVD method, or a silicon oxynitride (Si formed by a plasma CVD method is used.
A single film of (ON) film may be used. When these films are used, the dielectric constant can be significantly reduced as compared with the silicon nitride film, so that the wiring capacitance can be reduced and the operation speed of the semiconductor device can be improved. The silicon carbide film formed by the plasma CVD method includes, for example, the above BLOk (manufactured by AMAT). Further, in forming the SiCN film, for example, a mixed gas of helium (He), ammonia (NH 3 ) and trimethylsilane (3MS) is used. As the silicon oxynitride film formed by the plasma CVD method, for example, PE-TMS (C
manufactured by Anon, has a dielectric constant of 3.9), and when forming it, for example, a mixed gas of trimethoxysilane (TMS) gas and nitric oxide (N 2 O) gas is used.
【００３４】次に、絶縁膜２０上に絶縁膜２１を形成す
る。絶縁膜２１は、後述するように、還元性プラズマ処
理、例えばＮＨ3（アンモニア）プラズマ処理またはＮ2
／Ｈ 2プラズマ処理によってエッチングされ得る材料か
らなることが好ましい。このため、絶縁膜２１は、例え
ば上記Ｌｏｗ−Ｋ材料を用いることができる。しかしな
がら、絶縁膜２１は、最終的には除去されるので、誘電
率が低い必要はなく、Ｌｏｗ−Ｋ材料以外の材料を用い
ることもできる。Next, the insulating film 21 is formed on the insulating film 20.
It The insulating film 21 is treated with a reducing plasma as described later.
Reason, eg NH3(Ammonia) plasma treatment or N2
/ H 2Material that can be etched by plasma treatment
It is preferable that Therefore, the insulating film 21 is, for example,
For example, the above Low-K material can be used. But
However, since the insulating film 21 is finally removed, the dielectric film 21
It is not necessary that the rate is low, and materials other than Low-K materials are used.
You can also do it.
【００３５】次に、絶縁膜２１上に絶縁膜２２を形成す
る。絶縁膜２２は、例えば、窒化シリコン膜、炭化シリ
コン膜または炭窒化シリコン膜とその上の酸化シリコン
膜との２層からなる積層膜である。理解を簡単にするた
めに、図中では、絶縁膜２２は単層として示している。
また、絶縁膜２２を上記材料のいずれかの単体膜とする
こともできる。Next, the insulating film 22 is formed on the insulating film 21. The insulating film 22 is, for example, a laminated film composed of two layers of a silicon nitride film, a silicon carbide film or a silicon carbonitride film and a silicon oxide film thereon. To facilitate understanding, the insulating film 22 is shown as a single layer in the drawing.
Alternatively, the insulating film 22 may be a single film of any of the above materials.
【００３６】次に、図３に示すように、絶縁膜２２上に
反射防止膜２３ａおよびフォトレジスト膜を順に形成
し、露光によりフォトレジスト膜をパターン化してフォ
トレジストパターン２３ｂを形成する。そして、フォト
レジストパターン２３ｂをエッチングマスクにしたドラ
イエッチング法により、反射防止膜２３ａを選択的に除
去する。その後、フォトレジストパターン２３ｂをエッ
チングマスクにしたドライエッチング法により、絶縁膜
２２を選択的に除去し、開口部を形成する。それから、
絶縁膜２２の開口部から露出する絶縁膜２１をＮＨ3プ
ラズマ処理またはＮ2／Ｈ2プラズマ処理などによってエ
ッチングしながら、フォトレジストパターン２３ｂおよ
び反射防止膜２３ａをアッシングして除去する。そし
て、絶縁膜２１および２２の開口部から露出する絶縁膜
２０をドライエッチングによって除去する。これによ
り、図４に示されように、開口部または配線溝２４が形
成される。配線溝２４の底面からはプラグ１９の上面が
露出される。なお、フォトレジストパターン２３ｂをエ
ッチングマスクにしたドライエッチング法により、絶縁
膜２０、２１および２２を選択的に除去し、開口部また
は配線溝２４を形成した後、フォトレジストパターン２
３ｂおよび反射防止膜２３ａを除去することもできる。Next, as shown in FIG. 3, an antireflection film 23a and a photoresist film are sequentially formed on the insulating film 22, and the photoresist film is patterned by exposure to form a photoresist pattern 23b. Then, the antireflection film 23a is selectively removed by a dry etching method using the photoresist pattern 23b as an etching mask. After that, the insulating film 22 is selectively removed by a dry etching method using the photoresist pattern 23b as an etching mask to form an opening. then,
The photoresist pattern 23b and the antireflection film 23a are removed by ashing while etching the insulating film 21 exposed from the opening of the insulating film 22 by NH 3 plasma treatment or N 2 / H 2 plasma treatment. Then, the insulating film 20 exposed from the openings of the insulating films 21 and 22 is removed by dry etching. Thereby, as shown in FIG. 4, the opening or the wiring groove 24 is formed. The upper surface of the plug 19 is exposed from the bottom surface of the wiring groove 24. The insulating films 20, 21 and 22 are selectively removed by a dry etching method using the photoresist pattern 23b as an etching mask to form an opening or a wiring groove 24, and then the photoresist pattern 2 is formed.
It is also possible to remove 3b and the antireflection film 23a.
【００３７】次に、基板１の主面上の全面に、例えば窒
化チタン（ＴｉＮ）などからなる厚さ５０ｎｍ程度の薄
い導電性バリア膜（第１導体膜）２５ａをスパッタリン
グ法などを用いて形成する。導電性バリア膜２５ａは、
例えば後述の主導体膜形成用の銅の拡散を防止する機能
および主導体膜のリフロー時に銅の濡れ性を向上させる
機能などを有している。このような導電性バリア膜２５
ａの材料としては、窒化チタンに代えて、銅と殆ど反応
しない窒化タングステン（ＷＮ）または窒化タンタル
（ＴａＮ）などのような高融点金属窒化物を用いること
もできる。また、導電性バリア膜２５ａの材料として、
高融点金属窒化物にシリコン（Ｓｉ）を添加した材料
や、銅と反応し難いタンタル（Ｔａ）、チタン（Ｔ
ｉ）、タングステン（Ｗ）、チタンタングステン（Ｔｉ
Ｗ）合金などのような高融点金属を用いることもでき
る。Next, a thin conductive barrier film (first conductor film) 25a made of, for example, titanium nitride (TiN) and having a thickness of about 50 nm is formed on the entire main surface of the substrate 1 by sputtering or the like. To do. The conductive barrier film 25a is
For example, it has a function of preventing diffusion of copper for forming a main conductor film, which will be described later, and a function of improving wettability of copper during reflow of the main conductor film. Such a conductive barrier film 25
As a material of a, a refractory metal nitride such as tungsten nitride (WN) or tantalum nitride (TaN) which hardly reacts with copper can be used instead of titanium nitride. In addition, as a material of the conductive barrier film 25a,
A material obtained by adding silicon (Si) to a refractory metal nitride, tantalum (Ta) or titanium (T) that does not easily react with copper.
i), tungsten (W), titanium tungsten (Ti
It is also possible to use refractory metals such as W) alloys.
【００３８】続いて、導電性バリア膜２５ａ上に、例え
ば厚さ８００〜１６００ｎｍ程度の相対的に厚い銅から
なる主導体膜（第２導体膜）２５ｂを形成する。主導体
膜２５ｂは、例えばＣＶＤ法、スパッタリング法または
めっき法などを用いて形成することができる。その後、
例えば４７５℃程度の非酸化性雰囲気（例えば水素雰囲
気）中において基板１に対して熱処理を施すことにより
主導体膜２５ｂをリフローさせ、銅を配線溝２４の内部
に隙間なく埋め込む。Subsequently, a main conductor film (second conductor film) 25b made of relatively thick copper having a thickness of about 800 to 1600 nm, for example, is formed on the conductive barrier film 25a. The main conductor film 25b can be formed by using, for example, a CVD method, a sputtering method, a plating method, or the like. afterwards,
For example, the main conductor film 25b is reflowed by heat-treating the substrate 1 in a non-oxidizing atmosphere (for example, hydrogen atmosphere) at about 475 ° C., and copper is embedded in the wiring groove 24 without any space.
【００３９】次に、主導体膜２５ｂ、導電性バリア膜２
５ａおよび絶縁膜２２をＣＭＰ法によって、絶縁膜２１
の上面が露出するまで研磨する。これにより、図５に示
すように、相対的に薄い導電性バリア膜２５ａと相対的
に厚い主導体膜２５ｂとからなる第２層配線（配線）２
５を配線溝２４内に形成する。第２層配線２５は、プラ
グ１９を介して第１層配線１５と電気的に接続されてい
る。Next, the main conductor film 25b and the conductive barrier film 2 are formed.
5a and the insulating film 22 by the CMP method.
Polish until the top surface of is exposed. As a result, as shown in FIG. 5, the second layer wiring (wiring) 2 including the relatively thin conductive barrier film 25a and the relatively thick main conductor film 25b.
5 is formed in the wiring groove 24. The second layer wiring 25 is electrically connected to the first layer wiring 15 via the plug 19.
【００４０】図６は、図５に続く半導体装置の製造工程
中における図１に対応する領域の要部平面図を示し、図
７は図６のＡ−Ａ断面図である。なお、図７において
も、図２の絶縁膜１７より下の構造に対応する部分は図
示を省略している。FIG. 6 is a plan view of an essential part of a region corresponding to FIG. 1 during the manufacturing process of the semiconductor device following FIG. 5, and FIG. 7 is a sectional view taken along line AA of FIG. Note that, also in FIG. 7, a portion corresponding to the structure below the insulating film 17 in FIG. 2 is omitted.
【００４１】配線溝２４内に第２層配線（配線）２５を
形成した後、半導体基板１をプラズマＣＶＤ装置の処理
室内に配置し、アンモニアガスを導入してプラズマ電源
を印加することにより、基板１（特に第２層配線２５が
露出するＣＭＰ面）に対して、アンモニア（ＮＨ3）プ
ラズマ処理を施す。あるいは、Ｎ2ガスおよびＨ2ガスを
導入して、Ｎ2／Ｈ2プラズマ処理を施す。このような還
元性プラズマ処理により、ＣＭＰで酸化された銅配線表
面の酸化銅（ＣｕＯ、ＣｕＯ2）を銅（Ｃｕ）に還元
し、更に、窒化銅（ＣｕＮ）層が第２層配線２５の表面
（ごく薄い領域）に形成される。また、このプラズマ処
理によって、第２層配線２５間の絶縁膜２１がエッチン
グされ除去される。これにより、図６および図７に示さ
れる構造が得られる。従って、第２層配線２５を形成す
るために用いられた絶縁膜２１は、導電性バリア膜２５
ａおよび銅からなる主導体膜２５ｂに悪影響を与えない
ような処理、例えば還元性プラズマ処理、によって簡単
にエッチングされ得る材料を用いることが好ましい。酸
素プラズマ処理によって絶縁膜２１を除去する場合は、
第２層配線２５の上面の銅が酸化されてしまうので、第
２層配線２５の上面上に導電性バリア膜を選択的に形成
しておく必要がある。また、第２層配線２５は、その平
面形状が、図６に示すように、例えば帯状に形成されて
いる。After the second layer wiring (wiring) 25 is formed in the wiring groove 24, the semiconductor substrate 1 is placed in the processing chamber of the plasma CVD apparatus, ammonia gas is introduced, and a plasma power source is applied, whereby Ammonia (NH 3 ) plasma treatment is applied to 1 (particularly the CMP surface where the second layer wiring 25 is exposed). Alternatively, N 2 gas and H 2 gas are introduced to perform N 2 / H 2 plasma treatment. By such a reducing plasma treatment, the copper oxide (CuO, CuO 2 ) on the surface of the copper wiring oxidized by CMP is reduced to copper (Cu), and the copper nitride (CuN) layer forms the second layer wiring 25. Formed on the surface (thin area). Further, the insulating film 21 between the second layer wirings 25 is etched and removed by this plasma treatment. As a result, the structure shown in FIGS. 6 and 7 is obtained. Therefore, the insulating film 21 used for forming the second layer wiring 25 is the conductive barrier film 25.
It is preferable to use a material that can be easily etched by a treatment that does not adversely affect the main conductor film 25b made of a and copper, for example, a reducing plasma treatment. When removing the insulating film 21 by oxygen plasma treatment,
Since copper on the upper surface of the second layer wiring 25 is oxidized, it is necessary to selectively form a conductive barrier film on the upper surface of the second layer wiring 25. The second-layer wiring 25 has a planar shape, for example, in the shape of a band, as shown in FIG.
【００４２】なお、プラズマ処理とは、プラズマ状態に
ある環境に、基板表面、あるいは、基板上に絶縁膜、金
属膜等のような部材が形成されている時にはその部材表
面を暴露し、プラズマの化学的、機械的（ボンバードメ
ント）作用を表面に与えて処理することをいう。また、
還元性雰囲気のプラズマとは、還元作用、すなわち、酸
素を引き抜く作用を有するラジカル、イオン、原子、分
子等の反応種が支配的に存在するプラズマ環境をいう。The plasma treatment means exposing the surface of the substrate to the environment in a plasma state, or when a member such as an insulating film or a metal film is formed on the substrate, exposing the surface of the member. It is a treatment that gives a chemical or mechanical (bombardment) action to the surface. Also,
The plasma in a reducing atmosphere refers to a plasma environment in which reactive species such as radicals, ions, atoms, and molecules having a reducing action, that is, an action of extracting oxygen are predominantly present.
【００４３】図８は、図７に続く半導体装置の製造工程
中における要部断面図を示している。なお、図８におい
ても、図２の絶縁膜１７より下の構造に対応する部分は
図示を省略している。FIG. 8 is a cross-sectional view of essential parts in the manufacturing process of the semiconductor device, following FIG. Note that, also in FIG. 8, portions corresponding to the structure below the insulating film 17 in FIG. 2 are omitted.
【００４４】絶縁膜２１が除去された後、洗浄を行い、
その後、図８に示すように、半導体基板１の主面の全面
上に絶縁膜２６をプラズマＣＶＤ法などによって形成す
る。すなわち、第２層配線２５の上面および側面を覆う
ように、絶縁膜２６を絶縁膜２０上に形成する。絶縁膜
２６は、例えば窒化シリコン膜からなり、銅配線のバリ
ア絶縁膜として機能する。従って、絶縁膜２６は、第２
層配線２５の主導体膜２５ｂ中の銅が、後で形成される
層間絶縁膜２８中に拡散するのを抑制または防止する。
絶縁膜２６の他の材料として、例えば炭化シリコン（Ｓ
ｉＣ）膜、炭窒化シリコン（ＳｉＣＮ）膜または酸窒化
シリコン（ＳｉＯＮ）膜の単体膜を用いても良い。これ
らの膜を用いた場合、窒化シリコン膜に比べて誘電率を
大幅に下げることができるので、配線容量を低減するこ
とができ、半導体装置の動作速度を向上させることがで
きる。プラズマＣＶＤ法で形成された炭化シリコン膜に
は、例えばＢＬＯｋ（ＡＭＡＴ社製）がある。その成膜
ガスは、上記した通りである。上記ＳｉＣＮ膜の成膜に
際しては、例えばヘリウム（Ｈｅ）と、アンモニア（Ｎ
Ｈ3）と、トリメチルシラン（３ＭＳ）との混合ガスを
用いる。また、上記プラズマＣＶＤ法で形成された酸窒
化シリコン膜としては、例えばＰＥ−ＴＭＳ（Ｃａｎｏ
ｎ製、誘電率＝３．９）がある。上記酸窒化シリコン膜
の形成に際しては、例えばトリメトキシシラン（ＴＭ
Ｓ）ガスと酸化窒素（Ｎ2Ｏ）ガスとの混合ガスを用い
る。After the insulating film 21 is removed, cleaning is performed,
After that, as shown in FIG. 8, an insulating film 26 is formed on the entire main surface of the semiconductor substrate 1 by a plasma CVD method or the like. That is, the insulating film 26 is formed on the insulating film 20 so as to cover the upper surface and the side surface of the second layer wiring 25. The insulating film 26 is made of, for example, a silicon nitride film and functions as a barrier insulating film for copper wiring. Therefore, the insulating film 26 is
Copper in the main conductor film 25b of the layer wiring 25 is suppressed or prevented from diffusing into the interlayer insulating film 28 formed later.
As another material of the insulating film 26, for example, silicon carbide (S
An iC) film, a silicon carbonitride (SiCN) film, or a silicon oxynitride (SiON) film may be used alone. When these films are used, the dielectric constant can be significantly reduced as compared with the silicon nitride film, so that the wiring capacitance can be reduced and the operation speed of the semiconductor device can be improved. The silicon carbide film formed by the plasma CVD method includes, for example, BLOk (manufactured by AMAT). The film forming gas is as described above. When forming the SiCN film, for example, helium (He) and ammonia (N
A mixed gas of H 3 ) and trimethylsilane (3MS) is used. The silicon oxynitride film formed by the plasma CVD method is, for example, PE-TMS (Cano).
manufactured by N, dielectric constant = 3.9). When forming the silicon oxynitride film, for example, trimethoxysilane (TM
A mixed gas of S) gas and nitric oxide (N 2 O) gas is used.
【００４５】本実施の形態においては、最近接配線間
（最小隣接配線間、最小ピッチ配線間）のカバレージが
オーバーハングするような条件で、すなわち、最近接配
線間では絶縁膜２６がコンフォーマルには成膜されない
条件で、絶縁膜２６を成膜する。ここで、最近接配線と
は、同層配線において隣接する配線同士の間隔（隣接配
線間距離）が最小である配線に対応する。最近接配線間
では、寄生容量の低減がより重要である。In this embodiment, the insulating film 26 is conformal under the condition that the coverage between the closest wirings (between the minimum adjacent wirings and between the minimum pitch wirings) is overhung, that is, between the closest wirings. The insulating film 26 is formed under the condition that is not formed. Here, the closest wiring corresponds to a wiring having a minimum distance between adjacent wirings (distance between adjacent wirings) in the same layer wiring. It is more important to reduce the parasitic capacitance between the closest wirings.
【００４６】隣接配線間では、絶縁膜２６の堆積が進行
するに従って、対向する配線側面（配線対向面）の上部
２５ｃ近傍での堆積物に遮られて徐々に反応種が下方に
入り込みにくくなる。このため、対向する配線側面の下
部２５ｄ近傍での堆積速度は上部２５ｃ近傍での堆積速
度に比べて小さくなる。従って、対向する配線側面上に
堆積された絶縁膜２６の厚みは、均一にはならず、上部
２５ｃ近傍での厚みが下部２５ｄ近傍よりも厚くなる。
このような現象は、第２層配線２５の最近接配線間、す
なわち第２層配線２５のうちの最も近接した配線同士の
間では、より顕著である。Between the adjacent wirings, as the insulating film 26 is deposited, the reactive species are gradually less likely to enter downward as they are blocked by deposits in the vicinity of the upper portion 25c of the opposing wiring side surface (wiring facing surface). Therefore, the deposition rate in the vicinity of the lower portion 25d of the opposing wiring side surface becomes smaller than the deposition rate in the vicinity of the upper portion 25c. Therefore, the thickness of the insulating film 26 deposited on the opposing side surfaces of the wiring is not uniform, and the thickness in the vicinity of the upper portion 25c is larger than that in the vicinity of the lower portion 25d.
Such a phenomenon is more remarkable between the closest wirings of the second layer wirings 25, that is, between the closest wirings of the second layer wirings 25.
【００４７】このため、第２層配線２５の最近接配線間
では、絶縁膜２６は第２層配線２５の形状を反映したコ
ンフォーマルな形状にはならず、図８に示されるような
溝またはくぼみ部分２７ａが生じる。絶縁膜２６のくぼ
み部分２７ａの上方開口部２７ｂの寸法は、くぼみ部分
２７ａの内部の寸法よりも小さい。すなわち、上方開口
部２７ｂ近傍において、絶縁膜２６のくぼみ部分２７ａ
の対向する内壁（絶縁膜２６表面）は、上方開口部２７
ｂに近づくにつれて徐々に狭まっている。なお、図８に
おいては、くぼみ部分２７ａの断面形状は、模式的に示
されているに過ぎず、くぼみ部分２７ａは、略楕円形な
ど種々の断面形状を有することができる。また、くぼみ
部分２７ａの上方開口部２７ｂが閉じるまで絶縁膜２６
の成膜を行ってもよい。また、くぼみ部分２７ａの上方
開口部２７ｂおよび図示しない側方（図８の紙面に垂直
な方向）開口部が閉じるまで絶縁膜２６の成膜を行い、
図９に示されるように、第２層配線２５の最近接配線間
の絶縁膜２６中に絶縁膜２６の材料が存在しない空隙ま
たはボイド（void）２７ｃを形成してもよい。従って、
本実施の形態では、第２層配線２５の最近接配線間を絶
縁膜２６の材料で完全に満たすことはない。Therefore, between the closest wirings of the second layer wiring 25, the insulating film 26 does not have a conformal shape reflecting the shape of the second layer wiring 25, and a groove or a groove as shown in FIG. The hollow portion 27a is formed. The size of the upper opening 27b of the recessed portion 27a of the insulating film 26 is smaller than the size of the inside of the recessed portion 27a. That is, in the vicinity of the upper opening 27b, the recess 27a of the insulating film 26 is formed.
The inner walls (the surface of the insulating film 26) facing each other of the upper opening 27
It gradually narrows as it approaches b. In addition, in FIG. 8, the cross-sectional shape of the recessed portion 27a is only schematically shown, and the recessed portion 27a can have various cross-sectional shapes such as a substantially elliptical shape. In addition, the insulating film 26 is closed until the upper opening 27b of the recess 27a is closed.
May be formed. Further, the insulating film 26 is formed until the upper opening 27b of the recess 27a and the side opening (direction perpendicular to the paper surface of FIG. 8) not shown are closed.
As shown in FIG. 9, a void or void 27c in which the material of the insulating film 26 does not exist may be formed in the insulating film 26 between the closest wirings of the second layer wiring 25. Therefore,
In the present embodiment, the material of the insulating film 26 does not completely fill the space between the closest wirings of the second layer wiring 25.
【００４８】また、絶縁膜２６の成膜には、プラズマＣ
ＶＤ法などを用いることができ、絶縁膜２６の成膜条件
を調整することなどにより、上述のようなくぼみ部分２
７ａを最近接配線間に容易に形成することができる。第
２層配線２５を逆テーパ状に形成する必要はない。この
ため、第２層配線２５の上端部への電界集中を緩和する
ことができる。Plasma C is used for forming the insulating film 26.
A VD method or the like can be used, and by adjusting the film forming conditions of the insulating film 26, the recessed portion 2 as described above can be formed.
7a can be easily formed between the closest wirings. It is not necessary to form the second layer wiring 25 in an inverse tapered shape. Therefore, electric field concentration on the upper end of the second layer wiring 25 can be relaxed.
【００４９】また、本実施の形態では、第２層配線２５
の上面および側面をバリア絶縁膜としての絶縁膜２６で
覆うので、第２層配線２５において導電性バリア膜２５
ａを省略し、銅からなる主導体膜２５ｂだけで第２層配
線２５を形成することもできる。In the present embodiment, the second layer wiring 25 is used.
Since the upper surface and the side surface of the second layer wiring 25 are covered with the insulating film 26 as a barrier insulating film,
It is also possible to omit the a and form the second-layer wiring 25 only with the main conductor film 25b made of copper.
【００５０】図１０〜１９は、図８に続く半導体装置の
製造工程中における要部断面図を示している。なお、図
１０〜１９においても、図２の絶縁膜１７より下の構造
に対応する部分は図示を省略している。10 to 19 are sectional views of the essential part in the manufacturing process of the semiconductor device, following FIG. 10 to 19, parts corresponding to the structure below the insulating film 17 in FIG. 2 are omitted.
【００５１】絶縁膜２６を形成した後、絶縁膜２８を絶
縁膜２６上に形成する。本実施の形態では、図１０に示
すように、絶縁膜２８の材料が最近接配線間を完全には
埋めないように、すなわちくぼみ部分２７ａを完全には
埋めないように、絶縁膜２８を形成する。絶縁膜２８
は、絶縁膜１６と同様の材料、すなわちＬｏｗ−Ｋ材料
からなる。上述のように、絶縁膜２６のくぼみ部分２７
ａの上方開口部２７ｂの寸法は、くぼみ部分２７ａの内
部の寸法よりも小さい。このため、絶縁膜２８を例えば
塗布法で形成するとき、第２層配線２５の最近接配線間
のくぼみ部分２７ａの内部には絶縁膜２８の材料が、そ
の表面張力などのために、ほとんど入り込まない。従っ
て、絶縁膜２８が形成された段階で、第２層配線２５の
最近接配線間には、絶縁膜２６および２８の材料が存在
しない空隙またはボイド２７が形成される。ボイド２７
は絶縁膜２６および２８の材料によって囲まれた空間で
あり、その内部は真空であっても、あるいは絶縁膜２８
の成膜雰囲気の気体成分などが存在していても良い。一
方、第２層配線２５の隣接配線間距離が大きな領域で
は、絶縁膜２８の材料が第２層配線２５間を容易に埋
め、ボイド２７は形成されない。このため、機械的強度
を維持することが可能となる。After forming the insulating film 26, the insulating film 28 is formed on the insulating film 26. In the present embodiment, as shown in FIG. 10, the insulating film 28 is formed so that the material of the insulating film 28 does not completely fill the space between the closest wirings, that is, the hollow portion 27a is not completely filled. To do. Insulation film 28
Is made of the same material as the insulating film 16, that is, a Low-K material. As described above, the recessed portion 27 of the insulating film 26
The size of the upper opening 27b of a is smaller than the size of the inside of the recessed portion 27a. For this reason, when the insulating film 28 is formed by, for example, a coating method, the material of the insulating film 28 almost enters into the recessed portions 27a between the closest wirings of the second layer wiring 25 due to its surface tension. Absent. Therefore, when the insulating film 28 is formed, a void or void 27 in which the material of the insulating films 26 and 28 does not exist is formed between the closest wirings of the second layer wiring 25. Void 27
Is a space surrounded by the materials of the insulating films 26 and 28, and the inside thereof is vacuum, or the insulating film 28
The gas component of the film forming atmosphere may be present. On the other hand, in the region where the distance between the adjacent wirings of the second layer wiring 25 is large, the material of the insulating film 28 easily fills the space between the second layer wirings 25, and the void 27 is not formed. Therefore, it becomes possible to maintain the mechanical strength.
【００５２】また、絶縁膜２８をＣＶＤ法で形成する場
合も、第２層配線２５の最近接配線間の絶縁膜２６のく
ぼみ部分２７ａの内部には反応種が入り込みにくい。こ
のため、絶縁膜２６のくぼみ部分２７ａ内には絶縁膜２
８の材料がほとんど堆積されず、第２層配線２５の最近
接配線間にボイド２７が形成される。Also, when the insulating film 28 is formed by the CVD method, it is difficult for reactive species to enter into the recessed portions 27a of the insulating film 26 between the closest wirings of the second layer wiring 25. Therefore, the insulating film 2 is not formed in the recess 27a of the insulating film 26.
The material of No. 8 is hardly deposited, and the void 27 is formed between the closest wirings of the second layer wiring 25.
【００５３】なお、図１０は、図８のように第２層配線
２５の最近接配線間の絶縁膜２６にくぼみ２７ａが形成
されている状態で絶縁膜２８を絶縁膜２６上に形成した
場合について図示している。図９のように第２層配線２
５の最近接配線間の絶縁膜２６中にボイド２７ｃが形成
されている場合は、絶縁膜２６中のボイド２７ｃに絶縁
膜２８の材料が侵入することなく、絶縁膜２６上に絶縁
膜２８が形成される。これにより、第２層配線２５の最
近接配線間に、絶縁膜２６および２８の材料が存在しな
い空隙またはボイド２７が形成される。FIG. 10 shows a case where the insulating film 28 is formed on the insulating film 26 in the state where the recess 27a is formed in the insulating film 26 between the closest wirings of the second layer wiring 25 as shown in FIG. Is illustrated. Second layer wiring 2 as shown in FIG.
When the void 27c is formed in the insulating film 26 between the closest wirings of No. 5, the material of the insulating film 28 does not enter the void 27c in the insulating film 26, and the insulating film 28 is formed on the insulating film 26. It is formed. As a result, voids or voids 27 in which the materials of the insulating films 26 and 28 do not exist are formed between the closest wirings of the second layer wiring 25.
【００５４】また、上層配線（後述する第３層配線３
８）と下層配線（第２層配線）との間の寄生容量を低減
するために、絶縁膜２８を上記Ｌｏｗ−Ｋ材料を用いて
形成することが好ましいが、例えばＣＶＤ法で形成した
酸化シリコン膜などによって絶縁膜２８を形成すること
もできる。ただし、上層配線と下層配線との間の寄生容
量を低減するために、絶縁膜２８の誘電率は絶縁膜２６
の誘電率よりも低いことが好ましい。Further, the upper layer wiring (third layer wiring 3 described later)
8) and the lower layer wiring (second layer wiring) to reduce the parasitic capacitance, it is preferable to form the insulating film 28 by using the above-mentioned Low-K material. For example, silicon oxide formed by the CVD method. The insulating film 28 can also be formed of a film or the like. However, in order to reduce the parasitic capacitance between the upper layer wiring and the lower layer wiring, the dielectric constant of the insulating film 28 is set to the insulating film 26.
It is preferably lower than the dielectric constant of.
【００５５】次に、図１１に示されるように、絶縁膜２
８上に絶縁膜２９および３０をＣＶＤ法などを用いて順
に形成する。絶縁膜２９は、例えば窒化シリコン膜から
なり、絶縁膜３０は、例えば酸化シリコン膜からなる。
必要に応じてＣＭＰ処理を行い、絶縁膜３０の上面を平
坦化する。絶縁膜２９の他の材料として、例えば炭化シ
リコン膜またはＳｉＣＮ膜を用いても良い。また、絶縁
膜３０の他の材料として、例えばＰＥ−ＴＭＳ（Ｃａｎ
ｏｎ製、誘電率＝３．９）などの酸窒化シリコン（Ｓｉ
ＯＮ）膜を用いることができ、場合によっては、絶縁膜
３０は形成しなくともよい。Next, as shown in FIG. 11, the insulating film 2
Insulating films 29 and 30 are sequentially formed on 8 by a CVD method or the like. The insulating film 29 is made of, for example, a silicon nitride film, and the insulating film 30 is made of, for example, a silicon oxide film.
If necessary, CMP processing is performed to planarize the upper surface of the insulating film 30. As another material of the insulating film 29, for example, a silicon carbide film or a SiCN film may be used. Further, as another material of the insulating film 30, for example, PE-TMS (Can
On, silicon oxynitride (Si = 3.9), etc. (Si
(ON) film can be used, and in some cases, the insulating film 30 may not be formed.
【００５６】次に、絶縁膜３０上に、絶縁膜３１を形成
する。絶縁膜３１は、絶縁膜２１と同様の材料、すなわ
ち還元性プラズマ処理によってエッチングされ得る材料
からなることが好ましい。Next, the insulating film 31 is formed on the insulating film 30. The insulating film 31 is preferably made of the same material as the insulating film 21, that is, a material that can be etched by the reducing plasma treatment.
【００５７】次に、絶縁膜３１上に、絶縁膜３２および
３３を順に形成する。絶縁膜３２は、絶縁膜２２と同様
の材料から形成することができる。絶縁膜３３は、例え
ば窒化シリコン膜からなる。また、絶縁膜３３の他の材
料として、例えば炭化シリコン膜またはＳｉＣＮ膜を用
いても良い。Next, the insulating films 32 and 33 are sequentially formed on the insulating film 31. The insulating film 32 can be formed of the same material as the insulating film 22. The insulating film 33 is made of, for example, a silicon nitride film. Further, as the other material of the insulating film 33, for example, a silicon carbide film or a SiCN film may be used.
【００５８】次に、絶縁膜３３上に反射防止膜３４ａお
よびフォトレジスト膜を順に形成し、露光によりフォト
レジスト膜をパターン化してフォトレジストパターン３
４ｂを形成する。これにより、図１１に示される構造が
得られる。それから、フォトレジストパターン３４ｂを
エッチングマスクにしたドライエッチング法により、反
射防止膜３４ａを選択的に除去する。その後、フォトレ
ジストパターン３４ｂをエッチングマスクにしたドライ
エッチング法により、絶縁膜３３を選択的に除去し、開
口部３５を形成する。開口部３５の形成工程では、絶縁
膜３２をエッチングストッパとして機能させる。Next, an antireflection film 34a and a photoresist film are sequentially formed on the insulating film 33, and the photoresist film is patterned by exposure to form a photoresist pattern 3.
4b is formed. As a result, the structure shown in FIG. 11 is obtained. Then, the antireflection film 34a is selectively removed by a dry etching method using the photoresist pattern 34b as an etching mask. After that, the insulating film 33 is selectively removed by a dry etching method using the photoresist pattern 34b as an etching mask to form an opening 35. In the step of forming the opening 35, the insulating film 32 functions as an etching stopper.
【００５９】次に、残存するフォトレジストパターン３
４ｂおよび反射防止膜３４ａを除去した後、開口部３５
の内部を含む絶縁膜３３上に反射防止膜３６ａを形成す
る。そして、反射防止膜３６ａ上にフォトレジスト膜を
形成し、露光によりフォトレジスト膜をパターン化して
フォトレジストパターン３６ｂを形成する。これによ
り、図１２に示される構造が得られる。Next, the remaining photoresist pattern 3
After removing 4b and the antireflection film 34a, the opening 35 is formed.
An antireflection film 36a is formed on the insulating film 33 including the inside thereof. Then, a photoresist film is formed on the antireflection film 36a, and the photoresist film is patterned by exposure to form a photoresist pattern 36b. As a result, the structure shown in FIG. 12 is obtained.
【００６０】次に、フォトレジストパターン３６ｂをエ
ッチングマスクにしたドライエッチング法により、反射
防止膜３６ａを選択的に除去する。それから、フォトレ
ジストパターン３６ｂをエッチングマスクにしたドライ
エッチング法により、絶縁膜３２を選択的に除去して開
口部３７を形成し、開口部３７の底部で絶縁膜３１を露
出する。そして、開口部３７から露出した絶縁膜３１を
ＮＨ3プラズマ処理またはＮ2／Ｈ2プラズマ処理などに
よってエッチングしながら、フォトレジストパターン３
６ｂおよび反射防止膜３６ａをアッシングして除去す
る。これにより、図１３に示される構造が得られる。フ
ォトレジストパターン３６ｂおよび反射防止膜３６ａの
除去は、絶縁膜３１のエッチング工程の後に行うことも
できる。Next, the antireflection film 36a is selectively removed by a dry etching method using the photoresist pattern 36b as an etching mask. Then, the insulating film 32 is selectively removed by dry etching using the photoresist pattern 36b as an etching mask to form an opening 37, and the insulating film 31 is exposed at the bottom of the opening 37. Then, while etching the insulating film 31 exposed from the opening 37 by NH 3 plasma treatment or N 2 / H 2 plasma treatment, the photoresist pattern 3 is formed.
6b and the antireflection film 36a are removed by ashing. As a result, the structure shown in FIG. 13 is obtained. The removal of the photoresist pattern 36b and the antireflection film 36a can also be performed after the step of etching the insulating film 31.
【００６１】次に、図１４に示されるように、開口部３
７の底部で露出する絶縁膜３０とその下層の絶縁膜２９
と、開口部３５から露出する絶縁膜３２とを、ドライエ
ッチング法などによって除去し、開口部３７の底部で絶
縁膜２８を露出しかつ開口部３５から絶縁膜３１を露出
する。このとき、エッチングマスクとして機能する絶縁
膜３３は、上部がエッチングされて薄くなるが、絶縁膜
３３の形成時に比較的厚く形成しておけば、絶縁膜３３
が完全に除去されることはない。Next, as shown in FIG. 14, the opening 3
Insulation film 30 exposed at the bottom of 7 and insulation film 29 below it
And the insulating film 32 exposed from the opening 35 are removed by a dry etching method or the like to expose the insulating film 28 at the bottom of the opening 37 and the insulating film 31 from the opening 35. At this time, the upper portion of the insulating film 33 functioning as an etching mask is etched to be thin, but if the insulating film 33 is formed relatively thick when the insulating film 33 is formed, the insulating film 33 can be formed.
Are never completely removed.
【００６２】次に、図１５に示されるように、開口部３
７の底部で露出する絶縁膜２８と、開口部３５から露出
する絶縁膜３１とを、ドライエッチング法などによって
除去する。このとき、絶縁膜３３がエッチングマスクと
して機能し、かつ絶縁膜２６および絶縁膜３０がエッチ
ングストッパとして機能する。Next, as shown in FIG. 15, the opening 3
The insulating film 28 exposed at the bottom of 7 and the insulating film 31 exposed from the opening 35 are removed by a dry etching method or the like. At this time, the insulating film 33 functions as an etching mask, and the insulating films 26 and 30 function as an etching stopper.
【００６３】次に、図１６に示されるように、開口部３
７の底部で露出する絶縁膜２６をドライエッチング法な
どによって除去し、開口部３７の底部で第２層配線２５
を露出させる。このとき、露出した絶縁膜３０および絶
縁膜３３も除去される。Next, as shown in FIG. 16, the opening 3
The insulating film 26 exposed at the bottom of 7 is removed by a dry etching method or the like, and the second layer wiring 25 is formed at the bottom of the opening 37.
Expose. At this time, the exposed insulating film 30 and insulating film 33 are also removed.
【００６４】次に、基板１の主面上の全面に、導電性バ
リア膜２５ａと同様の材料、例えば窒化チタンからなる
導電性バリア膜３８ａをスパッタリング法などで形成す
る。それから、導電性バリア膜３８ａ上に、開口部３７
および開口部３５を埋めるように、銅からなる主導体膜
３８ｂを、主導体膜２５ｂと同様にして形成する。Next, a conductive barrier film 38a made of the same material as the conductive barrier film 25a, for example, titanium nitride is formed on the entire main surface of the substrate 1 by a sputtering method or the like. Then, the opening 37 is formed on the conductive barrier film 38a.
A main conductor film 38b made of copper is formed in the same manner as the main conductor film 25b so as to fill the opening 35.
【００６５】次に、主導体膜３８ｂ、導電性バリア膜３
８ａおよび絶縁膜３２をＣＭＰ法によって、絶縁膜３１
の上面が露出するまで研磨する。これにより、図１７に
示されるように、開口部３５および３７からなる配線溝
内に第３層配線（配線）３８を形成する。第３層配線３
８は、相対的に薄い導電性バリア膜３８ａと、相対的に
厚い主導体膜３８ｂとを有しており、第２層配線２５と
電気的に接続されている。Next, the main conductor film 38b and the conductive barrier film 3 are formed.
8a and the insulating film 32 by the CMP method.
Polish until the top surface of is exposed. As a result, as shown in FIG. 17, the third layer wiring (wiring) 38 is formed in the wiring groove formed of the openings 35 and 37. Third layer wiring 3
Reference numeral 8 has a relatively thin conductive barrier film 38 a and a relatively thick main conductor film 38 b, and is electrically connected to the second layer wiring 25.
【００６６】次に、第２層配線２５間の絶縁膜２１を除
去するプラズマ処理と同様の処理を施し、第３層配線３
８間の絶縁膜３１を除去する。それから、第３層配線３
８のバリア絶縁膜としての絶縁膜３９を、絶縁膜２６と
同様にして形成する。これにより、図１８に示されるよ
うに、くぼみ部分２７ａと同様のくぼみ部分４０ａが、
第３層配線３８の最近接配線間に生じる。Next, the same treatment as the plasma treatment for removing the insulating film 21 between the second layer wirings 25 is performed to form the third layer wiring 3
The insulating film 31 between 8 is removed. Then, the third layer wiring 3
The insulating film 39 as the barrier insulating film of No. 8 is formed in the same manner as the insulating film 26. As a result, as shown in FIG. 18, the recessed portion 40a similar to the recessed portion 27a is
It occurs between the closest wirings of the third layer wiring 38.
【００６７】次に、図１９に示されるように、絶縁膜３
９上に、絶縁膜２８と同様のＬｏｗ−Ｋ材料からなる絶
縁膜４１を形成する。絶縁膜２８の形成工程と同様、第
３層配線３８の最近接配線間の絶縁膜３９のくぼみ部分
４０ａの内部には絶縁膜４１の材料が、その表面張力な
どのために入り込めない。このため、絶縁膜４１を形成
した段階で、第３層配線３８の最近接配線間には空隙ま
たはボイド４０が形成される。一方、第３層配線３８の
隣接配線間距離が大きな領域では、絶縁膜４１の材料が
第２層配線３８間に入り込み、ボイドが形成されないの
で、機械的強度を維持することが可能となる。Next, as shown in FIG. 19, the insulating film 3
The insulating film 41 made of the same Low-K material as the insulating film 28 is formed on the insulating film 9. Similar to the step of forming the insulating film 28, the material of the insulating film 41 cannot enter the inside of the recessed portion 40a of the insulating film 39 between the closest wirings of the third layer wiring 38 due to its surface tension or the like. Therefore, when the insulating film 41 is formed, voids or voids 40 are formed between the closest wirings of the third layer wiring 38. On the other hand, in the region where the distance between the adjacent wirings of the third layer wiring 38 is large, the material of the insulating film 41 enters between the second layer wirings 38 and voids are not formed, so that the mechanical strength can be maintained.
【００６８】次に、絶縁膜４１上に絶縁膜４２をＣＶＤ
法などを用いて形成する。絶縁膜４１は、例えば窒化シ
リコン膜からなる。必要に応じてＣＭＰ処理を行い、絶
縁膜４１の上面を平坦化する。絶縁膜４１の他の材料と
して、例えば炭化シリコン膜、ＳｉＣＮ膜または酸窒化
シリコン膜を用いることもできる。これより、図１９に
示される構造が得られる。更に必要に応じて、同様の製
造工程を繰り返し、第４層配線以降の上層配線を形成す
ることもできる。また、第１層配線１５を、第２層配線
２５と同様にして形成した銅配線とし、第２層配線２５
を第３層配線３８と同様にして形成した銅配線とするこ
ともできる。Next, an insulating film 42 is formed on the insulating film 41 by CVD.
It is formed by using the method. The insulating film 41 is made of, for example, a silicon nitride film. If necessary, CMP processing is performed to planarize the upper surface of the insulating film 41. As another material of the insulating film 41, for example, a silicon carbide film, a SiCN film, or a silicon oxynitride film can be used. From this, the structure shown in FIG. 19 is obtained. Further, if necessary, the same manufacturing process may be repeated to form upper layer wirings on and after the fourth layer wiring. Further, the first layer wiring 15 is a copper wiring formed in the same manner as the second layer wiring 25, and the second layer wiring 25
Can be copper wiring formed in the same manner as the third layer wiring 38.
【００６９】本実施の形態によれば、同層配線間にＣＭ
Ｐ面（ＣＭＰで研磨された面）がない。すなわち、第２
層配線２５および第３層配線３８を形成するためのＣＭ
Ｐ工程で研磨された絶縁膜２１および３１は除去されて
おり、第２層配線２５および第３層配線３８を覆うよう
にバリア絶縁膜２６および３９が形成されている。この
ため、第２層配線２５および第３層配線３８において、
同層配線の上面同士がＣＭＰ面を介して連結されること
はない。これにより、ＴＤＤＢ寿命を向上し、配線間の
絶縁破壊耐性を向上させることができる。また、半導体
装置の信頼性を高めることができる。According to the present embodiment, the CM is provided between the wirings in the same layer.
There is no P surface (surface polished by CMP). That is, the second
CM for forming the layer wiring 25 and the third layer wiring 38
The insulating films 21 and 31 polished in the P step are removed, and barrier insulating films 26 and 39 are formed so as to cover the second layer wiring 25 and the third layer wiring 38. Therefore, in the second layer wiring 25 and the third layer wiring 38,
The upper surfaces of the same layer wiring are not connected via the CMP surface. Thereby, the TDDB life can be improved and the dielectric breakdown resistance between the wirings can be improved. In addition, the reliability of the semiconductor device can be improved.
【００７０】また、最も容量低減が必要な同層配線にお
ける最近接配線間に膜材料が存在しないボイド２７およ
び４０を形成するので、配線間容量を低減することがで
きる。配線のバリア絶縁膜２６および３９に比較的誘電
率の高い材料を用いたとしても、配線間容量の低減が可
能である。Further, since the voids 27 and 40 in which the film material does not exist are formed between the closest wirings in the same-layer wiring where the capacitance needs to be reduced most, the capacitance between wirings can be reduced. Even if a material having a relatively high dielectric constant is used for the barrier insulating films 26 and 39 of the wiring, the capacitance between the wirings can be reduced.
【００７１】また、同層配線の隣接配線間距離が大きな
領域では、配線間にボイドを形成せずＬｏｗ−Ｋ材料を
成膜する。このため、全体の機械的強度を維持すること
が可能となる。Further, in a region where the distance between adjacent wirings of the same layer wiring is large, a Low-K material is deposited without forming voids between the wirings. Therefore, it is possible to maintain the overall mechanical strength.
【００７２】また、本実施の形態では、最近接配線間で
なくとも、隣接配線間隔が比較的小さく、その間の寄生
容量を低減したい配線間にはボイド２７または４０を形
成してもよい。配線間距離がどの程度の場合までボイド
を形成するかは、絶縁膜２６または３９の成膜条件や絶
縁膜２８または４１の成膜条件などを調整することによ
って、制御することができる。これにより、配線パター
ン密度が疎の領域では、隣接配線間にボイドを形成して
配線間容量を低減し、配線パターンが密な領域では、配
線間をＬｏｗ−Ｋ材料で埋めて、機械的強度を確保する
ことができる。Further, in the present embodiment, the voids 27 or 40 may be formed between the wirings where the distance between adjacent wirings is relatively small and the parasitic capacitance between the adjacent wirings is desired to be reduced, not between the wirings closest to each other. The extent to which the voids are formed can be controlled by adjusting the film forming conditions of the insulating film 26 or 39, the film forming conditions of the insulating film 28 or 41, and the like. Thus, in a region where the wiring pattern density is sparse, voids are formed between adjacent wirings to reduce the inter-wiring capacitance, and in a region where the wiring pattern is dense, the space between the wirings is filled with a Low-K material to improve the mechanical strength. Can be secured.
【００７３】本発明者は、実験およびシミュレーション
により、本実施の形態の配線構造の容量低減効果につい
て調べた。比較例として、配線を埋め込むための絶縁膜
および層間絶縁膜をＬｏｗ−Ｋ材料で構成しかつ一般的
なダマシン技術で形成された銅配線構造を用いた。The present inventor investigated the capacity reduction effect of the wiring structure of the present embodiment by experiments and simulations. As a comparative example, a copper wiring structure was used in which an insulating film for filling wiring and an interlayer insulating film were made of a Low-K material and formed by a general damascene technique.
【００７４】その結果、本実施の形態の配線構造は、上
記比較例に対して、配線間容量を２０〜３０％程度低減
することができた。また、上層配線と下層配線の間の容
量はほとんど変わらず、同層の配線間容量のみが減少し
た。このため、配線のクロストークの影響を低減でき
る。また、実効誘電率εｒ（上記比較例の銅配線構造で
はεｒは３．１程度）を２．３〜２．７程度へ大幅に低
減することができた。従って、同世代のＬｏｗ−Ｋ材料
を層間絶縁膜に用いて、１世代以上先の低容量配線構造
を実現できる。As a result, in the wiring structure of this embodiment, the inter-wiring capacitance could be reduced by about 20 to 30% as compared with the comparative example. Further, the capacitance between the upper layer wiring and the lower layer wiring was almost unchanged, and only the capacitance between the wirings in the same layer was reduced. Therefore, the influence of wiring crosstalk can be reduced. Further, the effective permittivity εr (εr is about 3.1 in the copper wiring structure of the comparative example) can be significantly reduced to about 2.3 to 2.7. Therefore, a low-capacity wiring structure of one generation or more can be realized by using the same generation Low-K material for the interlayer insulating film.
【００７５】（実施の形態２）図２０〜２５は、本発明
の他の実施の形態である半導体装置の製造工程中の要部
断面図である。図１０までの製造工程は上記実施の形態
１と同様であるので、ここではその説明は省略し、図１
０に続く製造工程について説明する。(Embodiment 2) FIGS. 20 to 25 are cross-sectional views of essential parts in a manufacturing process of a semiconductor device according to another embodiment of the present invention. Since the manufacturing process up to FIG. 10 is the same as that of the first embodiment, the description thereof is omitted here.
The manufacturing process following 0 will be described.
【００７６】図１０に示される構造が形成された後、図
２０に示されるように、絶縁膜２８上に、例えば窒化シ
リコン膜からなる絶縁膜２９と例えば酸化シリコン膜か
らなる絶縁膜３０とをＣＶＤ法などを用いて順に形成す
る。必要に応じてＣＭＰ処理を行い、絶縁膜３０の上面
を平坦化する。場合によっては、絶縁膜３０は形成しな
くともよい。After the structure shown in FIG. 10 is formed, as shown in FIG. 20, an insulating film 29 made of, for example, a silicon nitride film and an insulating film 30 made of, for example, a silicon oxide film are formed on the insulating film 28. The layers are sequentially formed by using the CVD method or the like. If necessary, CMP processing is performed to planarize the upper surface of the insulating film 30. In some cases, the insulating film 30 may not be formed.
【００７７】次に、絶縁膜３３上に反射防止膜５０ａお
よびフォトレジスト膜を順に形成し、露光によりフォト
レジスト膜をパターン化してフォトレジストパターン５
０ｂを形成する。Next, an antireflection film 50a and a photoresist film are sequentially formed on the insulating film 33, and the photoresist film is patterned by exposure to form a photoresist pattern 5.
0b is formed.
【００７８】次に、図２１に示されるように、フォトレ
ジストパターン５０ｂをエッチングマスクにしたドライ
エッチング法により、反射防止膜５０ａを選択的に除去
した後、フォトレジストパターン５０ｂをエッチングマ
スクにしたドライエッチング法により、絶縁膜２９およ
び３０を選択的に除去し、開口部５１を形成する。開口
部５１の形成工程では、絶縁膜２８をエッチングストッ
パとして機能させる。その後、残存するフォトレジスト
パターン５０ｂおよび反射防止膜５０ａを除去する。Next, as shown in FIG. 21, the antireflection film 50a is selectively removed by a dry etching method using the photoresist pattern 50b as an etching mask, and then a dry etching using the photoresist pattern 50b as an etching mask. The insulating films 29 and 30 are selectively removed by an etching method to form the opening 51. In the step of forming the opening 51, the insulating film 28 functions as an etching stopper. Then, the remaining photoresist pattern 50b and antireflection film 50a are removed.
【００７９】次に、開口部５１内を含む絶縁膜３０上
に、絶縁膜３１を形成する。それから、絶縁膜３１上
に、絶縁膜３２を形成する。上記実施の形態１とは異な
り、本実施の形態では、絶縁膜３３は形成しなくともよ
い。Next, the insulating film 31 is formed on the insulating film 30 including the inside of the opening 51. Then, the insulating film 32 is formed on the insulating film 31. Unlike the first embodiment, the insulating film 33 need not be formed in this embodiment.
【００８０】次に、絶縁膜３２上に反射防止膜５２ａを
形成する。そして、反射防止膜５２ａ上にフォトレジス
ト膜を形成し、露光によりフォトレジスト膜をパターン
化してフォトレジストパターン５２ｂを形成する。これ
により、図２２に示される構造が得られる。Next, an antireflection film 52a is formed on the insulating film 32. Then, a photoresist film is formed on the antireflection film 52a, and the photoresist film is patterned by exposure to form a photoresist pattern 52b. As a result, the structure shown in FIG. 22 is obtained.
【００８１】次に、フォトレジストパターン５２ｂをエ
ッチングマスクにしたドライエッチング法により、反射
防止膜５２ａを選択的に除去する。それから、フォトレ
ジストパターン５２ｂをエッチングマスクにしたドライ
エッチング法により、絶縁膜３２を選択的に除去して開
口部５３を形成し、開口部５３の底部で絶縁膜３１を露
出する。その後、ＮＨ3プラズマ処理またはＮ2／Ｈ2プ
ラズマ処理などによって、開口部５３から露出した絶縁
膜３１と開口部５１から露出する絶縁膜２８とをエッチ
ングしながら、フォトレジストパターン５２ｂおよび反
射防止膜５２ａをアッシングして除去する。このとき、
かつ絶縁膜２６および絶縁膜３０がエッチングストッパ
として機能する。これにより、図２３に示される構造が
得られる。フォトレジストパターン５２ｂおよび反射防
止膜５２ａの除去は、絶縁膜２８および３１のエッチン
グ工程の後に行うこともできる。Next, the antireflection film 52a is selectively removed by a dry etching method using the photoresist pattern 52b as an etching mask. Then, the insulating film 32 is selectively removed by dry etching using the photoresist pattern 52b as an etching mask to form an opening 53, and the insulating film 31 is exposed at the bottom of the opening 53. Then, the photoresist pattern 52b and the antireflection film are etched while etching the insulating film 31 exposed from the opening 53 and the insulating film 28 exposed from the opening 51 by NH 3 plasma treatment or N 2 / H 2 plasma treatment. 52a is removed by ashing. At this time,
Moreover, the insulating film 26 and the insulating film 30 function as an etching stopper. As a result, the structure shown in FIG. 23 is obtained. The removal of the photoresist pattern 52b and the antireflection film 52a can also be performed after the step of etching the insulating films 28 and 31.
【００８２】次に、図２４に示されるように、開口部５
１の底部で露出する絶縁膜２６をドライエッチング法な
どによって除去し、開口部５１の底部で第２層配線２５
を露出させる。このとき、露出した絶縁膜３０および絶
縁膜３２も除去され得る。Next, as shown in FIG. 24, the opening 5
The insulating film 26 exposed at the bottom of the first layer is removed by a dry etching method or the like, and the second layer wiring 25 is formed at the bottom of the opening 51.
Expose. At this time, the exposed insulating film 30 and insulating film 32 can also be removed.
【００８３】次に、基板１の主面上の全面に、例えば窒
化チタンからなる導電性バリア膜３８ａをスパッタリン
グ法などで形成する。それから、導電性バリア膜３８ａ
上に、開口部５１および開口部５３を埋めるように、銅
からなる主導体膜３８ｂを形成する。Next, a conductive barrier film 38a made of, for example, titanium nitride is formed on the entire main surface of the substrate 1 by a sputtering method or the like. Then, the conductive barrier film 38a
A main conductor film 38b made of copper is formed thereover so as to fill the openings 51 and 53.
【００８４】次に、主導体膜３８ｂおよび導電性バリア
膜３８ａをＣＭＰ法によって、絶縁膜３１の上面が露出
するまで研磨する。これにより、図２５に示されるよう
に、開口部５１および５３からなる配線溝内に第３層配
線（配線）３８を形成する。第３層配線３８は、相対的
に薄い導電性バリア膜３８ａと、相対的に厚い主導体膜
３８ｂとを有しており、第２層配線２５と電気的に接続
されている。Next, the main conductor film 38b and the conductive barrier film 38a are polished by the CMP method until the upper surface of the insulating film 31 is exposed. As a result, as shown in FIG. 25, the third layer wiring (wiring) 38 is formed in the wiring groove formed of the openings 51 and 53. The third layer wiring 38 has a relatively thin conductive barrier film 38 a and a relatively thick main conductor film 38 b, and is electrically connected to the second layer wiring 25.
【００８５】これ以降の製造工程は、上記実施の形態１
の図１７以降の製造工程と同様であるので、その説明を
省略する。The subsequent manufacturing steps are the same as those in the first embodiment.
Since the manufacturing process is the same as that of FIG. 17 onward, description thereof will be omitted.
【００８６】（実施の形態３）図２６は、本発明の他の
実施の形態である半導体装置の製造工程中の要部断面図
である。本実施の形態の半導体装置は、上記実施の形態
１の第２層配線２５および第３層配線３６ように隣接配
線間にボイドを形成しかつ隣接配線間をＣＭＰ面で接続
しない配線層と、一般的な埋込配線技術を用いて形成さ
れた配線層とが組み合わされた多層配線構造を有してい
る。図２６において、絶縁膜４２の形成工程までは、上
記実施の形態１の図１９までの製造工程とほぼ同様であ
るので、その説明は省略し、ここではそれ以降の製造工
程について説明する。(Third Embodiment) FIG. 26 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device according to another embodiment of the present invention. The semiconductor device of the present embodiment has a wiring layer in which a void is formed between adjacent wirings and the adjacent wirings are not connected by a CMP plane like the second layer wiring 25 and the third layer wiring 36 of the first embodiment, It has a multilayer wiring structure in which a wiring layer formed by using a general embedded wiring technique is combined. In FIG. 26, the steps up to the step of forming the insulating film 42 are almost the same as the manufacturing steps up to FIG. 19 of the first embodiment, so the description thereof will be omitted and the manufacturing steps thereafter will be described.
【００８７】本実施の形態では、絶縁膜４２上に酸化シ
リコンなどからなる絶縁膜６０が形成され、第３層配線
３８と同様にして第４層配線６１が形成される。それか
ら、絶縁膜２６と同様にして、バリア絶縁膜として機能
する絶縁膜６２が形成され、その上に絶縁膜２８と同様
にして絶縁膜６４を形成する。第４層配線６１において
も、第２層配線２５および第３層配線３６と同様、最近
接配線間にボイド６３が形成される。In the present embodiment, the insulating film 60 made of silicon oxide or the like is formed on the insulating film 42, and the fourth layer wiring 61 is formed similarly to the third layer wiring 38. Then, an insulating film 62 that functions as a barrier insulating film is formed in the same manner as the insulating film 26, and an insulating film 64 is formed thereon similarly to the insulating film 28. In the fourth layer wiring 61 as well, as in the second layer wiring 25 and the third layer wiring 36, voids 63 are formed between the closest wirings.
【００８８】第５層以降の配線層は、一般的な埋込配線
技術、例えば一般的なデュアルダマシン技術を用いて形
成する。すなわち、絶縁膜６４上に、窒化シリコン、炭
化シリコン、炭窒化シリコンまたは酸窒化シリコン膜
（例えばＰＥ−ＴＭＳ（Ｃａｎｏｎ製））からなる絶縁
膜６５、酸化シリコンなどからなる絶縁膜６６、Ｌｏｗ
−Ｋ材料などからなる絶縁膜６７、絶縁膜６５と同様の
材料、例えば窒化シリコンなどからなる絶縁膜６８およ
び酸化シリコンなどからなる絶縁膜６９を形成する。そ
して、デュアルダマシン技術を用いて、絶縁膜６２、６
４〜６９に形成された配線溝に埋め込まれた第５層配線
７０を形成する。それから、第５層配線７０の上面を含
む絶縁膜６９上に、窒化シリコン、炭化シリコン、炭窒
化シリコンまたは酸窒化シリコン膜などからなる絶縁膜
７１を、バリア絶縁膜として形成する。その後、絶縁膜
７１上に、Ｌｏｗ−Ｋ材料などからなる絶縁膜７２、絶
縁膜６５と同様の材料、例えば窒化シリコンなどからな
る絶縁膜７３、酸化シリコンなどからなる絶縁膜７４、
Ｌｏｗ−Ｋ材料などからなる絶縁膜７５、絶縁膜６５と
同様の材料、例えば窒化シリコンなどからなる絶縁膜７
６および酸化シリコンなどからなる絶縁膜７７を形成す
る。そして、デュアルダマシン技術を用いて、絶縁膜７
１〜７７に形成された配線溝に埋め込まれた第６層配線
７８を形成する。それから、第６層配線７８の上面を含
む絶縁膜７７上に、絶縁膜７１と同様の材料、例えば窒
化シリコンなどからなる絶縁膜７９を、バリア絶縁膜と
して形成する。The fifth and subsequent wiring layers are formed by using a general embedded wiring technique, for example, a general dual damascene technique. That is, on the insulating film 64, an insulating film 65 made of silicon nitride, silicon carbide, silicon carbonitride, or silicon oxynitride film (for example, PE-TMS (manufactured by Canon)), an insulating film 66 made of silicon oxide, etc., Low.
An insulating film 67 made of a -K material or the like, an insulating film 68 made of a material similar to the insulating film 65, for example, silicon nitride or the like, and an insulating film 69 made of silicon oxide or the like are formed. Then, using the dual damascene technology, the insulating films 62, 6 are formed.
A fifth layer wiring 70 embedded in the wiring grooves formed in 4-69 is formed. Then, on the insulating film 69 including the upper surface of the fifth-layer wiring 70, an insulating film 71 made of a silicon nitride film, a silicon carbide film, a silicon carbonitride film, a silicon oxynitride film, or the like is formed as a barrier insulating film. After that, on the insulating film 71, an insulating film 72 made of a Low-K material or the like, an insulating film 73 made of the same material as the insulating film 65, for example, silicon nitride or the like, an insulating film 74 made of silicon oxide or the like,
An insulating film 75 made of a low-K material or the like, an insulating film 7 made of a material similar to the insulating film 65, for example, silicon nitride or the like.
6 and an insulating film 77 made of silicon oxide or the like is formed. Then, the insulating film 7 is formed by using the dual damascene technology.
A sixth layer wiring 78 embedded in the wiring grooves formed in 1 to 77 is formed. Then, on the insulating film 77 including the upper surface of the sixth-layer wiring 78, an insulating film 79 made of the same material as the insulating film 71, for example, silicon nitride is formed as a barrier insulating film.
【００８９】なお、絶縁膜２８、４１、６４、６７、７
２および７５としてＣＶＤ法を用いて形成した膜、例え
ば酸化シリコン膜、ＦＳＧ（ＳｉＯＦ系材料）膜、Ｓｉ
ＯＣ膜またはポーラスシリコン（Ｐｏｌｕｓ−Ｓｉ）系
材料膜を用いることもでき、その場合、絶縁膜３０、６
０、６６、６８、６９、７４、７６および７７の形成を
省略することもできる。The insulating films 28, 41, 64, 67, 7
2 and 75 are films formed by the CVD method, for example, a silicon oxide film, an FSG (SiOF based material) film, Si
An OC film or a porous silicon (Porus-Si) -based material film may be used, and in that case, the insulating films 30 and 6 are used.
The formation of 0, 66, 68, 69, 74, 76 and 77 can be omitted.
【００９０】多層配線構造において、隣接配線間隔が比
較的小さい、すなわち配線ピッチが比較的小さい配線層
では、配線間容量が増大しかつＴＤＤＢ寿命が低減しや
すい。本実施の形態によれば、そのような配線間容量が
増大しかつＴＤＤＢ寿命が低減しやすい配線層におい
て、同層配線間にＣＭＰ面をなくしてＴＤＤＢ寿命を向
上させ、かつ同層配線の最近接配線間にボイドを形成し
て配線間容量を低減することができる。In the multi-layer wiring structure, in the wiring layer in which the spacing between adjacent wirings is relatively small, that is, the wiring pitch is relatively small, the inter-wiring capacitance is likely to increase and the TDDB life is likely to be shortened. According to the present embodiment, in such a wiring layer in which the inter-wiring capacitance is increased and the TDDB life is easily reduced, the TDDB life is improved by eliminating the CMP surface between the wirings in the same layer, and Voids can be formed between adjacent wirings to reduce the capacitance between the wirings.
【００９１】（実施の形態４）図２７、２９〜３１は、
本発明の他の実施の形態である半導体装置の配線パター
ンを示す概念的な平面図である。図２８は図２７のＢ−
Ｂ断面図である。配線パターンの構造および形成工程は
上記実施の形態１の第２層配線２５または第３層配線３
６とほぼ同様であるので、ここではその説明は省略す
る。(Embodiment 4) FIGS.
It is a conceptual top view which shows the wiring pattern of the semiconductor device which is other embodiment of this invention. FIG. 28 shows B- of FIG.
It is a B sectional view. The structure and formation process of the wiring pattern are the same as those of the second layer wiring 25 or the third layer wiring 3 of the first embodiment.
Since it is almost the same as 6, the description thereof will be omitted here.
【００９２】本実施の形態においては、本体配線８１の
周囲に、ダミー配線８２を設ける。本体配線８１は、半
導体装置の電気回路として必要不可欠な配線パターンで
ある。本体配線８１は、例えば上記第２層配線２５また
は第３層配線３８などに対応し、ＭＩＳＦＥＴのゲート
やソース・ドレイン領域などに電気的に接続されてい
る。ダミー配線８２は、本体配線８１と同時に形成され
かつ同構造の導体パターンであるが、半導体装置の電気
回路としては必要とされない、すなわち配線としては機
能しない導体パターンである。ダミー配線８２は、例え
ば、ＭＩＳＦＥＴのゲートやソース・ドレイン領域など
に電気的に接続されることなく、接地電位とされてい
る。本実施の形態においては、隣接する本体配線８１間
にボイド（図示せず）を形成するとともに、本体配線８
１とダミー配線８２の間にもボイド（図示せず）を形成
する。ボイドの形成工程は、上記実施の形態１と同様で
ある。ダミー配線８２を設けたことにより、本体配線８
１の両側にボイドを形成することができる。このため、
本体配線８１の寄生容量をより低減することが可能にな
る。図２７〜３０は、本体配線８１とダミー配線８２の
形成パターンの例を示しており、必要に応じて、図２７
〜３０およびそれ以外の種々の配線パターンを形成する
ことができる。In the present embodiment, a dummy wiring 82 is provided around the main body wiring 81. The main body wiring 81 is a wiring pattern that is indispensable as an electric circuit of a semiconductor device. The main body wiring 81 corresponds to, for example, the second layer wiring 25, the third layer wiring 38, or the like, and is electrically connected to the gate, source / drain region, or the like of the MISFET. The dummy wiring 82 is a conductor pattern that is formed at the same time as the main body wiring 81 and has the same structure, but is not required as an electric circuit of a semiconductor device, that is, a conductor pattern that does not function as a wiring. The dummy wiring 82 is set to the ground potential without being electrically connected to, for example, the gate or the source / drain region of the MISFET. In the present embodiment, a void (not shown) is formed between the adjacent main body wirings 81, and the main body wirings 8 are formed.
A void (not shown) is also formed between 1 and the dummy wiring 82. The void forming process is the same as that in the first embodiment. By providing the dummy wiring 82, the body wiring 8
Voids can be formed on both sides of 1. For this reason,
It is possible to further reduce the parasitic capacitance of the main body wiring 81. 27 to 30 show examples of formation patterns of the main body wiring 81 and the dummy wiring 82, and as needed, FIG.
Various wiring patterns other than -30 and other wiring patterns can be formed.
【００９３】例えば、図２７および図２８に示されるよ
うに、孤立した一本の本体配線８１を囲むようにダミー
配線８２を設けることができる。For example, as shown in FIGS. 27 and 28, a dummy wiring 82 can be provided so as to surround one isolated body wiring 81.
【００９４】また、図２９に示されるように、互いに平
行に配列する複数の本体配線８１の全体を囲むようにダ
ミー配線８２を設けることができる。Further, as shown in FIG. 29, dummy wirings 82 can be provided so as to surround the whole of a plurality of main body wirings 81 arranged in parallel with each other.
【００９５】また、図３０に示されるように、互いに平
行に配列する複数の本体配線８１全体を囲むようにダミ
ー配線８２を設けるとともに、複数の本体配線８１間に
もダミー配線８２を設けることができる。Further, as shown in FIG. 30, dummy wirings 82 are provided so as to surround the plurality of main body wirings 81 arranged in parallel with each other, and dummy wirings 82 are also provided between the plurality of main body wirings 81. it can.
【００９６】また、ダミー配線８２パターンは連続して
形成しなくともよく、例えば図３１に示されるように、
不連続なダミー配線８２を設けることもできる。Further, the dummy wiring 82 pattern does not have to be formed continuously. For example, as shown in FIG.
Discontinuous dummy wirings 82 can also be provided.
【００９７】（実施の形態５）図３２は、本発明の他の
実施の形態である半導体装置の配線パターンを示す概念
的な平面図である。図３２の配線パターン８５は、例え
ば上記第２層配線２５または第３層配線３６に対応し、
その構造および形成工程は上記実施の形態１と同様であ
るので、ここではその説明は省略する。(Fifth Embodiment) FIG. 32 is a conceptual plan view showing a wiring pattern of a semiconductor device according to another embodiment of the present invention. The wiring pattern 85 of FIG. 32 corresponds to, for example, the second layer wiring 25 or the third layer wiring 36,
Since the structure and the forming process are the same as those in the first embodiment, the description thereof will be omitted here.
【００９８】本実施の形態では、配線パターン８５にお
いて、スルーホール形成領域８６の近傍で、配線幅広部
またはリザーバ部８７を設けている。これにより、スル
ーホールが配線パターンからずれる、目外れを防止す
る。図３２では、その上に形成すべきスルーホールに対
応する位置８６を点線で示してある。スルーホール形成
のためのフォトリソグラフィ工程において、フォトマス
クの位置ずれなどにより、実際に形成されたスルーホー
ルの位置が所望の位置（図３２の点線の位置）からずれ
る場合がある。このような場合でも、配線幅が広いリザ
ーバ部８７が設けられているので、スルーホールが配線
パターン８５から外れることを防止できる。このため、
配線８５に隣接して形成されるボイド（図示せず）が、
スルーホールの形成工程で露出することをより的確に防
止できる。In the present embodiment, in the wiring pattern 85, the wide wiring portion or the reservoir portion 87 is provided near the through hole forming region 86. This prevents the through-holes from being displaced from the wiring pattern and being out of alignment. In FIG. 32, the position 86 corresponding to the through hole to be formed thereon is shown by a dotted line. In the photolithography process for forming the through hole, the position of the actually formed through hole may deviate from the desired position (the position indicated by the dotted line in FIG. 32) due to displacement of the photomask. Even in such a case, since the reservoir portion 87 having a wide wiring width is provided, it is possible to prevent the through hole from coming off the wiring pattern 85. For this reason,
A void (not shown) formed adjacent to the wiring 85 is
It can be more accurately prevented from being exposed in the process of forming the through hole.
【００９９】（実施の形態６）図３３は、本発明の他の
実施の形態である半導体装置の製造工程中の要部断面図
であり、図１９の工程段階に対応する。(Embodiment 6) FIG. 33 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device according to another embodiment of the present invention, and corresponds to the process step in FIG.
【０１００】本実施の形態では、上記実施の形態１とは
異なり、銅配線のバリア絶縁膜として機能する絶縁膜２
６および３９を形成しない。本実施の形態では、銅配線
である第２層配線２５および第３層配線３８の上部に、
銅の拡散を防止する導電性バリア膜として、例えばタン
グステンなどからなる金属キャップ膜９１および９２を
形成する。従って、第２層配線２５は、導電性バリア膜
２５ａ、主導体膜２５ｂおよび金属キャップ膜９１から
構成され、第３層配線３８は、導電性バリア膜３８ａ、
主導体膜３８ｂおよび金属キャップ膜９２から構成され
る。また、絶縁膜２６および３９を形成しないので、Ｌ
ｏｗ−Ｋ材料からなる絶縁膜２８および３９が第２層配
線２５および第３層配線３６の同層隣接配線間を完全に
埋め、最近接配線間においてもボイド２７および４０は
形成されない。In this embodiment, unlike the first embodiment, the insulating film 2 functioning as a barrier insulating film for copper wiring is used.
Do not form 6 and 39. In the present embodiment, on the second layer wiring 25 and the third layer wiring 38 which are copper wiring,
Metal cap films 91 and 92 made of, for example, tungsten are formed as a conductive barrier film for preventing diffusion of copper. Therefore, the second layer wiring 25 is composed of the conductive barrier film 25a, the main conductor film 25b and the metal cap film 91, and the third layer wiring 38 is the conductive barrier film 38a.
The main conductor film 38b and the metal cap film 92 are included. Further, since the insulating films 26 and 39 are not formed, L
The insulating films 28 and 39 made of the ow-K material completely fill the space between the adjacent wirings of the second layer wiring 25 and the third layer wiring 36 in the same layer, and the voids 27 and 40 are not formed even between the closest wirings.
【０１０１】金属キャップ膜９１は、選択タングステン
ＣＶＤ法などによって形成することができる。例えば、
図５に示すように配線溝に埋め込まれた第２層配線２５
を形成した後、六フッ化タングステン（ＷＦ6）および
水素（Ｈ2）ガスを用いたＣＶＤ法により、絶縁膜２１
から露出した第２層配線２５の上面上にタングステン膜
を選択的に堆積することにより、金属キャップ膜９１を
形成する。その後、絶縁膜２１を除去し、バリア絶縁膜
２６を形成することなく、第２層配線２５を覆いかつ隣
接配線間を埋めるように、絶縁膜２８を形成する。金属
キャップ膜９２も金属キャップ膜９１と同様にして形成
することができる。金属キャップ膜９１および９２の他
の材料としては、バリア膜として機能する他の高融点金
属または高融点金属窒化物、例えば窒化チタン（Ｔｉ
Ｎ）または窒化タンタル（ＴａＮ）などを用いることが
できる。他の構造および製造工程は、上記実施の形態１
とほぼ同様であるので、ここでは詳しい説明を省略す
る。The metal cap film 91 can be formed by the selective tungsten CVD method or the like. For example,
As shown in FIG. 5, the second layer wiring 25 embedded in the wiring groove
Then, the insulating film 21 is formed by a CVD method using tungsten hexafluoride (WF 6 ) and hydrogen (H 2 ) gas.
A metal cap film 91 is formed by selectively depositing a tungsten film on the upper surface of the second-layer wiring 25 exposed from above. After that, the insulating film 21 is removed, and the insulating film 28 is formed so as to cover the second layer wiring 25 and fill the space between the adjacent wirings without forming the barrier insulating film 26. The metal cap film 92 can be formed similarly to the metal cap film 91. As another material of the metal cap films 91 and 92, another refractory metal or refractory metal nitride that functions as a barrier film, such as titanium nitride (Ti).
N) or tantalum nitride (TaN) can be used. Other structures and manufacturing steps are the same as those in the first embodiment.
The detailed description is omitted here.
【０１０２】本実施の形態によれば、銅配線としての第
２層配線２５および第３層配線３８において、銅からな
る主導体膜２５ｂおよび３８ｂの底面および側面を窒化
チタンなどからなる導電性バリア膜２５ａおよび３８ａ
で覆い、かつ主導体膜２５ｂおよび３８ｂの上面をタン
グステンなどからなる金属キャップ膜９１および９２で
覆う。このため、第２層配線２５および第３層配線３８
に対してバリア絶縁膜を形成する必要がない。同層配線
間にＣＭＰ面がないのでＴＤＤＢ寿命を向上し、配線間
の絶縁破壊耐性を向上させることができる。これによ
り、半導体装置の信頼性を高めることができる。また、
同層隣接配線間をＬｏｗ−Ｋ材料膜だけで埋めることが
できるので、配線間容量を低減することが可能となる。According to the present embodiment, in the second layer wiring 25 and the third layer wiring 38 as the copper wiring, the bottom surfaces and the side surfaces of the main conductor films 25b and 38b made of copper are made of a conductive barrier made of titanium nitride or the like. Membranes 25a and 38a
And the upper surfaces of the main conductor films 25b and 38b are covered with metal cap films 91 and 92 made of tungsten or the like. Therefore, the second layer wiring 25 and the third layer wiring 38
On the other hand, there is no need to form a barrier insulating film. Since there is no CMP surface between the wires in the same layer, the TDDB life can be improved and the dielectric breakdown resistance between the wires can be improved. Thereby, the reliability of the semiconductor device can be improved. Also,
Since it is possible to fill only the Low-K material film between the adjacent wirings in the same layer, it is possible to reduce the capacitance between the wirings.
【０１０３】（実施の形態７）図３４は、本発明の他の
実施の形態である半導体装置の製造工程中の要部断面図
であり、図１９の工程段階に対応する。(Embodiment 7) FIGS. 34A and 34B are cross-sectional views of the essential part during the manufacturing process of a semiconductor device according to another embodiment of the present invention, corresponding to the process steps in FIG.
【０１０４】本実施の形態では、上記実施の形態１とは
異なり、銅配線のバリア絶縁膜として機能する絶縁膜２
６および３９は、第２層配線２５および第３層配線３８
に対してコンフォーマルに形成されている。すなわち、
絶縁膜２６および３９は、第２層配線２５および第３層
配線３８の形状を反映した形状を有し、それぞれいずれ
の領域においてもほぼ均一な厚みを有している。このた
め、絶縁膜２６のくぼみ部分２７ｄの間口部の寸法は、
くぼみ部分２７ｄの内部の寸法とほぼ同じである。従っ
て、絶縁膜２８は、絶縁膜２８を構成するＬｏｗ−Ｋ材
料が絶縁膜２６のくぼみ部分２７ｄを埋めるように形成
される。すなわち、第２層配線２５の最近接配線間にお
いても、ボイドは形成されず、Ｌｏｗ−Ｋ材料が埋め込
まれる。第３層配線３８についても同様である。他の構
造および製造工程は、上記実施の形態１と同様であるの
で、ここでは詳しい説明を省略する。In this embodiment, unlike the first embodiment, the insulating film 2 which functions as a barrier insulating film for copper wiring is used.
6 and 39 are the second layer wiring 25 and the third layer wiring 38.
Conformally formed against. That is,
The insulating films 26 and 39 have a shape that reflects the shapes of the second-layer wiring 25 and the third-layer wiring 38, and have a substantially uniform thickness in each region. Therefore, the dimension of the opening of the recess 27d of the insulating film 26 is
It is almost the same as the internal size of the recessed portion 27d. Therefore, the insulating film 28 is formed so that the Low-K material forming the insulating film 28 fills the recess 27 d of the insulating film 26. That is, voids are not formed even between the closest wirings of the second layer wiring 25, and the Low-K material is embedded. The same applies to the third layer wiring 38. Since the other structure and manufacturing process are the same as those in the first embodiment, detailed description will be omitted here.
【０１０５】本実施の形態によれば、同層配線間にＣＭ
Ｐ面がないのでＴＤＤＢ寿命を向上し、配線間の絶縁破
壊耐性を向上させることができる。これにより、半導体
装置の信頼性を高めることができる。また、同層隣接配
線間をバリア絶縁膜とＬｏｗ−Ｋ材料膜だけで埋めるの
で、配線間容量を低減することができる。According to the present embodiment, CM is provided between wirings in the same layer.
Since there is no P plane, the TDDB life can be improved and the dielectric breakdown resistance between wirings can be improved. Thereby, the reliability of the semiconductor device can be improved. Further, since the space between the adjacent wirings in the same layer is filled only with the barrier insulating film and the Low-K material film, the capacitance between the wirings can be reduced.
【０１０６】（実施の形態８）図３５は、本発明の他の
実施の形態である半導体装置の製造工程中の要部断面図
であり、図１９の工程段階に対応する。(Embodiment 8) FIGS. 35A and 35B are sectional views of the essential part in the manufacturing process of a semiconductor device according to another embodiment of the present invention, which correspond to the process steps of FIG.
【０１０７】本実施の形態では、上記実施の形態６と同
様に、銅配線のバリア絶縁膜として機能する絶縁膜２６
および３９は形成せず、第２層配線２５および第３層配
線３８の上部に、銅の拡散を防止する導電性バリア膜と
して、例えばタングステンなどからなる金属キャップ膜
９１および９２を形成する。従って、第２層配線２５
は、導電性バリア膜２５ａ、主導体膜２５ｂおよび金属
キャップ膜９１から構成され、第３層配線３８は、導電
性バリア膜３８ａ、主導体膜３８ｂおよび金属キャップ
膜９２から構成される。In this embodiment, the insulating film 26 functioning as the barrier insulating film of the copper wiring is formed similarly to the sixth embodiment.
And 39 are not formed, and metal cap films 91 and 92 made of, for example, tungsten are formed on the second layer wiring 25 and the third layer wiring 38 as conductive barrier films for preventing diffusion of copper. Therefore, the second layer wiring 25
Is composed of a conductive barrier film 25a, a main conductor film 25b and a metal cap film 91, and the third layer wiring 38 is composed of a conductive barrier film 38a, a main conductor film 38b and a metal cap film 92.
【０１０８】しかしながら、本実施の形態では、上記実
施の形態６とは異なり、第２層配線２５および第３層配
線３６の同層隣接配線間、例えば最近接配線間に、ボイ
ド９３および９４が形成される。ボイド９３は、例えば
次のようにして形成することができる。第２層配線２５
を覆うように絶縁膜２０上に絶縁膜２８を形成する際
に、上記実施の形態１の絶縁膜２６の形成工程のよう
に、最近接配線間のカバレージがオーバーハングするよ
うな条件で絶縁膜２８を成膜する。絶縁膜２８は所定の
膜厚になるまで成膜される。これにより、最近接配線間
の絶縁膜２８中にボイド９３が形成される。ボイド９４
も、ボイド９３と同様にして形成することができる。従
って、本実施の形態では、絶縁膜２８および４１は、Ｃ
ＶＤ法で形成され得るＬｏｗ−Ｋ材料からなることが好
ましく、例えば、ＣＶＤ法で形成されたＦＳＧ（ＳｉＯ
Ｆ系材料）膜、ＳｉＯＣ膜またはポーラスシリコン（Ｐ
ｏｌｕｓ−Ｓｉ）系材料膜を用いることができる。ま
た、ＣＶＤ法を用いて形成した酸化シリコン膜を用いる
ことも可能である。他の構造および製造工程は、上記実
施の形態１とほぼ同様であるので、ここでは詳しい説明
を省略する。However, in the present embodiment, unlike the sixth embodiment, voids 93 and 94 are formed between the adjacent wirings in the same layer of the second layer wiring 25 and the third layer wiring 36, for example, between the closest wirings. It is formed. The void 93 can be formed as follows, for example. Second layer wiring 25
When forming the insulating film 28 on the insulating film 20 so as to cover the insulating film 20, the insulating film is formed under the condition that the coverage between the closest wirings overhangs like the forming process of the insulating film 26 of the first embodiment. 28 is deposited. The insulating film 28 is formed to a predetermined thickness. As a result, a void 93 is formed in the insulating film 28 between the closest wirings. Void 94
Can be formed similarly to the void 93. Therefore, in the present embodiment, the insulating films 28 and 41 are made of C
It is preferably made of a Low-K material that can be formed by the VD method, and for example, FSG (SiO formed by the CVD method).
F-based material) film, SiOC film or porous silicon (P
An olus-Si) -based material film can be used. Alternatively, a silicon oxide film formed by a CVD method can be used. Other structures and manufacturing steps are almost the same as those in the first embodiment, and therefore detailed description thereof is omitted here.
【０１０９】本実施の形態によれば、銅配線としての第
２層配線２５および第３層配線３８において、銅からな
る主導体膜２５ｂおよび３８ｂの底面および側面を窒化
チタンなどからなる導電性バリア膜２５ａおよび３８ａ
で覆い、かつ主導体膜２５ｂおよび３８ｂの上面をタン
グステンなどからなる金属キャップ膜９１および９２で
覆う。このため、第２層配線２５および第３層配線３８
に対してバリア絶縁膜を形成する必要がない。同層配線
間にＣＭＰ面がないのでＴＤＤＢ寿命を向上し、配線間
の絶縁破壊耐性を向上させることができる。これによ
り、半導体装置の信頼性を高めることができる。また、
最も容量低減が必要な同層配線における最近接配線間に
ボイドを形成し、ボイド以外の領域はＬｏｗ−Ｋ材料膜
だけで埋めることもできる。これにより、配線間容量を
低減することが可能である。According to the present embodiment, in the second-layer wiring 25 and the third-layer wiring 38 as the copper wiring, the bottom and side surfaces of the main conductor films 25b and 38b made of copper are made of a conductive barrier made of titanium nitride or the like. Membranes 25a and 38a
And the upper surfaces of the main conductor films 25b and 38b are covered with metal cap films 91 and 92 made of tungsten or the like. Therefore, the second layer wiring 25 and the third layer wiring 38
On the other hand, there is no need to form a barrier insulating film. Since there is no CMP surface between the wires in the same layer, the TDDB life can be improved and the dielectric breakdown resistance between the wires can be improved. Thereby, the reliability of the semiconductor device can be improved. Also,
It is also possible to form a void between the closest wirings in the same layer wiring that requires the most capacitance reduction, and fill the region other than the voids only with the Low-K material film. This makes it possible to reduce the capacitance between wirings.
【０１１０】（実施の形態９）図３６は、本発明の他の
実施の形態である半導体装置の製造工程中の要部断面図
であり、図１９の工程段階に対応する。(Ninth Embodiment) FIGS. 36A and 36B are sectional views of the essential part during the manufacturing process of a semiconductor device according to another embodiment of the present invention, corresponding to the process steps of FIG.
【０１１１】本実施の形態では、上記実施の形態６およ
び８と同様に、銅配線のバリア絶縁膜として機能する絶
縁膜２６および３９は形成せず、第２層配線２５および
第３層配線３８の上部に、銅の拡散を防止する導電性バ
リア膜として、例えばタングステンなどからなる金属キ
ャップ膜９１および９２を形成する。従って、第２層配
線２５は、導電性バリア膜２５ａ、主導体膜２５ｂおよ
び金属キャップ膜９１から構成され、第３層配線３８
は、導電性バリア膜３８ａ、主導体膜３８ｂおよび金属
キャップ膜９２から構成される。In this embodiment, as in the sixth and eighth embodiments, the insulating films 26 and 39 functioning as the barrier insulating films of the copper wiring are not formed, and the second layer wiring 25 and the third layer wiring 38 are formed. On the upper part of, the metal cap films 91 and 92 made of, for example, tungsten are formed as a conductive barrier film for preventing the diffusion of copper. Therefore, the second layer wiring 25 is composed of the conductive barrier film 25a, the main conductor film 25b and the metal cap film 91, and the third layer wiring 38.
Is composed of a conductive barrier film 38a, a main conductor film 38b, and a metal cap film 92.
【０１１２】しかしながら、本実施の形態では、上記実
施の形態６とは異なり、第２層配線２５および第３層配
線３６の同層隣接配線間、例えば最近接配線間に、ボイ
ド９６および９９が形成される。ボイド９６は、例えば
次のようにして形成することができる。However, in the present embodiment, unlike the sixth embodiment, voids 96 and 99 are formed between the adjacent wirings in the same layer of the second layer wiring 25 and the third layer wiring 36, for example, between the closest wirings. It is formed. The void 96 can be formed as follows, for example.
【０１１３】第２層配線２５を覆うように絶縁膜２０上
に絶縁膜９５をＣＶＤ法などによって形成する。絶縁膜
９５は、ＣＶＤ法で形成され得るＬｏｗ−Ｋ材料からな
ることが好ましく、例えば、ＣＶＤ法で形成されたＦＳ
Ｇ（ＳｉＯＦ系材料）膜、ＳｉＯＣ膜またはポーラスシ
リコン（Ｐｏｌｕｓ−Ｓｉ）系材料膜を用いることがで
きる。ＣＶＤ法を用いて形成した酸化シリコン膜を用い
ることも可能である。この際、上記実施の形態１の絶縁
膜２６の形成工程のように、最近接配線間のカバレージ
がオーバーハングするような条件で絶縁膜９５を成膜す
る。これにより、第２層配線２５の最近接配線間の絶縁
膜９５に、上記実施の形態１のくぼみ部分２７ａと同様
のくぼみ部分が形成される。それから、絶縁膜９５上に
絶縁膜９７を、塗布法などによって形成する。絶縁膜９
７は、塗布法によって形成され得るＬｏｗ−Ｋ材料から
なることが好ましいが、塗布法以外の方法によって形成
されるＬｏｗ−Ｋ材料を用いることもできる。上記実施
の形態１の絶縁膜２８の形成工程と同様、第２層配線２
５の最近接配線間の絶縁膜９５のくぼみ部分に絶縁膜９
７の材料が、その表面張力などのためにほとんど入り込
まない。このため、本実施の形態においては、上記実施
の形態１と同様、第２層配線２５の最近接配線間に、絶
縁膜９５および９７によって囲まれたボイド９６が形成
される。An insulating film 95 is formed on the insulating film 20 so as to cover the second layer wiring 25 by the CVD method or the like. The insulating film 95 is preferably made of a Low-K material that can be formed by a CVD method, for example, an FS formed by a CVD method.
A G (SiOF based material) film, a SiOC film or a porous silicon (Porus-Si) based material film can be used. It is also possible to use a silicon oxide film formed by the CVD method. At this time, as in the step of forming the insulating film 26 of the first embodiment, the insulating film 95 is formed under the condition that the coverage between the closest wirings overhangs. As a result, a recessed portion similar to the recessed portion 27a of the first embodiment is formed in the insulating film 95 between the closest wirings of the second layer wiring 25. Then, the insulating film 97 is formed on the insulating film 95 by a coating method or the like. Insulation film 9
7 is preferably made of a Low-K material that can be formed by a coating method, but a Low-K material that is formed by a method other than the coating method can also be used. Similar to the step of forming the insulating film 28 of the first embodiment, the second layer wiring 2
The insulating film 9 is formed on the recessed part of the insulating film 95 between the closest wirings of
The material of 7 hardly penetrates due to its surface tension and the like. For this reason, in the present embodiment, as in the first embodiment, the void 96 surrounded by the insulating films 95 and 97 is formed between the closest wirings of the second layer wiring 25.
【０１１４】ボイド９９も、ボイド９６と同様にして形
成することができる。すなわち、絶縁膜９５と同様の材
料からなる絶縁膜９８と、絶縁膜９７と同様の材料から
なる絶縁膜１００とが順に形成されて、第３層配線３６
の最近接配線間に、絶縁膜９８および１００によって囲
まれたボイド９９が形成される。他の構造および製造工
程は、上記実施の形態１とほぼ同様であるので、ここで
は詳しい説明を省略する。The void 99 can be formed in the same manner as the void 96. That is, the insulating film 98 made of the same material as the insulating film 95 and the insulating film 100 made of the same material as the insulating film 97 are sequentially formed, and the third layer wiring 36 is formed.
A void 99 surrounded by the insulating films 98 and 100 is formed between the closest wirings. Other structures and manufacturing steps are almost the same as those in the first embodiment, and therefore detailed description thereof is omitted here.
【０１１５】本実施の形態によれば、銅配線としての第
２層配線２５および第３層配線３８において、銅からな
る主導体膜２５ｂおよび３８ｂの底面および側面を窒化
チタンなどからなる導電性バリア膜２５ａおよび３８ａ
で覆い、かつ主導体膜２５ｂおよび３８ｂの上面をタン
グステンなどからなる金属キャップ膜９１および９２で
覆う。このため、第２層配線２５および第３層配線３８
に対してバリア絶縁膜を形成する必要がない。同層配線
間にＣＭＰ面がないのでＴＤＤＢ寿命を向上し、配線間
の絶縁破壊耐性を向上させることができる。これによ
り、半導体装置の信頼性を高めることができる。また、
最も容量低減が必要な同層配線における最近接配線間に
ボイドを形成し、ボイド以外の領域はＬｏｗ−Ｋ材料膜
だけで埋めることもできる。これにより、配線間容量を
低減することが可能である。According to the present embodiment, in the second-layer wiring 25 and the third-layer wiring 38 as the copper wiring, the bottom and side surfaces of the main conductor films 25b and 38b made of copper are made of a conductive barrier made of titanium nitride or the like. Membranes 25a and 38a
And the upper surfaces of the main conductor films 25b and 38b are covered with metal cap films 91 and 92 made of tungsten or the like. Therefore, the second layer wiring 25 and the third layer wiring 38
On the other hand, there is no need to form a barrier insulating film. Since there is no CMP surface between the wires in the same layer, the TDDB life can be improved and the dielectric breakdown resistance between the wires can be improved. Thereby, the reliability of the semiconductor device can be improved. Also,
It is also possible to form a void between the closest wirings in the same layer wiring that requires the most capacitance reduction, and fill the region other than the voids only with the Low-K material film. This makes it possible to reduce the capacitance between wirings.
【０１１６】以上、本発明者によってなされた発明をそ
の実施の形態に基づき具体的に説明したが、本発明は前
記実施の形態に限定されるものではなく、その要旨を逸
脱しない範囲で種々変更可能であることは言うまでもな
い。Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.
【０１１７】前記実施の形態では、ＣＭＩＳＦＥＴを有
する半導体装置について説明したが、本発明は、これに
限定されるものではなく、銅を主成分とする主導体膜を
含む配線を有する種々の半導体装置に適用することがで
きる。In the above embodiments, the semiconductor device having the CMISFET has been described, but the present invention is not limited to this, and various semiconductor devices having wirings containing a main conductor film containing copper as a main component. Can be applied to.
【０１１８】[0118]
【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば以
下のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
【０１１９】銅を主導体層とする配線間の絶縁破壊耐性
を向上することができる。It is possible to improve the dielectric breakdown resistance between wirings having copper as the main conductor layer.
【０１２０】銅を主導体層とする配線間の容量を低減す
ることができる。It is possible to reduce the capacitance between wirings having copper as the main conductor layer.
【図１】本発明の一実施の形態である半導体装置の製造
工程中の要部平面図である。FIG. 1 is a plan view of a principal part during a manufacturing process of a semiconductor device according to an embodiment of the present invention.
【図２】図１のＡ−Ａ線の断面図である。FIG. 2 is a cross-sectional view taken along the line AA of FIG.
【図３】図２に続く半導体装置の製造工程中における要
部断面図である。FIG. 3 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.
【図４】図３に続く半導体装置の製造工程中における要
部断面図である。FIG. 4 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.
【図５】図４に続く半導体装置の製造工程中における要
部断面図である。5 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.
【図６】図５に続く半導体装置の製造工程中における要
部平面図である。6 is a main-portion plan view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG.
【図７】図６のＡ−Ａ線の断面図である。7 is a cross-sectional view taken along the line AA of FIG.
【図８】図７に続く半導体装置の製造工程中における要
部断面図である。8 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.
【図９】図７に続く半導体装置の製造工程中における要
部断面図である。9 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.
【図１０】図８に続く半導体装置の製造工程中における
要部断面図である。10 is a main-portion cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8;
【図１１】図１０に続く半導体装置の製造工程中におけ
る要部断面図である。11 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.
【図１２】図１１に続く半導体装置の製造工程中におけ
る要部断面図である。12 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.
【図１３】図１２に続く半導体装置の製造工程中におけ
る要部断面図である。FIG. 13 is a main-portion cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 12;
【図１４】図１３に続く半導体装置の製造工程中におけ
る要部断面図である。FIG. 14 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process thereof, which is subsequent to FIG. 13;
【図１５】図１４に続く半導体装置の製造工程中におけ
る要部断面図である。15 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.
【図１６】図１５に続く半導体装置の製造工程中におけ
る要部断面図である。16 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG.
【図１７】図１６に続く半導体装置の製造工程中におけ
る要部断面図である。FIG. 17 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process thereof, which is subsequent to FIG. 16;
【図１８】図１７に続く半導体装置の製造工程中におけ
る要部断面図である。FIG. 18 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process thereof, which is subsequent to FIG. 17;
【図１９】図１８に続く半導体装置の製造工程中におけ
る要部断面図である。FIG. 19 is a main-portion cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 18;
【図２０】本発明の他の実施の形態である半導体装置の
製造工程中の要部断面図である。FIG. 20 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device being another embodiment of the present invention.
【図２１】図２０に続く半導体装置の製造工程中におけ
る要部断面図である。FIG. 21 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process thereof, which is subsequent to FIG. 20;
【図２２】図２１に続く半導体装置の製造工程中におけ
る要部断面図である。FIG. 22 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process thereof, which is subsequent to FIG. 21;
【図２３】図２２に続く半導体装置の製造工程中におけ
る要部断面図である。FIG. 23 is a main-portion cross-sectional view of the semiconductor device during the manufacturing process thereof, which is subsequent to FIG. 22;
【図２４】図２３に続く半導体装置の製造工程中におけ
る要部断面図である。FIG. 24 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 23;
【図２５】図２４に続く半導体装置の製造工程中におけ
る要部断面図である。25 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device subsequent to FIG. 24.
【図２６】本発明の他の実施の形態である半導体装置の
製造工程中の要部断面図である。FIG. 26 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device according to another embodiment of the present invention.
【図２７】本発明の他の実施の形態である半導体装置の
配線パターンを示す平面図である。FIG. 27 is a plan view showing a wiring pattern of a semiconductor device according to another embodiment of the present invention.
【図２８】図２７のＢ−Ｂ線の断面図である。28 is a cross-sectional view taken along the line BB of FIG.
【図２９】本発明の他の実施の形態である半導体装置の
配線パターンを示す平面図である。FIG. 29 is a plan view showing a wiring pattern of a semiconductor device according to another embodiment of the present invention.
【図３０】本発明の他の実施の形態である半導体装置の
配線パターンを示す平面図である。FIG. 30 is a plan view showing a wiring pattern of a semiconductor device according to another embodiment of the present invention.
【図３１】本発明の他の実施の形態である半導体装置の
配線パターンを示す平面図である。FIG. 31 is a plan view showing a wiring pattern of a semiconductor device according to another embodiment of the present invention.
【図３２】本発明の他の実施の形態である半導体装置の
配線パターンを示す平面図である。FIG. 32 is a plan view showing a wiring pattern of a semiconductor device according to another embodiment of the present invention.
【図３３】本発明の他の実施の形態である半導体装置の
製造工程中の要部断面図である。FIG. 33 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device being another embodiment of the present invention.
【図３４】本発明の他の実施の形態である半導体装置の
製造工程中の要部断面図である。FIG. 34 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device being another embodiment of the present invention.
【図３５】本発明の他の実施の形態である半導体装置の
製造工程中の要部断面図である。FIG. 35 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device being another embodiment of the present invention.
【図３６】本発明の他の実施の形態である半導体装置の
製造工程中の要部断面図である。FIG. 36 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor device being another embodiment of the present invention.
１ 半導体基板 ２ 素子分離領域 ３ ｐ型ウエル ４ ｎ型ウエル ５ ｎチャネル型ＭＩＳＦＥＴ ６ ｐチャネル型ＭＩＳＦＥＴ ７ ゲート絶縁膜 ８ ゲート電極 ９ サイドウォール １０ａ ｎ-型半導体領域 １０ｂ ｎ+型半導体領域 １１ａ ｐ-型半導体領域 １１ｂ ｐ+型半導体領域 １２ 絶縁膜 １３ コンタクトホール １４ プラグ １４ａ 窒化チタン膜 １５ 第１層配線 １６，１７ 絶縁膜 １８ スルーホール １９ プラグ ２０〜２２ 絶縁膜 ２３ａ 反射防止膜 ２３ｂ フォトレジストパターン ２４ 配線溝 ２５ 第２層配線 ２５ａ 導電性バリア膜 ２５ｂ 主導体膜 ２６ 絶縁膜 ２７ ボイド ２７ａ くぼみ部分 ２７ｂ 開口部 ２７ｃ ボイド ２８〜３３ 絶縁膜 ３４ａ 反射防止膜 ３４ｂ フォトレジストパターン ３５ 開口部 ３６ａ 反射防止膜 ３６ｂ フォトレジストパターン ３７ 開口部 ３８ 第３層配線 ３８ａ 導電性バリア膜 ３８ｂ 主導体膜 ３９ 絶縁膜 ４０ ボイド ４０ａ くぼみ部分 ４１，４２ 絶縁膜 ５０ａ 反射防止膜 ５０ｂ フォトレジストパターン ５１ 開口部 ５２ａ 反射防止膜 ５２ｂ フォトレジストパターン ５３ 開口部 ６０ 絶縁膜 ６１ 第４層配線 ６２ 絶縁膜 ６３ ボイド ６４〜６９ 絶縁膜 ７０ 第５層配線 ７１〜７７ 絶縁膜 ７８ 第６層配線 ７９ 絶縁膜 ８１ 本体配線 ８２ ダミー配線 ８５ 配線パターン ８６ スルーホール形成位置 ８７ リザーバ部 ９１，９２ 金属キャップ膜 ９３，９４ ボイド ９５ 絶縁膜 ９６ ボイド ９７ 絶縁膜 ９８ 絶縁膜 ９９ ボイド １００ 絶縁膜1 semiconductor substrate 2 isolation region 3 p-type well 4 n-type well 5 n-channel type MISFET 6 p-channel type MISFET 7 gate insulating film 8 the gate electrode 9 side wall 10a n - -type semiconductor region 10b n + -type semiconductor region 11a p - Type semiconductor region 11b p + type semiconductor region 12 Insulating film 13 Contact hole 14 Plug 14a Titanium nitride film 15 First layer wiring 16, 17 Insulating film 18 Through hole 19 Plug 20-22 Insulating film 23a Antireflection film 23b Photoresist pattern 24 Wiring groove 25 Second layer wiring 25a Conductive barrier film 25b Main conductor film 26 Insulating film 27 Void 27a Recessed portion 27b Opening 27c Voids 28 to 33 Insulating film 34a Antireflection film 34b Photoresist pattern 35 Opening 36a Antireflection film 36b Photoresist pattern 37 Opening 38 Third layer wiring 38a Conductive barrier film 38b Main conductor film 39 Insulating film 40 Void 40a Recessed portions 41, 42 Insulating film 50a Antireflection film 50b Photoresist pattern 51 Opening 52a Antireflection film 52b Photoresist pattern 53 Opening Part 60 Insulating film 61 Fourth layer wiring 62 Insulating film 63 Voids 64 to 69 Insulating film 70 Fifth layer wiring 71 to 77 Insulating film 78 Sixth layer wiring 79 Insulating film 81 Main body wiring 82 Dummy wiring 85 Wiring pattern 86 Through hole formation Position 87 Reservoir portion 91, 92 Metal cap film 93, 94 Void 95 Insulating film 96 Void 97 Insulating film 98 Insulating film 99 Void 100 Insulating film
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Claims (23)
配線、 前記配線の上面および側面上と前記第１の絶縁膜上とに
形成され、銅の拡散を抑制または防止する機能を有する
第２の絶縁膜、および、 前記第２の絶縁膜上に形成され、前記第２の絶縁膜の誘
電率より低い誘電率を有する第３の絶縁膜、 を具備することを特徴とする半導体装置。1. A semiconductor substrate, a first insulating film formed on the semiconductor substrate, a wiring formed on the first insulating film and containing copper as a main component, an upper surface and a side surface of the wiring, and the wiring. A second insulating film formed on the first insulating film and having a function of suppressing or preventing copper diffusion; and a dielectric constant of the second insulating film formed on the second insulating film. A semiconductor device comprising: a third insulating film having a lower dielectric constant.
特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein a void is formed between adjacent wirings of the wiring.
ことを特徴とする半導体装置。3. The semiconductor device according to claim 2, wherein the void is formed between the closest wirings of the wirings.
の絶縁膜とで囲まれたボイドが形成されていることを特
徴とする半導体装置。4. The semiconductor device according to claim 1, wherein the second insulating film and the third insulating film are provided between adjacent wirings of the wiring.
A semiconductor device having a void surrounded by the insulating film and the insulating film.
イドが形成されていることを特徴とする半導体装置。5. The semiconductor device according to claim 1, wherein a void is formed in the second insulating film filling the space between the adjacent wirings of the wiring.
で、配線幅広部を有することを特徴とする半導体装置。6. The semiconductor device according to claim 2, wherein the wiring has a wide wiring portion in a region where a through hole is to be formed thereon.
第１の導体膜と、前記第１の導体膜の側面および底面上
に形成され、銅の拡散を抑制または防止する機能を有す
る第２の導体膜と、前記第１の導体膜の上面上に形成さ
れ、銅の拡散を抑制または防止する機能を有する第３の
導体膜とを有する配線、および、 前記配線を覆うように、前記第１の絶縁膜上に形成され
た第２の絶縁膜、 を具備することを特徴とする半導体装置。7. A semiconductor substrate, a first insulating film formed on the semiconductor substrate, a first conductive film formed on the first insulating film and containing copper as a main component, and the first insulating film. A second conductor film formed on the side surface and the bottom surface of the conductor film and having a function of suppressing or preventing the diffusion of copper, and a second conductor film formed on the upper surface of the first conductor film to suppress or prevent the diffusion of copper. A semiconductor device comprising: a wiring having a third conductor film having a function; and a second insulating film formed on the first insulating film so as to cover the wiring.
特徴とする半導体装置。8. The semiconductor device according to claim 7, wherein a void is formed between adjacent wirings of the wiring.
を有する半導体装置であって、前記複数の配線層のうち
の少なくとも１つの配線層は、 第１の絶縁膜上に形成され、銅を主成分として含む第１
の配線、 前記第１の配線の上面および側面上と前記第１の絶縁膜
上とに形成され、銅の拡散を抑制または防止する機能を
有する第２の絶縁膜、および、 前記第２の絶縁膜上に形成され、前記第２の絶縁膜の誘
電率より低い誘電率を有する第３の絶縁膜、 を有し、前記第１の配線の隣接配線間にボイドが形成さ
れていることを特徴とする半導体装置。9. A semiconductor device having a plurality of wiring layers formed on a semiconductor substrate, wherein at least one wiring layer of the plurality of wiring layers is formed on a first insulating film and is formed of copper. First containing as a main component
Wiring, a second insulating film formed on the upper surface and the side surface of the first wiring and on the first insulating film, and having a function of suppressing or preventing the diffusion of copper, and the second insulating film. A third insulating film formed on the film and having a dielectric constant lower than that of the second insulating film, wherein voids are formed between adjacent wires of the first wire. Semiconductor device.
は、 開口部を有する第４の絶縁膜、 前記開口部を埋め込むように形成され、銅を主成分とし
て含む第２の配線、 前記第４の絶縁膜および前記配線上に形成され、銅の拡
散を抑制または防止する機能を有する第５の絶縁膜、お
よび、 前記第５の絶縁膜上に形成され、前記第５の絶縁膜の誘
電率より低い誘電率を有する第６の絶縁膜、 を有することを特徴とする半導体装置。10. The semiconductor device according to claim 9, wherein at least one other wiring layer of the plurality of wiring layers is formed so as to fill the opening with a fourth insulating film having an opening. A second wiring containing copper as a main component, a fifth insulating film formed on the fourth insulating film and the wiring, the fifth insulating film having a function of suppressing or preventing the diffusion of copper, and the fifth insulating film. A sixth insulating film, which is formed on the film and has a dielectric constant lower than that of the fifth insulating film.
配線、 前記第１の絶縁膜上に、前記配線に隣接して設けられた
導体部分、 前記配線の上面および側面上と、前記導体部分の上面お
よび側面上と、前記第１の絶縁膜上とに形成され、銅の
拡散を抑制または防止する機能を有する２の絶縁膜、お
よび、 前記第２の絶縁膜上に形成され、前記第２の絶縁膜の誘
電率より低い誘電率を有する第３の絶縁膜、 を具備し、 前記配線と前記導体部分との間にボイドが形成されてい
ることを特徴とする半導体装置。11. A semiconductor substrate, a first insulating film formed on the semiconductor substrate, a wiring formed on the first insulating film and containing copper as a main component, and a wiring formed on the first insulating film. A conductor portion provided adjacent to the wiring, formed on the upper surface and the side surface of the wiring, on the upper surface and the side surface of the conductor portion, and on the first insulating film to suppress or prevent the diffusion of copper. A second insulating film having a function of: and a third insulating film formed on the second insulating film and having a dielectric constant lower than that of the second insulating film. A semiconductor device, wherein a void is formed between the conductor portion and the conductor portion.
て、 前記導体部分が、前記配線と同時に形成され、かつ半導
体装置の配線としては機能しない導体パターンであるこ
とを特徴とする半導体装置。12. The semiconductor device according to claim 11, wherein the conductor portion is a conductor pattern that is formed at the same time as the wiring and does not function as a wiring of the semiconductor device.
半導体装置の製造方法； （ａ）半導体基板を準備する工程、（ｂ）前記半導体基
板上に第１の絶縁膜を形成する工程、（ｃ）前記第１の
絶縁膜上に銅を主成分として含む配線を形成する工程、
（ｄ）銅の拡散を抑制または防止する機能を有する第２
の絶縁膜を、その材料で前記配線の隣接配線間が満たさ
れないように、前記配線の上面および側面上と前記第１
の絶縁膜上とに形成する工程、および、（ｅ）前記第２
の絶縁膜の誘電率より低い誘電率を有する第３の絶縁膜
を、前記第２の絶縁膜上に形成する工程。13. A method of manufacturing a semiconductor device, comprising: (a) preparing a semiconductor substrate; (b) forming a first insulating film on the semiconductor substrate; c) a step of forming a wiring containing copper as a main component on the first insulating film,
(D) Second having a function of suppressing or preventing the diffusion of copper
The insulating film on the upper surface and side surfaces of the wiring and the first wiring so that the material does not fill the space between the adjacent wirings.
And (e) the second step.
Forming a third insulating film having a dielectric constant lower than that of the insulating film on the second insulating film.
法において、 前記（ｅ）工程では、前記配線の隣接配線間に前記第２
の絶縁膜と前記第３の絶縁膜とで囲まれたボイドが形成
されることを特徴とする半導体装置の製造方法。14. The method of manufacturing a semiconductor device according to claim 13, wherein in the step (e), the second wiring is provided between adjacent wirings of the wirings.
A method of manufacturing a semiconductor device, characterized in that a void surrounded by the third insulating film and the second insulating film is formed.
法において、 前記（ｅ）工程では、前記配線の最近接配線間に前記第
２の絶縁膜と前記第３の絶縁膜とで囲まれたボイドが形
成されることを特徴とする半導体装置の製造方法。15. The method of manufacturing a semiconductor device according to claim 13, wherein in the step (e), the wiring is surrounded by the second insulating film and the third insulating film between the closest wirings of the wirings. A method of manufacturing a semiconductor device, wherein voids are formed.
法において、 前記（ｄ）工程では、前記配線の隣接配線間を埋める前
記第２の絶縁膜中にボイドが形成されることを特徴とす
る半導体装置の製造方法。16. The method of manufacturing a semiconductor device according to claim 13, wherein in the step (d), a void is formed in the second insulating film filling a space between adjacent wirings of the wiring. Manufacturing method of semiconductor device.
法において、 前記（ｄ）工程では、前記配線の隣接配線間において、
対向する配線側面の上方での前記第２の絶縁膜の堆積速
度が下方での堆積速度より大きくなるように前記第２の
絶縁膜が形成されることを特徴とする半導体装置の製造
方法。17. The method of manufacturing a semiconductor device according to claim 14, wherein in the step (d), between adjacent wirings of the wiring,
A method of manufacturing a semiconductor device, wherein the second insulating film is formed such that a deposition rate of the second insulating film above a side surface of the wiring facing each other is higher than a deposition rate of the second insulating film below.
法において、 前記（ｅ）工程では、前記第２の絶縁膜で覆われた前記
配線の隣接配線間が前記第３の絶縁膜で満たされないこ
とによって、前記隣接配線間に前記第２の絶縁膜と前記
第３の絶縁膜とで囲まれたボイドが形成されることを特
徴とする半導体装置の製造方法。18. The method of manufacturing a semiconductor device according to claim 13, wherein in the step (e), a space between adjacent wirings of the wiring covered with the second insulating film is not filled with the third insulating film. As a result, a void surrounded by the second insulating film and the third insulating film is formed between the adjacent wirings.
法において、 前記（ｃ）工程は、 前記第１の絶縁膜上に第４の絶縁膜を形成する工程、 前記第４絶縁膜に開口部を形成する工程、 前記第４絶縁膜の前記開口部内に、銅を主成分として含
む配線を形成する工程、および、 前記第４の絶縁膜を除去する工程、 を有することを特徴とする半導体装置の製造方法。19. The method of manufacturing a semiconductor device according to claim 13, wherein the step (c) is a step of forming a fourth insulating film on the first insulating film, and an opening is formed in the fourth insulating film. A step of forming a wiring containing copper as a main component in the opening of the fourth insulating film, and a step of removing the fourth insulating film. Manufacturing method.
法において、 前記第４の絶縁膜は、還元性プラズマ処理によりエッチ
ングされ得る材料を含み、 前記第４の絶縁膜を除去する工程では、還元性プラズマ
処理により前記第４の絶縁膜が除去されることを特徴と
する半導体装置の製造方法。20. The method of manufacturing a semiconductor device according to claim 19, wherein the fourth insulating film contains a material that can be etched by a reducing plasma treatment, and the fourth insulating film is reduced in the step of removing the fourth insulating film. A method for manufacturing a semiconductor device, wherein the fourth insulating film is removed by a reactive plasma treatment.
半導体装置の製造方法； （ａ）半導体基板を準備する工程、（ｂ）前記半導体基
板上に第１の絶縁膜を形成する工程、（ｃ）前記第１の
絶縁膜上に第２の絶縁膜を形成する工程、（ｄ）前記第
２の絶縁膜に開口部を形成する工程、（ｅ）前記開口部
の底部および側壁上を含む前記第２の絶縁膜上に、銅の
拡散を抑制または防止する機能を有する第１の導体膜を
形成する工程、（ｆ）前記開口部を埋めるように、前記
第１の導体膜上に銅を主成分として含む第２の導体膜を
形成する工程、（ｇ）前記開口部内の前記第１および第
２の導体膜が残され、それ以外の前記第１および第２の
導体膜が除去されるように、前記第１および第２の導体
膜を研磨する工程、（ｈ）前記開口部内に残された前記
第１および第２の導体膜上に、銅の拡散を抑制または防
止する機能を有する第３の導体膜を選択的に形成する工
程、（ｉ）前記第２の絶縁膜を除去する工程、および
（ｊ）前記第１、第２および第３の導体膜からなる配線
を覆うように、第３の絶縁膜を前記第１の絶縁膜上に形
成する工程。21. A method of manufacturing a semiconductor device, comprising: (a) preparing a semiconductor substrate; (b) forming a first insulating film on the semiconductor substrate; c) including a step of forming a second insulating film on the first insulating film, (d) a step of forming an opening in the second insulating film, and (e) including a bottom and a side wall of the opening. Forming a first conductor film having a function of suppressing or preventing diffusion of copper on the second insulating film; (f) copper on the first conductor film so as to fill the opening. Forming a second conductor film containing as a main component, (g) removing the first and second conductor films in the opening and removing the other first and second conductor films. Polishing the first and second conductor films, so that (h) it is left in the opening. A step of selectively forming a third conductor film having a function of suppressing or preventing the diffusion of copper on the first and second conductor films, (i) a step of removing the second insulating film, And (j) a step of forming a third insulating film on the first insulating film so as to cover the wiring made of the first, second and third conductor films.
法において、 前記（ｊ）工程では、前記配線の隣接配線間を埋める前
記第３の絶縁膜中にボイドが形成されることを特徴とす
る半導体装置の製造方法。22. The method of manufacturing a semiconductor device according to claim 21, wherein in the step (j), a void is formed in the third insulating film filling a space between adjacent wirings of the wiring. Manufacturing method of semiconductor device.
法において、 前記（ｊ）工程では、 前記第３の絶縁膜の材料で前記配線の隣接配線間が満た
されないように、前記配線の上面および側面上と前記第
１の絶縁膜上とに前記第３の絶縁膜が形成され、 前記（ｊ）工程の後に、更に、 前記配線の隣接配線間に前記第３の絶縁膜と第４の絶縁
膜とで囲まれたボイドが形成されるように、前記第３の
絶縁膜上に第４の絶縁膜を形成する工程、 を有することを特徴とする半導体装置の製造方法。23. The method of manufacturing a semiconductor device according to claim 21, wherein in the step (j), the material of the third insulating film does not fill the space between adjacent wirings of the wirings and the upper surface of the wirings. The third insulating film is formed on the side surface and on the first insulating film, and after the step (j), the third insulating film and the fourth insulating film are further provided between adjacent wirings of the wiring. And a step of forming a fourth insulating film on the third insulating film so that a void surrounded by the film is formed.
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| US10/387,504 US7042095B2 (en) | 2002-03-29 | 2003-03-14 | Semiconductor device including an interconnect having copper as a main component |
| TW092106945A TW200404353A (en) | 2002-03-29 | 2003-03-27 | A semiconductor device and a method of manufacturing the same |
| KR10-2003-0019462A KR20030078750A (en) | 2002-03-29 | 2003-03-28 | Semiconductor device and method of manufacturing the same |
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