JP2003243517A - Semiconductor device having resistor element and manufacturing method therefor - Google Patents
Semiconductor device having resistor element and manufacturing method thereforInfo
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- JP2003243517A JP2003243517A JP2002038124A JP2002038124A JP2003243517A JP 2003243517 A JP2003243517 A JP 2003243517A JP 2002038124 A JP2002038124 A JP 2002038124A JP 2002038124 A JP2002038124 A JP 2002038124A JP 2003243517 A JP2003243517 A JP 2003243517A
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- Prior art keywords
- oxide film
- semiconductor device
- pattern
- resistance element
- manufacturing
- Prior art date
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- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置とその
製造方法に関し、特に抵抗素子を有する半導体装置及び
その製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a resistance element and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】機器の小型化に伴い、トランジスタ等の
半導体装置もバイアス抵抗等の周辺部品を同一半導体基
板上に形成する、小型化が進んでいる。2. Description of the Related Art With the miniaturization of equipment, semiconductor devices such as transistors are also miniaturized by forming peripheral parts such as bias resistors on the same semiconductor substrate.
【０００３】図６は、従来のトランジスタ等半導体装置
の上面から見たパターンを示し、半導体装置１の限られ
たエリアに、ポリシリコンからなる所定幅のパターン３
が配線されている。抵抗素子２に相当する部分にはパタ
ーン３が所定の間隔を保って、つづら折り状に配列形成
されており、パターン３の断面積および長さにより所望
の抵抗値を実現させている。FIG. 6 shows a pattern of a conventional semiconductor device such as a transistor as seen from the upper surface, and a pattern 3 of a predetermined width made of polysilicon is provided in a limited area of the semiconductor device 1.
Is wired. Patterns 3 are formed in a zigzag pattern at a portion corresponding to the resistance element 2 at a predetermined interval, and a desired resistance value is realized by the cross-sectional area and length of the pattern 3.
【０００４】また、図７（ａ）乃至（ｅ）は、従来の半
導体装置の抵抗素子２の製造方法を工程順に示す図であ
り、（ａ）乃至（ｃ）は断面図、（ｄ）乃至（ｅ）は、
上面図である。図に示されるように、まず、半導体基板
１０上に絶縁膜として酸化膜１１を形成し（ａ）、次に
酸化膜１１上にポリシリコン膜１２を蒸着させ（ｂ）、
次にポリシリコン膜１２にＮ型もしくはＰ型不純物イオ
ンを注入１３し（ｃ）、ポリシリコン膜１２上にレジス
ト膜１４をパターニングし（ｄ）、レジスト膜１４をマ
スクとして選択的にポリシリコン膜１２をエッチングす
ることにより所望のパターンを形成し、レジスト膜を除
去する（ｅ）。以上の工程により、図６に示される抵抗
素子２が形成される。7A to 7E are views showing a method of manufacturing the resistance element 2 of the conventional semiconductor device in the order of steps, FIGS. 7A to 7C are sectional views, and FIGS. (E) is
It is a top view. As shown in the figure, first, an oxide film 11 is formed as an insulating film on the semiconductor substrate 10 (a), and then a polysilicon film 12 is deposited on the oxide film 11 (b),
Then, N-type or P-type impurity ions are implanted 13 into the polysilicon film 12 (c), the resist film 14 is patterned on the polysilicon film 12 (d), and the polysilicon film is selectively used as a mask. A desired pattern is formed by etching 12 and the resist film is removed (e). Through the above steps, the resistance element 2 shown in FIG. 6 is formed.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、従来の
抵抗素子を有する半導体装置では、外部から静電気等の
高い電圧が印加された場合、図８に示されるように抵抗
素子２０を形成するパターン２１のコーナー部であるＡ
−Ａ’間の電位差が大きくなり、電流が抵抗素子のパタ
ーンを通らずに、Ａ−Ａ’間を最短距離で流れるため、
半導体装置が破壊を起こしてしまうという問題がある。
また、サージ耐圧とＡ−Ａ’間距離とは、絶縁酸化膜の
特性等も関係するが、基本的に比例関係にあり、サージ
耐圧の向上を図る方法としては、コーナー部のパターン
間のＡ−Ａ’間距離を大きくすれば良いが、半導体装置
上の抵抗素子を形成できるエリアには、限界がある。ま
た、Ａ−Ａ’間距離を大きくとるには、パターンの厚み
ｔ１を大きくし、幅ｔ２を狭くする方法が考えられる
が、段切れ等の信頼性上の問題が、新たに発生する。However, in the conventional semiconductor device having the resistance element, when a high voltage such as static electricity is applied from the outside, the pattern 21 forming the resistance element 20 is formed as shown in FIG. A which is the corner
-The potential difference between A'becomes large, and the current flows in the shortest distance between AA 'without passing through the pattern of the resistance element.
There is a problem that the semiconductor device is destroyed.
Further, the surge withstand voltage and the AA ′ distance are basically in a proportional relationship although the characteristics of the insulating oxide film and the like are related, and as a method for improving the surge withstand voltage, A between the patterns at the corners is used. Although it is sufficient to increase the −A ′ distance, there is a limit to the area where the resistance element on the semiconductor device can be formed. Further, in order to increase the distance between AA ′, a method of increasing the pattern thickness t1 and narrowing the width t2 can be considered, but a reliability problem such as step breakage newly occurs.
【０００６】本発明は、上記問題に鑑み、半導体装置内
の抵抗素子の占有面積を広げることなく、また、安定し
た品質を確保したままで、サージ耐圧を向上させること
ができる抵抗素子を有する半導体装置およびその製造方
法を提供することを目的とする。In view of the above problems, the present invention is a semiconductor device having a resistance element capable of improving the surge withstand voltage without increasing the area occupied by the resistance element in the semiconductor device and while maintaining stable quality. An object of the present invention is to provide a device and a manufacturing method thereof.
【０００７】[0007]
【課題を解決するための手段】前記目的を達成するため
に、本発明の半導体装置は、抵抗素子を形成するつづら
折り状に形成された隣り合うパターンの少なくとも一方
側が他方側と非同一高さとなるように階段状の酸化膜上
に形成されたことを特徴としている。このように、抵抗
素子のパターンの１部を立体化することで、電位差が大
きいコーナー部間の距離を平面上にパターンを形成する
よりも、大きくとることができるため、半導体装置内の
抵抗素子の占有面積を広げることなく、サージ耐圧を向
上させることができる。In order to achieve the above object, in a semiconductor device of the present invention, at least one side of a zigzag-shaped adjoining pattern forming a resistance element has a height that is not the same as the other side. It is characterized in that it is formed on the stepped oxide film. As described above, by making a part of the pattern of the resistance element three-dimensional, the distance between the corner portions having a large potential difference can be made larger than that in the case where the pattern is formed on a plane, and thus the resistance element in the semiconductor device is formed. The surge withstand voltage can be improved without expanding the area occupied by the surge voltage.
【０００８】また本発明の半導体装置の抵抗素子は、半
導体基板上に第１の酸化膜を形成する工程と、前記酸化
膜上に、フォトレジストを所定の形状にパターニングし
た後、前記第１の酸化膜をエッチングする工程と、表面
に第２の酸化膜を形成する工程と、前記第２の酸化膜上
に、フォトレジストを所定の形状にパターニングした
後、前記第２の酸化膜をエッチングする工程と、フォト
レジストの形状を変え、前記第２の酸化膜を形成する工
程および前記第２の酸化膜をエッチングする工程を繰り
返すことにより、複数の段差を有する酸化膜を形成する
工程と、前記複数の段差を有する酸化膜上にポリシリコ
ンを蒸着する工程と、前記ポリシリコンにイオン注入
し、フォトレジストを所定の形状にパターニングした
後、前記ポリシリコンをエッチングする工程とを有して
いる。この工程により安定した品質の半導体装置を製造
することができる。Further, in the resistance element of the semiconductor device of the present invention, the first oxide film is formed on the semiconductor substrate, and the first oxide film is patterned on the oxide film into a predetermined shape, and then the first oxide film is formed. Etching the oxide film, forming a second oxide film on the surface, and patterning a photoresist on the second oxide film into a predetermined shape, and then etching the second oxide film. A step of forming an oxide film having a plurality of steps by repeating a step, a step of changing the shape of the photoresist, a step of forming the second oxide film, and a step of etching the second oxide film; A step of depositing polysilicon on an oxide film having a plurality of steps, and ion implantation into the polysilicon, patterning a photoresist into a predetermined shape, and then removing the polysilicon. And a step of etching. Through this step, a semiconductor device of stable quality can be manufactured.
【０００９】[0009]
【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照しながら詳細に説明する。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
【００１０】図１は本発明の半導体装置に係る抵抗素子
パターン３０を側面から見た断面図である。抵抗素子パ
ターン３０は、半導体基板３３上に形成された階段状の
酸化膜３１上に、厚さが例えば０．５μｍからなる最下
段のパターン３０ａ、階段状のパターン３０ｂ、最上段
のパターン３０ｃから形成されている。FIG. 1 is a side sectional view of a resistance element pattern 30 according to the semiconductor device of the present invention. The resistive element pattern 30 includes a lowermost pattern 30a, a stepwise pattern 30b, and an uppermost pattern 30c each having a thickness of, for example, 0.5 μm on the stepwise oxide film 31 formed on the semiconductor substrate 33. Has been formed.
【００１１】図２は、本発明の半導体装置の抵抗素子部
パターン３５を上面から見た図である。抵抗素子部パタ
ーン３５は、例えば１０μｍ幅のポリシリコンからなる
最下段のパターン３０ａと最上段のパターン３０ｃと階
段状パターン３０ｂにより、例えば１０μｍの間隔を設
けて、つづら折り状に配列形成される。FIG. 2 is a top view of the resistance element portion pattern 35 of the semiconductor device of the present invention. The resistive element portion pattern 35 is formed in a zigzag shape, for example, with a lowermost pattern 30a made of polysilicon having a width of 10 μm, an uppermost pattern 30c, and a staircase pattern 30b at intervals of, for example, 10 μm.
【００１２】図３は、本発明の半導体装置の抵抗素子部
パターン３５を斜め方向から見た図である。階段状パタ
ーン３０ｂにより、高電圧が印加された場合の電流経路
の距離Ｂ−Ｂ’が、従来例の図８における平面状に形成
された場合の距離Ａ−Ａ’より、長くとることができる
ため、サージ耐圧を向上させることができる。FIG. 3 is a view of the resistance element portion pattern 35 of the semiconductor device of the present invention as seen from an oblique direction. Due to the step-like pattern 30b, the distance BB 'of the current path when a high voltage is applied can be made longer than the distance A-A' of the conventional example formed in a plane in FIG. Therefore, the surge withstand voltage can be improved.
【００１３】なお、階段状パターン３０ｂの段数、抵抗
素子部パターン幅、間隔は一例であり、本発明はこれに
限定されるものではない。The number of steps of the staircase pattern 30b, the width of the resistive element pattern, and the interval are merely examples, and the present invention is not limited to these.
【００１４】次に本発明における半導体装置の特徴であ
る抵抗素子パターンの製造方法について、図を参照しな
がら説明する。図４（ａ）乃至（ｆ）、図５（ｇ）乃至
（ｋ）は、抵抗素子パターンの階段状の部分の製造方法
を示す断面図である。まず、半導体基板５０上に第１酸
化膜５１を、例えば０．４μｍの厚さに形成する（図４
（ａ））。次に、第１酸化膜５１上に、フォトレジスト
５２をパターニングし（図４（ｂ））、フォトレジスト
５２をマスクとして、選択的に第１酸化膜５１をエッチ
ングし、１段の段差を有する酸化膜５３を形成する（図
４（ｃ））。次に、半導体基板５０および酸化膜５３上
に第２酸化膜５４を、例えば０．４μｍの厚さに形成す
る（図４（ｄ））。次に、第２酸化膜５４上に、フォト
レジスト５５をパターニングし（図４（ｅ））、フォト
レジスト５５をマスクとして、選択的に第２酸化膜５４
をエッチングし、２段の段差を有する酸化膜５６を形成
する（図４（ｆ））。更に、半導体基板５０及び酸化膜
５６上に第３酸化膜５７を、例えば０．４μｍの厚さに
形成する（図５（ｇ））。次に、第３酸化膜５７上に、
フォトレジスト５８をパターニングし（図５（ｈ））、
フォトレジスト５８をマスクとして、第３酸化膜５７を
選択的に除去し、３段の段差を有する酸化膜５９を形成
する（図５（ｉ））。次に、半導体基板５０及び酸化膜
５９上に酸化膜６０を、例えば０．４μｍの厚さに形成
する（図５（ｊ））。後は、従来工程と同等の工程によ
り、抵抗素子パターンを形成する（図５（ｋ））。Next, a method of manufacturing a resistance element pattern, which is a feature of the semiconductor device of the present invention, will be described with reference to the drawings. FIGS. 4A to 4F and FIGS. 5G to 5K are cross-sectional views showing a method for manufacturing a stepped portion of the resistance element pattern. First, the first oxide film 51 is formed on the semiconductor substrate 50 to have a thickness of 0.4 μm, for example (FIG. 4).
(A)). Next, a photoresist 52 is patterned on the first oxide film 51 (FIG. 4B), and the first oxide film 51 is selectively etched using the photoresist 52 as a mask to form a step. The oxide film 53 is formed (FIG. 4C). Then, a second oxide film 54 is formed on the semiconductor substrate 50 and the oxide film 53 to have a thickness of 0.4 μm, for example (FIG. 4D). Next, a photoresist 55 is patterned on the second oxide film 54 (FIG. 4E), and the second oxide film 54 is selectively used with the photoresist 55 as a mask.
Is etched to form an oxide film 56 having two steps (FIG. 4 (f)). Further, a third oxide film 57 is formed on the semiconductor substrate 50 and the oxide film 56 to have a thickness of 0.4 μm, for example (FIG. 5G). Next, on the third oxide film 57,
Patterning the photoresist 58 (FIG. 5 (h)),
The third oxide film 57 is selectively removed by using the photoresist 58 as a mask to form an oxide film 59 having three steps (FIG. 5 (i)). Next, the oxide film 60 is formed on the semiconductor substrate 50 and the oxide film 59 to have a thickness of 0.4 μm, for example (FIG. 5 (j)). After that, a resistance element pattern is formed by the same process as the conventional process (FIG. 5K).
【００１５】以上説明した半導体装置の製造方法により
階段状の抵抗素子パターンが形成される。A stepwise resistance element pattern is formed by the method of manufacturing a semiconductor device described above.
【００１６】なお、ここでは、階段状パターンを３段で
説明したが、これに限るものではなく、また、酸化膜の
厚さについても、一例であり、これに限るものではな
い。Here, the staircase-like pattern has been described in three stages, but the present invention is not limited to this, and the thickness of the oxide film is also an example, and the present invention is not limited to this.
【００１７】[0017]
【発明の効果】以上詳述したように、本発明の半導体装
置によれば、つづら折り状に形成された抵抗素子パター
ンの隣り合うパターンの一方を階段状パターンにより立
体化構造としたことにより、電位差の大きいコーナー部
間の距離を大きくとることができるため、占有面積を増
大させることなく、静電気等の高電圧に対するサージ耐
圧を向上させることができる。As described above in detail, according to the semiconductor device of the present invention, one of the adjoining patterns of the resistance element pattern formed in a zigzag shape has a three-dimensional structure with a stepped pattern, so that the potential difference Since it is possible to increase the distance between the large corner portions, it is possible to improve the surge withstand voltage against a high voltage such as static electricity without increasing the occupied area.
【００１８】また、本発明の半導体装置の製造方法によ
れば、抵抗素子パターンを複数の酸化膜形成工程を繰り
返すことにより、階段状の酸化膜を形成でき、その上に
抵抗パターンを形成することにより、段切れに強い抵抗
パターンを形成することができる。Further, according to the method of manufacturing a semiconductor device of the present invention, a stepwise oxide film can be formed by repeating a plurality of oxide film forming steps for the resistance element pattern, and the resistance pattern is formed thereon. This makes it possible to form a resistance pattern that is resistant to step breakage.
【図１】本発明の半導体装置の抵抗素子の側面から見た
断面図FIG. 1 is a cross-sectional view of a resistance element of a semiconductor device of the present invention seen from a side surface.
【図２】本発明の半導体装置の抵抗素子を上面から見た
図FIG. 2 is a view of a resistance element of the semiconductor device of the present invention seen from above.
【図３】本発明の半導体装置の抵抗素子を斜めから見た
図FIG. 3 is a diagram of a resistance element of a semiconductor device according to the present invention seen obliquely.
【図４】（ａ）〜（ｆ）は本発明の半導体装置の抵抗素
子の製造方法を示す断面図4A to 4F are cross-sectional views showing a method of manufacturing a resistance element of a semiconductor device of the present invention.
【図５】（ｇ）〜（ｋ）は本発明の半導体装置の抵抗素
子の製造方法を示す断面図5 (g) to 5 (k) are cross-sectional views showing a method for manufacturing a resistance element of a semiconductor device of the present invention.
【図６】従来の半導体装置の上面から見たパターン図FIG. 6 is a pattern diagram seen from the upper surface of a conventional semiconductor device.
【図７】（ａ）〜（ｅ）は従来の半導体装置の抵抗素子
の製造方法を示す図7A to 7E are diagrams showing a conventional method for manufacturing a resistance element of a semiconductor device.
【図８】従来の半導体装置の抵抗素子を斜めから見た図FIG. 8 is a view of a resistance element of a conventional semiconductor device seen from an oblique direction.
１ 半導体装置 ２、３５ 抵抗素子 ３ パターン １０ 半導体基板 １１ 酸化膜 １２ ポリシリコン膜 １３ イオン注入 １４ レジスト膜 ３０ａ 最下段パターン ３０ｂ 階段状パターン ３０ｃ 最上段パターン 1 Semiconductor device 2,35 resistance element 3 patterns 10 Semiconductor substrate 11 Oxide film 12 Polysilicon film 13 Ion implantation 14 Resist film 30a bottom pattern 30b staircase pattern 30c uppermost pattern
Claims (2)
からなる所定幅のパターンが所定の間隔を設けて、つづ
ら折り状に形成された抵抗素子を有する半導体装置にお
いて、前記抵抗素子を形成するつづら折り状に形成され
た隣り合うパターンの少なくとも一方側が他方側と非同
一高さとなるように階段状の酸化膜上に形成されたこと
を特徴とする半導体装置。1. A semiconductor device having a resistance element in which a pattern of polysilicon having a predetermined width is formed in a zigzag shape on an oxide film on a semiconductor substrate at a predetermined interval, and the resistance element is formed. A semiconductor device, wherein at least one side of adjacent patterns formed in a zigzag shape is formed on a stepwise oxide film such that at least one side is not flush with the other side.
程と、前記酸化膜上に、フォトレジストを所定の形状に
パターニングした後、前記第１の酸化膜をエッチングす
る工程と、表面に第２の酸化膜を形成する工程と、前記
第２の酸化膜上に、フォトレジストを所定の形状にパタ
ーニングした後、前記第２の酸化膜をエッチングする工
程と、フォトレジストの形状を変え、前記第２の酸化膜
を形成する工程および前記第２の酸化膜をエッチングす
る工程を繰り返すことにより、複数の段差を有する酸化
膜を形成する工程と、前記複数の段差を有する酸化膜上
にポリシリコンを蒸着する工程と、前記ポリシリコンに
イオン注入し、フォトレジストを所定の形状にパターニ
ングした後、前記ポリシリコンをエッチングする工程に
より抵抗素子を形成することを特徴とする半導体装置の
製造方法。2. A step of forming a first oxide film on a semiconductor substrate, a step of patterning a photoresist on the oxide film in a predetermined shape, and then etching the first oxide film, and a surface. Forming a second oxide film on the second oxide film, patterning a photoresist on the second oxide film into a predetermined shape, and then etching the second oxide film, and changing the shape of the photoresist. A step of forming an oxide film having a plurality of steps by repeating the step of forming the second oxide film and the step of etching the second oxide film; and a step of forming an oxide film having a plurality of steps on the oxide film having a plurality of steps. A resistance element is formed by a step of depositing polysilicon, a step of implanting ions into the polysilicon, patterning a photoresist into a predetermined shape, and then etching the polysilicon. The method of manufacturing a semiconductor device which is characterized in that.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002038124A JP2003243517A (en) | 2002-02-15 | 2002-02-15 | Semiconductor device having resistor element and manufacturing method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002038124A JP2003243517A (en) | 2002-02-15 | 2002-02-15 | Semiconductor device having resistor element and manufacturing method therefor |
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| JP2003243517A true JP2003243517A (en) | 2003-08-29 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010038174A1 (en) | 2008-09-30 | 2010-04-08 | Nxp B.V. | Robust high aspect ratio semiconductor device |
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2002
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010038174A1 (en) | 2008-09-30 | 2010-04-08 | Nxp B.V. | Robust high aspect ratio semiconductor device |
| US8809982B2 (en) | 2008-09-30 | 2014-08-19 | Nxp B.V. | Robust high aspect ratio semiconductor device |
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