JP2003224357A - Thin film multilayer wiring substrate and its manufacturing method - Google Patents
Thin film multilayer wiring substrate and its manufacturing methodInfo
- Publication number
- JP2003224357A JP2003224357A JP2002020436A JP2002020436A JP2003224357A JP 2003224357 A JP2003224357 A JP 2003224357A JP 2002020436 A JP2002020436 A JP 2002020436A JP 2002020436 A JP2002020436 A JP 2002020436A JP 2003224357 A JP2003224357 A JP 2003224357A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductor
- insulating layer
- side wall
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は，薄膜多層配線基板
に関し、特に高周波の信号伝送に適した薄膜多層配線基
板とその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film multilayer wiring board, and more particularly to a thin film multilayer wiring board suitable for high frequency signal transmission and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】電子機器は高密度実装化が進展し、電子
機器の信号速度も高速化している。このような状況下に
あって、信号伝達におけるノイズ対策が重要になってい
る。2. Description of the Related Art Electronic devices have been developed in high-density packaging, and the signal speed of electronic devices has been increased. Under such circumstances, measures against noise in signal transmission have become important.
【０００３】そうしたノイズ対策のひとつとして、厚膜
多層印刷配線板において同軸配線を形成することが行わ
れている（特開平４−２６７５８６号公報）。この同軸
配線パターンの形成方法では、アルミナセラミックス等
のべース基板の表面に下部導体パターンを厚膜印刷法等
により形成後、その上に感光性絶縁膜を形成する。この
絶縁膜を乾燥後、ホトリソグラフィ技術により絶縁膜に
バイアホールを形成し、このバイアホールに導体ペース
トを充填し焼結して側方導体を形成後に、薄膜めっき法
により絶縁膜上に信号配線パターンを形成する。引き続
き同様の工程で絶縁膜の形成，バイアホールの形成，導
体ペーストによる側方導体の形成後、上部導体パターン
を形成して、同軸配線構造が形成される。As one of such measures against noise, a coaxial wiring is formed in a thick film multilayer printed wiring board (Japanese Patent Laid-Open No. 4-267586). In this coaxial wiring pattern forming method, a lower conductor pattern is formed on the surface of a base substrate such as alumina ceramics by a thick film printing method or the like, and then a photosensitive insulating film is formed thereon. After drying this insulation film, a via hole is formed in the insulation film by photolithography technology, and after filling the via hole with a conductor paste and sintering to form a side conductor, a signal wiring is formed on the insulation film by a thin film plating method. Form a pattern. Subsequently, in the same process, an insulating film is formed, a via hole is formed, a side conductor is formed by a conductor paste, and then an upper conductor pattern is formed to form a coaxial wiring structure.
【０００４】[0004]
【発明が解決しようとする課題】特開平４−２６７５８
６号公報に開示されている方法においては、厚膜印刷法
によって形成した信号配線とホトリソグラフィ技術によ
って形成した側方導体用のバイアホールの間隔を、相対
的な位置ずれを考慮し１００μｍ程度に設計していた。
これは、既に形成してある導体パターンに対してバイア
ホールのフィルムを合わせる際位置ずれを生じるためで
あり、位置ずれの原因はフィルム合わせ誤差のほか、基
板の寸法変化、フィムの寸法変化等がある。そのように
信号配線と側方導体との間隔を１００μｍに設計した場
合、信号配線ピッチは５００μｍ程度が限界あり、それ
以上の微細化は困難であった。DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In the method disclosed in Japanese Patent Publication No. 6, the distance between the signal wiring formed by the thick film printing method and the via hole for the side conductor formed by the photolithography technique is set to about 100 μm in consideration of the relative positional deviation. I was designing.
This is because the misalignment occurs when the via hole film is aligned with the conductor pattern that has already been formed.The misalignment is caused by not only the film alignment error but also the dimensional change of the substrate and the dimensional change of the film. is there. When the distance between the signal wiring and the side conductors is designed to be 100 μm, the signal wiring pitch is limited to about 500 μm, and further miniaturization is difficult.
【０００５】本発明の目的は、信号配線と側方導体の間
隔をより狭く設計でき、高密度実装化と信号速度の高速
化を実現できる薄膜多層配線基板と、その製造方法を提
供することにある。An object of the present invention is to provide a thin film multi-layer wiring board which can be designed with a narrower distance between the signal wiring and the side conductors, and which can realize high-density mounting and high signal speed, and a manufacturing method thereof. is there.
【０００６】[0006]
【課題を解決するための手段】本発明による薄膜多層配
線基板は、絶縁層により切り離された複数の配線層を有
し、当該配線層のうちの少なくとも１つに、内部導体部
材とその周囲を取り囲む導体層とにより構成される配線
を含むことを特徴とする。A thin-film multilayer wiring board according to the present invention has a plurality of wiring layers separated by an insulating layer, and at least one of the wiring layers has an internal conductor member and its periphery. It is characterized in that it includes a wiring constituted by a surrounding conductor layer.
【０００７】このような薄膜多層配線基板は、絶縁層と
配線層の形成をそれぞれ所定の回数行うことにより、絶
縁層により切り離された所定の数の配線層を有し、当該
配線層のうちの少なくとも１つに、内部導体部材とその
周囲を取り囲む導体層とにより構成される配線を含む薄
膜多層配線基板を製造する方法であって、当該内部導体
部材とその周囲を取り囲む導体層とにより構成される配
線を、絶縁層の上に、上記内部導体部材の周囲を取り囲
む導体層のうちの下部導体層を形成し、下部導体層の上
に、上記内部導体部材の周囲を取り囲む導体層のうちの
側方導体層を形成し、その際に上記内部導体部材を、当
該側方導体層の一部を形成するのと同時に形成し、そし
て上記内部導体部材の周囲を取り囲む導体層のうちの上
部導体層を形成することにより作製することを特徴とす
る方法により製造することができる。Such a thin-film multilayer wiring board has a predetermined number of wiring layers separated by the insulating layer by forming the insulating layer and the wiring layer a predetermined number of times. A method of manufacturing a thin-film multilayer wiring board including at least one wiring comprising an inner conductor member and a conductor layer surrounding the inner conductor member, the method comprising: Forming a lower conductor layer of the conductor layer surrounding the periphery of the internal conductor member on the insulating layer, and forming a lower conductor layer of the conductor layer surrounding the periphery of the internal conductor member on the lower conductor layer. A side conductor layer is formed, and at the same time, the inner conductor member is formed at the same time as forming a part of the side conductor layer, and an upper conductor of the conductor layers surrounding the inner conductor member. Forming layers It can be prepared by a process characterized by prepared by.
【０００８】一つの態様では、本発明の薄膜多層配線基
板は、内部導体部材とその周囲を取り囲む導体層とによ
り構成される配線を、絶縁層の上に下部導体層を形成す
る工程、下部導体層の上に側方導体層の一部となる側壁
下部を形成する工程、側壁下部の側面を覆い上面を露出
する絶縁層を形成する工程、露出した側壁下部の上面
と、一対の側壁下部の中間位置の絶縁層の上に、側方導
体層の一部となる側壁中間部と内部導体部材とをそれぞ
れ形成する工程、側壁中間部の上面に、側方導体層の一
部となる側壁上部を形成する工程、内部導体部材を覆い
側壁上部の上面を露出する絶縁層を形成する工程、そし
てこの絶縁層の上に、露出した側壁上部に接合する上部
導体層を形成する工程、により作製して製造することが
できる。In one aspect, the thin-film multilayer wiring board of the present invention comprises a step of forming a lower conductor layer on an insulating layer, and a wiring formed of an inner conductor member and a conductor layer surrounding the inner conductor member. A step of forming a side wall lower part which becomes a part of the lateral conductor layer on the layer, a step of forming an insulating layer which covers the side surface of the side wall lower part and exposes the upper surface, the exposed upper surface of the side wall lower part, and a pair of side wall lower parts. A step of forming a sidewall intermediate portion and an internal conductor member, each of which is a part of the lateral conductor layer, on the insulating layer at an intermediate position, and a sidewall upper portion, which is a part of the lateral conductor layer, on the upper surface of the sidewall intermediate portion. And a step of forming an insulating layer that covers the inner conductor member and exposes the upper surface of the side wall upper portion, and a step of forming an upper conductive layer that is bonded to the exposed side wall upper portion on the insulating layer. Can be manufactured.
【０００９】もう一つの態様では、本発明の薄膜多層配
線基板は、内部導体部材とその周囲を取り囲む導体層と
により構成される配線を、溝を形成した絶縁層の上に下
部導体層を形成する工程、下部導体層の上に側方導体層
の一部となる側壁下部を形成する工程、側壁下部の側面
を覆い上面を露出する絶縁層を形成する工程、露出した
側壁下部の上面と、一対の側壁下部の中間で、側壁下部
の側面を覆って形成した絶縁層に上記絶縁層の溝の形状
にならって形成された溝の中とに、側方導体層の一部と
なる側壁上部と内部導体部材とをそれぞれ形成する工
程、内部導体部材を覆い側壁上部の上面を露出する絶縁
層を形成する工程、そしてこの絶縁層の上に、露出した
側壁上部に接合する上部導体層を形成する工程、により
作製して製造することができる。In another aspect, the thin-film multilayer wiring board of the present invention has a wiring formed of an internal conductor member and a conductor layer surrounding the inner conductor member, and a lower conductor layer formed on an insulating layer having a groove. The step of forming a side wall lower part that is a part of the lateral conductor layer on the lower conductor layer, the step of forming an insulating layer that covers the side surface of the lower side wall and exposes the upper surface, and the exposed upper surface of the lower side wall, In the middle of the pair of lower side walls, in the groove formed in the insulating layer formed to cover the side surface of the lower side wall and in the shape of the groove of the insulating layer, the upper side wall which becomes a part of the side conductor layer is formed. And a step of forming an inner conductor member, a step of forming an insulating layer that covers the inner conductor member and exposes the upper surface of the side wall upper portion, and an upper conductor layer that is bonded to the exposed side wall upper portion on the insulating layer. The process of Can.
【００１０】[0010]
【発明の実施の形態】本発明による薄膜多層配線基板
は、配線層のうちの少なくとも１つが、信号伝送部材で
ある内部導体部材と、その周囲を絶縁材料を介して取り
囲む導体層とにより構成される同軸構造の配線を含むこ
とを特徴とする。同軸構造の配線は１つの配線層のみに
存在してもよく、複数の配線層に存在してもよい。同様
に、１つの配線層に同軸構造の配線と外側導体のない通
常の配線とが混在することも可能である。配線層は、銅
又は銅合金、あるいはアルミニウム又はアルミニウム合
金などの導体で作製することができる。同軸構造の配線
を含む配線層は、一般に絶縁層中に埋め込まれ、同軸構
造の配線を含まない配線層は、絶縁層中に埋め込まれて
いても、薄膜多層配線基板の表面の絶縁層上に露出され
ていてもよい。BEST MODE FOR CARRYING OUT THE INVENTION In the thin-film multilayer wiring board according to the present invention, at least one of the wiring layers is composed of an inner conductor member which is a signal transmission member and a conductor layer which surrounds the inner conductor member with an insulating material. It is characterized in that it includes a coaxial structure wiring. The wiring having the coaxial structure may exist in only one wiring layer, or may exist in a plurality of wiring layers. Similarly, it is possible to mix the coaxial wiring and the normal wiring without the outer conductor in one wiring layer. The wiring layer can be made of a conductor such as copper or a copper alloy, or aluminum or an aluminum alloy. The wiring layer including the wiring of the coaxial structure is generally embedded in the insulating layer, and the wiring layer not including the wiring of the coaxial structure is formed on the insulating layer on the surface of the thin-film multilayer wiring board even if it is embedded in the insulating layer. It may be exposed.
【００１１】絶縁層は、一般的な絶縁材料で形成するこ
とができる。例えば、エポキシ樹脂やポリイミド樹脂を
使用することができる。このほかに、例えばポリベンゾ
オキサゾール樹脂やベンゾシクロブテン樹脂などを使用
することもでき、これらの低誘電率材料の使用は高周波
の信号伝送にとって特に有利である。The insulating layer can be formed of a general insulating material. For example, an epoxy resin or a polyimide resin can be used. Besides, for example, polybenzoxazole resin or benzocyclobutene resin can be used, and use of these low dielectric constant materials is particularly advantageous for high frequency signal transmission.
【００１２】次に、図面を参照して本発明を更に説明す
ることにする。図１（ａ）に示したように、パイレック
ス（商品名）ガラスのベース１を用意し、その上面に厚
さ０．１μｍのクロム膜（図示せず）を形成後、このク
ロム膜上に非感光性のポリイミド樹脂をスピンコート法
により約１０μｍ塗布する。塗布方法としては、スピン
コート法以外に、スクリーン印刷法、スプレー法、カー
テンコート法、ロールコート法、又はディップ法などを
使用してもよい。次いで、この樹脂膜を８０℃で３０分
乾燥させ、その後、３５０℃で３０分加熱して樹脂を硬
化させ、絶縁層２を形成する。ベース１としては、ガラ
ス以外の剛性材料の使用も可能である。上記のクロム膜
は、絶縁層２をガラス材料のベース１へ密着させておく
ために設けるものであり、それに代えて絶縁層２のベー
ス１への密着性を高めるのに有効なほかの材料の膜を使
用してもよい。The invention will now be further described with reference to the drawings. As shown in FIG. 1A, a base 1 of Pyrex (trade name) glass is prepared, and a chrome film (not shown) having a thickness of 0.1 μm is formed on the upper surface thereof. A photosensitive polyimide resin is applied by spin coating to about 10 μm. As a coating method, other than the spin coating method, a screen printing method, a spray method, a curtain coating method, a roll coating method, a dipping method, or the like may be used. Next, this resin film is dried at 80 ° C. for 30 minutes, and then heated at 350 ° C. for 30 minutes to cure the resin and form the insulating layer 2. It is also possible to use a rigid material other than glass as the base 1. The above-mentioned chromium film is provided to keep the insulating layer 2 in close contact with the base 1 of the glass material, and instead of other materials effective for enhancing the adhesiveness of the insulating layer 2 to the base 1. Membranes may be used.
【００１３】続いて、絶縁層２の表面に電解銅めっきを
行うための電極層（図示せず）をスパッタリング法によ
り形成後、電解銅めっきを行い、電極層の表面に厚さ約
５μｍの下部導体層３を形成する（図１（ｂ））。電極
層の形成は、絶縁層表面を過マンガン酸液にて処理して
粗面化した後、触媒処理及び無電解銅めっきを施す方法
によることもできる。Subsequently, an electrode layer (not shown) for electrolytic copper plating is formed on the surface of the insulating layer 2 by a sputtering method, and then electrolytic copper plating is performed to form a lower portion having a thickness of about 5 μm on the surface of the electrode layer. The conductor layer 3 is formed (FIG. 1B). The electrode layer may be formed by a method of treating the surface of the insulating layer with a permanganate solution to roughen the surface, and then subjecting the surface to catalytic treatment and electroless copper plating.
【００１４】次に、下部導体層1の表面に厚さ約１０μ
ｍのレジストを塗布し、ガラスマスクを重ねて水銀ラン
プにて４００ｍＪ／ｃｍ2の露光を行い、アルカリを含
む現像液にて露光部分を溶解除去して開口を形成する。
その後、電解銅めっきを行い、開口の底部に露出してい
る下部導体層３の表面に厚さ約５μｍの側壁下部５を形
成し、次いでレジスト膜を除去する（図１（ｃ））。Next, a thickness of about 10 μm is formed on the surface of the lower conductor layer 1.
m of resist is applied, a glass mask is overlaid, exposure is performed at 400 mJ / cm 2 with a mercury lamp, and an exposed portion is dissolved and removed with a developer containing alkali to form an opening.
Then, electrolytic copper plating is performed to form a sidewall lower portion 5 having a thickness of about 5 μm on the surface of the lower conductor layer 3 exposed at the bottom of the opening, and then the resist film is removed (FIG. 1C).
【００１５】次いで、スピンコート法を用い、側壁下部
５を覆うように絶縁性樹脂を約１０μｍ塗布し、８０
℃、３０分の乾燥を行う。この後、３５０℃で３０分加
熱して樹脂を硬化させ、絶縁層６を形成する（図１
（ｄ））。次いで、ＣＭＰ（化学機械研磨）により絶縁
層６の一部を取り除き、図１（ｅ）に示したように側壁
下部５の上部を露出させる。Next, an insulating resin is applied by a spin coating method so as to cover the lower portion 5 of the side wall by about 10 μm.
Dry at 30 ° C. for 30 minutes. Then, the resin is cured by heating at 350 ° C. for 30 minutes to form the insulating layer 6 (see FIG. 1).
(D)). Next, a part of the insulating layer 6 is removed by CMP (Chemical Mechanical Polishing) to expose the upper portion of the side wall lower portion 5 as shown in FIG.
【００１６】続いて、この露出させた側壁下部５の上面
と残りの絶縁層６の表面に、電解銅めっきを行うための
電極層（図示せず）をスパッタ法を用いて形成する。こ
の電極層の表面に厚さ約１０μｍのレジストを塗布し、
ガラスマスクを重ねて水銀ランプにて４００ｍＪ／ｃｍ
2 の露光を行い、アルカリを含む現像液にて露光部分を
溶解除去して、電極層を露出させる開口を側壁下部５の
上方と二つの側壁下部５の中間にの位置に形成する。そ
の後、電解銅めっきを行い、 内部導体部材７及び側壁
中間部８を約５μｍの厚さに形成し、そしてレジスト膜
を除去する（図２（ａ））。Subsequently, an electrode layer (not shown) for electrolytic copper plating is formed on the exposed upper surface of the lower side wall 5 and the surface of the remaining insulating layer 6 by the sputtering method. Apply a resist of about 10 μm thickness on the surface of this electrode layer,
400 mJ / cm with a mercury lamp overlaid with a glass mask
The second exposure is performed, the exposed portion is dissolved and removed with a developer containing alkali, and an opening for exposing the electrode layer is formed at a position above the side wall lower part 5 and between the two side wall lower parts 5. Then, electrolytic copper plating is performed to form the inner conductor member 7 and the side wall intermediate portion 8 to a thickness of about 5 μm, and the resist film is removed (FIG. 2A).
【００１７】次に、電極層、内部導体部材７及び側壁中
間部８を覆って厚さ約１０μｍのレジストを塗布し、ガ
ラスマスクを重ねて水銀ランプにて４００ｍＪ／ｃｍ2
の露光を行い、アルカリを含む現像液にて露光部分を溶
解除去し、側壁中間部８の上面を露出させる開口を形成
する。続いて電解銅めっきを行って側壁中間部８の上面
に厚さ約５μｍの側壁上部９を形成し、そしてレジスト
膜を除去し、続いてこれにより露出した電極層を除去す
る（図２（ｂ））。Next, a resist having a thickness of about 10 μm is applied so as to cover the electrode layer, the internal conductor member 7 and the side wall intermediate portion 8, a glass mask is overlaid, and 400 mJ / cm 2 is applied by a mercury lamp.
Exposure is performed, the exposed portion is dissolved and removed with a developing solution containing alkali, and an opening for exposing the upper surface of the side wall intermediate portion 8 is formed. Subsequently, electrolytic copper plating is performed to form a sidewall upper portion 9 having a thickness of about 5 μm on the upper surface of the sidewall intermediate portion 8, and the resist film is removed, and subsequently, the electrode layer exposed thereby is removed (FIG. )).
【００１８】次に、内部導体部材７と、側壁中間部８及
びその上の側壁上部９を覆うように絶縁層６上にスピン
コート法を用いて絶縁性樹脂を約１０μｍ塗布し、８０
℃、３０分の乾燥を行う。この後、３５０℃で３０分加
熱して樹脂を硬化させ、絶縁層１０を形成し、そしてＣ
ＭＰにより絶縁層１０の一部を取り除き、図２（ｃ）に
示したように側壁上部９の上面を露出させる。Next, an insulating resin is applied to the insulating layer 6 so as to cover the inner conductor member 7, the side wall intermediate portion 8 and the side wall upper portion 9 on the side wall upper portion 9 by spin coating to a thickness of about 10 μm.
Dry at 30 ° C. for 30 minutes. Then, the resin is cured by heating at 350 ° C. for 30 minutes to form the insulating layer 10, and C
A part of the insulating layer 10 is removed by MP to expose the upper surface of the side wall upper portion 9 as shown in FIG.
【００１９】次いで、この露出させた側壁上部９と残り
の絶縁層１０の表面に、電解銅めっきを行うための電極
層（図示せず）をスパッタ法を用いて形成した。その
後、電解銅めっきを行ない、厚さ約５μｍの上部導体層
１１を形成し、続いてその上に絶縁層１２を形成する
（図２（ｄ））。Next, an electrode layer (not shown) for electrolytic copper plating was formed on the exposed upper surface 9 of the side wall and the remaining surface of the insulating layer 10 by a sputtering method. After that, electrolytic copper plating is performed to form an upper conductor layer 11 having a thickness of about 5 μm, and then an insulating layer 12 is formed thereon (FIG. 2 (d)).
【００２０】図１及び図２で説明した薄膜多層配線基板
の下部及び上部導体層３、１０はパターニングされてい
ないが、場合によってはそれらをパターニングし、隣り
合う同軸構造配線の周囲導体層を互いに他方から切り離
すことも可能である。Although the lower and upper conductor layers 3 and 10 of the thin-film multilayer wiring board described with reference to FIGS. 1 and 2 are not patterned, they may be patterned in some cases so that the neighboring conductor layers of adjacent coaxial structure wirings are mutually connected. It can also be separated from the other.
【００２１】このようにして、周囲を絶縁材料で取り囲
まれた同軸構造の配線を含む基板を得ることができる。
絶縁層１２の表面には、通常、別の配線層が形成され、
同軸構造の内部導体部材７は上部導体層１１に設けられ
た開口部を貫通するバイアにより絶縁膜１２上の別の配
線につながれる。この開口部は、上部導体層１１の形成
後にそれをパターニングすることで簡単に形成すること
ができ、それを貫通するバイアも、先に説明した手法を
利用するなどして簡単に形成することができる。あるい
は、内部導体部材７は、バイアの先端に設けたパッド上
のバンプを介し、他部品に接続することもできる。In this way, it is possible to obtain the substrate including the wiring of the coaxial structure surrounded by the insulating material.
Another wiring layer is usually formed on the surface of the insulating layer 12,
The inner conductor member 7 having the coaxial structure is connected to another wiring on the insulating film 12 by a via penetrating the opening provided in the upper conductor layer 11. This opening can be easily formed by patterning it after forming the upper conductor layer 11, and the via penetrating it can also be easily formed by using the method described above. it can. Alternatively, the internal conductor member 7 can be connected to another component through a bump on a pad provided at the tip of the via.
【００２２】図３に、そのような構造の薄膜多層配線基
板３０の断面を模式的に示す。この図において、図１及
び２で説明したのと同じ部材は、それらと同じ符号で示
されている。この薄膜多層配線基板３０の表面には配線
３１とパッド３２が設けられ、パッド３２の上にバンプ
３７が位置していて、同軸構造の配線層の内部導体部材
７から引き出されたバイア３４が外側導体層３３に設け
られた開口部３５を通り抜けてパッド３２に接続してい
る。FIG. 3 schematically shows a cross section of the thin film multilayer wiring board 30 having such a structure. In this figure, the same members as described in FIGS. 1 and 2 are designated by the same reference numerals. Wirings 31 and pads 32 are provided on the surface of the thin film multilayer wiring board 30, bumps 37 are located on the pads 32, and vias 34 drawn from the internal conductor member 7 of the wiring layer having the coaxial structure are located outside. It passes through an opening 35 provided in the conductor layer 33 and is connected to the pad 32.
【００２３】図３に示した剛性材料のパイレックスガラ
スのベース１を取り除いて、例えばＴＡＢテープのよう
に可撓性を持つ薄膜多層配線基板を得ることもできる。
図３に示した薄膜多層配線基板３０からベース１を切り
離すためには、例えば次のような方法を利用することが
できる。By removing the base 1 of the Pyrex glass of the rigid material shown in FIG. 3, it is possible to obtain a thin film multilayer wiring board having flexibility such as a TAB tape.
In order to separate the base 1 from the thin film multilayer wiring board 30 shown in FIG. 3, for example, the following method can be used.
【００２４】まず、図４（ａ）に示したように、ガラス
のベース４１の表面の一部に、パターン化したクロム膜
４２を、例えばリフトオフ法により形成する。次に、上
で説明した構成の薄膜多層配線構造体４３を形成する
（図４（ｂ））。次いで、図４（ｃ）に示したように、
２つのクロム膜４２の対向する側壁４２ａの付近の領域
（図中の斜線部分）の薄膜多層配線構造体４３にＹＡＧ
レーザ光４４を照射してこの領域から薄膜多層構造体を
なくし、クロム膜４２の上に載る部分のない薄膜多層配
線構造体４３’を他の部分から切り離す（図４
（ｄ））。この薄膜多層配線構造体４３’は、ガラスの
ベース４１との界面にクロム膜がないため、ベース４１
から容易に剥離することができ、そして剥離した構造体
４３’は、ベース４１から独立した可撓性のある薄膜多
層配線基板として使用することができる。First, as shown in FIG. 4A, a patterned chromium film 42 is formed on a part of the surface of a glass base 41 by, for example, a lift-off method. Next, the thin film multilayer wiring structure 43 having the structure described above is formed (FIG. 4B). Then, as shown in FIG.
YAG is formed on the thin-film multilayer wiring structure 43 in the region (hatched portion in the drawing) near the opposite side walls 42a of the two chromium films 42.
The thin film multilayer structure is removed from this region by irradiating the laser beam 44, and the thin film multilayer wiring structure 43 'having no portion on the chromium film 42 is separated from other parts (FIG. 4).
(D)). This thin-film multilayer wiring structure 43 'has no chromium film at the interface with the glass base 41,
The peeled structure 43 ′ can be used as a flexible thin film multilayer wiring board independent of the base 41.
【００２５】ベース４１から独立した薄膜多層配線基板
を、図３と同様の模式断面図である図５に示す。この図
において、図３に見られるのと同じ部材は、それらと同
じ符号で示されている。この図の薄膜多層配線基板５０
には、上面に形成した配線３１とパッド３２のほかに、
下面にも配線５１が形成され、同軸構造の配線の内部導
体部材７から引き出されたバイア５２が配線５１の１つ
に接続している。この図には示していないが、下面にも
上面と同様に、他部品へ接続するためのパッドとバンプ
を設け、そのパッドにバイア５２をつなぐこともでき
る。A thin-film multilayer wiring board independent of the base 41 is shown in FIG. 5, which is a schematic sectional view similar to FIG. In this figure, the same elements as seen in FIG. 3 are designated with the same reference numerals. Thin-film multilayer wiring board 50 of this figure
In addition to the wiring 31 and the pad 32 formed on the upper surface,
A wiring 51 is also formed on the lower surface, and a via 52 drawn from the inner conductor member 7 of the wiring having the coaxial structure is connected to one of the wirings 51. Although not shown in this figure, similarly to the upper surface, pads and bumps for connecting to other components may be provided on the lower surface, and the vias 52 may be connected to the pads.
【００２６】本発明の方法では、同軸構造の配線の内部
導体部材とその側方の側方導体層を、厚膜法によらず、
微細パターンの形成に適した薄膜法のみで形成できるこ
とから、内部導体部材の幅を例えば５μｍ程度、内部導
体部材と側方導体層との間隔を例えばやはり５μｍ程度
として、高集積化に有利な微細な同軸構造の配線を作製
することができる。In the method of the present invention, the inner conductor member of the coaxial wiring and the side conductor layer on the side of the inner conductor member are not formed by the thick film method,
Since it can be formed only by a thin film method suitable for forming a fine pattern, the width of the inner conductor member is, for example, about 5 μm, and the distance between the inner conductor member and the side conductor layer is, for example, about 5 μm, which is advantageous for high integration. It is possible to manufacture a wiring having a simple coaxial structure.
【００２７】図３の薄膜多層配線基板３０の上面の配線
３１の上に絶縁層を形成し、その上に別の配線層を設け
ることで、更に多層化した基板とすることも可能であ
り、この場合、バンプ３７につながるパッド３２は一番
上の配線層に設けられる。同様に、図５に示した薄膜多
層配線基板も、その上面、下面、あるいはその両方に更
に絶縁層と配線層を積層して、更に多層化することが可
能である。By forming an insulating layer on the wiring 31 on the upper surface of the thin-film multilayer wiring board 30 of FIG. 3 and providing another wiring layer on it, it is possible to make a further multilayered board. In this case, the pad 32 connected to the bump 37 is provided in the uppermost wiring layer. Similarly, the thin-film multilayer wiring board shown in FIG. 5 can be further multilayered by further laminating an insulating layer and a wiring layer on its upper surface, lower surface, or both.
【００２８】そのようにより多層化した薄膜多層配線基
板においては、同軸構造の配線は１つの配線層のみに存
在してもよく、複数の配線層に存在してもよい。同様
に、１つの配線層に同軸構造の配線と外側導体のない通
常の配線とが混在することも可能である。この場合の通
常の配線は、内部導体部材の形成と同時に行うことがで
きる。In such a multi-layered thin film multilayer wiring board, the wiring having the coaxial structure may exist in only one wiring layer or in a plurality of wiring layers. Similarly, it is possible to mix the coaxial wiring and the normal wiring without the outer conductor in one wiring layer. Normal wiring in this case can be performed simultaneously with the formation of the internal conductor member.
【００２９】図３と５に示した薄膜多層配線基板３０、
５０においては、内部導体部材７がバイア３４、５２の
貫通部分を除いて外側の導体層により完全に取り囲まれ
ている。本発明の薄膜多層配線基板では、特に高周波信
号の伝送に支障をきたさない限り、外側の導体層が不連
続であったり、あるいはその先端（図３及び５に示した
外側導体層の左右の垂直部分）が閉じられていないよう
な同軸構造の配線を使用することも可能である。The thin film multilayer wiring board 30 shown in FIGS. 3 and 5,
At 50, the inner conductor member 7 is completely surrounded by the outer conductor layer except for the through portions of the vias 34, 52. In the thin-film multilayer wiring board of the present invention, the outer conductor layer is discontinuous, or the tip thereof (vertical left and right of the outer conductor layer shown in FIGS. 3 and 5) is provided unless it interferes with high-frequency signal transmission. It is also possible to use coaxially structured wiring in which the (part) is not closed.
【００３０】また、図１と２を参照して説明した薄膜多
層配線基板の製造では、１つの同軸構造の配線について
信号伝送部材である内部導体部材を１つ形成しているだ
けであるが、複数（通常は２つ）の内部導体部材を形成
することもできる。Further, in the manufacture of the thin film multilayer wiring board described with reference to FIGS. 1 and 2, only one internal conductor member which is a signal transmission member is formed for one coaxial structure wiring. It is also possible to form a plurality (usually two) of inner conductor members.
【００３１】更に、本発明による薄膜多層配線基板で
は、上で説明したものにおけるように矩形断面の外側導
体層ばかりでなく、それ以外の断面形状の外側導体層を
備えた同軸構造の配線を使用することもできる。その一
例を図６の断面図に示す。この例においては、台形断面
の溝を形成した下層絶縁層６１を覆って下部導体層６２
が位置し、その上の絶縁層６３に側壁下部６４が形成さ
れている。この絶縁層６３の上にもう一つの絶縁層６５
が位置し、そしてこの絶縁層６５に側壁上部６６が形成
されており、更に２つの側壁上部６６の間の台形断面の
溝内に、内部配線部材６７が配置されていて、これは側
壁上部６６の形成と同時に形成することができる。この
ように、この態様の場合には、先に説明した矩形断面の
外側導体層を備えた態様の薄膜多層配線基板の同軸構造
の配線における側壁中間部の形成を省くことができる。
絶縁層６５の上面は、側壁上部６６の上面が露出した平
坦面となるようにすることができ、その上に上部導体層
６８と上層絶縁層６９を順次形成することができる。な
お、下部絶縁層の溝の断面形状は台形でなく、矩形であ
っても差し支えない。Further, in the thin film multilayer wiring board according to the present invention, not only the outer conductor layer having a rectangular cross section as in the one described above, but also the wiring having the coaxial structure having the outer conductor layer having the other sectional shape is used. You can also do it. An example thereof is shown in the sectional view of FIG. In this example, the lower conductor layer 62 covers the lower insulating layer 61 in which a groove having a trapezoidal cross section is formed.
Is located, and the side wall lower portion 64 is formed on the insulating layer 63 thereabove. Another insulating layer 65 is formed on the insulating layer 63.
Is formed on the insulating layer 65, and a side wall upper portion 66 is formed on the insulating layer 65. Further, an internal wiring member 67 is arranged in the groove of the trapezoidal cross section between the two side wall upper portions 66, which is formed on the side wall upper portion 66. Can be formed simultaneously with the formation of. Thus, in the case of this aspect, it is possible to omit the formation of the intermediate portion of the side wall in the wiring of the coaxial structure of the thin film multilayer wiring board of the aspect including the outer conductor layer having the rectangular cross section described above.
The upper surface of the insulating layer 65 may be a flat surface where the upper surface of the sidewall upper portion 66 is exposed, and the upper conductor layer 68 and the upper insulating layer 69 may be sequentially formed thereon. The cross-sectional shape of the groove of the lower insulating layer may be rectangular instead of trapezoidal.
【００３２】本発明は以上説明したとおりであるが、そ
れをその様々な実施形態とともに付記として列挙すれ
ば、次のとおりである。
（付記１）絶縁層により切り離された複数の配線層を有
し、当該配線層のうちの少なくとも１つに、内部導体部
材とその周囲を取り囲む導体層とにより構成される配線
を含むことを特徴とする薄膜多層配線基板。
（付記２）１つ又は複数の内部導体部材が１つの導体層
により取り囲まれている、付記１記載の薄膜多層配線基
板。
（付記３）前記内部導体部材とその周囲を取り囲む導体
層とにより構成される配線が１つ又は複数の配線層に含
まれている、付記１又は２記載の薄膜多層配線基板。
（付記４）前記配線層に、前記内部導体部材とその周囲
を取り囲む導体層とにより構成される配線とともに、導
体層により周囲を取り囲まれない配線が存在する、付記
３記載の薄膜多層配線基板。
（付記５）前記内部導体部材及びその周囲を取り囲む導
体層の材料が、銅又は銅合金、あるいはアルミニウム又
はアルミニウム合金である、付記１〜４のいずれか１つ
に記載の薄膜多層配線基板。
（付記６）前記絶縁層の材料が、エポキシ樹脂、ポリイ
ミド樹脂、ポリベンゾオキサゾール樹脂、又はベンゾシ
クロブテン樹脂である、付記１〜５のいずれか１つに記
載の薄膜多層配線基板。
（付記７）前記絶縁層及び前記配線層の積層体が上に配
置された剛性のベースを含む、付記１〜６のいずれか１
つに記載の薄膜多層配線基板。
（付記８）絶縁層と配線層の形成をそれぞれ所定の回数
行うことにより、絶縁層により切り離された所定の数の
配線層を有し、当該配線層のうちの少なくとも１つに、
内部導体部材とその周囲を取り囲む導体層とにより構成
される配線を含む薄膜多層配線基板を製造する方法であ
って、当該内部導体部材とその周囲を取り囲む導体層と
により構成される配線を、絶縁層の上に、上記内部導体
部材の周囲を取り囲む導体層のうちの下部導体層を形成
し、下部導体層の上に、上記内部導体部材の周囲を取り
囲む導体層のうちの側方導体層を形成し、その際に上記
内部導体部材を、当該側方導体層の一部を形成するのと
同時に形成し、そして上記内部導体部材の周囲を取り囲
む導体層のうちの上部導体層を形成することにより作製
することを特徴とする、薄膜多層配線基板の製造方法。
（付記９）前記内部導体部材とその周囲を取り囲む導体
層とにより構成される配線を、絶縁層の上に下部導体層
を形成する工程、下部導体層の上に側方導体層の一部と
なる側壁下部を形成する工程、側壁下部の側面を覆い上
面を露出する絶縁層を形成する工程、露出した側壁下部
の上面と、一対の側壁下部の中間位置の絶縁層の上に、
側方導体層の一部となる側壁中間部と内部導体部材とを
それぞれ形成する工程、側壁中間部の上面に、側方導体
層の一部となる側壁上部を形成する工程、内部導体部材
を覆い側壁上部の上面を露出する絶縁層を形成する工
程、そしてこの絶縁層の上に、露出した側壁上部に接合
する上部導体層を形成する工程、により作製する、付記
８記載の方法。
（付記１０）前記内部導体部材とその周囲を取り囲む導
体層とにより構成される配線を、溝を形成した絶縁層の
上に下部導体層を形成する工程、下部導体層の上に側方
導体層の一部となる側壁下部を形成する工程、側壁下部
の側面を覆い上面を露出する絶縁層を形成する工程、露
出した側壁下部の上面と、一対の側壁下部の中間で、側
壁下部の側面を覆って形成した絶縁層に上記絶縁層の溝
の形状にならって形成された溝の中とに、側方導体層の
一部となる側壁上部と内部導体部材とをそれぞれ形成す
る工程、内部導体部材を覆い側壁上部の上面を露出する
絶縁層を形成する工程、そしてこの絶縁層の上に、露出
した側壁上部に接合する上部導体層を形成する工程、に
より作製する、付記８記載の方法。
（付記１１）前記絶縁層と配線層の形成を、当該絶縁層
の１つを上に形成した剛性のベース上で行う、付記８〜
１０のいずれか１つに記載の方法。
（付記１２）前記剛性ベースとその上の前記絶縁層との
間に、当該絶縁層の当該剛性ベースへの密着性を高める
材料の膜を設ける、付記１１記載の方法。
（付記１３）前記膜を前記剛性ベース上の一部分のみに
設け、そして前記絶縁層と配線層のそれぞれ所定回数の
形成を終了後に、当該剛性ベース上の当該膜の設けられ
ていない領域から薄膜多層配線基板を剥離する、付記１
２記載の方法。
（付記１４）前記内部導体部材及びその周囲を取り囲む
導体層の形成を、電極層の形成とこれに続く電解めっき
により行う、付記８〜１３のいずれか１つに記載の方
法。
（付記１５）前記内部導体部材及び前記側方導体層の形
成のための電解めっきを、パターニングした開口内にお
いて行う、付記１４記載の方法。The present invention has been described above, but it will be as follows if it is enumerated as additional notes together with its various embodiments. (Supplementary Note 1) A plurality of wiring layers separated by an insulating layer are provided, and at least one of the wiring layers includes a wiring including an internal conductor member and a conductor layer surrounding the internal conductor member. Thin film multilayer wiring board. (Supplementary Note 2) The thin film multilayer wiring board according to Supplementary Note 1, wherein one or a plurality of internal conductor members are surrounded by one conductor layer. (Supplementary Note 3) The thin-film multilayer wiring board according to Supplementary Note 1 or 2, wherein the wiring constituted by the internal conductor member and a conductor layer surrounding the internal conductor member is included in one or a plurality of wiring layers. (Supplementary Note 4) The thin film multilayer wiring board according to Supplementary Note 3, wherein in the wiring layer, there are wirings that are not surrounded by the conductor layer, as well as wirings that are configured by the internal conductor member and a conductor layer that surrounds the inner conductor member. (Supplementary Note 5) The thin film multilayer wiring board according to any one of Supplementary notes 1 to 4, wherein the material of the internal conductor member and the conductor layer surrounding the internal conductor member is copper or a copper alloy, or aluminum or an aluminum alloy. (Supplementary note 6) The thin-film multilayer wiring board according to any one of supplementary notes 1 to 5, wherein the material of the insulating layer is an epoxy resin, a polyimide resin, a polybenzoxazole resin, or a benzocyclobutene resin. (Supplementary note 7) Any one of supplementary notes 1 to 6, including a rigid base on which the laminate of the insulating layer and the wiring layer is arranged.
The thin film multilayer wiring board described in 1. (Supplementary Note 8) The insulating layer and the wiring layer are formed a predetermined number of times to have a predetermined number of wiring layers separated by the insulating layer, and at least one of the wiring layers is
A method of manufacturing a thin-film multilayer wiring board including wiring formed of an internal conductor member and a conductor layer surrounding the inner conductor member, wherein the wiring formed by the inner conductor member and the conductor layer surrounding the periphery is insulated. A lower conductor layer of the conductor layers surrounding the inner conductor member is formed on the layer, and a side conductor layer of the conductor layers surrounding the inner conductor member is formed on the lower conductor layer. Forming the inner conductor member at the same time as forming a part of the lateral conductor layer, and forming an upper conductor layer of the conductor layers surrounding the inner conductor member. A method of manufacturing a thin-film multilayer wiring board, comprising: (Supplementary Note 9) A step of forming a lower conductor layer on an insulating layer, a wiring including the inner conductor member and a conductor layer surrounding the inner conductor member, and a part of a side conductor layer on the lower conductor layer. Forming a lower side wall, a step of forming an insulating layer that covers the side surface of the lower side wall and exposes the upper surface, the exposed upper surface of the lower side wall and the insulating layer at the intermediate position between the pair of lower side walls,
A step of forming a side wall intermediate portion which is a part of the side conductor layer and an internal conductor member, a step of forming a side wall upper portion which is a part of the side conductor layer on the upper surface of the side wall intermediate portion, 9. The method according to appendix 8, which is produced by a step of forming an insulating layer that exposes an upper surface of the upper side wall of the cover and a step of forming an upper conductor layer that is bonded to the exposed upper side wall on the insulating layer. (Supplementary Note 10) A step of forming a lower conductor layer on an insulating layer having a groove, a wiring including the inner conductor member and a conductor layer surrounding the inner conductor member, and a side conductor layer on the lower conductor layer. A side wall lower part that is a part of the side wall lower part, a step of forming an insulating layer that covers the side wall lower part side surface and exposes the upper surface, and a side wall lower part side surface is formed between the exposed side wall lower part upper surface and the pair of side wall lower parts. A step of forming an upper part of a side wall and a part of a side conductor layer and an internal conductor member in a groove formed in the insulating layer formed so as to cover the insulating layer in the shape of the groove of the insulating layer; 9. The method according to appendix 8, which is produced by a step of forming an insulating layer that covers the member and exposes the upper surface of the upper side wall, and a step of forming an upper conductor layer that is bonded to the exposed upper side wall on the insulating layer. (Supplementary Note 11) The formation of the insulating layer and the wiring layer is performed on a rigid base on which one of the insulating layers is formed.
The method according to any one of 10. (Supplementary note 12) The method according to supplementary note 11, wherein a film of a material that enhances adhesion of the insulating layer to the rigid base is provided between the rigid base and the insulating layer thereon. (Supplementary Note 13) The film is provided only on a part of the rigid base, and after the insulating layer and the wiring layer are formed a predetermined number of times, a thin film multilayer is formed from a region where the film is not provided on the rigid base. Note 1 peeling off the wiring board
2. The method described in 2. (Supplementary note 14) The method according to any one of supplementary notes 8 to 13, wherein the formation of the inner conductor member and the conductor layer surrounding the inner conductor member is performed by forming an electrode layer and subsequent electroplating. (Supplementary note 15) The method according to supplementary note 14, wherein electrolytic plating for forming the internal conductor member and the lateral conductor layer is performed in a patterned opening.
【００３３】[0033]
【発明の効果】以上説明したように、本発明の薄膜多層
配線基板は、例えば信号伝送部材の幅が５μｍ、この信
号伝送部材とその側方の側壁との間隔が５μｍといった
微細な同軸構造の配線を有することができる。従って、
本発明によれば、高密度で、しかも特に高周波信号の伝
送に好適な薄膜多層配線基板を提供することが可能にな
る。As described above, the thin film multilayer wiring board of the present invention has a fine coaxial structure in which the width of the signal transmission member is 5 μm and the distance between the signal transmission member and the side wall is 5 μm. Can have wiring. Therefore,
According to the present invention, it is possible to provide a thin film multilayer wiring board which has a high density and is particularly suitable for transmission of high frequency signals.
【図１】本発明の薄膜多層配線基板製造方法の前半の工
程を説明する図である。FIG. 1 is a diagram illustrating a first half of a method of manufacturing a thin film multilayer wiring board according to the present invention.
【図２】本発明の薄膜多層配線基板製造方法の後半の工
程を説明する図である。FIG. 2 is a diagram for explaining the latter half of the method of manufacturing the thin film multilayer wiring board according to the present invention.
【図３】本発明の薄膜多層配線基板の態様の一つを説明
する断面図である。FIG. 3 is a cross-sectional view illustrating one aspect of the thin film multilayer wiring board of the present invention.
【図４】本発明の薄膜多層配線基板の製造で利用する基
板剥離方法の一例を説明する図である。FIG. 4 is a diagram illustrating an example of a substrate peeling method used in manufacturing the thin film multilayer wiring substrate of the present invention.
【図５】本発明の薄膜多層配線基板のもう一つの態様を
説明する断面図である。FIG. 5 is a cross-sectional view illustrating another aspect of the thin film multilayer wiring board of the present invention.
【図６】本発明の薄膜多層配線基板の更に別の態様を説
明する断面図である。FIG. 6 is a cross-sectional view illustrating still another aspect of the thin film multilayer wiring board of the present invention.
１、４１…ベース ２、６、１０、１２…絶縁層 ３…下部導体層 ５…側壁下部 ７…内部導体部材 ８…側壁中間部 ９…側壁上部 １１…上部導体層 ３０、５０…薄膜多層配線基板 ３１、５１…配線 ３２…パッド ３３…外側導体層 ３４、５２…バイア ３７…バンプ ４２…クロム膜 ４３、４３’…薄膜多層配線構造体 ６１…下層絶縁層 ６２…下部導体層 ６３、６５…絶縁層 ６４…側壁下部 ６６…側壁上部 ６７…内部配線部材 ６８…上部導体層 ６９…上層配線層 1, 41 ... Base 2, 6, 10, 12 ... Insulating layer 3 ... Lower conductor layer 5 ... Lower side wall 7 ... Inner conductor member 8 ... Side wall middle part 9 ... Upper side wall 11 ... Upper conductor layer 30, 50 ... Thin film multilayer wiring board 31, 51 ... Wiring 32 ... Pad 33 ... Outer conductor layer 34, 52 ... Bahia 37 ... Bump 42 ... Chrome film 43, 43 '... Thin film multilayer wiring structure 61 ... Lower insulating layer 62 ... Lower conductor layer 63, 65 ... Insulating layer 64 ... Lower side wall 66 ... Upper side wall 67 ... Internal wiring member 68 ... Upper conductor layer 69 ... Upper wiring layer
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5E338 AA03 CC02 CC05 CD02 EE13 5E346 AA12 AA15 AA32 AA35 AA43 AA51 BB02 BB04 BB06 BB11 CC08 CC32 DD22 FF01 FF12 GG28 HH04 HH06 ─────────────────────────────────────────────────── ─── Continued front page F-term (reference) 5E338 AA03 CC02 CC05 CD02 EE13 5E346 AA12 AA15 AA32 AA35 AA43 AA51 BB02 BB04 BB06 BB11 CC08 CC32 DD22 FF01 FF12 GG28 HH04 HH06
Claims (10)
を有し、当該配線層のうちの少なくとも１つに、内部導
体部材とその周囲を取り囲む導体層とにより構成される
配線を含むことを特徴とする薄膜多層配線基板。1. A plurality of wiring layers separated by an insulating layer, wherein at least one of the wiring layers includes a wiring including an inner conductor member and a conductor layer surrounding the inner conductor member. Characteristic thin film multilayer wiring board.
体層により取り囲まれている、請求項１記載の薄膜多層
配線基板。2. The thin-film multilayer wiring board according to claim 1, wherein the one or more internal conductor members are surrounded by one conductor layer.
む導体層の材料が、銅又は銅合金、あるいはアルミニウ
ム又はアルミニウム合金である、請求項１又は２記載の
薄膜多層配線基板。3. The thin-film multilayer wiring board according to claim 1, wherein the material of the inner conductor member and the conductor layer surrounding the inner conductor member is copper or a copper alloy, or aluminum or an aluminum alloy.
リイミド樹脂、ポリベンゾオキサゾール樹脂、又はベン
ゾシクロブテン樹脂である、請求項１又は２記載の薄膜
多層配線基板。4. The thin-film multilayer wiring board according to claim 1, wherein the material of the insulating layer is an epoxy resin, a polyimide resin, a polybenzoxazole resin, or a benzocyclobutene resin.
回数行うことにより、絶縁層により切り離された所定の
数の配線層を有し、当該配線層のうちの少なくとも１つ
に、内部導体部材とその周囲を取り囲む導体層とにより
構成される配線を含む薄膜多層配線基板を製造する方法
であって、当該内部導体部材とその周囲を取り囲む導体
層とにより構成される配線を、絶縁層の上に、上記内部
導体部材の周囲を取り囲む導体層のうちの下部導体層を
形成し、下部導体層の上に、上記内部導体部材の周囲を
取り囲む導体層のうちの側方導体層を形成し、その際に
上記内部導体部材を、当該側方導体層の一部を形成する
のと同時に形成し、そして上記内部導体部材の周囲を取
り囲む導体層のうちの上部導体層を形成することにより
作製することを特徴とする、薄膜多層配線基板の製造方
法。5. An insulating layer and a wiring layer are formed a predetermined number of times respectively to have a predetermined number of wiring layers separated by the insulating layer, and at least one of the wiring layers has an internal conductor. A method for manufacturing a thin-film multilayer wiring board including wiring formed of a member and a conductor layer surrounding the member, wherein wiring formed of the internal conductor member and a conductor layer surrounding the member A lower conductor layer of the conductor layers surrounding the inner conductor member is formed on the upper conductor layer, and a side conductor layer of the conductor layers surrounding the inner conductor member is formed on the lower conductor layer. At that time, the inner conductor member is formed at the same time as forming a part of the lateral conductor layer, and the upper conductor layer of the conductor layers surrounding the inner conductor member is formed. Characterized by A method for manufacturing a thin-film multilayer wiring board.
導体層とにより構成される配線を、絶縁層の上に下部導
体層を形成する工程、下部導体層の上に側方導体層の一
部となる側壁下部を形成する工程、側壁下部の側面を覆
い上面を露出する絶縁層を形成する工程、露出した側壁
下部の上面と、一対の側壁下部の中間位置の絶縁層の上
に、側方導体層の一部となる側壁中間部と内部導体部材
とをそれぞれ形成する工程、側壁中間部の上面に、側方
導体層の一部となる側壁上部を形成する工程、内部導体
部材を覆い側壁上部の上面を露出する絶縁層を形成する
工程、そしてこの絶縁層の上に、露出した側壁上部に接
合する上部導体層を形成する工程、により作製する、請
求項５記載の方法。6. A step of forming a lower conductor layer on an insulating layer, a wiring including the inner conductor member and a conductor layer surrounding the inner conductor member, and a part of a side conductor layer on the lower conductor layer. Forming a side wall lower portion, a step of forming an insulating layer that covers the side surface of the side wall lower portion and exposes the upper surface, and a side surface on the exposed upper surface of the side wall lower portion and the insulating layer in the middle position of the pair of side wall lower portions. A step of forming a side wall intermediate part which is a part of the conductor layer and an internal conductor member, a step of forming a side wall upper part which is a part of the side conductor layer on the upper surface of the side wall intermediate part, and a side wall covering the internal conductor member 6. The method according to claim 5, wherein the method is performed by forming an insulating layer exposing the upper surface of the upper portion, and forming an upper conductor layer on the insulating layer to be joined to the exposed upper side wall.
導体層とにより構成される配線を、溝を形成した絶縁層
の上に下部導体層を形成する工程、下部導体層の上に側
方導体層の一部となる側壁下部を形成する工程、側壁下
部の側面を覆い上面を露出する絶縁層を形成する工程、
露出した側壁下部の上面と、一対の側壁下部の中間で、
側壁下部の側面を覆って形成した絶縁層に上記絶縁層の
溝の形状にならって形成された溝の中とに、側方導体層
の一部となる側壁上部と内部導体部材とをそれぞれ形成
する工程、内部導体部材を覆い側壁上部の上面を露出す
る絶縁層を形成する工程、そしてこの絶縁層の上に、露
出した側壁上部に接合する上部導体層を形成する工程、
により作製する、請求項５記載の方法。7. A step of forming a lower conductor layer on an insulating layer having a groove, a wiring including the inner conductor member and a conductor layer surrounding the inner conductor member, and a side conductor on the lower conductor layer. A step of forming a lower side wall which is a part of the layer, a step of forming an insulating layer which covers a side surface of the lower side wall and exposes an upper surface,
Between the exposed upper surface of the lower side wall and the middle of the pair of lower side walls,
An upper side wall and an internal conductor member, which are a part of the lateral conductor layer, are formed in the groove formed in the insulating layer formed to cover the side surface of the lower side wall in the shape of the groove of the insulating layer. The step of forming an insulating layer covering the inner conductor member and exposing the upper surface of the upper side wall, and forming an upper conductive layer on the insulating layer to be joined to the upper side wall exposed.
The method according to claim 5, which is produced by
層の１つを上に形成した剛性のベース上で行う、請求項
５〜７のいずれか１つに記載の方法。8. The method according to claim 5, wherein the insulating layer and the wiring layer are formed on a rigid base on which one of the insulating layers is formed.
の間に、当該絶縁層の当該剛性ベースへの密着性を高め
る材料の膜を設ける、請求項８記載の方法。9. The method of claim 8, wherein a film of a material that enhances the adhesion of the insulating layer to the rigid base is provided between the rigid base and the insulating layer thereon.
みに設け、そして前記絶縁層と配線層のそれぞれ所定回
数の形成を終了後に、当該剛性ベース上の当該膜の設け
られていない領域から薄膜多層配線基板を剥離する、請
求項９記載の方法。10. The thin film is provided from a region where the film is not provided on the rigid base after the film is provided only on a part of the rigid base and the insulating layer and the wiring layer are formed a predetermined number of times. The method according to claim 9, wherein the multilayer wiring board is peeled off.
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|---|---|---|---|
| JP2002020436A JP4067313B2 (en) | 2002-01-29 | 2002-01-29 | Manufacturing method of thin film multilayer wiring board |
| US10/338,646 US6943447B2 (en) | 2002-01-10 | 2003-01-09 | Thin film multi-layer wiring substrate having a coaxial wiring structure in at least one layer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002020436A JP4067313B2 (en) | 2002-01-29 | 2002-01-29 | Manufacturing method of thin film multilayer wiring board |
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| Publication Number | Publication Date |
|---|---|
| JP2003224357A true JP2003224357A (en) | 2003-08-08 |
| JP4067313B2 JP4067313B2 (en) | 2008-03-26 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005276957A (en) * | 2004-03-23 | 2005-10-06 | Fujitsu Ltd | Printed circuit board |
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2002
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005276957A (en) * | 2004-03-23 | 2005-10-06 | Fujitsu Ltd | Printed circuit board |
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