JP2003218115A - Wiring structure provided with via - Google Patents
Wiring structure provided with viaInfo
- Publication number
- JP2003218115A JP2003218115A JP2002013655A JP2002013655A JP2003218115A JP 2003218115 A JP2003218115 A JP 2003218115A JP 2002013655 A JP2002013655 A JP 2002013655A JP 2002013655 A JP2002013655 A JP 2002013655A JP 2003218115 A JP2003218115 A JP 2003218115A
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- Japan
- Prior art keywords
- wiring
- insulating film
- island
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- view
- Prior art date
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は配線構造および半導
体装置に係わり、特に高速動作・低消費電力化に好適な
配線構造およびそれを有する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure and a semiconductor device, and more particularly to a wiring structure suitable for high speed operation and low power consumption and a semiconductor device having the wiring structure.
【０００２】[0002]
【従来の技術】半導体素子の微細化・高速化のために配
線材料として銅の導入、層間絶縁膜として低誘電率材料
の導入が盛んに検討されている。さらに多層化に際して
の平坦化のために、ＣＭＰ（Chemical Mechanical Po
lishing；化学機械的研磨法）を使ったダマシン法で配
線を形成する方法が広まりつつある。2. Description of the Related Art In order to miniaturize and speed up semiconductor devices, introduction of copper as a wiring material and introduction of a low dielectric constant material as an interlayer insulating film have been actively studied. In addition, CMP (Chemical Mechanical Po
A method of forming wiring by a damascene method using lishing (chemical mechanical polishing method) is becoming widespread.
【０００３】図１、図２、図３(a)、図４（ａ）は、従
来検討されてきた銅もしくはアルミニウムダマシン配線
の形状を示す平面図と鳥瞰図である。実素子ではこの配
線が絶縁膜に埋め込まれているが、この図では周囲の絶
縁膜を描いてない。図において、１は上層配線、２は上
下配線層接続部（ヴィア）、３は下層配線である。1, FIG. 2, FIG. 3 (a) and FIG. 4 (a) are a plan view and a bird's-eye view showing the shape of a copper or aluminum damascene wiring which has been conventionally studied. In an actual device, this wiring is embedded in an insulating film, but the surrounding insulating film is not drawn in this figure. In the figure, 1 is an upper layer wiring, 2 is an upper / lower wiring layer connecting portion (via), and 3 is a lower layer wiring.
【０００４】[0004]
【発明が解決しようとする課題】配線の多層化が３〜４
層以下あるいは配線寸法があまり微細化されていない状
態（ヴィア径０．５μm程度以上）では、上記図１、図
２、図３(a)、図４（ａ）もしくは図３（ｂ），（ｃ）
もしくは図４（ｂ），（ｃ）のような配線構造でも十分
な特性が得られていた。しかし多層化、微細化がすすむ
につれて問題があることが分かってきた。すなわち配線
抵抗、電流密度の都合で太い（幅広の）配線に微細なヴ
ィアが接続する図３（ａ），（ｂ），（ｃ）、図４
（ａ），（ｂ），（ｃ）のような構造があると、配線を
多層化していく過程で上記のような接続領域が優先的に
劣化する（高抵抗化）するという問題が生じることが分
かった。同じ形状のヴィアでも、図１、図２のような細
い配線に接続したヴィアではそのような劣化が起きにく
い。[Problems to be Solved by the Invention] Multilayering of wiring is 3-4.
In the state where the layers or less or the wiring dimension is not miniaturized (via diameter of about 0.5 μm or more), the above-described FIG. 1, FIG. 2, FIG. 3 (a), FIG. 4 (a) or FIG. 3 (b), ( c)
Alternatively, sufficient characteristics were obtained even with the wiring structure shown in FIGS. 4B and 4C. However, it has become clear that there are problems as the number of layers and miniaturization progress. That is, fine vias are connected to thick (wide) wiring due to wiring resistance and current density, as shown in FIGS. 3 (a), (b), (c), and FIG.
If there are structures such as (a), (b), and (c), the problem arises that the above-mentioned connection region is preferentially deteriorated (increased resistance) in the process of multilayering wiring. I understood. Even if the vias have the same shape, such deterioration is unlikely to occur in the vias connected to the thin wiring as shown in FIGS.
【０００５】上記の配線構造で、熱処理法または絶縁膜
の形成方法あるいは形成条件を変えると、定量的な不良
率等の変動はみられるが、確かな信頼性を得る十分なマ
ージンを得られるプロセスにはなり難かった。また微細
化がさらに進めば、そのマージンは狭まってくる。In the above wiring structure, when the heat treatment method, the method of forming the insulating film, or the forming conditions are changed, a change in quantitative defect rate or the like is observed, but a sufficient margin for obtaining reliable reliability is obtained. It was hard to be. Further, if the miniaturization further progresses, the margin becomes narrower.
【０００６】本発明の目的は、上述のようなプロセス条
件とは別の、高信頼度の配線構造およびそれを有する半
導体素子を形成できる抜本的な改善策を提供することに
ある。An object of the present invention is to provide a drastic improvement measure capable of forming a highly reliable wiring structure and a semiconductor device having the wiring structure different from the above process conditions.
【０００７】[0007]
【課題を解決するための手段】本発明は、ヴィア近傍の
配線パターンを最適化することにより、上記課題を解決
したものである。すなわち、先に述べた劣化現象の原因
は十分解明されてはいないものの、以下のようないくつ
かの可能性をあげることができる。The present invention solves the above problems by optimizing the wiring pattern in the vicinity of vias. That is, although the cause of the above-mentioned deterioration phenomenon has not been fully clarified, the following several possibilities can be mentioned.
【０００８】（１）幅広配線内の銅の収縮により、ヴィ
ア内の銅が吸い上げられ、ヴィア内に空洞が発生し、接
続部が高抵抗化する。すなわち銅の収縮は、高温で熱処
理される際、成膜時にできた格子欠陥（原子空孔・粒
界）が集合して大きな欠損・空隙を作るために起こる薄
膜金属に一般的な現象であるが、このとき作られる空隙
の割合は配線の幅によらず一定であるが、幅の広い配線
では空隙の絶対量が大きくなるため、接続しているヴィ
アへの影響が激しいものと考えられる。(1) Due to the contraction of copper in the wide wiring, the copper in the via is sucked up, a cavity is generated in the via, and the resistance of the connection portion becomes high. That is, copper shrinkage is a general phenomenon in thin film metals that occurs when lattice defects (atomic vacancies / grain boundaries) formed during film formation are aggregated to form large defects / voids during heat treatment at high temperature. However, the ratio of the voids created at this time is constant regardless of the width of the wiring, but since the absolute amount of the voids becomes large in a wide wiring, it is considered that the effect on the connecting via is severe.
【０００９】（２）熱処理時に配線の周囲の絶縁膜が銅
配線を取り囲んでいる体積（容積）を増加させるように
変形し、それに追随して配線内の銅も移動し、ヴィア内
に空隙を形成する。ここで、絶縁膜の変形現象は、高い
応力を持った膜の場合に特に顕著であり、アルミニウム
配線ではこのメカニズムによるボイド形成が報告されて
いる（文献１；Y.Sugano他，プロシーディングズ オブ
インタナショナル リライアビリティ フィジクス
（Proc. International Reliability Physics）pp.3
4−38（1988），文献２；K.Hinode他,アイイーイーイー
トランザクションズ オン エレクトロンデバイシズ
（IEEE Trans. On ED），vol.36,pp.1050−1055（19
89））。さらに、幅広配線では上記変形が著しくなる、
あるいは同じ変形量でも電気特性に及ぼす影響が著しく
なる場合がある。(2) During the heat treatment, the insulating film around the wiring is deformed so as to increase the volume (volume) surrounding the copper wiring, and the copper in the wiring is also moved to follow it, forming a void in the via. Form. Here, the deformation phenomenon of the insulating film is particularly remarkable in the case of a film having high stress, and void formation by this mechanism has been reported in the aluminum wiring (Reference 1: Y. Sugano et al., Proceedings of International Reliability Physics (Proc. International Reliability Physics) pp.3
4-38 (1988), Ref. 2; K. Hinode et al., IEEE Trans. On ED, vol.36, pp.1050-1055 (19).
89)). Furthermore, the above deformation becomes remarkable in wide wiring,
Alternatively, even if the amount of deformation is the same, the effect on the electrical characteristics may be significant.
【００１０】（３）幅広配線、もしくはそこに接続して
いるヴィア内の銅の膜質が悪い（格子欠陥が多い）た
め、そのような場所での劣化が著しくなる。(3) Since the quality of the copper film in the wide wiring or in the via connected to the wide wiring is poor (there are many lattice defects), the deterioration in such a place becomes remarkable.
【００１１】以上に考えられる３つの場合を説明した
が、細い配線に接続しているヴィアは十分な特性である
ので、幅広配線に接続したヴィアにおいても、ヴィアと
の接続部近傍では細い配線に接続しているのと同等の構
造にしてやれば、上記３つの可能性のどれであっても対
策できる。その方法として、本発明においては、幅広配
線内のヴィア近傍に絶縁膜の島を設け、ヴィアに接続す
る配線の幅を狭くしてやることで、幅広配線に特有の劣
化現象を克服したものである。The three possible cases have been described above. Since the vias connected to the thin wiring have sufficient characteristics, even the vias connected to the wide wiring have a narrow wiring in the vicinity of the connection portion with the via. Any of the above three possibilities can be dealt with if the structure is equivalent to that of connecting. As a method, in the present invention, an island of an insulating film is provided in the wide wiring in the vicinity of the via and the width of the wiring connected to the via is narrowed to overcome the deterioration phenomenon peculiar to the wide wiring.
【００１２】[0012]
【発明の実施の形態】＜実施例１＞図５（ａ）、図６
（ａ）、図７（ａ）、図８（ａ）は１層目銅配線（図示
略）上にヴィア２と上層（２層目）配線１とを同時に形
成（溝・孔埋め込みおよびＣＭＰ）する、いわゆるデュ
アルダマシン法を採用した配線構造の平面図を示してい
る。BEST MODE FOR CARRYING OUT THE INVENTION <Embodiment 1> FIGS.
(A), FIG. 7 (a), and FIG. 8 (a) simultaneously form a via 2 and an upper layer (second layer) wiring 1 on a first layer copper wiring (not shown) (groove / hole filling and CMP). 2 shows a plan view of a wiring structure that employs a so-called dual damascene method.
【００１３】半導体基板上にトランジスタ、キャパシタ
等の素子を形成したのち素子の上に絶縁膜を形成してか
ら（図示略）その上に本発明のような層間配線構造を形
成した。層間の絶縁膜（図示略）は代表的なｐ−ＣＶＤ
−ＳｉＯ2膜（Plasma Enhanced Chemical Vapor De
position）であるＴＥＯＳ（Tetra−Ethoxy Silane）
膜を用い、エッチングストップ（図示略）としてｐ−Ｃ
ＶＤ−ＳｉＮ（Silicon Nitride；窒化シリコン）膜を
積層した。膜厚はヴィア深さ０．５μm、配線厚さ０．
３μmとなるようにした。After forming elements such as transistors and capacitors on a semiconductor substrate, an insulating film was formed on the elements (not shown), and then an interlayer wiring structure according to the present invention was formed thereon. An insulating film (not shown) between layers is a typical p-CVD
-SiO 2 film (Plasma Enhanced Chemical Vapor De
position) TEOS (Tetra-Ethoxy Silane)
Using a film, p-C as an etching stop (not shown)
A VD-SiN (Silicon Nitride) film was laminated. The film thickness is via depth 0.5 μm, and wiring thickness is 0.
It was set to 3 μm.
【００１４】本実施例では、ヴィア２に接して（フォト
工程による合わせずれのため僅かな隙間ができる場合も
含む）各図に示すような絶縁膜の島４を設けた。島の形
状についての制約はないが、配線抵抗への影響が少なく
電流経路をできるだけ妨げないように、できるだけ小さ
く、平面図上の長手方向が配線の長手方向に平行になる
よう形成するのが望ましい。以上はヴィアの上層配線に
島を設けたものであるが、同様の製造工程で下層配線に
島を設けたものをそれぞれ図５（ｂ）、図６（ｂ）、図
７（ｂ）、図８（ｂ）に、上下両層の配線に島を設けた
ものを図５（ｃ）、図６（ｃ）、図７（ｃ）、図８
（ｃ）に示す。In this embodiment, the island 4 of the insulating film as shown in each drawing is provided in contact with the via 2 (including the case where a slight gap is formed due to misalignment due to a photo process). Although there is no restriction on the shape of the island, it is desirable to form it so that the longitudinal direction on the plan view is parallel to the longitudinal direction of the wiring so that the wiring resistance is less affected and the current path is prevented as much as possible. . The above is a via provided with islands in the upper wiring, but FIG. 5 (b), FIG. 6 (b), FIG. 7 (b), and FIG. 8 (b) is a wiring in which upper and lower layers are provided with islands, and FIG. 5 (c), FIG. 6 (c), FIG. 7 (c), and FIG.
It shows in (c).
【００１５】図９（ａ）、図１０（ａ）、図１１
（ａ）、図１２（ａ）の実施例は、ヴィア２に接しては
いないものの、ヴィア２の近傍に前記実施例と同様形状
の絶縁膜の島４を設けたものである。この実施例ではヴ
ィア２に接して島４を設けた実施例に比べて相対的に高
信頼化の程度は劣るが、島４を設けたことによる配線抵
抗等への影響は前記実施例よりも減らすことができるの
で、要求に応じて使い分ければよい。以上はヴィアの上
層配線に島を設けたものであるが、同様の製造工程で下
層配線に島を設けたものをそれぞれ図９（ｂ）、図１０
（ｂ）、図１１（ｂ）、図１２（ｂ）に、上下両層の配
線に島を設けたものを、図９（ｃ）、図１０（ｃ）、図
１１ｃ）、図１２（ｃ）に示す。9 (a), 10 (a) and 11
In the embodiment of FIGS. 12A and 12A, although not in contact with the via 2, an island 4 of an insulating film having the same shape as that of the above embodiment is provided in the vicinity of the via 2. In this embodiment, the degree of high reliability is relatively inferior to the embodiment in which the island 4 is provided in contact with the via 2, but the influence on the wiring resistance and the like due to the provision of the island 4 is more than that in the above-mentioned embodiment. Since it can be reduced, it can be used properly according to requirements. Although the above is the one in which the island is provided in the upper wiring of the via, FIG. 9B and FIG. 10 show the one in which the island is provided in the lower wiring in the same manufacturing process.
FIGS. 9 (c), 10 (c), 11c), and 12 (c) are shown in FIGS. 9 (b), 11 (b), and 12 (b) in which islands are provided in the upper and lower wirings. ).
【００１６】上層ないし下層の幅の太い配線の幅を５μ
m、細い配線の幅を０．２μmとしてとし、ヴィア２の径
を３μmおよび０．２μmとしてそれぞれ１００００個、
直列に接続したＴＥＧ（Test Element Group；特性評
価用のパターン）を形成し、本発明の効果を評価した結
果を表１, 表２, 表３に示す。The width of the thick wiring in the upper or lower layer is set to 5 μm.
m, the width of the fine wiring is 0.2 μm, the diameter of the via 2 is 3 μm and 0.2 μm, and 10000 pieces each.
Tables 1, 2 and 3 show the results of evaluating the effects of the present invention by forming TEGs (Test Element Group; patterns for characteristic evaluation) connected in series.
【表１】 [Table 1]
【表２】 [Table 2]
【表３】 [Table 3]
【００１７】上記の結果は次のようにまとめられる。配
線形成初期はあまり構造によらず、ほとんど１００％の
歩留まりが得られている。しかし、追加熱処理を施すと
構造の差が見えてくる。まず熱処理温度が高いほど、そ
してヴィア径が小さいほど劣化が著しい。島の設け方に
よる差も見られる。図５（ａ），（ｂ），（ｃ）の構造
でも従来構造に比べると大きな改善効果があるが、今回
の熱処理に対しては必ずしも充分ではない。できるだけ
ヴィアの近くに置いた大面積のものほど効果が大きくな
っている。The above results can be summarized as follows. At the initial stage of wiring formation, the yield was almost 100% regardless of the structure. However, when the additional heat treatment is applied, the difference in structure becomes apparent. First, the higher the heat treatment temperature and the smaller the via diameter, the more remarkable the deterioration. There are also differences depending on how the islands are set up. The structures of FIGS. 5A, 5B, and 5C also have a great improvement effect as compared with the conventional structure, but are not always sufficient for the heat treatment of this time. The larger the area placed as close to the via as possible, the greater the effect.
【００１８】今回の熱処理に対しては、図６（ａ）、図
７（ａ）、図８（ａ）、もしくは図６（ｂ）、図７
（ｂ）、図８（ｂ）、もしくは図６（ｃ）、図７
（ｃ）、図８（ｃ）の構造を採れば十分な耐性が確保で
きる。より熱処理条件の軽いものに対しては他の構造で
も対応できる場合がある。For the heat treatment of this time, FIG. 6 (a), FIG. 7 (a), FIG. 8 (a), or FIG. 6 (b), FIG.
(B), FIG. 8 (b), or FIG. 6 (c), FIG.
Sufficient durability can be ensured by adopting the structure of (c) and FIG. 8 (c). In some cases, other structures can be applied to those with lighter heat treatment conditions.
【００１９】＜実施例２＞ 繰り返し熱処理による劣化
の実施例
高温での熱処理が短時間であったり、１・２回ですむ場
合は上記の構造で対処できる。しかし、配線が５層以上
に多層化される場合も少なくない。実施例１で述べた配
線構造は１層分であるが、これを５回積層して、５層配
線を形成した。すなわち最下層の配線は少なくとも５回
の熱処理を経ることになる。Example 2 Example of Deterioration by Repeated Heat Treatment When the heat treatment at high temperature is short or only once or twice, the above structure can be used. However, there are not a few cases where the wiring is multi-layered into five or more layers. Although the wiring structure described in Example 1 is for one layer, it was laminated five times to form a five-layer wiring. That is, the lowermost wiring is subjected to heat treatment at least 5 times.
【００２０】この熱処理に対しては、実施例１で述べた
図６（ａ）、図７（ａ）、図８（ａ）の構造でも劣化が
著しく、実際の素子ではさらに耐性を向上させる必要が
ある。そのため、図１３（ａ）、図１４（ａ）、図１５
（ａ）、図１６（ａ）、図１７（ａ）、図１８（ａ）、
図１９（ａ）、図２０（ａ）のようにヴィアの２方向以
上に絶縁膜の島４を設けた構造の配線を５層積層したＴ
ＥＧを形成し、前実施例と同様にして１層目のヴィアチ
ェーンの歩留まりを測定した。ここで、各図は前記実施
例と同様に１層目配線（図示略）上にヴィア２と２層目
配線１を形成した場合の平面図を示している。With respect to this heat treatment, the structures shown in FIGS. 6 (a), 7 (a) and 8 (a) described in the first embodiment are significantly deteriorated, and it is necessary to further improve resistance in an actual device. There is. Therefore, FIG. 13 (a), FIG. 14 (a), and FIG.
(A), FIG. 16 (a), FIG. 17 (a), FIG. 18 (a),
As shown in FIG. 19A and FIG. 20A, five layers of wiring having a structure in which islands 4 of an insulating film are provided in two or more directions of vias are laminated T
EG was formed, and the yield of the via chain of the first layer was measured in the same manner as in the previous example. Here, each drawing shows a plan view in the case where the via 2 and the second layer wiring 1 are formed on the first layer wiring (not shown) as in the above-described embodiment.
【００２１】この場合もヴィアと上層配線とを同時に形
成（溝・孔埋め込みおよびＣＭＰ）する、いわゆるデュ
アルダマシン法を採用している。層間の絶縁膜は実施例
１と同様に、ＴＥＯＳ膜を用い、エッチングストップと
してＳｉＮ膜を積層した。１層分の膜厚はヴィア深さ
０．５μm、配線厚さ０．３μmとなるようにした。ま
た、このＴＥＧでは１層形成するために、４００℃以下
で総計約１５分間、４２５℃で約１０分間の熱処理が施
されている。歩留まり測定前に熱処理は施していない。Also in this case, a so-called dual damascene method is adopted in which the via and the upper layer wiring are simultaneously formed (groove / hole filling and CMP). A TEOS film was used as the interlayer insulating film as in Example 1, and a SiN film was laminated as an etching stop. The film thickness for one layer was such that the via depth was 0.5 μm and the wiring thickness was 0.3 μm. In addition, in order to form one layer in this TEG, heat treatment is performed at 400 ° C. or lower for a total of about 15 minutes and at 425 ° C. for about 10 minutes. No heat treatment was performed before the yield measurement.
【００２２】図１３（ａ）、図１４（ａ）、図１５
（ａ）、図１６（ａ）ではヴィア２に接して図に示すよ
うな絶縁膜の島４を設けた。また、図１７（ａ）、図１
８（ａ）、図１９（ａ）、図２０（ａ）はヴィア径分の
距離を置いてヴィア２の近傍に同様の絶縁膜４の島を設
けたものである。作用の項で述べたように、数種類の劣
化機構のいずれが働くとしても、原子拡散、応力、結晶
粒成長のどれかで島の影響が見えると高信頼化の効果が
期待できる。その観点からヴィア径もしくは膜厚の２倍
程度までは効果が強く５倍程度を越えると効果が僅かに
なる。今の場合膜厚はヴィア径とほぼ同じである。図１
７（ａ）、図１８（ａ）、図１９（ａ）、図２０（ａ）
の例ではヴィアに接して島を設けたものに比べて、高信
頼化の程度は劣るが、島を設けたことによる配線抵抗等
への影響をより減らすことができるので、実施に当たっ
ては、要求に応じて使い分ければよいことは前述と同様
である。ここでも実施例１と同様の製造工程で下層配線
に島を設けたものをそれぞれ図１３（ｂ）、図１４
（ｂ）、図１５（ｂ）、図１６（ｂ）、図１７（ｂ）、
図１８（ｂ）、図１９（ｂ）、図２０（ｂ）に、上下両
層の配線に島を設けたものを、図１３（ｃ）、図１４
（ｃ）、図１５（ｃ）、図１６（ｃ）、図１７（ｃ）、
図１８（ｃ）、図１９（ｃ）、図２０（ｃ）に示す。実
施例１と同様に上層ないし下層の幅の太い配線の幅を５
μm、細い配線の幅を０．２μmとし、ヴィア径として
０．３μmおよび０．２μmのものをそれぞれ１００００
個直列に接続したＴＥＧを形成して評価した結果を表
４, 表５, 表６に示す。13 (a), 14 (a) and 15
In FIGS. 16A and 16A, the island 4 of the insulating film as shown in the figure is provided in contact with the via 2. 17 (a) and FIG.
8 (a), FIG. 19 (a), and FIG. 20 (a), the same island of the insulating film 4 is provided in the vicinity of the via 2 with a distance corresponding to the via diameter. As described in the section of action, regardless of which of several kinds of deterioration mechanisms works, if the effect of the island can be seen in any of atomic diffusion, stress, and grain growth, the effect of high reliability can be expected. From that point of view, the effect is strong up to about twice the via diameter or the film thickness, and the effect becomes small if it exceeds about 5 times. In this case, the film thickness is almost the same as the via diameter. Figure 1
7 (a), FIG. 18 (a), FIG. 19 (a), and FIG. 20 (a)
In the example above, the degree of high reliability is inferior to the one in which an island is provided in contact with the via, but the effect on the wiring resistance etc. due to the provision of the island can be further reduced. It is the same as described above that it can be used properly according to. Also in this case, the lower wirings provided with islands in the same manufacturing process as in Embodiment 1 are shown in FIGS.
(B), FIG. 15 (b), FIG. 16 (b), FIG. 17 (b),
18 (b), 19 (b), and 20 (b), wirings of upper and lower layers having islands are shown in FIGS.
(C), FIG. 15 (c), FIG. 16 (c), FIG. 17 (c),
18 (c), 19 (c), and 20 (c). As in the first embodiment, the width of the thick wiring in the upper or lower layer is set to 5
μm, the width of thin wiring is 0.2 μm, and the via diameters are 0.3 μm and 0.2 μm, respectively.
Tables 4, 5, and 6 show the results of evaluation by forming TEGs connected in series.
【表４】 [Table 4]
【表５】 [Table 5]
【表６】 [Table 6]
【００２３】上記の結果は次のようにまとめられる。ヴ
ィア径が小さいほど劣化が著しく初期歩留まりが低い。
島の設け方による差も見られ、図１３（ａ），（ｂ），
（ｃ）の構造では図６（ａ），（ｂ），（ｃ）の構造と
大差なく、このプロセスで十分な耐性を持っていない。
図１４（ａ），（ｂ），（ｃ）ないし図１６（ａ），
（ｂ），（ｃ）のように、できるだけヴィアの近くに置
いた大面積の島ほど効果が大きくなっている。今回の熱
処理に対しては、図１４（ａ），（ｂ），（ｃ）また
は、図１６（ａ），（ｂ），（ｃ）の構造を採れば十分
な耐性が確保できる。層数の少ないものに対しては他の
構造でも対応できる場合がある。また、図１５（ｂ）の
ように４つの方向に絶縁体の島を設けると効果が大き
い。後の実施例で述べるように島の長さはヴィア径もし
くは配線厚の５倍程度以上が有効な範囲だが４方に設け
ることでヴィア径もしくは配線厚と同程度以上で効果が
みられる。表５に示した歩留まりの値は島の長さがヴィ
ア径もしくは配線厚の２倍の場合の値である。The above results can be summarized as follows. The smaller the via diameter, the more significant the deterioration and the lower the initial yield.
There are some differences depending on how the islands are set up, as shown in Figures 13 (a), (b),
The structure of (c) is not so different from the structures of FIGS. 6 (a), (b), and (c), and does not have sufficient resistance in this process.
14 (a), (b), (c) to FIG. 16 (a),
As shown in (b) and (c), the larger the area of the island placed as close to the via, the greater the effect. Sufficient resistance can be secured to this heat treatment by adopting the structure of FIGS. 14A, 14B, and 14C or FIGS. 16A, 16B, and 16C. Other structures may be applicable to those with a small number of layers. Further, as shown in FIG. 15B, the effect is great when the islands of the insulator are provided in four directions. As will be described in a later example, the island length is in an effective range of about 5 times the via diameter or the wiring thickness, but by providing the islands on four sides, the effect can be seen at the same level or more as the via diameter or the wiring thickness. The yield values shown in Table 5 are the values when the island length is twice the via diameter or the wiring thickness.
【００２４】＜実施例３＞図２１（ａ）、図２２
（ａ）、図２３（ａ）、図２４（ａ）も前記実施例と同
様に１層目配線（図示略）上にヴィア２と２層目配線１
を形成した場合の平面図を示している。本実施例は、複
数のヴィアがある場合に、できるだけヴィアの多数の方
向に島を設け、かつ配線への影響が少なくなるように島
を配置した例である。<Embodiment 3> FIGS. 21 (a) and 22.
In FIGS. 23 (a), 23 (a) and 24 (a), the via 2 and the second layer wiring 1 are formed on the first layer wiring (not shown) as in the above-described embodiment.
It shows a plan view in the case of forming. The present embodiment is an example in which when there are a plurality of vias, islands are provided in as many directions as possible and the islands are arranged so as to reduce the influence on the wiring.
【００２５】図２１（ａ）、図２２（ａ）、図２３
（ａ）、図２４（ａ）の構造で配線を５層積層したＴＥ
Ｇを形成し、前の実施例と同様にして１層目のヴィアチ
ェーンの歩留まりを測定した。このＴＥＧでは一層形成
するための熱処理として、４００℃以下の熱処理が総計
約１５分間、４２５℃で約１０分間の熱処理が施されて
いる。歩留まり測定前に熱処理は施していない。21 (a), 22 (a) and 23
(A), TE with 5 layers of wiring laminated in the structure of FIG. 24 (a)
G was formed, and the yield of the first layer via chain was measured in the same manner as in the previous example. In this TEG, as a heat treatment for forming one layer, a heat treatment at 400 ° C. or less is performed for a total of about 15 minutes, and a heat treatment at 425 ° C. for about 10 minutes. No heat treatment was performed before the yield measurement.
【００２６】この場合もヴィアと上層配線とを同時に形
成（溝・孔埋め込みおよびＣＭＰ）する、いわゆるデュ
アルダマシン法を採用している。層間の絶縁膜（図示
略）は実施例１と同様にＴＥＯＳ膜を用い、エッチング
ストップ（図示略）としてＳｉＮ膜を積層した。１層分
の膜厚はヴィア深さ０．５μm、配線厚さ０．３μmとな
るようにした。Also in this case, a so-called dual damascene method is adopted in which the via and the upper wiring are simultaneously formed (groove / hole filling and CMP). A TEOS film was used as an interlayer insulating film (not shown) as in Example 1, and a SiN film was laminated as an etching stop (not shown). The film thickness for one layer was such that the via depth was 0.5 μm and the wiring thickness was 0.3 μm.
【００２７】前記実施例と同様に、下層幅広配線に島を
設けるもの（図２１（ｂ）、図２２（ｂ）、図２３
（ｂ）、図２４（ｂ））、上下両層配線に島を設けるも
の（図２１（ｃ）、図２２（ｃ）、図２３（ｃ）、２４
（ｃ））を同じ製造工程で作製した。上層もしくは下層
の幅の広い配線の幅は５μm、幅の狭い配線の幅は0.2μ
mとし、ヴィア２の径として０．３μmおよび０．２μm
のものをそれぞれ１００００個直列に接続したＴＥＧを
形成して評価した。この結果、図２１（ａ）、図２２
（ａ）、図２３（ａ）、図２４（ａ）および図２１
（ｂ）、図２２（ｂ）、図２３（ｂ）、図２４（ｂ）お
よび図２１（ｃ）、図２２（ｃ）、図２３（ｃ）、２４
（ｃ）の構造でほぼ９８％以上の歩留まりが得られ、こ
のようなヴィア近傍の島の配置が高信頼化に有効である
ことを確認した。Similar to the above-mentioned embodiment, the lower wide wiring is provided with islands (FIG. 21 (b), FIG. 22 (b), FIG. 23).
(B), FIG. 24 (b), those in which islands are provided in the upper and lower wirings (FIG. 21 (c), FIG. 22 (c), FIG. 23 (c), 24)
(C)) was manufactured in the same manufacturing process. The width of the wide wiring in the upper or lower layer is 5 μm, and the width of the narrow wiring is 0.2 μm.
m and the diameter of via 2 is 0.3 μm and 0.2 μm
Each of 10,000 TEGs was connected in series to form a TEG and evaluated. As a result, FIG.
(A), FIG. 23 (a), FIG. 24 (a) and FIG.
(B), FIG. 22 (b), FIG. 23 (b), FIG. 24 (b) and FIG. 21 (c), FIG. 22 (c), FIG. 23 (c), 24
With the structure of (c), a yield of approximately 98% or more was obtained, and it was confirmed that such an island arrangement in the vicinity of vias is effective for high reliability.
【００２８】＜実施例４＞図２５ないし図２６は、複数
のヴィア２がある場合に、島の形成による電気特性の劣
化ができるだけ少なくなるように島を配置した例であ
る。前記実施例と同様に１層目配線（図示略）上にヴィ
ア２と２層目配線１を形成した場合の平面図を示してい
る。また、図２７ないし図２８はヴィアの２方向以上に
絶縁膜を設ける際、一方向を島ではなく、配線端で兼用
させた場合の島の配置例である。<Embodiment 4> FIGS. 25 to 26 are examples in which the islands are arranged so that the deterioration of the electrical characteristics due to the formation of the islands is minimized when there are a plurality of vias 2. Similar to the above embodiment, a plan view is shown in which the via 2 and the second layer wiring 1 are formed on the first layer wiring (not shown). 27 to 28 are examples of island arrangement when the insulating film is provided in two or more directions of the via, and one direction is used not as the island but as the wiring end.
【００２９】図２５ないし図２８の構造で配線を５層積
層したＴＥＧを形成し、前の実施例と同様にして１層目
のヴィアチェーンの歩留まりを測定した。このＴＥＧで
は１層形成するたびに、４００℃以下で総計約１５分
間、４２５℃で約１０分間の熱処理が施されている。歩
留まり測定前に熱処理は施していない。A TEG having five layers of wiring having the structure of FIGS. 25 to 28 was formed, and the yield of the via chain of the first layer was measured in the same manner as in the previous example. Each time one layer is formed in this TEG, heat treatment is performed at 400 ° C. or lower for a total of about 15 minutes and at 425 ° C. for about 10 minutes. No heat treatment was performed before the yield measurement.
【００３０】この場合もヴィアと上層配線とを同時に形
成（溝・孔埋め込みおよびＣＭＰ）する、いわゆるデュ
アルダマシン法を採用している。層間の絶縁膜は実施例
１と同様に、ＴＥＯＳ膜を用い、エッチングストップと
してＳｉＮ膜を積層した。１層分の膜厚はヴィア深さ
０．５μm、配線厚さ０．３μmとなるようにした。上層
配線の幅は５μmとし、ヴィア径として０．３μmおよび
０．２μmのものをそれぞれ１００００個直列に接続し
たＴＥＧを形成して評価した。Also in this case, the so-called dual damascene method is adopted in which the via and the upper wiring are simultaneously formed (groove / hole filling and CMP). A TEOS film was used as the interlayer insulating film as in Example 1, and a SiN film was laminated as an etching stop. The film thickness for one layer was such that the via depth was 0.5 μm and the wiring thickness was 0.3 μm. The width of the upper layer wiring was set to 5 μm, and 10000 pieces of via diameters of 0.3 μm and 0.2 μm were connected in series to form a TEG for evaluation.
【００３１】その結果、図２５から図２８の構造でほぼ
９８％以上の歩留まりが得られ、島を設けないもの（歩
留まりは３０％以下）に比べて極めて高く、本実施例の
ようなヴィア近傍の島の配置が高信頼化に有効であるこ
とを確認した。As a result, a yield of about 98% or more can be obtained in the structure of FIGS. 25 to 28, which is extremely higher than that of the structure without an island (yield of 30% or less). It was confirmed that the island layout was effective for high reliability.
【００３２】また、図２９ないし図３２、および図３３
ないし図３６に示すように、島を設けるのではなく、配
線の側面を変形させても本発明の効果を得ることができ
るのは言うまでもない。これらは下層の配線の幅が広い
ときも同様に配線の側面を変形させることで同等の効果
を得ることが出来た。その際もヴィア近傍（ヴィア径若
しくは配線厚さの２倍程度以内の距離）に配線側面を設
けることで高い効果を得られるが、５倍程度の距離以上
に離れると効果は僅かになる。29 to 32 and 33.
It is needless to say that the effect of the present invention can be obtained by deforming the side surface of the wiring instead of providing the island as shown in FIG. Even when the width of the wiring in the lower layer was wide, the same effect could be obtained by similarly deforming the side surface of the wiring. Also in this case, a high effect can be obtained by providing the wiring side surface in the vicinity of the via (a distance within about twice the via diameter or the wiring thickness), but the effect becomes small when the distance is more than about five times.
【００３３】＜実施例５＞実施例１と同様のＴＥＧで、
上層配線の幅を変えたものを作成し、歩留まりを測定し
比較した結果を表７に示す。<Embodiment 5> With the same TEG as in Embodiment 1,
Table 7 shows the results of making and changing the width of the upper layer wiring and measuring the yield.
【表７】 [Table 7]
【００３４】本実施例の結果、上層配線の幅が狭い場
合、劣化が生じにくく、ヴィアの径もしくは配線厚さ
（今の場合共に0.2-0.3μｍ）の５倍程度以下では殆ど
劣化がない。配線幅がヴィア径もしくは配線厚さの１０
倍程度を超えると熱処理による劣化が著しくなることが
わかる。配線厚さやヴィアの寸法が変化したときもこの
ような傾向は保たれる。厳密な数値ではないが５倍程度
以下では劣化が殆どなく、１０倍程度以上では効果が不
充分となる。As a result of this embodiment, when the width of the upper layer wiring is narrow, deterioration is unlikely to occur, and there is almost no deterioration when the diameter of the via or the wiring thickness (in this case, 0.2-0.3 μm) is about 5 times or less. Wiring width is via diameter or wiring thickness 10
It can be seen that if it exceeds about twice, deterioration due to heat treatment becomes remarkable. This tendency is maintained even when the wiring thickness and the via size change. Although it is not a strict numerical value, there is almost no deterioration at about 5 times or less, and the effect becomes insufficient at about 10 times or more.
【００３５】＜実施例６＞実施例５と同様に、下層配線
の幅を変えたものを作成し、歩留まりを測定し比較し
た。その結果、実施例５とほぼ同等の高信頼化効果が得
られた。下層配線の幅が狭い場合、劣化が生じにくく、
ヴィアの径もしくは配線厚さ（今の場合共に0.2-0.3μ
ｍ）の５倍程度以下では殆ど劣化がない。配線幅がヴィ
ア径もしくは配線厚さの１０倍程度を超えると熱処理に
よる劣化が著しくなることがわかる。配線厚さやヴィア
の寸法が変化したときもこのような傾向は保たれる。厳
密な数値ではないが５倍程度以下では劣化が殆どなく、
１０倍程度以上では効果が不充分となる。<Embodiment 6> As in the case of Embodiment 5, those in which the width of the lower layer wiring was changed were prepared, and the yields were measured and compared. As a result, a high-reliability effect almost equal to that of Example 5 was obtained. When the width of the lower layer wiring is narrow, deterioration does not easily occur,
Via diameter or wiring thickness (in this case 0.2-0.3μ
There is almost no deterioration at about 5 times or less than m). It can be seen that when the wiring width exceeds about 10 times the via diameter or the wiring thickness, the deterioration due to the heat treatment becomes remarkable. This tendency is maintained even when the wiring thickness and the via size change. It is not a strict number, but there is almost no deterioration at about 5 times or less,
If it is about 10 times or more, the effect becomes insufficient.
【００３６】＜実施例７＞実施例１と同様のＴＥＧで、
上下両層配線の幅を変えたものを作成し、歩留まりを測
定し比較した。その結果、実施例５とほぼ同等の高信頼
化効果が得られた。上下層配線の幅が狭い場合、劣化が
生じにくく、ヴィアの径もしくは配線厚さ（今の場合共
に0.2-0.3μｍ）の５倍程度以下では殆ど劣化がない。
配線幅がヴィア径もしくは配線厚さの１０倍程度を超え
ると熱処理による劣化が著しくなることがわかる。配線
厚さやヴィアの寸法が変化したときもこのような傾向は
保たれる。厳密な数値ではないが５倍程度以下では劣化
が殆どなく、１０倍程度以上では効果が不充分となる。<Embodiment 7> With the same TEG as in Embodiment 1,
The widths of the upper and lower wiring layers were changed, and the yields were measured and compared. As a result, a high-reliability effect almost equal to that of Example 5 was obtained. When the width of the upper and lower wirings is narrow, deterioration is unlikely to occur. Almost no deterioration occurs when the width of the vias or the wiring thickness (in this case, 0.2 to 0.3 μm) is about 5 times or less.
It can be seen that when the wiring width exceeds about 10 times the via diameter or the wiring thickness, the deterioration due to the heat treatment becomes remarkable. This tendency is maintained even when the wiring thickness and the via size change. Although it is not a strict numerical value, there is almost no deterioration at about 5 times or less, and the effect becomes insufficient at about 10 times or more.
【００３７】＜実施例８＞島の大きさ（長さ）依存性に
ついて評価するために、実施例１の図６（ａ）、図１０
（ａ）、図１４（ａ）と同様のＴＥＧで、島の長さを変
えたものを作成し、歩留まりを測定し比較した結果を表
８に示す。<Embodiment 8> In order to evaluate the size (length) dependency of the island, FIG. 6A and FIG.
Table 8 shows the results obtained by making TEGs similar to (a) and FIG. 14 (a) with different island lengths, measuring yields, and comparing them.
【表８】
上記の結果はヴィアの径に比べて上層配線中の島の長さ
が短いと劣化しやすいものの、島を十分長くし、ヴィア
径若しくは配線厚さの５倍程度を超えると高い信頼度が
得られることを示している。配線厚さやヴィアの寸法が
変化したときもこのような傾向は保たれる。厳密な数値
ではないが５倍程度以上で十分な効果が得られる。表４
では島の長さについてのみ検討した結果を示したが、島
の幅等にも依存すると考えられる。配線の電気特性に対
する悪影響が最小で効果が最大の形状については、個々
の場合について求めて最適化すればよい。[Table 8] The above results show that if the length of the island in the upper layer wiring is shorter than the diameter of the via, it tends to deteriorate, but if the island is made sufficiently long and exceeds 5 times the via diameter or wiring thickness, high reliability can be obtained. Is shown. This tendency is maintained even when the wiring thickness and the via size change. Although not a strict numerical value, a sufficient effect can be obtained at about 5 times or more. Table 4
In the above, the result of studying only the island length was shown, but it is considered that it also depends on the island width and the like. The shape having the minimum adverse effect on the electrical characteristics of the wiring and the maximum effect may be obtained and optimized for each case.
【００３８】＜実施例９＞島の大きさ（長さ）依存性に
ついて評価するために、実施例１の図６（ｂ）、図1０
（ｂ）、図１４（ｂ）と同様のＴＥＧで、島の長さを変
えたものを作成し、歩留まりを測定し比較した。実施例
６とほぼ同傾向の結果がえられた。すなわちヴィアの径
に比べて下層配線中の島の長さが短いと劣化しやすいも
のの、島を十分長くし、ヴィア径若しくは配線厚さの５
倍程度を超える長さにすると高い信頼度が得られる。配
線厚さやヴィアの寸法が変化したときもこのような傾向
は保たれる。厳密な数値ではないが５倍程度以上で十分
な効果が得られる。配線の電気特性に対する悪影響が最
小で効果が最大の形状については、個々の場合について
求めて最適化すればよい。<Embodiment 9> In order to evaluate the island size (length) dependence, FIG. 6B and FIG.
TEGs similar to those shown in FIGS. 14B and 14B were prepared with different island lengths, and the yields were measured and compared. The result having almost the same tendency as in Example 6 was obtained. That is, when the length of the island in the lower layer wiring is shorter than the diameter of the via, the island is easily deteriorated, but the island is sufficiently long and the via diameter or the wiring thickness is 5
High reliability can be obtained if the length exceeds about twice. This tendency is maintained even when the wiring thickness and the via size change. Although not a strict numerical value, a sufficient effect can be obtained at about 5 times or more. The shape having the minimum adverse effect on the electrical characteristics of the wiring and the maximum effect may be obtained and optimized for each case.
【００３９】＜実施例１０＞島の大きさ（長さ）依存性
について評価するために、実施例１の図６（ｃ）、図1
０（ｃ）、図１４（ｃ）と同様のＴＥＧで、島の長さを
変えたものを作成し、歩留まりを測定し比較した。実施
例６とほぼ同傾向の結果がえられた。すなわちヴィアの
径に比べて上下層配線中の島の長さが短いと劣化しやす
いものの、島を十分長くし、ヴィア径若しくは配線厚さ
の５倍程度を超える長さにすると高い信頼度が得られ
る。上層、若しくは下層それぞれを高信頼化することで
全体としても高信頼化できる。配線厚さやヴィアの寸法
が変化したときもこのような傾向は保たれる。厳密な数
値ではないが５倍程度以上で十分な効果が得られる。配
線の電気特性に対する悪影響が最小で効果が最大の形状
については、個々の場合について求めて最適化すればよ
い。<Embodiment 10> In order to evaluate the island size (length) dependency, FIG. 6C and FIG.
0 (c), TEGs similar to those shown in FIG. 14 (c) were produced with different island lengths, and the yields were measured and compared. The result having almost the same tendency as in Example 6 was obtained. That is, if the length of the islands in the upper and lower wirings is shorter than the diameter of the vias, the islands are likely to deteriorate, but if the islands are made sufficiently long and the length exceeds about 5 times the via diameter or the wiring thickness, high reliability can be obtained. . By making the upper layer or the lower layer highly reliable, the reliability as a whole can be made high. This tendency is maintained even when the wiring thickness and the via size change. Although not a strict numerical value, a sufficient effect can be obtained at about 5 times or more. The shape having the minimum adverse effect on the electrical characteristics of the wiring and the maximum effect may be obtained and optimized for each case.
【００４０】＜実施例１１＞本発明の実施例はすべてダ
マシン法で形成した配線について説明している。その方
法では溝と孔を形成した絶縁膜に金属（この実施例では
銅）を埋め込み、ＣＭＰ法で不要部分の銅を除去し、残
したところを配線とする。銅を埋め込む際、シードと呼
ばれる下地層として銅をスパッタ法で薄く形成（最終配
線厚さの１／１０程度）したものに、電解めっき法で厚
い銅を形成している。<Embodiment 11> In all the embodiments of the present invention, the wiring formed by the damascene method is described. In this method, a metal (copper in this embodiment) is embedded in an insulating film having a groove and a hole, unnecessary portions of copper are removed by a CMP method, and the remaining portion is used as a wiring. When burying copper, thick copper is formed by electrolytic plating on a thin layer of copper (about 1/10 of the final wiring thickness) formed by sputtering as an underlayer called a seed.
【００４１】しかし、上記の工程で、比較的深いヴィア
孔を埋め込むための条件と浅い配線溝を埋め込む条件で
は、最適条件が異なる場合が多い。これについては、印
加電流条件をめっき成膜の途中で変化させる手法が一般
に用いられているが、必ずしも十分な効果をあげていな
い。それはヴィアに接続している配線の幅が異なり、デ
ユアルダマシン法の埋め込みの際に、孔と溝が一体とな
って形成されている形状（アスペクト）が広い分布をも
つからである。今回のヴィア近傍に絶縁膜の島を設ける
方法を採用すると、全てのヴィア部のアスペクトを狭い
範囲に収められるため、その形状（アスペクト）に最適
なめっき条件を選択することができる。However, in the above process, the optimum condition is often different between the condition for burying a relatively deep via hole and the condition for burying a shallow wiring groove. For this, a method of changing the applied current condition in the middle of plating film formation is generally used, but it does not always exhibit a sufficient effect. This is because the width of the wiring connected to the via is different and the shape (aspect) in which the hole and the groove are integrally formed has a wide distribution when the dual damascene method is used for embedding. If the method of forming the island of the insulating film in the vicinity of the via is adopted this time, the aspect of all the via portions can be kept within a narrow range, so that the optimum plating condition for the shape (aspect) can be selected.
【００４２】このような考え方に基づき、硫酸銅を主成
分とするめっき液を用いる銅めっきチャンバを２つ用意
し、表９のような組成のめっき液を調整作成した。Based on such an idea, two copper plating chambers using a plating solution containing copper sulfate as a main component were prepared, and a plating solution having a composition shown in Table 9 was prepared.
【表９】
めっきを（１）Ａチャンバのみで最終膜厚まで形成、
（２）Ｂチャンバで最終膜厚まで形成、（３）最初Ａチ
ャンバで１／５の膜厚を形成後、ウェハをＢチャンバに
設置し直して残りの膜厚を形成の３通りの場合について
膜厚均一性、埋め込み性について評価し比較した結果を
表１０に示す。[Table 9] Plating (1) Forming the final film thickness only in chamber A,
(2) In case of forming the final film thickness in the B chamber, (3) First forming the film thickness of ⅕ in the A chamber, then placing the wafer in the B chamber and forming the remaining film thickness in three cases Table 10 shows the results of comparing and comparing the film thickness uniformity and the embedding property.
【表１０】
プロセスが複雑化する欠点があるが、埋め込み性と膜厚
均一性を同時に実現できるという点では表１０の（３）
の方法が（１）または（２）に比べて優れていることが
明らかである。ヴィアの見かけの形状（アスペクト）を
統一することで、このような２段階埋め込みが可能にな
り、ＬＳＩ配線製造に好適な成膜ができるようになるこ
とも、本発明の優れた効果といえる。[Table 10] Although it has a drawback of complicating the process, (3) in Table 10 shows that embedding property and film thickness uniformity can be realized at the same time.
It is clear that the method (1) is superior to the method (1) or (2). By unifying the apparent shape (aspect) of vias, such two-step embedding becomes possible, and it becomes possible to form a film suitable for LSI wiring manufacturing, which is also an excellent effect of the present invention.
【００４３】[0043]
【発明の効果】本発明のヴィア近傍の配線に絶縁膜の島
を設けることで、多層配線の歩留まり、信頼性を向上す
ることができ、高性能のＬＳＩを実現することが可能に
なる。By providing islands of an insulating film in the wiring near the via of the present invention, the yield and reliability of the multilayer wiring can be improved and a high-performance LSI can be realized.
【図１】従来の多層配線のヴィア接続方法の一例を示す
平面図。FIG. 1 is a plan view showing an example of a conventional via connection method for multilayer wiring.
【図２】従来の多層配線のヴィア接続方法の一例を示す
鳥瞰図。FIG. 2 is a bird's-eye view showing an example of a conventional via connection method for multilayer wiring.
【図３】従来の多層配線のヴィア接続方法の一例を示す
平面図。FIG. 3 is a plan view showing an example of a conventional via connection method for multilayer wiring.
【図４】従来の多層配線のヴィア接続方法の一例を示す
鳥瞰図。FIG. 4 is a bird's-eye view showing an example of a conventional via connection method for multilayer wiring.
【図５】本発明の多層配線のヴィア接続方法の一例を示
す平面図。FIG. 5 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図６】本発明の多層配線のヴィア接続方法の一例を示
す平面図。FIG. 6 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図７】本発明の多層配線のヴィア接続方法の一例を示
す平面図。FIG. 7 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図８】本発明の多層配線のヴィア接続方法の一例を示
す平面図。FIG. 8 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図９】本発明の多層配線のヴィア接続方法の一例を示
す平面図。FIG. 9 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図１０】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 10 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図１１】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 11 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図１２】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 12 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図１３】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 13 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図１４】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 14 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図１５】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 15 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図１６】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 16 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図１７】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 17 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図１８】本発明の多層配線のヴィア接続方法の一例を
示す平面図および断面図。18A and 18B are a plan view and a cross-sectional view showing an example of a via connection method for multilayer wiring according to the present invention.
【図１９】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 19 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図２０】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 20 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図２１】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 21 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図２２】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 22 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図２３】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 23 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図２４】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 24 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図２５】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 25 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図２６】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 26 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図２７】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 27 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図２８】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 28 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図２９】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 29 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図３０】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 30 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図３１】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 31 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図３２】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 32 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図３３】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 33 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図３４】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 34 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図３５】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 35 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
【図３６】本発明の多層配線のヴィア接続方法の一例を
示す平面図。FIG. 36 is a plan view showing an example of a via connection method for multilayer wiring according to the present invention.
１…上層配線、２…上下配線層接続孔、３…下層配線、
４…上層配線中に設けた絶縁膜の島、５…下層配線中に
設けた絶縁膜の島、６…上下配線層間の絶縁膜。1 ... Upper layer wiring, 2 ... Upper and lower wiring layer connection holes, 3 ... Lower layer wiring,
4 ... Island of insulating film provided in upper wiring, 5 ... Island of insulating film provided in lower wiring, 6 ... Insulating film between upper and lower wiring layers.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 武田 健一 東京都国分寺市東恋ケ窪一丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 花岡 裕子 東京都国分寺市東恋ケ窪一丁目280番地 株式会社日立製作所中央研究所内 Ｆターム(参考） 5F033 HH08 HH11 JJ01 JJ08 JJ11 KK08 KK11 LL08 MM02 MM29 PP15 PP27 PP33 QQ25 QQ48 QQ73 QQ84 RR04 RR06 SS15 UU04 WW01 XX00 XX01 XX03 XX04 XX05 XX06 XX19 XX28 5F064 EE09 EE23 EE27 EE32 EE33 EE42 EE56 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Kenichi Takeda 1-280, Higashi Koikekubo, Kokubunji, Tokyo Central Research Laboratory, Hitachi, Ltd. (72) Inventor Yuko Hanaoka 1-280, Higashi Koikekubo, Kokubunji, Tokyo Central Research Laboratory, Hitachi, Ltd. F term (reference) 5F033 HH08 HH11 JJ01 JJ08 JJ11 KK08 KK11 LL08 MM02 MM29 PP15 PP27 PP33 QQ25 QQ48 QQ73 QQ84 RR04 RR06 SS15 UU04 WW01 XX00 XX01 XX03 XX04 XX05 XX06 XX19 XX28 5F064 EE09 EE23 EE27 EE32 EE33 EE42 EE56
Claims (5)
配線と下層配線からなる配線構造において、該ヴィアに
接続し、該ヴィア径よりも幅の広い銅もしくはアルミニ
ウムを主成分とする該下層配線で、該ヴィア近傍の配線
内部に該絶縁膜の領域があることを特徴とする配線構
造。1. In a wiring structure comprising an upper layer wiring and a lower layer wiring connected to a via opened in an insulating film, the lower layer mainly composed of copper or aluminum which is connected to the via and has a width wider than the via diameter. A wiring structure in which there is a region of the insulating film inside the wiring near the via.
配線と下層配線からなる配線構造において、該上層配線
または下層配線はバリア等導電性物質の境界なしにヴィ
アに接続していることを特徴とする請求項１に記載の配
線構造。2. A wiring structure comprising an upper layer wiring and a lower layer wiring connected to a via opened in an insulating film, wherein the upper layer wiring or the lower layer wiring is connected to the via without a boundary of a conductive substance such as a barrier. The wiring structure according to claim 1, wherein the wiring structure is provided.
配線と下層配線からなる配線構造において、該上層配線
とヴィアはデュアルダマシン構造で下層配線に接続され
ていることを特徴とする請求項１に記載の配線構造。3. A wiring structure comprising an upper layer wiring and a lower layer wiring connected to a via opened in an insulating film, wherein the upper layer wiring and the via are connected to the lower layer wiring in a dual damascene structure. The wiring structure according to 1.
配線と下層配線からなる配線構造において、該絶縁膜の
領域は該ヴィア断面積の半分以上の領域をしめることを
特徴とする請求項１から３のいずれか１項に記載の記載
の配線構造。4. A wiring structure comprising an upper layer wiring and a lower layer wiring connected to vias opened in an insulating film, wherein a region of the insulating film occupies a region of half or more of the via cross-sectional area. The wiring structure according to any one of 1 to 3.
配線と下層配線からなる配線構造において、該ヴィア径
の５倍もしくは該ヴィア高さの５倍より広い幅の銅もし
くはアルミニウムを主成分とする該下層配線であること
を特徴とする請求項１〜４のいずれか１項に記載の配線
構造。5. In a wiring structure comprising an upper layer wiring and a lower layer wiring connected to vias opened in an insulating film, copper or aluminum having a width wider than 5 times the via diameter or 5 times the via height is a main component. The wiring structure according to any one of claims 1 to 4, wherein the wiring is the lower layer wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002013655A JP2003218115A (en) | 2002-01-23 | 2002-01-23 | Wiring structure provided with via |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002013655A JP2003218115A (en) | 2002-01-23 | 2002-01-23 | Wiring structure provided with via |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003218115A true JP2003218115A (en) | 2003-07-31 |
Family
ID=27650558
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002013655A Pending JP2003218115A (en) | 2002-01-23 | 2002-01-23 | Wiring structure provided with via |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003218115A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005109336A (en) * | 2003-10-01 | 2005-04-21 | Toshiba Microelectronics Corp | Automated design method and device, reticle set, semiconductor integrated circuit, and design program |
| JP2006186036A (en) * | 2004-12-27 | 2006-07-13 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| WO2009147768A1 (en) * | 2008-06-06 | 2009-12-10 | パナソニック株式会社 | Semiconductor device |
| JP2010157697A (en) * | 2008-12-29 | 2010-07-15 | Internatl Business Mach Corp <Ibm> | Electromigration resistant via-to-line interconnect |
| JP2014056991A (en) * | 2012-09-13 | 2014-03-27 | Fujitsu Semiconductor Ltd | Semiconductor device manufacturing method |
-
2002
- 2002-01-23 JP JP2002013655A patent/JP2003218115A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005109336A (en) * | 2003-10-01 | 2005-04-21 | Toshiba Microelectronics Corp | Automated design method and device, reticle set, semiconductor integrated circuit, and design program |
| JP4509521B2 (en) * | 2003-10-01 | 2010-07-21 | 東芝マイクロエレクトロニクス株式会社 | Automatic design method, automatic design apparatus, reticle set, semiconductor integrated circuit, and design program |
| JP2006186036A (en) * | 2004-12-27 | 2006-07-13 | Matsushita Electric Ind Co Ltd | Semiconductor device |
| WO2009147768A1 (en) * | 2008-06-06 | 2009-12-10 | パナソニック株式会社 | Semiconductor device |
| JP2009295873A (en) * | 2008-06-06 | 2009-12-17 | Panasonic Corp | Semiconductor device |
| US8143725B2 (en) | 2008-06-06 | 2012-03-27 | Panasonic Corporation | Semiconductor device |
| JP2010157697A (en) * | 2008-12-29 | 2010-07-15 | Internatl Business Mach Corp <Ibm> | Electromigration resistant via-to-line interconnect |
| US8922022B2 (en) | 2008-12-29 | 2014-12-30 | International Business Machines Corporation | Electromigration resistant via-to-line interconnect |
| JP2014056991A (en) * | 2012-09-13 | 2014-03-27 | Fujitsu Semiconductor Ltd | Semiconductor device manufacturing method |
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