JP2003124430A - Integrated circuit device and capacitor for integrated circuit - Google Patents

Integrated circuit device and capacitor for integrated circuit

Info

Publication number
JP2003124430A
JP2003124430A JP2001318343A JP2001318343A JP2003124430A JP 2003124430 A JP2003124430 A JP 2003124430A JP 2001318343 A JP2001318343 A JP 2001318343A JP 2001318343 A JP2001318343 A JP 2001318343A JP 2003124430 A JP2003124430 A JP 2003124430A
Authority
JP
Japan
Prior art keywords
integrated circuit
capacitor
electrode pads
wiring board
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001318343A
Other languages
Japanese (ja)
Inventor
Tomokazu Tokoro
知一 所
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2001318343A priority Critical patent/JP2003124430A/en
Publication of JP2003124430A publication Critical patent/JP2003124430A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit device and a capacitor for an integrated circuit, capable of suppressing switching noise more efficiently. SOLUTION: An integrated circuit device comprises an integrated circuit chip which is flip-chip mounted on a wiring board. A capacitor is mounted between the integrated circuit chip and the wiring board. The capacitor comprises a pair of first electrode pads connected to one electrode of the capacitor, and a pair of second electrode pads connected to the other electrode. One of the first electrode pads is connected to a power source terminal of the integrated circuit chip while the other of the first electrode pads is connected to a power source terminal of the wiring board. One of the second electrode pads is connected to an earth terminal of the integrated circuit chip while the other of the second electrode pads is connected to an earth terminal of the wiring board.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、集積回路（ＩＣ：
Integrated Circuit）チップ等が配線基板上にフリップ
チップ実装された集積回路装置に関し、特に、集積回路
装置におけるノイズ除去用コンデンサの実装技術に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit (IC:
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device in which a chip or the like is flip-chip mounted on a wiring board, and particularly to a mounting technology of a noise removing capacitor in the integrated circuit device.

【０００２】[0002]

【従来の技術】従来から、集積回路、特に、大規模集積
回路（以下「ＬＳＩ（Large-Scale Integration）」と
いう）の高速スイッチングに伴い電源自身の応答速度が
ＬＳＩの電流変動に追従できないことや、電源の給電経
路におけるインダクタンス成分により生じるスイッチン
グノイズを抑えるため、集積回路装置における配線基板
上若しくは、配線基板上のＬＳＩ用パッケージ基板上に
コンデンサを実装することが知られている。2. Description of the Related Art Conventionally, due to high-speed switching of integrated circuits, especially large-scale integrated circuits (hereinafter referred to as "LSI (Large-Scale Integration)"), the response speed of the power source itself cannot follow the current fluctuation of the LSI. It is known to mount a capacitor on a wiring board in an integrated circuit device or on an LSI package board on the wiring board in order to suppress switching noise generated by an inductance component in a power supply path of a power supply.

【０００３】図８に、従来のフリップチップ実装型の集
積回路装置を横から見た構造の概念図を示す。図８に示
すように、配線基板８１およびパッケージ基板８２上に
は、コンデンサ８４がそれぞれ実装されており、かかる
コンデンサ８４は、配線基板８１における電源回路と接
地回路との間および、パッケージ基板８２における電源
回路と接地回路との間に、それぞれ接続されている。こ
れにより、コンデンサ８４は、ＬＳＩのスイッチングノ
イズを抑えるためのパスコン（バイパスコンデンサ）と
して機能する。FIG. 8 shows a conceptual view of a structure of a conventional flip-chip mounting type integrated circuit device viewed from the side. As shown in FIG. 8, capacitors 84 are mounted on the wiring board 81 and the package board 82, respectively. The capacitors 84 are provided between the power supply circuit and the ground circuit on the wiring board 81 and on the package board 82. They are respectively connected between the power supply circuit and the ground circuit. As a result, the capacitor 84 functions as a bypass capacitor (bypass capacitor) for suppressing switching noise of the LSI.

【０００４】しかしながら、このような従来の集積回路
装置における構造では、ＬＳＩチップ８３とパッケージ
基板８２間および、パッケージ基板８２と配線基板８１
間には、バンプ８５が存在するために、コンデンサ８４
を、図８に示すような位置に実装していた。その結果、
ＬＳＩチップ８３とコンデンサ８４との実装位置が必然
的に離れることになるため、ＬＳＩチップ８３とコンデ
ンサ８４との間の配線等によるインダクタンス成分が大
きくなり、これによって、スイッチングノイズを低減し
きれないという問題があった。また、配線基板８１およ
びパッケージ基板８２上に、コンデンサ８４を実装する
スペースを確保しなければならないので、集積回路装置
の小型化を図れないという問題があった。However, in the structure of such a conventional integrated circuit device, between the LSI chip 83 and the package substrate 82, and between the package substrate 82 and the wiring substrate 81.
Because of the presence of the bump 85 between them, the capacitor 84
Was mounted at the position shown in FIG. as a result,
Since the mounting positions of the LSI chip 83 and the capacitor 84 are inevitably separated from each other, the inductance component due to the wiring between the LSI chip 83 and the capacitor 84 becomes large, and thus the switching noise cannot be reduced. There was a problem. In addition, since it is necessary to secure a space for mounting the capacitor 84 on the wiring board 81 and the package board 82, there is a problem that the integrated circuit device cannot be downsized.

【０００５】このため、特開２００１−１０２５１２号
公報に開示されたコンデンサ実装構造についての発明で
は、ＬＳＩチップとそのパッケージ基板および、パッケ
ージ基板と配線基板との間のバンプ間に、コンデンサを
実装することとしている。具体的には、かかる公報で開
示された集積回路装置を横から見た構造の概念図を、図
９に示す。図９に示すように、コンデンサ９４は、ＬＳ
Ｉチップ９３とそのパッケージ基板９２および、パッケ
ージ基板９２と配線基板９１との間にそれぞれ実装さ
れ、ＬＳＩチップ９３における電源回路と接地回路との
間および、パッケージ基板９２における電源回路と接地
回路との間に、それぞれ接続されている。これにより、
ＬＳＩチップ９３とコンデンサ９４との間の給電経路
（配線経路）を短くし、配線等によるインダクタンス成
分を低減するとともに、コンデンサ９４を実装するため
に確保する上記スペースの問題を解消している。Therefore, in the invention regarding the capacitor mounting structure disclosed in Japanese Patent Laid-Open No. 2001-102512, a capacitor is mounted between the LSI chip and its package substrate and between the bumps between the package substrate and the wiring substrate. I have decided. Specifically, FIG. 9 shows a conceptual diagram of the structure of the integrated circuit device disclosed in this publication as viewed from the side. As shown in FIG. 9, the capacitor 94 has an LS
The I chip 93 and its package substrate 92, and the package substrate 92 and the wiring substrate 91 are mounted respectively, and are mounted between the power circuit and the ground circuit of the LSI chip 93 and between the power circuit and the ground circuit of the package substrate 92. In between. This allows
The power supply path (wiring path) between the LSI chip 93 and the capacitor 94 is shortened to reduce the inductance component due to wiring or the like, and the problem of the space secured for mounting the capacitor 94 is solved.

【０００６】[0006]

【発明が解決しようとする課題】しかしながら、図９に
示すような従来の集積回路装置では、ＬＳＩチップ９３
下面および、パッケージ基板９２上下面並びに、配線基
板９１上面には、フリップチップ接続するための外部接
続端子が多数設けられており、これらの外部接続端子
は、バンプ９６によって、上記チップ９３−基板９２間
および、基板９２−基板９１間で接続されることになる
ため、これらの基板等の間に実装されるコンデンサ９４
の位置にも制約がある。However, in the conventional integrated circuit device as shown in FIG. 9, the LSI chip 93 is used.
A large number of external connection terminals for flip-chip connection are provided on the lower surface, the upper and lower surfaces of the package board 92, and the upper surface of the wiring board 91. These external connection terminals are provided by the bumps 96 to the chip 93-board 92. And between the board 92 and the board 91, the capacitor 94 mounted between these boards and the like.
There are also restrictions on the position of.

【０００７】即ち、コンデンサ９４は、バンプ９６が存
在する位置には、配置することができないので、必然的
に実装することができるコンデンサの個数（総面積）も
制限される。その結果、コンデンサの容量を十分に大き
くとれず、スイッチングノイズを低減するために十分な
効果を得られないという問題があった。That is, since the capacitors 94 cannot be arranged at the positions where the bumps 96 are present, the number of capacitors (total area) that can be mounted is necessarily limited. As a result, there is a problem in that the capacitance of the capacitor cannot be made sufficiently large and a sufficient effect for reducing switching noise cannot be obtained.

【０００８】また、コンデンサ９４は、例えば、ＬＳＩ
チップ９３の電源端子および接地端子から、リード線を
引き出し、その間に接続することとなるが、かかるリー
ド線によるインダクタンス成分よりスイッチングノイズ
を低減しきれないという問題もあった。The capacitor 94 is, for example, an LSI.
Lead wires are drawn out from the power supply terminal and the ground terminal of the chip 93 and connected between them, but there is also a problem that switching noise cannot be reduced enough due to the inductance component due to the lead wires.

【０００９】そこで、本発明は、上記問題に鑑みてなさ
れたものであり、より効果的にスイッチングノイズを抑
えることが可能な集積回路装置および集積回路用コンデ
ンサを提供することを目的とする。Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide an integrated circuit device and an integrated circuit capacitor capable of more effectively suppressing switching noise.

【００１０】[0010]

【課題を解決するための手段】上記課題を解決するた
め、請求項１に記載の発明は、集積回路チップが配線基
板にフリップチップ実装された集積回路装置において、
前記集積回路チップと前記配線基板との間にコンデンサ
が実装され、前記コンデンサは、当該コンデンサの一方
の電極に接続された一対の第１の電極パッドと、他方の
電極に接続された一対の第２の電極パッドを有し、前記
第１の電極パッドの一方は前記集積回路チップの電源端
子に、前記第１の電極パッドの他方は前記配線基板の電
源端子にそれぞれ接続されているとともに、前記第２の
電極パッドの一方は前記集積回路チップの接地端子に、
前記第２の電極パッドの他方は前記配線基板の接地端子
にそれぞれ接続されているように構成する。ここで、集
積回路（ＩＣ）チップには、ＬＳＩチップ、ＭＳＩ（Me
dium-Scale Integration）チップ、ＶＬＳＩ（Very Lar
ge-Scale Integration）チップなど、表面実装型のすべ
ての集積回路チップが含まれる。また、フリップチップ
実装とは、集積回路チップ下面および、配線基板上面に
設けられた外部接続端子（信号入出力端子、電源端子、
接地端子を含む）を用い、バンプ（例えば、ハンダボー
ル）などにより、かかる外部接続端子どうしを接続する
実装形態をいう。In order to solve the above problems, the invention according to claim 1 provides an integrated circuit device in which an integrated circuit chip is flip-chip mounted on a wiring board,
A capacitor is mounted between the integrated circuit chip and the wiring board, and the capacitor has a pair of first electrode pads connected to one electrode of the capacitor and a pair of first electrode pads connected to the other electrode. Two electrode pads, one of the first electrode pads is connected to a power supply terminal of the integrated circuit chip, and the other of the first electrode pads is connected to a power supply terminal of the wiring board. One of the second electrode pads is connected to the ground terminal of the integrated circuit chip,
The other of the second electrode pads is configured to be connected to the ground terminal of the wiring board, respectively. Here, the integrated circuit (IC) chip includes an LSI chip, an MSI (Me
dium-Scale Integration) chip, VLSI (Very Lar)
ge-Scale Integration) chips, including all surface mount integrated circuit chips. Flip-chip mounting means external connection terminals (signal input / output terminal, power supply terminal,
A mounting form in which the external connection terminals are connected to each other by bumps (for example, solder balls) using a ground terminal).

【００１１】請求項１に記載された発明によれば、コン
デンサは、集積回路チップの近傍に配置され、集積回路
チップの電源回路および接地回路との間に接続されてス
イッチングノイズの発生を防止するとともに、集積回路
チップと配線基板の電源端子間および、集積回路チップ
と配線基板の接地端子間を接続する機能を兼ねることと
なる。従って、コンデンサの実装面積をより広くとるこ
とができ、その容量範囲を大きくとることができ、しか
も、集積回路チップの電源端子および接地端子に直接接
続するので、従来のように、リード線部分のインダクタ
ンス成分をなくすことができる。よって、より効果的に
スイッチングノイズを抑えることが可能となる。According to the invention described in claim 1, the capacitor is arranged in the vicinity of the integrated circuit chip and is connected between the power supply circuit and the ground circuit of the integrated circuit chip to prevent generation of switching noise. At the same time, it also has a function of connecting between the integrated circuit chip and the power supply terminal of the wiring board and between the integrated circuit chip and the ground terminal of the wiring board. Therefore, the mounting area of the capacitor can be made wider, its capacitance range can be made larger, and moreover, since it is directly connected to the power supply terminal and the ground terminal of the integrated circuit chip, as in the conventional case, The inductance component can be eliminated. Therefore, the switching noise can be suppressed more effectively.

【００１２】請求項２に記載の発明は、請求項１に記載
の集積回路装置において、前記一対の第１の電極パッド
のうち一方は前記集積回路チップ側に設けられ他方は前
記配線基板側に設けられるとともに、前記一対の第２の
電極パッドのうち一方は前記集積回路チップ側に設けら
れ他方は前記配線基板側に設けられており、前記集積回
路チップ側の電極パッドおよび前記配線基板側の電極パ
ッドは、前記配線基板面に垂直な方向に配置されるよう
に構成する。ここで、配線基板面に垂直には、もちろ
ん、多少の誤差範囲が考慮される。According to a second aspect of the present invention, in the integrated circuit device according to the first aspect, one of the pair of first electrode pads is provided on the integrated circuit chip side and the other is provided on the wiring board side. One of the pair of second electrode pads is provided on the integrated circuit chip side and the other of the pair of second electrode pads is provided on the wiring board side. The electrode pads on the integrated circuit chip side and the wiring board side are provided. The electrode pads are arranged so as to be arranged in a direction perpendicular to the wiring board surface. Here, of course, some error range is taken into consideration perpendicularly to the wiring board surface.

【００１３】請求項２に記載の発明によれば、コンデン
サの一対の第１の電極パッドにより集積回路チップと配
線基板の電源端子間を、一対の第２の電極パッドにより
集積回路チップと配線基板の接地端子間を、精度良く接
続することができる。According to the second aspect of the present invention, the pair of first electrode pads of the capacitor are provided between the integrated circuit chip and the power supply terminal of the wiring board, and the pair of second electrode pads are provided between the integrated circuit chip and the wiring board. It is possible to accurately connect between the ground terminals.

【００１４】請求項３に記載の発明は、請求項１または
２に記載の集積回路装置において、前記コンデンサは、
複数対の前記第１の電極パッドと、複数対の前記第２の
電極パッドを有し、前記コンデンサの前記配線基板面に
平行な面の形状が、前記集積回路チップの電源端子およ
び接地端子の配列に応じた形状であるように構成する。According to a third aspect of the present invention, in the integrated circuit device according to the first or second aspect, the capacitor is
The capacitor has a plurality of pairs of the first electrode pads and a plurality of pairs of the second electrode pads, and the shape of the surface of the capacitor parallel to the wiring board surface corresponds to the power supply terminal and the ground terminal of the integrated circuit chip. It is configured to have a shape according to the arrangement.

【００１５】請求項３に記載の発明によれば、より合理
的にコンデンサを実装することができるので、より効果
的にスイッチングノイズの発生を防止することが可能と
なる。According to the third aspect of the present invention, since the capacitor can be mounted more rationally, it is possible to more effectively prevent the generation of switching noise.

【００１６】請求項４に記載の発明は、請求項１乃至３
の何れか１項に記載の集積回路装置において、前記コン
デンサの前記配線基板面に平行な面の面積は、信号入出
力端子が配置された前記集積回路チップ面のうち、当該
信号入出力端子部分を含む所定領域を除く領域の面積と
等しいように構成する。ここで、信号入出力端子部分を
含む所定領域は、信号入出力端子部分のみの領域であっ
てもよいし、信号入出力端子部分および当該部分の周囲
の所定領域であってもよい。なお、信号入出力端子部分
の周囲の所定領域は、当該請求項４に記載の発明の効果
を十分確保できる範囲内で設定される。The invention according to claim 4 is the invention according to claims 1 to 3.
2. The integrated circuit device according to any one of 1 to 3, wherein the area of the surface of the capacitor parallel to the wiring board surface is the signal input / output terminal portion of the integrated circuit chip surface on which the signal input / output terminal is arranged. It is configured to be equal to the area of a region excluding a predetermined region including. Here, the predetermined area including the signal input / output terminal portion may be an area of only the signal input / output terminal portion, or may be a predetermined area around the signal input / output terminal portion and the portion. The predetermined area around the signal input / output terminal portion is set within a range in which the effect of the invention described in claim 4 can be sufficiently ensured.

【００１７】請求項４に記載の発明によれば、コンデン
サを実装する面積を大幅に広くとることができるので、
極めて効果的にスイッチングノイズを抑えることが可能
となる。According to the invention described in claim 4, since the area for mounting the capacitor can be significantly widened,
It becomes possible to suppress the switching noise extremely effectively.

【００１８】請求項５に記載の発明は、集積回路チップ
がパッケージ基板にフリップチップ実装され、かつ、前
記パッケージ基板が配線基板にフリップチップ実装され
た集積回路装置において、前記集積回路チップと前記パ
ッケージ基板との間にコンデンサが実装され、前記コン
デンサは、当該コンデンサの一方の電極に接続された一
対の第１の電極パッドと、他方の電極に接続された一対
の第２の電極パッドを有し、前記第１の電極パッドの一
方は前記集積回路チップの電源端子に、前記第１の電極
パッドの他方は前記パッケージ基板の電源端子にそれぞ
れ接続されているとともに、前記第２の電極パッドの一
方は前記集積回路チップの接地端子に、前記第２の電極
パッドの他方は前記パッケージ基板の接地端子にそれぞ
れ接続されているように構成する。ここで、パッケージ
基板とは、集積回路チップを保護し、配線基板との接続
の仲介をする役目を担うものである。According to a fifth aspect of the present invention, in an integrated circuit device in which an integrated circuit chip is flip-chip mounted on a package substrate, and the package substrate is flip-chip mounted on a wiring substrate, the integrated circuit chip and the package are provided. A capacitor is mounted between the substrate and the capacitor, and the capacitor has a pair of first electrode pads connected to one electrode of the capacitor and a pair of second electrode pads connected to the other electrode. , One of the first electrode pads is connected to a power supply terminal of the integrated circuit chip, and the other of the first electrode pads is connected to a power supply terminal of the package substrate, and one of the second electrode pads is connected. Is connected to the ground terminal of the integrated circuit chip, and the other of the second electrode pads is connected to the ground terminal of the package substrate. Sea urchin to configure. Here, the package substrate plays a role of protecting the integrated circuit chip and mediating the connection with the wiring substrate.

【００１９】請求項５に記載の発明によれば、コンデン
サは、集積回路チップの近傍に配置され、集積回路チッ
プの電源回路および接地回路との間に接続されてスイッ
チングノイズの発生を防止するとともに、集積回路チッ
プとパッケージ基板の電源端子間および、集積回路チッ
プとパッケージ基板の接地端子間を接続する機能を兼ね
ることとなる。According to the invention described in claim 5, the capacitor is arranged in the vicinity of the integrated circuit chip and is connected between the integrated circuit chip and the power supply circuit and the ground circuit to prevent generation of switching noise. , And also has a function of connecting between the integrated circuit chip and the power supply terminal of the package substrate and between the integrated circuit chip and the ground terminal of the package substrate.

【００２０】従って、集積回路チップを搭載したパッケ
ージ基板を、配線基板にフリップチップ実装する場合に
おいても、請求項１に記載の発明の効果と同等の効果を
得ることができる。Therefore, even when the package substrate on which the integrated circuit chip is mounted is flip-chip mounted on the wiring substrate, the same effect as that of the invention described in claim 1 can be obtained.

【００２１】請求項６に記載の発明は、請求項５に記載
の集積回路装置において、前記一対の第１の電極パッド
のうち一方は前記集積回路チップ側に設けられ他方は前
記パッケージ基板側に設けられるとともに、前記一対の
第２の電極パッドのうち一方は前記集積回路チップ側に
設けられ他方は前記パッケージ基板側に設けられてお
り、前記集積回路チップ側の電極パッドおよび前記パッ
ケージ基板側の電極パッドは、前記配線基板面に垂直な
方向に配置されるように構成する。According to a sixth aspect of the present invention, in the integrated circuit device according to the fifth aspect, one of the pair of first electrode pads is provided on the integrated circuit chip side and the other is provided on the package substrate side. One of the pair of second electrode pads is provided on the integrated circuit chip side and the other of the pair of second electrode pads is provided on the package substrate side. The integrated circuit chip side electrode pad and the package substrate side are provided. The electrode pads are arranged so as to be arranged in a direction perpendicular to the wiring board surface.

【００２２】請求項６に記載の発明によれば、集積回路
チップを搭載したパッケージ基板を、配線基板にフリッ
プチップ実装する場合においても、請求項２に記載の発
明の効果と同等の効果を得ることができる。According to the invention described in claim 6, even when the package substrate on which the integrated circuit chip is mounted is flip-chip mounted on the wiring board, the same effect as the effect of the invention described in claim 2 is obtained. be able to.

【００２３】請求項７に記載の発明は、請求項５または
６に記載の集積回路装置において、前記コンデンサは、
複数対の前記第１の電極パッドと、複数対の前記第２の
電極パッドを有し、前記コンデンサの前記配線基板面に
平行な面の形状が、前記集積回路チップの電源端子およ
び接地端子の配列に応じた形状であるように構成する。According to a seventh aspect of the present invention, in the integrated circuit device according to the fifth or sixth aspect, the capacitor is
The capacitor has a plurality of pairs of the first electrode pads and a plurality of pairs of the second electrode pads, and the shape of the surface of the capacitor parallel to the wiring board surface corresponds to the power supply terminal and the ground terminal of the integrated circuit chip. It is configured to have a shape according to the arrangement.

【００２４】請求項７に記載の発明によれば、集積回路
チップを搭載したパッケージ基板を、配線基板にフリッ
プチップ実装する場合においても、請求項３に記載の発
明の効果と同等の効果を得ることができる。According to the invention described in claim 7, even when the package substrate on which the integrated circuit chip is mounted is flip-chip mounted on the wiring substrate, the same effect as the effect of the invention described in claim 3 is obtained. be able to.

【００２５】請求項８に記載の発明は、請求項５乃至７
の何れか１項に記載の集積回路装置において、前記コン
デンサの前記配線基板面に平行な面の面積は、信号入出
力端子が配置された前記集積回路チップ面のうち、当該
信号入出力端子部分を含む所定領域を除く領域の面積と
等しいように構成する。The invention described in claim 8 is the invention according to claims 5 to 7.
2. The integrated circuit device according to any one of 1 to 3, wherein the area of the surface of the capacitor parallel to the wiring board surface is the signal input / output terminal portion of the integrated circuit chip surface on which the signal input / output terminal is arranged. It is configured to be equal to the area of a region excluding a predetermined region including.

【００２６】請求項８に記載の発明によれば、集積回路
チップを搭載したパッケージ基板を、配線基板にフリッ
プチップ実装する場合においても、請求項４に記載の発
明の効果と同等の効果を得ることができる。According to the invention described in claim 8, even when the package substrate on which the integrated circuit chip is mounted is flip-chip mounted on the wiring board, the same effect as the effect of the invention described in claim 4 is obtained. be able to.

【００２７】請求項９に記載の発明は、集積回路チップ
が搭載されたパッケージ基板が配線基板にフリップチッ
プ実装された集積回路装置において、前記パッケージ基
板と前記配線基板との間にコンデンサが実装され、前記
コンデンサは、当該コンデンサの一方の電極に接続され
た一対の第１の電極パッドと、他方の電極に接続された
一対の第２の電極パッドを有し、前記第１の電極パッド
の一方は前記パッケージ基板の電源端子に、前記第１の
電極パッドの他方は前記配線基板の電源端子にそれぞれ
接続されているとともに、前記第２の電極パッドの一方
は前記パッケージ基板の接地端子に、前記第２の電極パ
ッドの他方は前記配線基板の接地端子にそれぞれ接続さ
れているように構成する。ここで、集積回路チップが搭
載された前記パッケージ基板には、ＣＳＰ（Chip Size
Package：ＩＣチップとほぼ同等か僅かに大きいパッケ
ージ）も含まれる。According to a ninth aspect of the present invention, in an integrated circuit device in which a package board on which an integrated circuit chip is mounted is flip-chip mounted on a wiring board, a capacitor is mounted between the package board and the wiring board. , The capacitor has a pair of first electrode pads connected to one electrode of the capacitor, and a pair of second electrode pads connected to the other electrode, one of the first electrode pad Is connected to a power supply terminal of the package board, the other of the first electrode pads is connected to a power supply terminal of the wiring board, and one of the second electrode pads is connected to a ground terminal of the package board. The other of the second electrode pads is configured to be connected to the ground terminal of the wiring board, respectively. Here, the package substrate on which the integrated circuit chip is mounted has a CSP (Chip Size).
Package: A package that is almost the same as or slightly larger than the IC chip) is also included.

【００２８】請求項９に記載の発明によれば、コンデン
サは、集積回路チップの近傍に配置され、パッケージ基
板の電源回路および接地回路との間に接続されてスイッ
チングノイズの発生を防止するとともに、パッケージ基
板と配線基板の電源端子間および、パッケージ基板と配
線基板の接地端子間を接続する機能を兼ねることとな
る。従って、集積回路チップを搭載したパッケージ基板
を、配線基板にフリップチップ実装する場合において
も、請求項１に記載の発明の効果と同等の効果を得るこ
とができる。According to the ninth aspect of the present invention, the capacitor is arranged in the vicinity of the integrated circuit chip and is connected between the power supply circuit and the ground circuit of the package substrate to prevent generation of switching noise. It also has a function of connecting between the power supply terminals of the package board and the wiring board and between the ground terminals of the package board and the wiring board. Therefore, even when the package substrate on which the integrated circuit chip is mounted is flip-chip mounted on the wiring substrate, the same effect as the effect of the invention described in claim 1 can be obtained.

【００２９】請求項１０に記載の発明は、請求項９に記
載の集積回路装置において、前記一対の第１の電極パッ
ドのうち一方は前記パッケージ基板側に設けられ他方は
前記配線基板側に設けられるとともに、前記一対の第２
の電極パッドのうち一方は前記パッケージ基板側に設け
られ他方は前記配線基板側に設けられており、前記パッ
ケージ基板側の電極パッドおよび前記配線基板側の電極
パッドは、前記配線基板面に垂直な方向に配置されるよ
うに構成する。According to a tenth aspect of the invention, in the integrated circuit device according to the ninth aspect, one of the pair of first electrode pads is provided on the package substrate side and the other is provided on the wiring substrate side. And a pair of the second
One of the electrode pads is provided on the package board side and the other is provided on the wiring board side. The electrode pad on the package board side and the electrode pad on the wiring board side are perpendicular to the wiring board surface. It is configured to be arranged in the direction.

【００３０】請求項１０に記載の発明によれば、集積回
路チップを搭載したパッケージ基板を、配線基板にフリ
ップチップ実装する場合においても、請求項２に記載の
発明の効果と同等の効果を得ることができる。According to the invention described in claim 10, even when the package substrate on which the integrated circuit chip is mounted is flip-chip mounted on the wiring substrate, the same effect as the effect of the invention described in claim 2 is obtained. be able to.

【００３１】請求項１１に記載の発明は、請求項９また
は１０に記載の集積回路装置において、前記コンデンサ
は、複数対の前記第１の電極パッドと、複数対の前記第
２の電極パッドを有し、前記コンデンサの前記配線基板
面に平行な面の形状が、前記パッケージ基板の電源端子
および接地端子の配列に応じた形状であるように構成す
る。According to an eleventh aspect of the present invention, in the integrated circuit device according to the ninth or tenth aspect, the capacitor includes a plurality of pairs of the first electrode pads and a plurality of pairs of the second electrode pads. The capacitor is configured such that the shape of the surface of the capacitor parallel to the wiring board surface is a shape corresponding to the arrangement of the power supply terminal and the ground terminal of the package board.

【００３２】請求項１１に記載の発明によれば、集積回
路チップを搭載したパッケージ基板を、配線基板にフリ
ップチップ実装する場合においても、請求項３に記載の
発明の効果と同等の効果を得ることができる。According to the eleventh aspect of the present invention, even when the package substrate on which the integrated circuit chip is mounted is flip-chip mounted on the wiring substrate, the same effect as that of the third aspect of the invention is obtained. be able to.

【００３３】請求項１２に記載の発明は、請求項９乃至
１１の何れか１項に記載の集積回路装置において、前記
コンデンサの前記配線基板面に平行な面の面積は、信号
入出力端子が配置された前記パッケージ基板面のうち、
当該信号入出力端子部分を含む所定領域を除く領域の面
積と等しいように構成する。According to a twelfth aspect of the present invention, in the integrated circuit device according to any one of the ninth to eleventh aspects, an area of a plane parallel to the wiring board surface of the capacitor is such that a signal input / output terminal is Of the arranged package substrate surface,
It is configured to have the same area as the area excluding a predetermined area including the signal input / output terminal portion.

【００３４】請求項１２に記載の発明によれば、集積回
路チップを搭載したパッケージ基板を、配線基板にフリ
ップチップ実装する場合においても、請求項４に記載の
発明の効果と同等の効果を得ることができる。According to the twelfth aspect of the invention, even when the package substrate on which the integrated circuit chip is mounted is flip-chip mounted on the wiring substrate, the same effect as that of the fourth aspect of the invention is obtained. be able to.

【００３５】請求項１３に記載の発明は、集積回路チッ
プとパッケージ基板との間または、集積回路チップと配
線基板との間の少なくとも何れか一方に実装される集積
回路用コンデンサであって、前記コンデンサは、当該コ
ンデンサの一方の電極に接続された一対の第１の電極パ
ッドと、他方の電極に接続された一対の第２の電極パッ
ドとを、それぞれ複数有し、前記コンデンサの前記配線
基板面に平行な面の形状が、前記集積回路チップの電源
端子および接地端子の配列に応じた形状であるように構
成する。According to a thirteenth aspect of the present invention, there is provided an integrated circuit capacitor mounted between at least one of the integrated circuit chip and the package substrate or between the integrated circuit chip and the wiring substrate. The capacitor has a plurality of pairs of first electrode pads connected to one electrode of the capacitor and a plurality of pairs of second electrode pads connected to the other electrode, respectively, and the wiring board of the capacitor The shape of the surface parallel to the surface is configured according to the arrangement of the power supply terminal and the ground terminal of the integrated circuit chip.

【００３６】請求項１４に記載の発明は、請求項１３に
記載の集積回路用コンデンサにおいて、前記コンデンサ
の前記配線基板面に平行な面の面積は、信号入出力端子
が配置された前記集積回路チップ面のうち、当該信号入
出力端子部分を含む所定領域を除く領域の面積と等しい
ように構成する。According to a fourteenth aspect of the present invention, in the integrated circuit capacitor according to the thirteenth aspect, the area of the surface of the capacitor parallel to the wiring board surface is the integrated circuit in which signal input / output terminals are arranged. The area of the chip surface is equal to the area of a region excluding a predetermined region including the signal input / output terminal portion.

【００３７】請求項１３または請求項１４に記載の発明
に記載の発明によれば、当該コンデンサを請求項１また
は請求項５に記載の集積回路装置に実装することによ
り、請求項１に記載の発明と同様の効果を得ることがで
きる。According to the invention described in claim 13 or claim 14, the capacitor is mounted on the integrated circuit device according to claim 1 or claim 5, whereby the capacitor according to claim 1 is mounted. The same effect as the invention can be obtained.

【００３８】請求項１５に記載の発明は、パッケージ基
板と配線基板との間に実装される集積回路用コンデンサ
であって、前記コンデンサは、当該コンデンサの一方の
電極に接続された一対の第１の電極パッドと、他方の電
極に接続された一対の第２の電極パッドとを、それぞれ
複数有し、前記コンデンサの前記配線基板面に平行な面
の形状が、前記パッケージ基板の電源端子および接地端
子の配列に応じた形状であるように構成する。According to a fifteenth aspect of the present invention, there is provided an integrated circuit capacitor mounted between a package substrate and a wiring substrate, wherein the capacitor is a pair of first electrodes connected to one electrode of the capacitor. A plurality of electrode pads and a pair of second electrode pads connected to the other electrode, respectively, and the shape of the surface of the capacitor parallel to the wiring board surface is the power supply terminal and ground of the package board. It is configured to have a shape according to the arrangement of the terminals.

【００３９】請求項１６に記載の発明は、請求項１５に
記載の集積回路用コンデンサにおいて、前記コンデンサ
の前記配線基板面に平行な面の面積は、信号入出力端子
が配置された前記パッケージ基板面のうち、当該信号入
出力端子部分を含む所定領域を除く領域の面積と等しい
ように構成する。According to a sixteenth aspect of the present invention, in the integrated circuit capacitor according to the fifteenth aspect, the area of the surface of the capacitor parallel to the wiring board surface is the package substrate on which signal input / output terminals are arranged. The area of the surface is equal to the area of the area excluding the predetermined area including the signal input / output terminal portion.

【００４０】請求項１５または請求項１６に記載の発明
に記載の発明によれば、当該コンデンサを請求項９に記
載の集積回路装置に実装することにより、請求項９に記
載の発明と同様の効果を得ることができる。According to the invention described in claim 15 or 16, the same capacitor as the invention described in claim 9 is obtained by mounting the capacitor in the integrated circuit device according to claim 9. The effect can be obtained.

【００４１】[0041]

【発明の実施の形態】以下、本発明の好適な実施の形態
を添付図面に基づいて説明する。 （第１実施形態）先ず、本発明にかかる第１実施形態に
おける集積回路装置の構造について、図１乃至図６を参
照して説明する。Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. (First Embodiment) First, the structure of an integrated circuit device according to a first embodiment of the present invention will be described with reference to FIGS.

【００４２】図１に、第１実施形態における集積回路装
置を横から見た構造の概念図の一例を示す。図１に示す
ように、集積回路装置１００は、集積回路チップとして
のＬＳＩチップ１と、配線基板２と、コンデンサ３と、
を含んで構成される。ＬＳＩチップ１の下面には、複数
の外部接続端子が、例えば、１ｍｍピッチで設けられて
いる。この外部接続端子は、信号入出力端子（例えば、
ＬＳＩ中のＭＯＳ−ＦＥＴのゲート）、電源端子、接地
端子に区分される。また、配線基板２の上面には、ＬＳ
Ｉチップ１に設けられた、それぞれの外部接続端子に対
応する外部接続端子が設けられている。FIG. 1 shows an example of a conceptual view of the structure of the integrated circuit device according to the first embodiment as viewed from the side. As shown in FIG. 1, an integrated circuit device 100 includes an LSI chip 1 as an integrated circuit chip, a wiring board 2, a capacitor 3, and
It is configured to include. On the lower surface of the LSI chip 1, a plurality of external connection terminals are provided, for example, at a pitch of 1 mm. This external connection terminal is a signal input / output terminal (for example,
It is divided into a MOS-FET gate in an LSI), a power supply terminal, and a ground terminal. Further, on the upper surface of the wiring board 2, the LS
External connection terminals corresponding to the respective external connection terminals provided on the I-chip 1 are provided.

【００４３】ＬＳＩチップ１の信号入出力端子と配線基
板２の信号入出力端子とは、バンプ（ハンダボール）４
によってフリップチップ接続される。そして、ＬＳＩチ
ップ１と配線基板２との間には、コンデンサ３がバンプ
５を介して実装される。なお、バンプ４および５は、例
えば、銅ボールの表面を、ハンダ（Ｐｂ−Ｓｎ）によっ
て被覆して形成される。The signal input / output terminal of the LSI chip 1 and the signal input / output terminal of the wiring board 2 are connected to bumps (solder balls) 4
Flip chip connection. Then, the capacitor 3 is mounted between the LSI chip 1 and the wiring board 2 via the bump 5. The bumps 4 and 5 are formed, for example, by coating the surface of a copper ball with solder (Pb-Sn).

【００４４】図２に、図１におけるコンデンサ３を横か
ら見た構造の概念図（拡大図）を示す。なお、本実施形
態においては、コンデンサ３には、積層形セラミックチ
ップコンデンサを適用するが、これに限定されるもので
はない。図２に示すように、コンデンサ３は、絶縁膜層
３１と、下部電極層３２と、誘電体（誘電体セラミッ
ク）層３３と、上部電極層３４と、が積層されて形成さ
れており、さらに、当該コンデンサ３は、下部電極層３
２に接続された一対の第１の電極パッド３５および３６
と、上部電極層３４に接続された一対の第２の電極パッ
ド３７および３８を有している。FIG. 2 shows a conceptual view (enlarged view) of the structure of the capacitor 3 in FIG. 1 as seen from the side. In this embodiment, a multilayer ceramic chip capacitor is used as the capacitor 3, but the capacitor 3 is not limited to this. As shown in FIG. 2, the capacitor 3 is formed by laminating an insulating film layer 31, a lower electrode layer 32, a dielectric (dielectric ceramic) layer 33, and an upper electrode layer 34. , The capacitor 3 is a lower electrode layer 3
A pair of first electrode pads 35 and 36 connected to 2
And a pair of second electrode pads 37 and 38 connected to the upper electrode layer 34.

【００４５】第１の電極パッド３５と３６は、ともに配
線基板２面に垂直な方向に配置され、当該第１の電極パ
ッド３５と３６との間に導電材が充填されて形成された
ビアホール３９によって下部電極層３２に接続されてい
る。一方、第２の電極パッド３７と３８は、ともに配線
基板２面に垂直な方向に配置され、当該第２の電極パッ
ド３７と３８との間に導電材が充填されて形成されたビ
アホール４０によって上部電極層３４に接続されてい
る。Both the first electrode pads 35 and 36 are arranged in a direction perpendicular to the surface of the wiring board 2, and a via hole 39 formed by filling a conductive material between the first electrode pads 35 and 36. Is connected to the lower electrode layer 32. On the other hand, the second electrode pads 37 and 38 are both arranged in a direction perpendicular to the surface of the wiring board 2, and the via holes 40 formed by filling the space between the second electrode pads 37 and 38 with a conductive material. It is connected to the upper electrode layer 34.

【００４６】そして、図１に示すように、コンデンサ３
の一方の第１の電極パッド３５とＬＳＩチップ１の電源
端子とがバンプ５によってフリップチップ接続されると
ともに、コンデンサ３の他方の第１の電極パッド３６と
配線基板２の電源端子とがバンプ５によってフリップチ
ップ接続される。また、コンデンサ３の一方の第２の電
極パッド３７とＬＳＩチップ１の接地端子とがバンプ５
によってフリップチップ接続されるとともに、コンデン
サ３の他方の第２の電極パッド３８と配線基板２の接地
端子とがバンプ５によってフリップチップ接続される。Then, as shown in FIG.
One of the first electrode pads 35 and the power supply terminal of the LSI chip 1 are flip-chip connected by the bumps 5, and the other of the first electrode pads 36 of the capacitor 3 and the power supply terminal of the wiring board 2 are connected to the bumps 5. Flip chip connection. Further, one of the second electrode pads 37 of the capacitor 3 and the ground terminal of the LSI chip 1 are connected to the bump 5
The second electrode pad 38 of the capacitor 3 and the ground terminal of the wiring board 2 are flip-chip connected by the bumps 5 while being flip-chip connected by the bumps 5.

【００４７】即ち、かかるコンデンサ３は、ＬＳＩチッ
プ１における電源回路と接地回路との間および、配線基
板２における電源回路と接地回路との間の双方に直接接
続されるとともに、さらに、バンプ４の代わりに、ＬＳ
Ｉチップ１の外部接続端子（電源端子または、接地端
子）と、配線基板２の外部接続端子（電源端子または、
接地端子）とをフリップチップ接続する機能を有する。
これにより、従来のように、電源端子および接地端子か
らリード線を引き出すことなく、直接に、バンプ４の機
能も兼ねて、どの電源端子および接地端子に対しても、
コンデンサを接続することができる。また、コンデンサ
３をＬＳＩチップ１と配線基板２に実装する上で従来の
ような制約もなく、コンデンサ３の実装面積をより広く
とることができる。That is, the capacitor 3 is directly connected to both the power supply circuit and the ground circuit of the LSI chip 1 and the power supply circuit and the ground circuit of the wiring board 2, and further, to the bump 4 of the bump 4. Instead of LS
The external connection terminal (power supply terminal or ground terminal) of the I-chip 1 and the external connection terminal (power supply terminal or
It has a function of flip-chip connection with the ground terminal).
As a result, unlike the conventional case, the lead wire is not pulled out from the power supply terminal and the ground terminal, and the function of the bump 4 is directly provided to any power supply terminal and the ground terminal.
Capacitors can be connected. Further, there is no limitation in mounting the capacitor 3 on the LSI chip 1 and the wiring board 2 as in the conventional case, and the mounting area of the capacitor 3 can be made wider.

【００４８】図３（Ａ）に、従来の集積回路装置の等価
回路を、図３（Ｂ）に、第１実施形態における集積回路
装置１００の等価回路を、それぞれ示す。図示のよう
に、従来の集積回路装置と、第１実施形態における集積
回路装置１００との何れにおいても、コンデンサ（図３
（Ａ）では、コンデンサ９４。図３（Ｂ）では、コンデ
ンサ３）は、ＬＳＩチップ１内のＬＳＩ（図３（Ａ）で
は、ＬＳＩ９３ａ。図３（Ｂ）では、ＬＳＩ１ａ）と並
列に接続されているが、第１実施形態における集積回路
装置１００では、ＬＳＩチップの電源端子１５および接
地端子１６に直接コンデンサ３が接続されるので、従来
の集積回路装置におけるリード線部分のインダクタンス
成分をなくすことができる。さらに、第１実施形態にお
ける集積回路装置１００では、上述の通り、コンデンサ
３を実装する面積を、従来より広くとることができるの
で、その容量範囲を大きくとることができる。従って、
より効果的にスイッチングノイズを抑えることが可能と
なる。また、従来のように、コンデンサを実装するため
のスペースを確保するために、電源端子および接地端子
の数を減らす必要がなくなる。FIG. 3A shows an equivalent circuit of the conventional integrated circuit device, and FIG. 3B shows an equivalent circuit of the integrated circuit device 100 in the first embodiment. As shown in the figure, in both the conventional integrated circuit device and the integrated circuit device 100 in the first embodiment, a capacitor (see FIG.
In (A), the capacitor 94. In FIG. 3B, the capacitor 3 is connected in parallel with the LSI in the LSI chip 1 (LSI 93a in FIG. 3A. LSI 1a in FIG. 3B). In the integrated circuit device 100, the capacitor 3 is directly connected to the power supply terminal 15 and the ground terminal 16 of the LSI chip, so that the inductance component of the lead wire portion in the conventional integrated circuit device can be eliminated. Furthermore, in the integrated circuit device 100 according to the first embodiment, as described above, the area for mounting the capacitor 3 can be made wider than in the conventional case, so that the capacitance range can be made large. Therefore,
It becomes possible to suppress the switching noise more effectively. Further, unlike the conventional case, it is not necessary to reduce the number of power supply terminals and ground terminals in order to secure a space for mounting a capacitor.

【００４９】ところで、図２の例には、説明の便宜上、
第１の電極パッド３５および３６と、第２の電極パッド
３７および３８とが、それぞれ１組づつ設けられた、い
わば最小単位のコンデンサ３を示したが、実際には、第
１の電極パッドおよび第２の電極パッドを、それぞれ複
数対設ける構成とした方が好ましい。さらに、コンデン
サの配線基板面に平行な面の形状を、ＬＳＩチップ１の
電源端子および接地端子の配列に応じて形成するように
構成すれば、より大きな有効電極面積が得られ、容量範
囲を大きくとることができる。By the way, in the example of FIG. 2, for convenience of explanation,
The capacitor 3 which is a so-called minimum unit in which the first electrode pads 35 and 36 and the second electrode pads 37 and 38 are respectively provided in one set is shown, but in reality, the first electrode pads and It is preferable that a plurality of pairs of second electrode pads be provided. Further, if the shape of the surface of the capacitor parallel to the wiring board surface is formed according to the arrangement of the power supply terminals and the ground terminals of the LSI chip 1, a larger effective electrode area can be obtained and the capacitance range can be increased. Can be taken.

【００５０】例えば、図４は、ＬＳＩチップ１の外部接
続端子の配列に応じた形状に形成したコンデンサを実装
した場合の集積回路装置を横から見た構造の概念図の一
例である。図１に示す集積回路装置１００では、１つの
ＬＳＩチップ１にコンデンサ３を複数実装しているのに
対し、図４に示す集積回路装置２００では、１つのＬＳ
Ｉチップ１にコンデンサ７を１つ実装している点で異な
る。図５（Ａ）は、図４に示す集積回路装置２００にお
けるＬＳＩチップ１の下面の外部接続端子の配列を示す
（ＬＳＩチップ１の上面から見た）ものであり、図５
（Ｂ）は、図５（Ａ）におけるＬＳＩチップ１の外部接
続端子の配列に応じた形状に形成したコンデンサ７の上
面図を示すものである。また、図６は、コンデンサ７を
横から見た構造の概念図を示すものである。For example, FIG. 4 is an example of a conceptual view of a structure of a side view of an integrated circuit device in which a capacitor having a shape corresponding to the arrangement of external connection terminals of the LSI chip 1 is mounted. In the integrated circuit device 100 shown in FIG. 1, a plurality of capacitors 3 are mounted on one LSI chip 1, whereas in the integrated circuit device 200 shown in FIG.
The difference is that one capacitor 7 is mounted on the I-chip 1. 5A shows the arrangement of external connection terminals on the lower surface of the LSI chip 1 in the integrated circuit device 200 shown in FIG. 4 (as seen from the upper surface of the LSI chip 1).
5B is a top view of the capacitor 7 formed in a shape corresponding to the arrangement of the external connection terminals of the LSI chip 1 in FIG. 5A. Further, FIG. 6 shows a conceptual view of the structure of the capacitor 7 as seen from the side.

【００５１】図５（Ａ）および（Ｂ）に示すように、コ
ンデンサ７の第１の電極パッド７１は、ＬＳＩチップ１
の電源端子１５の位置に配置され、第２の電極パッド７
３は、ＬＳＩチップ１の接地端子１６の位置に配置され
ている。また、ＬＳＩチップ１の信号入出力端子１７の
位置は、信号入出力端子間をフリップチップ接続するた
めのバンプ４を配置できるように、当該信号入出力端子
部分および当該部分の周囲の所定領域が切り取られてい
る。なお、図５（Ｂ）の例では、ＬＳＩチップ１の信号
入出力端子１７の位置は、バンプ４を配置できるように
四角形状に切り取られているが、これとは別に、バンプ
４が配置できる範囲で円形状に切り取り、コンデンサ７
の配線基板面に平行な面の面積を増すように構成しても
よい。As shown in FIGS. 5A and 5B, the first electrode pad 71 of the capacitor 7 is the LSI chip 1
Of the second electrode pad 7 disposed at the position of the power supply terminal 15 of
3 is arranged at the position of the ground terminal 16 of the LSI chip 1. Further, the position of the signal input / output terminal 17 of the LSI chip 1 is such that the signal input / output terminal portion and a predetermined area around the portion are arranged so that the bump 4 for flip-chip connecting the signal input / output terminals can be arranged. It has been cut off. In the example of FIG. 5B, the position of the signal input / output terminal 17 of the LSI chip 1 is cut out in a square shape so that the bump 4 can be arranged, but the bump 4 can be arranged separately. Cut into a circular shape in the range, and capacitor 7
The area of the surface parallel to the surface of the wiring board may be increased.

【００５２】また、図６に示すように、コンデンサ７の
全ての第１の電極パッド７１および７２は下部電極層７
５に、第２の電極パッド７３および７４は上部電極層７
６に、それぞれ接続されている。Further, as shown in FIG. 6, all the first electrode pads 71 and 72 of the capacitor 7 are formed in the lower electrode layer 7.
5, the second electrode pads 73 and 74 are formed on the upper electrode layer 7
6 are connected respectively.

【００５３】このように、図５（Ｂ）に示すコンデンサ
７の配線基板面に平行な面の面積は、ＬＳＩチップ１の
信号入出力端子が配置されたＬＳＩチップ面のうち、当
該信号入出力端子部分および当該部分の周囲の所定領域
を除く領域の面積と等しくすることができ、容量範囲
を、従来に比べ非常に大きくとることができる。この信
号入出力端子部分の周囲の所定領域は、本発明の効果を
十分確保できる範囲内で設定する。As described above, the area of the surface parallel to the wiring board surface of the capacitor 7 shown in FIG. 5B is the signal input / output of the LSI chip surface on which the signal input / output terminals of the LSI chip 1 are arranged. It is possible to make the area equal to the area of the terminal portion and the area around the portion excluding a predetermined area, and the capacitance range can be made much larger than in the conventional case. The predetermined area around the signal input / output terminal portion is set within a range in which the effects of the present invention can be sufficiently ensured.

【００５４】なお、図４には、１つのＬＳＩチップ１に
対し、当該ＬＳＩチップ１の電源端子および接地端子の
配列に応じて形成された１つのコンデンサ７を実装する
例を示したが、このコンデンサ７を、任意の平面の形状
の複数のコンデンサに分割して、全体としてコンデンサ
７と同じ平面の形状を有するように構成しても、コンデ
ンサ７と同様の効果を有する。Although FIG. 4 shows an example in which one capacitor 7 formed according to the arrangement of the power supply terminals and the ground terminals of the LSI chip 1 is mounted on one LSI chip 1, Even if the capacitor 7 is divided into a plurality of capacitors each having an arbitrary planar shape and configured to have the same planar shape as the capacitor 7 as a whole, the same effect as the capacitor 7 can be obtained.

【００５５】次に、図４に示すような集積回路装置２０
０の製造方法について、図４乃至図６を参照して説明す
る。Next, an integrated circuit device 20 as shown in FIG.
The manufacturing method of 0 will be described with reference to FIGS.

【００５６】先ず、図６に示すようなコンデンサ７を製
造するには、例えば、ＬＳＩチップ１の平面と同寸法の
セラミックグリーンシートを用意し、予め、ＬＳＩチッ
プ１の電源端子および接地端子の配列に応じた形状にパ
ターン化されたレジストをエッチングマスクとして、セ
ラミックグリーンシートをエッチングする。First, in order to manufacture the capacitor 7 as shown in FIG. 6, for example, a ceramic green sheet having the same size as the plane of the LSI chip 1 is prepared, and the power supply terminals and the ground terminals of the LSI chip 1 are arranged in advance. The ceramic green sheet is etched using the resist patterned into a shape corresponding to the above as an etching mask.

【００５７】次に、そのセラミックグリーンシートの上
面において、ＬＳＩチップ１の電源端子が配置される部
分に対応する領域に、例えば、円形状のマスクをする。
一方、そのセラミックグリーンシートの下面において、
ＬＳＩチップ１の接地端子が配置される部分に対応する
領域に、例えば、円形状のマスクをする。ここで、かか
るマスクの直径は、後述するビアホール７８の直径より
も大きくとる。そして、そのセラミックグリーンシート
の両面に、例えば、蒸着法またはスパッタ法により、金
属膜を付着させた後、上記マスクを除去し、下部電極層
７５および上部電極層７６を形成する。Next, on the upper surface of the ceramic green sheet, for example, a circular mask is formed in a region corresponding to the portion where the power supply terminals of the LSI chip 1 are arranged.
On the other hand, on the lower surface of the ceramic green sheet,
For example, a circular mask is formed in a region corresponding to a portion where the ground terminal of the LSI chip 1 is arranged. Here, the diameter of the mask is set larger than the diameter of a via hole 78 described later. Then, after depositing a metal film on both surfaces of the ceramic green sheet by, for example, a vapor deposition method or a sputtering method, the above mask is removed, and a lower electrode layer 75 and an upper electrode layer 76 are formed.

【００５８】次に、下部電極層７５および上部電極層７
６が形成されたセラミックグリーンシートの両面に、例
えば、蒸着法またはスパッタ法により、ＳｉＯ２膜を付
着し、絶縁膜層７７を形成する。Next, the lower electrode layer 75 and the upper electrode layer 7
An SiO 2 film is attached to both surfaces of the ceramic green sheet on which the insulating film 6 is formed by, for example, a vapor deposition method or a sputtering method to form an insulating film layer 77.

【００５９】次に、絶縁膜層７７等が形成されたセラミ
ックグリーンシートにおいて、ＬＳＩチップ１の電源端
子および接地端子が配置される部分に対応する領域の上
面と下面との間を貫通するビアホール７８および７９
を、例えば、パンチングまたはエッチングにより形成
し、かかるビアホール７８および７９内に導電材を充填
する。こうして、形成されたビアホール７８は下部電極
層７５に、ビアホール７９は上部電極層７６に、それぞ
れ接続されることになる。即ち、上記マスクがされた領
域には、下部電極層７５および上部電極層７６が形成さ
れないので、その領域では、ビアホール７８および７９
と、下部電極層７５および上部電極層７６は接続される
ことはない。Next, in the ceramic green sheet on which the insulating film layer 77 and the like are formed, a via hole 78 penetrating between the upper surface and the lower surface of the region corresponding to the portion where the power supply terminal and the ground terminal of the LSI chip 1 are arranged. And 79
Are formed by, for example, punching or etching, and the via holes 78 and 79 are filled with a conductive material. The via hole 78 thus formed is connected to the lower electrode layer 75, and the via hole 79 is connected to the upper electrode layer 76. That is, since the lower electrode layer 75 and the upper electrode layer 76 are not formed in the masked area, the via holes 78 and 79 are formed in that area.
, The lower electrode layer 75 and the upper electrode layer 76 are not connected.

【００６０】次に、ビアホール７８および７９等が形成
されたセラミックグリーンシートにおいて、ＬＳＩチッ
プ１の電源端子が配置される部分に対応する領域の上面
と下面に、金属からなる第１の電極パッド７１および７
２を、ビアホール７８に接続させつつ形成し、ＬＳＩチ
ップ１の接地端子が配置される部分に対応する領域の上
面と下面に金属からなる第２の電極パッド７３および７
４を、ビアホール７９に接続させつつ形成する。こうし
て、コンデンサ７が製造されることになる。Next, in the ceramic green sheet in which the via holes 78 and 79 are formed, the first electrode pad 71 made of metal is formed on the upper surface and the lower surface of the region corresponding to the portion where the power supply terminal of the LSI chip 1 is arranged. And 7
Second electrode pads 73 and 7 made of metal on the upper surface and the lower surface of the region of the LSI chip 1 corresponding to the portion where the ground terminal is arranged.
4 is formed while being connected to the via hole 79. Thus, the capacitor 7 is manufactured.

【００６１】次に、図４に示す配線基板２の電源端子お
よび接地端子にバンプ５を搭載、加熱溶融し、その上に
製造されたコンデンサ７を搭載してバンプ５によって、
当該コンデンサ７下面の第１の電極パッド７２と配線基
板２の電源端子とを、第２の電極パッド７４と配線基板
２の接地端子とを、それぞれフリップチップ接続（溶
着）する。Next, the bump 5 is mounted on the power supply terminal and the ground terminal of the wiring board 2 shown in FIG. 4, heated and melted, and the manufactured capacitor 7 is mounted on the bump 5, and the bump 5 is used.
The first electrode pad 72 on the lower surface of the capacitor 7 and the power supply terminal of the wiring board 2 are flip-chip connected (welded) to the second electrode pad 74 and the ground terminal of the wiring board 2, respectively.

【００６２】次に、配線基板２の信号入出力端子にバン
プ４を搭載、加熱溶融し、コンデンサ７上面の第１の電
極パッド７１および、第２の電極パッド７３にバンプ５
を搭載、加熱溶融し、その上にＬＳＩチップ１を搭載す
る。そして、バンプ４によって、配線基板２の信号入出
力端子とＬＳＩチップ１の信号入出力端子とをフリップ
チップ接続（溶着）するとともに、バンプ５によって、
当該コンデンサ７上面の第１の電極パッド７１とＬＳＩ
チップ１の電源端子とを、第２の電極パッド７３とＬＳ
Ｉチップ１の接地端子とを、それぞれフリップチップ接
続（溶着）する。こうして、図４に示すような集積回路
装置２００が製造される。Next, the bumps 4 are mounted on the signal input / output terminals of the wiring board 2, heated and melted, and the bumps 5 are formed on the first electrode pads 71 and the second electrode pads 73 on the upper surface of the capacitor 7.
Is mounted, heated and melted, and the LSI chip 1 is mounted thereon. Then, the signal input / output terminals of the wiring board 2 and the signal input / output terminals of the LSI chip 1 are flip-chip connected (welded) by the bumps 4, and by the bumps 5,
The first electrode pad 71 on the upper surface of the capacitor 7 and the LSI
The power supply terminal of the chip 1 is connected to the second electrode pad 73 and the LS.
The ground terminals of the I-chip 1 are flip-chip connected (welded) to each other. Thus, the integrated circuit device 200 as shown in FIG. 4 is manufactured.

【００６３】以上説明したように第１実施形態によれ
ば、コンデンサを、ＬＳＩチップと配線基板の間に実装
し、ＬＳＩチップの電源端子および接地端子に、電源端
子および接地端子からリード線を引き出すことなく、直
接に、バンプの機能も兼ねて、接続するように構成した
ので、従来の集積回路装置におけるリード線部分のイン
ダクタンス成分をなくすことができ、また、コンデンサ
を実装する面積を広くとることができるのでその容量範
囲を大きくとることができる。従って、より効果的にス
イッチングノイズを抑えることが可能となる。As described above, according to the first embodiment, the capacitor is mounted between the LSI chip and the wiring board, and the lead wire is drawn from the power supply terminal and the ground terminal to the power supply terminal and the ground terminal of the LSI chip. Since it is configured to be connected directly with the function of bumps, it is possible to eliminate the inductance component of the lead wire portion in the conventional integrated circuit device and to increase the area for mounting the capacitor. Therefore, the capacity range can be increased. Therefore, the switching noise can be suppressed more effectively.

【００６４】さらに、コンデンサの配線基板面に平行な
面の形状を、ＬＳＩチップの電源端子および接地端子の
配列に応じて形成するように構成したので、大幅にコン
デンサを実装する面積を広くとることができ、極めて効
果的にスイッチングノイズを抑えることが可能となる。 （第２実施形態）次に、本発明にかかる第２実施形態に
おける集積回路装置の構造について、図７を参照して説
明する。なお、第２実施形態における集積回路装置の説
明において、第１実施形態における集積回路装置１００
と同様の構成部分については、同一符号を付して説明
し、重複する説明は省略することとする。Further, since the shape of the surface of the capacitor parallel to the surface of the wiring board is formed in accordance with the arrangement of the power supply terminals and the ground terminals of the LSI chip, the area for mounting the capacitor should be made large. Therefore, the switching noise can be suppressed very effectively. (Second Embodiment) Next, the structure of an integrated circuit device according to a second embodiment of the present invention will be described with reference to FIG. In the description of the integrated circuit device according to the second embodiment, the integrated circuit device 100 according to the first embodiment will be described.
Constituent parts similar to those described above are denoted by the same reference numerals, and redundant description will be omitted.

【００６５】図７に、第２実施形態における集積回路装
置を横から見た構造の概念図の一例を示す。図７に示す
ように、集積回路装置３００は、ＬＳＩチップ１と、パ
ッケージ基板１１と、配線基板２と、コンデンサ３と、
を含んで構成される。図１に示す集積回路装置１００と
の違いは、ＬＳＩチップ１を保護しＬＳＩチップ１との
配線基板２との接続の仲介をする役目を担うパッケージ
基板１１を有する点である。FIG. 7 shows an example of a conceptual view of the structure of the integrated circuit device according to the second embodiment as viewed from the side. As shown in FIG. 7, the integrated circuit device 300 includes an LSI chip 1, a package substrate 11, a wiring substrate 2, a capacitor 3, and
It is configured to include. The difference from the integrated circuit device 100 shown in FIG. 1 is that it has a package substrate 11 that protects the LSI chip 1 and acts as an intermediary for connection between the LSI chip 1 and the wiring substrate 2.

【００６６】パッケージ基板１１の上面には、ＬＳＩチ
ップ１に設けられた、それぞれの外部接続端子に対応す
る上面外部接続端子が設けられており、パッケージ基板
１１の下面には、それぞれの上面外部接続端子に接続す
る下面外部接続端子が設けられている。On the upper surface of the package substrate 11, upper surface external connection terminals corresponding to the respective external connection terminals provided on the LSI chip 1 are provided, and on the lower surface of the package substrate 11, the respective upper surface external connection terminals are provided. A lower surface external connection terminal for connecting to the terminal is provided.

【００６７】そして、図７に示すように、ＬＳＩチップ
１の信号入出力端子とパッケージ基板１１の信号入出力
端子とは、バンプ４によってフリップチップ接続され
る。また、パッケージ基板１１の信号入出力端子と配線
基板２の信号入出力端子とは、バンプ４によってフリッ
プチップ接続される。そして、ＬＳＩチップ１とパッケ
ージ基板１１との間には、コンデンサ３がバンプ５を介
して実装される。また、パッケージ基板１１と配線基板
２との間にも、コンデンサ３がバンプ５を介して実装さ
れる。このようなコンデンサ３の構成は、第１実施形態
と同様である。Then, as shown in FIG. 7, the signal input / output terminals of the LSI chip 1 and the signal input / output terminals of the package substrate 11 are flip-chip connected by the bumps 4. Further, the signal input / output terminal of the package substrate 11 and the signal input / output terminal of the wiring substrate 2 are flip-chip connected by the bump 4. Then, the capacitor 3 is mounted between the LSI chip 1 and the package substrate 11 via the bump 5. Further, the capacitor 3 is also mounted between the package substrate 11 and the wiring substrate 2 via the bump 5. The configuration of such a capacitor 3 is similar to that of the first embodiment.

【００６８】ＬＳＩチップ１とパッケージ基板１１との
間においては、コンデンサ３の一方の第１の電極パッド
３５とＬＳＩチップ１の電源端子とがバンプ５によって
フリップチップ接続されるとともに、コンデンサ３の他
方の第１の電極パッド３６とパッケージ基板１１の電源
端子とがバンプ５によってフリップチップ接続される。
また、コンデンサ３の一方の第２の電極パッド３７とＬ
ＳＩチップ１の接地端子とがバンプ５によってフリップ
チップ接続されるとともに、コンデンサ３の他方の第２
の電極パッド３８とパッケージ基板１１の接地端子とが
バンプ５によってフリップチップ接続される。Between the LSI chip 1 and the package substrate 11, the first electrode pad 35 of one of the capacitors 3 and the power supply terminal of the LSI chip 1 are flip-chip connected by the bumps 5, and the other of the capacitors 3 is connected. The first electrode pad 36 and the power supply terminal of the package substrate 11 are flip-chip connected by the bump 5.
The second electrode pad 37 of one side of the capacitor 3 and L
The ground terminal of the SI chip 1 is flip-chip connected by the bump 5, and the other second terminal of the capacitor 3 is connected.
The electrode pad 38 and the ground terminal of the package substrate 11 are flip-chip connected by the bump 5.

【００６９】パッケージ基板１１と配線基板２との間に
おいては、コンデンサ３の一方の第１の電極パッド３５
とパッケージ基板１１の電源端子とがバンプ５によって
フリップチップ接続されるとともに、コンデンサ３の他
方の第１の電極パッド３６と配線基板２の電源端子とが
バンプ５によってフリップチップ接続される。また、コ
ンデンサ３の一方の第２の電極パッド３７とパッケージ
基板１１の接地端子とがバンプ５によってフリップチッ
プ接続されるとともに、コンデンサ３の他方の第２の電
極パッド３８と配線基板２の接地端子とがバンプ５によ
ってフリップチップ接続される。Between the package substrate 11 and the wiring substrate 2, one of the first electrode pads 35 of the capacitor 3 is provided.
And the power supply terminal of the package substrate 11 are flip-chip connected by the bump 5, and the other first electrode pad 36 of the capacitor 3 and the power supply terminal of the wiring substrate 2 are flip-chip connected by the bump 5. Further, one second electrode pad 37 of the capacitor 3 and the ground terminal of the package substrate 11 are flip-chip connected by the bumps 5, and the other second electrode pad 38 of the capacitor 3 and the ground terminal of the wiring substrate 2 are connected. And are flip-chip connected by the bumps 5.

【００７０】このように、ＬＳＩチップ１とパッケージ
基板１１との間に実装されるコンデンサ３は、ＬＳＩチ
ップ１における電源回路と接地回路との間および、パッ
ケージ基板１１における電源回路と接地回路との間の双
方に直接接続されるとともに、さらに、コンデンサ３
は、バンプ４の代わりに、ＬＳＩチップ１の外部接続端
子（電源端子または、接地端子）と、パッケージ基板１
１の外部接続端子（電源端子または、接地端子）とをフ
リップチップ接続する機能を有する。As described above, the capacitors 3 mounted between the LSI chip 1 and the package substrate 11 are arranged between the power supply circuit and the ground circuit in the LSI chip 1 and between the power supply circuit and the ground circuit in the package substrate 11. It is directly connected to both sides of the
Instead of the bumps 4, the external connection terminals (power supply terminals or ground terminals) of the LSI chip 1 and the package substrate 1
It has a function of flip-chip connecting with one external connection terminal (power supply terminal or ground terminal).

【００７１】また、パッケージ基板１１と配線基板２と
の間に実装されるコンデンサ３は、パッケージ基板１１
における電源回路と接地回路との間および、配線基板２
における電源回路と接地回路との間の双方に直接接続さ
れるとともに、さらに、コンデンサ３は、バンプ４の代
わりに、パッケージ基板１１の外部接続端子（電源端子
または、接地端子）と、配線基板２の外部接続端子（電
源端子または、接地端子）とをフリップチップ接続する
機能を有する。The capacitor 3 mounted between the package board 11 and the wiring board 2 is
Between the power circuit and the ground circuit in the wiring board 2
In addition to being directly connected to both the power supply circuit and the ground circuit in the above, the capacitor 3 is replaced with the bump 4 by an external connection terminal (power supply terminal or ground terminal) of the package board 11 and the wiring board 2. The external connection terminal (power supply terminal or ground terminal) has a function of flip-chip connection.

【００７２】なお、第２実施形態における集積回路装置
３００においても、図５を参照して説明したコンデンサ
７を適用することができるのはいうまでもない。この場
合において、パッケージ基板１１と配線基板２との間に
実装するコンデンサは、パッケージ基板１１の電源端子
および接地端子の配列に応じて形成するように構成す
る。また、第２実施形態における集積回路装置３００
は、図４に示す集積回路装置２００と同様の手法で製造
することができる。Needless to say, the capacitor 7 described with reference to FIG. 5 can be applied to the integrated circuit device 300 according to the second embodiment. In this case, the capacitors mounted between the package board 11 and the wiring board 2 are formed according to the arrangement of the power supply terminals and the ground terminals of the package board 11. Further, the integrated circuit device 300 according to the second embodiment.
Can be manufactured by a method similar to that of the integrated circuit device 200 shown in FIG.

【００７３】以上説明したように、第２実施形態によれ
ば、集積回路装置にパッケージ基板を備える場合であっ
ても、コンデンサを、ＬＳＩチップとパッケージ基板の
間や、パッケージ基板と配線基板の間に実装することに
より、第１実施形態と同様の効果を得ることができる。As described above, according to the second embodiment, capacitors are provided between the LSI chip and the package substrate or between the package substrate and the wiring substrate even when the integrated circuit device is provided with the package substrate. The same effect as in the first embodiment can be obtained by implementing the above.

【００７４】なお、第２実施形態にかかる集積回路装置
３００では、コンデンサを、ＬＳＩチップとパッケージ
基板との間と、パッケージ基板と配線基板との間の双方
に実装する構成例を示したが、当該コンデンサを、ＬＳ
Ｉチップとパッケージ基板との間のみ、或いは、パッケ
ージ基板と配線基板との間のみに実装するように構成し
ても、上記実施形態と同様の効果を得ることができる。
コンデンサをパッケージ基板と配線基板との間のみ実装
する場合において、パッケージ基板に搭載されるＬＳＩ
チップは、図７に示すようなフリップチップ実装でなく
ともよく、例えば、いわゆるワイヤボンディング方式に
よる実装形態でも構わない。In the integrated circuit device 300 according to the second embodiment, the configuration example in which the capacitors are mounted both between the LSI chip and the package substrate and between the package substrate and the wiring substrate has been shown. Replace the capacitor with LS
Even if it is configured to be mounted only between the I chip and the package substrate or only between the package substrate and the wiring substrate, the same effect as that of the above embodiment can be obtained.
LSI mounted on the package board when the capacitor is mounted only between the package board and the wiring board
The chip does not have to be flip-chip mounted as shown in FIG. 7, and may be mounted by a so-called wire bonding method, for example.

【００７５】また、第１および第２実施形態におけるコ
ンデンサは、単層構造であるが、多層構造、つまり、複
数の上部電極層および下部電極層を形成するようにして
も同様の効果を得ることができる。Although the capacitors in the first and second embodiments have a single-layer structure, a similar effect can be obtained even if a multilayer structure, that is, a plurality of upper electrode layers and lower electrode layers are formed. You can

【００７６】[0076]

【発明の効果】以上説明したように、本発明によれば、
コンデンサを、集積回路チップと配線基板間等の集積回
路チップの近傍に配置し、集積回路チップ等の電源回路
および接地回路との間に接続するとともに、集積回路チ
ップと配線基板の電源端子間および、集積回路チップと
配線基板の接地端子間等を接続する機能を兼ねるように
構成したので、コンデンサの実装面積をより広くとり、
その容量範囲を大きくとることができ、従来のようなリ
ード線部分のインダクタンス成分をなくすことができ
る。よって、より効果的にスイッチングノイズを抑える
ことができる。As described above, according to the present invention,
The capacitor is arranged in the vicinity of the integrated circuit chip such as between the integrated circuit chip and the wiring board and connected between the power supply circuit such as the integrated circuit chip and the ground circuit, and between the integrated circuit chip and the power supply terminal of the wiring board and Since the integrated circuit chip and the grounding terminal of the wiring board are connected together, the mounting area of the capacitor is increased,
The capacitance range can be increased, and the conventional inductance component of the lead wire portion can be eliminated. Therefore, switching noise can be suppressed more effectively.

【図面の簡単な説明】[Brief description of drawings]

【図１】第１実施形態における集積回路装置を横から見
た構造の概念図である。FIG. 1 is a conceptual diagram of a structure of an integrated circuit device according to a first embodiment as viewed from the side.

【図２】図１におけるコンデンサ３の断面構造を横から
見た構造の概念図である。FIG. 2 is a conceptual diagram of a cross-sectional structure of a capacitor 3 in FIG. 1 viewed from the side.

【図３】（Ａ）は、従来の集積回路装置の等価回路を、
（Ｂ）は、第１実施形態における集積回路装置１００の
等価回路を、それぞれ示す図である。FIG. 3A shows an equivalent circuit of a conventional integrated circuit device,
FIG. 3B is a diagram showing an equivalent circuit of the integrated circuit device 100 according to the first embodiment.

【図４】ＬＳＩチップ１の外部接続端子の配列に応じた
形状に形成したコンデンサを実装した場合の集積回路装
置を横から見た構造の概念図である。FIG. 4 is a conceptual view of a structure of a side view of an integrated circuit device in which a capacitor formed in a shape corresponding to an arrangement of external connection terminals of an LSI chip 1 is mounted.

【図５】（Ａ）は、図４に示す集積回路装置２００にお
けるＬＳＩチップ１の下面の外部接続端子の配列を示す
図であり、（Ｂ）は、（Ａ）におけるＬＳＩチップ１の
外部接続端子の配列に応じた形状に形成したコンデンサ
７の上面図である。5A is a diagram showing an arrangement of external connection terminals on the lower surface of the LSI chip 1 in the integrated circuit device 200 shown in FIG. 4, and FIG. 5B is an external connection of the LSI chip 1 in FIG. It is a top view of the capacitor 7 formed in the shape according to the arrangement of the terminals.

【図６】コンデンサ７を横から見た構造の概念図であ
る。FIG. 6 is a conceptual diagram of a structure of the capacitor 7 seen from the side.

【図７】第２実施形態における集積回路装置を横から見
た構造の概念図である。FIG. 7 is a conceptual diagram of a structure of the integrated circuit device according to the second embodiment as viewed from the side.

【図８】従来の集積回路装置を横から見た構造の概念図
である。FIG. 8 is a conceptual diagram of a structure of a conventional integrated circuit device viewed from the side.

【図９】図８とは別の従来の集積回路装置を横から見た
構造の概念図である。9 is a conceptual diagram of a structure of a conventional integrated circuit device different from that of FIG. 8 as viewed from the side.

【符号の説明】[Explanation of symbols]

１ ＬＳＩチップ １ａ ＬＳＩ ２ 配線基板 ３、７ コンデンサ ４、５ バンプ １１ パッケージ基板 １５ 電源端子 １６ 接地端子 １７ 信号入出力端子 ３１ 絶縁膜層 ３２ 下部電極層 ３３ 誘電体 ３４ 上部電極層 ３５、３６ 第１の電極パッド ３７、３８ 第２の電極パッド ３９、４０ ビアホール ７１、７２ 第１の電極パッド ７３、７４ 第２の電極パッド ７５ 下部電極層 ７６ 上部電極層 ７７ 絶縁層膜 ７８、７９ ビアホール ８１ 配線基板 ８２ パッケージ基板 ８３ ＬＳＩチップ ８４ コンデンサ ８５ バンプ ９１ 配線基板 ９２ パッケージ基板 ９３ ＬＳＩチップ ９３ａ ＬＳＩ ９４ コンデンサ ９６ バンプ ９７ 電源端子 ９８ 接地端子 1 LSI chip 1a LSI 2 wiring board 3, 7 capacitor 4,5 bumps 11 Package substrate 15 Power terminal 16 Ground terminal 17 Signal input / output terminal 31 Insulating film layer 32 Lower electrode layer 33 Dielectric 34 Upper electrode layer 35, 36 First electrode pad 37, 38 Second electrode pad 39, 40 beer holes 71, 72 First electrode pad 73, 74 Second electrode pad 75 Lower electrode layer 76 Upper electrode layer 77 Insulating layer film 78, 79 beer holes 81 wiring board 82 Package substrate 83 LSI chip 84 capacitor 85 bumps 91 wiring board 92 Package substrate 93 LSI chip 93a LSI 94 capacitors 96 bump 97 Power supply terminal 98 Ground terminal

Claims (16)

【特許請求の範囲】[Claims] 【請求項１】 集積回路チップが配線基板にフリップチ
ップ実装された集積回路装置において、 前記集積回路チップと前記配線基板との間にコンデンサ
が実装され、前記コンデンサは、当該コンデンサの一方
の電極に接続された一対の第１の電極パッドと、他方の
電極に接続された一対の第２の電極パッドを有し、 前記第１の電極パッドの一方は前記集積回路チップの電
源端子に、前記第１の電極パッドの他方は前記配線基板
の電源端子にそれぞれ接続されているとともに、前記第
２の電極パッドの一方は前記集積回路チップの接地端子
に、前記第２の電極パッドの他方は前記配線基板の接地
端子にそれぞれ接続されていることを特徴とする集積回
路装置。1. An integrated circuit device in which an integrated circuit chip is flip-chip mounted on a wiring board, wherein a capacitor is mounted between the integrated circuit chip and the wiring board, and the capacitor is provided on one electrode of the capacitor. It has a pair of first electrode pads connected to each other and a pair of second electrode pads connected to the other electrode, and one of the first electrode pads is connected to a power supply terminal of the integrated circuit chip, and The other one of the electrode pads is connected to the power supply terminal of the wiring board, one of the second electrode pads is connected to the ground terminal of the integrated circuit chip, and the other of the second electrode pads is connected to the wiring. An integrated circuit device, which is connected to a ground terminal of a substrate, respectively. 【請求項２】 前記一対の第１の電極パッドのうち一方
は前記集積回路チップ側に設けられ他方は前記配線基板
側に設けられるとともに、前記一対の第２の電極パッド
のうち一方は前記集積回路チップ側に設けられ他方は前
記配線基板側に設けられており、 前記集積回路チップ側の電極パッドおよび前記配線基板
側の電極パッドは、前記配線基板面に垂直な方向に配置
されることを特徴とする請求項１に記載の集積回路装
置。2. One of the pair of first electrode pads is provided on the integrated circuit chip side and the other is provided on the wiring board side, and one of the pair of second electrode pads is the integrated circuit chip. It is provided on the circuit chip side and the other is provided on the wiring board side, and the electrode pad on the integrated circuit chip side and the electrode pad on the wiring board side are arranged in a direction perpendicular to the wiring board surface. The integrated circuit device according to claim 1, which is characterized in that. 【請求項３】 前記コンデンサは、複数対の前記第１の
電極パッドと、複数対の前記第２の電極パッドを有し、 前記コンデンサの前記配線基板面に平行な面の形状が、
前記集積回路チップの電源端子および接地端子の配列に
応じた形状であることを特徴とする請求項１または２に
記載の集積回路装置。3. The capacitor has a plurality of pairs of the first electrode pads and a plurality of pairs of the second electrode pads, and a shape of a surface of the capacitor parallel to the wiring board surface is
The integrated circuit device according to claim 1 or 2, wherein the integrated circuit device has a shape corresponding to an arrangement of a power supply terminal and a ground terminal of the integrated circuit chip. 【請求項４】 前記コンデンサの前記配線基板面に平行
な面の面積は、信号入出力端子が配置された前記集積回
路チップ面のうち、当該信号入出力端子部分を含む所定
領域を除く領域の面積と等しいことを特徴とする請求項
１乃至３の何れか１項に記載の集積回路装置。4. The area of a surface of the capacitor parallel to the wiring board surface is the area of the integrated circuit chip surface on which the signal input / output terminals are arranged, excluding a predetermined area including the signal input / output terminal portion. The integrated circuit device according to claim 1, wherein the integrated circuit device has the same area. 【請求項５】 集積回路チップがパッケージ基板にフリ
ップチップ実装され、かつ、前記パッケージ基板が配線
基板にフリップチップ実装された集積回路装置におい
て、 前記集積回路チップと前記パッケージ基板との間にコン
デンサが実装され、前記コンデンサは、当該コンデンサ
の一方の電極に接続された一対の第１の電極パッドと、
他方の電極に接続された一対の第２の電極パッドを有
し、 前記第１の電極パッドの一方は前記集積回路チップの電
源端子に、前記第１の電極パッドの他方は前記パッケー
ジ基板の電源端子にそれぞれ接続されているとともに、
前記第２の電極パッドの一方は前記集積回路チップの接
地端子に、前記第２の電極パッドの他方は前記パッケー
ジ基板の接地端子にそれぞれ接続されていることを特徴
とする集積回路装置。5. An integrated circuit device in which an integrated circuit chip is flip-chip mounted on a package substrate, and the package substrate is flip-chip mounted on a wiring substrate, wherein a capacitor is provided between the integrated circuit chip and the package substrate. Mounted, the capacitor includes a pair of first electrode pads connected to one electrode of the capacitor,
A pair of second electrode pads connected to the other electrode, one of the first electrode pads being a power supply terminal of the integrated circuit chip, and the other of the first electrode pads being a power supply of the package substrate. While being connected to each terminal,
An integrated circuit device, wherein one of the second electrode pads is connected to a ground terminal of the integrated circuit chip and the other of the second electrode pads is connected to a ground terminal of the package substrate. 【請求項６】 前記一対の第１の電極パッドのうち一方
は前記集積回路チップ側に設けられ他方は前記パッケー
ジ基板側に設けられるとともに、前記一対の第２の電極
パッドのうち一方は前記集積回路チップ側に設けられ他
方は前記パッケージ基板側に設けられており、 前記集積回路チップ側の電極パッドおよび前記パッケー
ジ基板側の電極パッドは、前記配線基板面に垂直な方向
に配置されることを特徴とする請求項５に記載の集積回
路装置。6. One of the pair of first electrode pads is provided on the integrated circuit chip side and the other is provided on the package substrate side, and one of the pair of second electrode pads is the integrated circuit. The other one is provided on the circuit chip side and the other is provided on the package substrate side, and the integrated circuit chip side electrode pad and the package substrate side electrode pad are arranged in a direction perpendicular to the wiring substrate surface. The integrated circuit device according to claim 5, which is characterized in that: 【請求項７】 前記コンデンサは、複数対の前記第１の
電極パッドと、複数対の前記第２の電極パッドを有し、 前記コンデンサの前記配線基板面に平行な面の形状が、
前記集積回路チップの電源端子および接地端子の配列に
応じた形状であることを特徴とする請求項５または６に
記載の集積回路装置。7. The capacitor has a plurality of pairs of the first electrode pads and a plurality of pairs of the second electrode pads, and a shape of a surface of the capacitor parallel to the wiring board surface is
7. The integrated circuit device according to claim 5, wherein the integrated circuit device has a shape corresponding to the arrangement of the power supply terminal and the ground terminal of the integrated circuit chip. 【請求項８】 前記コンデンサの前記配線基板面に平行
な面の面積は、信号入出力端子が配置された前記集積回
路チップ面のうち、当該信号入出力端子部分を含む所定
領域を除く領域の面積と等しいことを特徴とする請求項
５乃至７の何れか１項に記載の集積回路装置。8. The area of a surface of the capacitor parallel to the wiring board surface is the area of the integrated circuit chip surface on which the signal input / output terminals are arranged, excluding a predetermined area including the signal input / output terminal portion. The integrated circuit device according to claim 5, wherein the integrated circuit device has the same area. 【請求項９】 集積回路チップが搭載されたパッケージ
基板が配線基板にフリップチップ実装された集積回路装
置において、 前記パッケージ基板と前記配線基板との間にコンデンサ
が実装され、前記コンデンサは、当該コンデンサの一方
の電極に接続された一対の第１の電極パッドと、他方の
電極に接続された一対の第２の電極パッドを有し、 前記第１の電極パッドの一方は前記パッケージ基板の電
源端子に、前記第１の電極パッドの他方は前記配線基板
の電源端子にそれぞれ接続されているとともに、前記第
２の電極パッドの一方は前記パッケージ基板の接地端子
に、前記第２の電極パッドの他方は前記配線基板の接地
端子にそれぞれ接続されていることを特徴とする集積回
路装置。9. In an integrated circuit device in which a package board having an integrated circuit chip mounted thereon is flip-chip mounted on a wiring board, a capacitor is mounted between the package board and the wiring board, and the capacitor is the capacitor. A pair of first electrode pads connected to one electrode and a pair of second electrode pads connected to the other electrode, one of the first electrode pads being a power supply terminal of the package substrate The other one of the first electrode pads is connected to the power supply terminal of the wiring board, and one of the second electrode pads is connected to the ground terminal of the package board, and the other of the second electrode pads is connected to the ground terminal of the package board. Are connected to the ground terminals of the wiring board, respectively. 【請求項１０】 前記一対の第１の電極パッドのうち一
方は前記パッケージ基板側に設けられ他方は前記配線基
板側に設けられるとともに、前記一対の第２の電極パッ
ドのうち一方は前記パッケージ基板側に設けられ他方は
前記配線基板側に設けられており、 前記パッケージ基板側の電極パッドおよび前記配線基板
側の電極パッドは、前記配線基板面に垂直な方向に配置
されることを特徴とする請求項９に記載の集積回路装
置。10. One of the pair of first electrode pads is provided on the package substrate side and the other is provided on the wiring substrate side, and one of the pair of second electrode pads is the package substrate. And the other is provided on the wiring board side, and the electrode pad on the package board side and the electrode pad on the wiring board side are arranged in a direction perpendicular to the wiring board surface. The integrated circuit device according to claim 9. 【請求項１１】 前記コンデンサは、複数対の前記第１
の電極パッドと、複数対の前記第２の電極パッドを有
し、 前記コンデンサの前記配線基板面に平行な面の形状が、
前記パッケージ基板の電源端子および接地端子の配列に
応じた形状であることを特徴とする請求項９または１０
に記載の集積回路装置。11. The capacitor comprises a plurality of pairs of the first capacitors.
Electrode pad and a plurality of pairs of the second electrode pad, the shape of the surface of the capacitor parallel to the wiring substrate surface,
11. The shape according to the arrangement of the power supply terminal and the ground terminal of the package substrate.
The integrated circuit device according to. 【請求項１２】 前記コンデンサの前記配線基板面に平
行な面の面積は、信号入出力端子が配置された前記パッ
ケージ基板面のうち、当該信号入出力端子部分を含む所
定領域を除く領域の面積と等しいことを特徴とする請求
項９乃至１１の何れか１項に記載の集積回路装置。12. An area of a surface of the capacitor parallel to the wiring board surface is an area of a region of the package board surface on which the signal input / output terminals are arranged, excluding a predetermined area including the signal input / output terminal portion. 12. The integrated circuit device according to claim 9, wherein the integrated circuit device is equal to. 【請求項１３】 集積回路チップとパッケージ基板との
間または、集積回路チップと配線基板との間の少なくと
も何れか一方に実装される集積回路用コンデンサであっ
て、 前記コンデンサは、当該コンデンサの一方の電極に接続
された一対の第１の電極パッドと、他方の電極に接続さ
れた一対の第２の電極パッドとを、それぞれ複数有し、 前記コンデンサの前記配線基板面に平行な面の形状が、
前記集積回路チップの電源端子および接地端子の配列に
応じた形状であることを特徴とする集積回路用コンデン
サ。13. A capacitor for an integrated circuit, which is mounted between at least one of an integrated circuit chip and a package substrate or between an integrated circuit chip and a wiring substrate, wherein the capacitor is one of the capacitors. A pair of first electrode pads connected to the electrodes of the capacitor and a pair of second electrode pads connected to the other electrode, respectively, and a shape of a surface parallel to the wiring board surface of the capacitor. But,
A capacitor for an integrated circuit, which has a shape corresponding to an arrangement of a power supply terminal and a ground terminal of the integrated circuit chip. 【請求項１４】 前記コンデンサの前記配線基板面に平
行な面の面積は、信号入出力端子が配置された前記集積
回路チップ面のうち、当該信号入出力端子部分を含む所
定領域を除く領域の面積と等しいことを特徴とする請求
項１３に記載の集積回路用コンデンサ。14. The area of a surface of the capacitor parallel to the wiring board surface is the area of the integrated circuit chip surface on which the signal input / output terminals are arranged, excluding a predetermined area including the signal input / output terminal portion. 14. The capacitor for an integrated circuit according to claim 13, which is equal to the area. 【請求項１５】 パッケージ基板と配線基板との間に実
装される集積回路用コンデンサであって、 前記コンデンサは、当該コンデンサの一方の電極に接続
された一対の第１の電極パッドと、他方の電極に接続さ
れた一対の第２の電極パッドとを、それぞれ複数有し、 前記コンデンサの前記配線基板面に平行な面の形状が、
前記パッケージ基板の電源端子および接地端子の配列に
応じた形状であることを特徴とする集積回路用コンデン
サ。15. An integrated circuit capacitor mounted between a package substrate and a wiring substrate, wherein the capacitor comprises a pair of first electrode pads connected to one electrode of the capacitor and another capacitor. A plurality of pairs of second electrode pads connected to the electrodes are respectively provided, and a shape of a surface of the capacitor parallel to the wiring board surface is
A capacitor for an integrated circuit, which has a shape corresponding to an arrangement of a power supply terminal and a ground terminal of the package substrate. 【請求項１６】 前記コンデンサの前記配線基板面に平
行な面の面積は、信号入出力端子が配置された前記パッ
ケージ基板面のうち、当該信号入出力端子部分を含む所
定領域を除く領域の面積と等しいことを特徴とする請求
項１５に記載の集積回路用コンデンサ。16. The area of the surface of the capacitor parallel to the wiring board surface is the area of the area of the package board surface on which the signal input / output terminals are arranged, excluding a predetermined area including the signal input / output terminal portion. 16. The capacitor for an integrated circuit according to claim 15, which is equal to
JP2001318343A 2001-10-16 2001-10-16 Integrated circuit device and capacitor for integrated circuit Pending JP2003124430A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001318343A JP2003124430A (en) 2001-10-16 2001-10-16 Integrated circuit device and capacitor for integrated circuit

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6859352B1 (en) 2004-02-19 2005-02-22 Fujitsu Limited Capacitor sheet
WO2005024945A1 (en) * 2003-09-01 2005-03-17 Fujitsu Limited Integrated circuit component and mounting method
JP2005244068A (en) * 2004-02-27 2005-09-08 Shinko Electric Ind Co Ltd Laminated semiconductor device
JP2010183073A (en) * 2009-02-05 2010-08-19 Northern Lights Semiconductor Corp Integrated circuit package for magnetic capacitor
JP2017084961A (en) * 2015-10-28 2017-05-18 株式会社村田製作所 Mounting structure of integrated circuit element

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005024945A1 (en) * 2003-09-01 2005-03-17 Fujitsu Limited Integrated circuit component and mounting method
US7375429B2 (en) 2003-09-01 2008-05-20 Fujitsu Limited Integrated circuit component and mounting method thereof
US6859352B1 (en) 2004-02-19 2005-02-22 Fujitsu Limited Capacitor sheet
JP2005244068A (en) * 2004-02-27 2005-09-08 Shinko Electric Ind Co Ltd Laminated semiconductor device
JP2010183073A (en) * 2009-02-05 2010-08-19 Northern Lights Semiconductor Corp Integrated circuit package for magnetic capacitor
JP2017084961A (en) * 2015-10-28 2017-05-18 株式会社村田製作所 Mounting structure of integrated circuit element

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