JP2003110641A - Demodulator - Google Patents
DemodulatorInfo
- Publication number
- JP2003110641A JP2003110641A JP2001306006A JP2001306006A JP2003110641A JP 2003110641 A JP2003110641 A JP 2003110641A JP 2001306006 A JP2001306006 A JP 2001306006A JP 2001306006 A JP2001306006 A JP 2001306006A JP 2003110641 A JP2003110641 A JP 2003110641A
- Authority
- JP
- Japan
- Prior art keywords
- output
- local oscillator
- signal
- frequency
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、局所発振器の発
振信号に基き、受信信号を中間周波数信号に変調させて
受信信号の復調を行う復調装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator which modulates a received signal into an intermediate frequency signal based on an oscillation signal of a local oscillator to demodulate the received signal.
【０００２】[0002]
【従来の技術】従来、移動体通信においては、受信電波
の復調を行うため、局所発振器を用いて中間周波数にダ
ウンコンバートさせて復調処理を行うことが多い。2. Description of the Related Art Conventionally, in mobile communication, in order to demodulate a received radio wave, a local oscillator is often used for down-conversion to an intermediate frequency for demodulation processing.
【０００３】従来におけるＱＰＳＫ変調（Quadrature P
hase Shift keying:４値移相変調）方式の復調装置の構
成例を図５に示す。１は従来例における第１局所発振器
を、２は乗算器を、３は乗算器出力の不要周波数成分を
除去するバンドパスフィルタを、４はリミッタを、５は
リミッタ出力の高調波成分を除去するローパスフィルタ
を、６は高調波成分が除去されたリミッタ出力信号をサ
ンプリングする第２局所発振器を、７はＡＤ変換器を、
８はＡＤ変換器出力を直交検波する直交検波部を、９は
直交検波出力の位相を検出する位相検出部を、１０は位
相検出部より出力される位相検出データより遅延検波を
行う遅延検波部を、１１は減算器を、１２は積分器を、
１３は１１と１２より主に構成される従来のＡＦＣ（Au
tomaticFrequency Control：自動周波数制御）部を、１
４はＡＦＣ部より出力された信号を用いて、ビット同期
させてクロック信号を抽出・再生しデータ信号を復調す
ることによって、受信データと再生クロックを出力する
ＢＴＲ（Bit Timing Recovery：ビットタイミング再
生）部を表す。Conventional QPSK modulation (Quadrature P
FIG. 5 shows a configuration example of a demodulator of a hase shift keying (four-valued phase shift keying) system. Reference numeral 1 is a first local oscillator in the conventional example, 2 is a multiplier, 3 is a bandpass filter for removing unnecessary frequency components of the multiplier output, 4 is a limiter, and 5 is a harmonic component of the limiter output. A low-pass filter, 6 is a second local oscillator for sampling the limiter output signal from which harmonic components are removed, and 7 is an AD converter.
Reference numeral 8 is a quadrature detection unit for quadrature detection of the AD converter output, 9 is a phase detection unit for detecting the phase of the quadrature detection output, and 10 is a delay detection unit for performing delay detection from the phase detection data output from the phase detection unit. , 11 is a subtractor, 12 is an integrator,
13 is a conventional AFC (Au
tomaticFrequency Control: 1)
Reference numeral 4 is a BTR (Bit Timing Recovery) that outputs received data and a reproduction clock by extracting and reproducing a clock signal in a bit-synchronized manner and demodulating a data signal by using a signal output from the AFC unit. Represents a part.
【０００４】図５のように従来においては、周波数ｆｃ
の受信電波と周波数ｆＬＯ１の第１局所発振器１を乗算
器２に入力し、周波数ｆｉｆを中心周波数とする中間周
波数信号を作成する。このとき、後段での復調処理のし
やすさを考慮し、中心周波数を伝送速度の２Ｎ倍に選択
させる場合がある。例えば伝送速度が２．０４８Ｍｂａ
ｕｄ（シンボル／秒）の場合、中間周波数信号は２．０
４８Ｍｂａｕｄの２Ｎ倍が選択される。乗算器出力はバ
ンドパスフィルタ３により不要周波数成分を除去され
る。バンドパスフィルタ３の出力はリミッタ４に入力さ
れ振幅が揃えられる。しかし、位相に情報を持たせる位
相変調方式の場合、振幅情報は考慮しなくてもよく、リ
ミッタ４を用いた場合でも位相情報については保持され
る。リミッタ４の出力はローパスフィルタ５に入力さ
れ、リミッタ出力の高調波成分を除去する。高調波成分
を除去されたリミッタ出力信号はＡＤ変換器７に入力さ
れ、第２局所発振器６によりサンプリングされる。例え
ば、ディジタル処理を用いた直交検波のしやすさを考慮
してサンプリング周波数は中間周波数信号の中心周波数
の４倍に設定される。図５では４ｆｉｆとしている。サ
ンプリングされた信号は直交検波部８により直交検波さ
れ、直交検波出力の位相を検出する位相検出部９により
位相情報が検出される。位相検出部９より出力された位
相検出データをもとに遅延検波部１０において遅延検波
を行う。従来のＡＦＣ部１３は減算器１１と積分器１２
より主に構成されている。遅延検波部１０より出力され
た信号は、従来のＡＦＣ部１３に入力され、減算器１１
を用いて積分器１２から出力される位相誤差を減算する
ことで周波数オフセット補正を行う。周波数オフセット
補正された信号は更に積分器１２に入力され、位相誤差
を更新し減算器１１に入力される。このように図５記載
の従来のＡＦＣ部１３はフィードバック構造である。補
正後の減算結果をＡＦＣ出力とし、ＢＴＲ部１４に入力
し、受信データと再生クロックを出力する。Conventionally, as shown in FIG. 5, the frequency fc
The received radio wave and the first local oscillator 1 having the frequency fLO1 are input to the multiplier 2 to create an intermediate frequency signal having the frequency fif as the center frequency. At this time, the center frequency may be selected to be 2N times the transmission rate in consideration of the ease of demodulation processing in the subsequent stage. For example, the transmission speed is 2.048Mba
In case of ud (symbol / second), the intermediate frequency signal is 2.0
2N times 48 Mbaud is selected. The bandpass filter 3 removes unnecessary frequency components from the multiplier output. The output of the bandpass filter 3 is input to the limiter 4 and its amplitudes are made uniform. However, in the case of the phase modulation method in which the phase has information, it is not necessary to consider the amplitude information, and the phase information is held even when the limiter 4 is used. The output of the limiter 4 is input to the low-pass filter 5 to remove the harmonic component of the limiter output. The limiter output signal from which the harmonic components have been removed is input to the AD converter 7 and sampled by the second local oscillator 6. For example, the sampling frequency is set to four times the center frequency of the intermediate frequency signal in consideration of the ease of quadrature detection using digital processing. In FIG. 5, it is set to 4fif. The sampled signal is quadrature detected by the quadrature detection unit 8, and phase information is detected by the phase detection unit 9 which detects the phase of the quadrature detection output. Based on the phase detection data output from the phase detection unit 9, the delay detection unit 10 performs delay detection. The conventional AFC unit 13 includes a subtractor 11 and an integrator 12
More mainly composed. The signal output from the differential detection unit 10 is input to the conventional AFC unit 13 and the subtractor 11
Is used to subtract the phase error output from the integrator 12 to perform frequency offset correction. The frequency offset-corrected signal is further input to the integrator 12, which updates the phase error and is input to the subtractor 11. As described above, the conventional AFC unit 13 shown in FIG. 5 has a feedback structure. The corrected subtraction result is used as the AFC output and is input to the BTR unit 14 to output the reception data and the reproduction clock.
【０００５】[0005]
【発明が解決しようとする課題】ところで、従来例にお
いて伝送速度が例えば２．０４８Ｍｂａｕｄの場合、中
間周波数信号の中心周波数としては伝送速度の２Ｎ倍が
選択されるため、中心周波数ｆｉｆとして８．１９２Ｍ
Ｈｚ、１２．２９２ＭＨｚなどの中心周波数が選択され
ることとなる。従って、例えば５８４０ＭＨｚの搬送波
を受信電波とした場合、中間周波数信号にダウンコンバ
ートするに際して、５８３１．８０８ＭＨｚの中心周波
数をもつ第１局所発振器を採用しなくてはならない。When the transmission rate is 2.048 Mbaud in the conventional example, 2N times the transmission rate is selected as the center frequency of the intermediate frequency signal, and therefore the center frequency fif is 8.192M.
A center frequency such as Hz or 12.292 MHz will be selected. Therefore, for example, when a carrier wave of 5840 MHz is used as the received radio wave, the first local oscillator having the center frequency of 5831.808 MHz must be adopted when down-converting to the intermediate frequency signal.
【０００６】しかし、第１局所発振器の周波数が５８３
１．８０８ＭＨｚなどのようになると、桁数が多くなり
高精度の局所発振器が要求されるため、精度が十分満足
されない場合、位相雑音が増え、受信性能が劣化する可
能性がある。However, the frequency of the first local oscillator is 583.
In the case of 1.808 MHz or the like, the number of digits increases and a highly accurate local oscillator is required. Therefore, if the accuracy is not sufficiently satisfied, phase noise increases and the reception performance may deteriorate.
【０００７】そこで本発明は、十分な精度を必要としな
い局所発振器を用いて中間周波数信号を作成し、受信信
号を復調させる復調装置を得ることを目的とする。Therefore, an object of the present invention is to obtain a demodulation device for producing an intermediate frequency signal by using a local oscillator which does not require sufficient accuracy and demodulating a received signal.
【０００８】[0008]
【課題を解決するための手段】第１の発明による復調装
置は、固定周波数分オフセットされた発振信号を出力す
る局所発振器と、受信電波を局所発振器の出力に基いて
中間周波数信号にダウンコンバートさせる乗算器と、前
記乗算器の出力信号をディジタル信号に変換するＡＤ変
換器と、前記ＡＤ変換器の出力と前記固定周波数分のオ
フセットに基いて、周波数オフセット補正を行う制御器
とを備えたものである。A demodulator according to a first aspect of the present invention down-converts a local oscillator that outputs an oscillation signal offset by a fixed frequency, and a received radio wave into an intermediate frequency signal based on the output of the local oscillator. A multiplier, an AD converter that converts the output signal of the multiplier into a digital signal, and a controller that performs frequency offset correction based on the output of the AD converter and the offset of the fixed frequency Is.
【０００９】第２の発明による復調装置は、固定周波数
分オフセットされた発振信号を出力する第１の局所発振
器と、受信電波を第１の局所発振器の出力に基いて中間
周波数信号にダウンコンバートさせる乗算器と、前記乗
算器より出力される中間周波数信号の不要周波数成分ま
たは高調波成分を除去するフィルタと、第２の局所発振
器と、前記高調波成分が除去された出力信号を前記第２
の局所発振器に基いてサンプリングし、ディジタル信号
に変換するＡＤ変換器と、前記ＡＤ変換器の出力を直交
検波する直交検波部と、前記直交検波出力の位相を検出
する位相検出部と、前記位相検出部より出力される位相
検出データより遅延検波を行う遅延検波部と、前記遅延
検波部の出力の積分値に前記固定周波数分のオフセット
を加算し、前記遅延検波部の出力から当該加算値の位相
誤差を減算して周波数オフセット補正を行うＡＦＣ部
と、前記ＡＦＣ部の出力信号から受信データと再生クロ
ックを出力するＢＴＲ部とを備えたものである。A demodulator according to a second aspect of the present invention down-converts a first local oscillator which outputs an oscillation signal offset by a fixed frequency and a received radio wave into an intermediate frequency signal based on the output of the first local oscillator. A multiplier, a filter for removing an unnecessary frequency component or a harmonic component of the intermediate frequency signal output from the multiplier, a second local oscillator, and an output signal from which the harmonic component is removed,
An AD converter for sampling based on the local oscillator and converting it into a digital signal, a quadrature detection section for quadrature detection of the output of the AD converter, a phase detection section for detecting the phase of the quadrature detection output, and the phase A delay detection unit that performs delay detection from the phase detection data output from the detection unit, and an offset for the fixed frequency is added to the integrated value of the output of the delay detection unit, and the added value of the added value from the output of the delay detection unit. An AFC unit for subtracting a phase error to correct a frequency offset, and a BTR unit for outputting received data and a reproduced clock from an output signal of the AFC unit are provided.
【００１０】第３の発明による復調装置は、固定周波数
分オフセットされた発振信号を出力する第１の局所発振
器と、受信電波を第１の局所発振器の出力に基いて中間
周波数信号にダウンコンバートさせる乗算器と、前記乗
算器より出力される中間周波数信号の不要周波数成分ま
たは高調波成分を除去するフィルタと、第２の局所発振
器と、前記高調波成分が除去された出力信号を前記第２
の局所発振器に基いてサンプリングし、ディジタル信号
に変換するＡＤ変換器と、前記ＡＤ変換器の出力を直交
検波する直交検波部と、前記直交検波出力の位相を検出
する位相検出部と、前記位相検出部より出力される位相
検出データより遅延検波を行う遅延検波部と、前記遅延
検波部の出力に前記固定周波数分のオフセットを加算す
る加算器と、前記加算器の出力から当該加算器の積分値
の位相誤差を減算して周波数オフセット補正を行うＡＦ
Ｃ部と、前記ＡＦＣ部の出力信号から受信データと再生
クロックを出力するＢＴＲ部とを備えたものである。A demodulator according to a third aspect of the present invention down-converts a first local oscillator that outputs an oscillation signal offset by a fixed frequency and a received radio wave into an intermediate frequency signal based on the output of the first local oscillator. A multiplier, a filter for removing an unnecessary frequency component or a harmonic component of the intermediate frequency signal output from the multiplier, a second local oscillator, and an output signal from which the harmonic component is removed,
An AD converter for sampling based on the local oscillator and converting it into a digital signal, a quadrature detection section for quadrature detection of the output of the AD converter, a phase detection section for detecting the phase of the quadrature detection output, and the phase A delay detection unit that performs delay detection based on the phase detection data output from the detection unit, an adder that adds the offset of the fixed frequency to the output of the delay detection unit, and an integration of the adder from the output of the adder AF that performs frequency offset correction by subtracting the phase error of the value
It is provided with a C section and a BTR section for outputting received data and a reproduction clock from the output signal of the AFC section.
【００１１】[0011]
【発明の実施の形態】実施の形態１．図１はこの発明の
実施の形態１の構成を示すブロック図である。図におい
て、１５は本発明における固定周波数オフセットを持っ
た第１局所発振器を、１６は本発明におけるバンドパス
フィルタを、１７は加算器を、１８は減算器１１と積分
器１２と加算器１７より主に構成されている改良ＡＦＣ
部を表し、それ以外の符号のものについては従来例と同
一もしくは同一相当である。BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. 1 is a block diagram showing a configuration of a first embodiment of the present invention. In the figure, 15 is a first local oscillator having a fixed frequency offset according to the present invention, 16 is a bandpass filter according to the present invention, 17 is an adder, and 18 is a subtractor 11, an integrator 12, and an adder 17. Improved AFC mainly composed
Parts other than the above are denoted by the same reference numerals as those in the conventional example.
【００１２】次に動作について説明する。図１におい
て、周波数ｆｃの受信電波と周波数ｆＬＯ１＋Δｆの第
１局所発振器１５からの発振信号を、乗算器２に入力
し、周波数ｆｉｆ−Δｆを中心周波数とする中間周波数
信号を作成する。ここでΔｆは固定周波数オフセットを
表し、ｆＬＯ１＋Δｆで第１局所発振器の中心周波数の
桁数を少なくさせるようにした周波数オフセットであ
る。以下具体例として、ＥＴＣ（Electric toll collec
tion system）用の通信装置等のＤＳＲＣ（専用狭帯域
通信）で利用される、受信電波の中心周波数ｆｃを５８
４０ＭＨｚとした場合の例について説明する。この際、
伝送速度を２．０４８Ｍｂａｕｄとし、後段での復調処
理のしやすさを考慮して、中間周波数信号の中心周波数
を伝送速度の４倍である８．１９２ＭＨｚとする。Next, the operation will be described. In FIG. 1, a received radio wave having a frequency fc and an oscillation signal from the first local oscillator 15 having a frequency fLO1 + Δf are input to the multiplier 2 to create an intermediate frequency signal having a frequency fif−Δf as a center frequency. Here, Δf represents a fixed frequency offset, and fLO1 + Δf is a frequency offset that reduces the number of digits of the center frequency of the first local oscillator. As a specific example, ETC (Electric toll collec)
The center frequency fc of the received radio wave used in DSRC (dedicated narrow band communication) of a communication device for communication system) is set to 58
An example in the case of 40 MHz will be described. On this occasion,
The transmission rate is set to 2.048 Mbaud, and the center frequency of the intermediate frequency signal is set to 8.192 MHz, which is four times the transmission rate, in consideration of the ease of demodulation processing in the subsequent stage.
【００１３】このとき、従来例の装置では、第１局所発
振器の周波数を５８３１．８０８ＭＨｚとして中間周波
数信号を作成する必要がある。しかし、周波数の桁数が
多いため、１９２ｋＨｚの固定周波数オフセットを持た
せ、第１局所発振器の周波数を５８３２ＭＨｚとする。
この例においては、１９２ｋＨｚがΔｆに相当し、５８
３２ＭＨｚがｆＬＯ＋Δｆに相当する。従って乗算器出
力である中間周波数信号の中心周波数ｆｉｆ−Δｆは８
ＭＨｚとなる。乗算器出力は中心周波数がｆｉｆ−Δｆ
であるバンドパスフィルタ１６により不要周波数成分を
除去される。バンドパスフィルタ１６の出力から遅延検
波部１０までの処理は従来例と同様である。遅延検波部
１０の出力を改良ＡＦＣ部に入力させる。改良ＡＦＣ部
１８は従来のＡＦＣ部１３に固定周波数オフセットを補
正させる機能を付加したものである。それは図１にもあ
るように積分器１２と減算器１１との間に加算器１７を
加え、積分器出力に固定周波数オフセットΔｆ分を加え
たもので遅延検波出力を減算することにより固定周波数
オフセットを含む周波数オフセットを補正するものであ
る。図１では加算器に固定周波数オフセット分Δｆを加
えており、シンボルレートで動作することを想定してい
る。固定周波数オフセットを含む周波数オフセットの補
正後の減算結果をＡＦＣ出力とし、ＢＴＲ部１４に入力
し、受信データと再生クロックを出力する。この改良Ａ
ＦＣ部１８を用いることで、固定周波数オフセットを持
った中間周波数信号でも復調を行うことが可能となる。At this time, in the conventional device, it is necessary to create an intermediate frequency signal by setting the frequency of the first local oscillator to 5831.808 MHz. However, since the number of digits of the frequency is large, a fixed frequency offset of 192 kHz is provided and the frequency of the first local oscillator is set to 5832 MHz.
In this example, 192 kHz corresponds to Δf,
32 MHz corresponds to fLO + Δf. Therefore, the center frequency fif-Δf of the intermediate frequency signal, which is the output of the multiplier, is 8
It becomes MHz. The center frequency of the multiplier output is fif−Δf
The unnecessary frequency component is removed by the bandpass filter 16 which is The processing from the output of the bandpass filter 16 to the differential detection unit 10 is the same as in the conventional example. The output of the differential detection unit 10 is input to the improved AFC unit. The improved AFC unit 18 is the conventional AFC unit 13 having a function of correcting a fixed frequency offset. As shown in FIG. 1, an adder 17 is added between the integrator 12 and the subtractor 11, and a fixed frequency offset Δf is added to the integrator output to subtract the delay detection output to obtain a fixed frequency offset. The frequency offset including is corrected. In FIG. 1, a fixed frequency offset Δf is added to the adder, and it is assumed that the adder operates at the symbol rate. The corrected subtraction result of the frequency offset including the fixed frequency offset is used as the AFC output, which is input to the BTR unit 14 to output the received data and the recovered clock. This improvement A
By using the FC unit 18, it becomes possible to demodulate even an intermediate frequency signal having a fixed frequency offset.
【００１４】実施の形態２．図２はこの発明の実施の形
態２の構成を示すブロック図である。図において、１７
は加算器、１３は従来のＡＦＣ部を表し、それ以外は図
１と同様である。Embodiment 2. 2 is a block diagram showing the configuration of the second embodiment of the present invention. In the figure, 17
Is an adder, 13 is a conventional AFC unit, and is otherwise the same as FIG.
【００１５】次に動作について説明する。乗算器２から
遅延検波１０までの動作は実施の形態１と同様である。
実施の形態２では遅延検波部１０と従来のＡＦＣ部１３
との間に加算器１７を挿入させる。遅延検波出力と固定
周波数オフセットΔｆを加算器１７に入れることにより
固定周波数オフセットΔｆの補正を行う。なお、図２で
は加算器１７の処理はシンボルレートで行っていること
を想定している。固定周波数オフセットを補正された信
号である加算器出力を従来のＡＦＣ部１３に入力し、通
常の周波数オフセット補正を行う。従来のＡＦＣ部１３
より出力されたＡＦＣ出力はＢＴＲ部１４に入力され受
信データと、それに同期した再生クロックを出力する。
このように、従来のＡＦＣ部１３の前に加算器１７を挿
入し固定周波数オフセットを補正させることにより、実
施の形態１と同様の効果が得られ、また従来のＡＦＣ部
をそのまま使用することが可能となる。Next, the operation will be described. The operation from the multiplier 2 to the differential detection 10 is the same as in the first embodiment.
In the second embodiment, the differential detection unit 10 and the conventional AFC unit 13 are used.
The adder 17 is inserted between and. The fixed frequency offset Δf is corrected by inserting the differential detection output and the fixed frequency offset Δf into the adder 17. In FIG. 2, it is assumed that the processing of the adder 17 is performed at the symbol rate. The adder output, which is a signal whose fixed frequency offset is corrected, is input to the conventional AFC unit 13 to perform normal frequency offset correction. Conventional AFC unit 13
The AFC output thus output is input to the BTR unit 14 and outputs the received data and the reproduction clock synchronized with the received data.
Thus, by inserting the adder 17 in front of the conventional AFC unit 13 and correcting the fixed frequency offset, the same effect as that of the first embodiment can be obtained, and the conventional AFC unit can be used as it is. It will be possible.
【００１６】実施の形態３．実施の形態１、及び２にお
いては復調装置にリミッタを用いているが、他の実施の
形態として、図３、または図４のようにＡＧＣ(Auto Ga
in Control)を用いても構わない。また実施の形態１、
及び２における構成以外でも、第１局所発振器で固定周
波数オフセットを持たせ、実施の形態１のように固定周
波数オフセット補正機能を付加した改良ＡＦＣ部を用い
る、または実施の形態２のように従来のＡＦＣ部の前段
に加算器を付加させ固定周波数オフセットを補正させる
ことで復調可能な構成ならば、別構成の復調装置でもよ
い。Embodiment 3. Although a limiter is used in the demodulation device in the first and second embodiments, as another embodiment, as shown in FIG.
in Control) may be used. In addition, the first embodiment,
In addition to the configurations in 2 and 2, the first local oscillator has a fixed frequency offset and the improved AFC unit having the fixed frequency offset correction function as in the first embodiment is used, or the conventional AFC unit as in the second embodiment is used. A demodulation device having a different configuration may be used as long as it can be demodulated by adding an adder in the preceding stage of the AFC unit and correcting the fixed frequency offset.
【００１７】[0017]
【発明の効果】第１の発明によれば、従来よりも桁数の
少ない周波数で発振する局所発振器を用いて中間周波数
信号を復調させることが可能となる。According to the first aspect of the present invention, it becomes possible to demodulate an intermediate frequency signal by using a local oscillator that oscillates at a frequency of which the number of digits is smaller than that of the conventional one.
【００１８】第２の発明によれば、固定周波数オフセッ
トを持った第１局所発振器と、乗算器と、バンドパスフ
ィルタと、リミッタと、ローパスフィルタと、第２局所
発振器と、ＡＤ変換器と、直交検波部と、位相検出部
と、遅延検波部と、固定周波数オフセット分の補正を行
うＡＦＣ部と、ＢＴＲ部を備えることで、従来よりも桁
数の少ない周波数で発振する局所発振器を用いて中間周
波数信号を復調させることが可能となる。According to the second invention, the first local oscillator having a fixed frequency offset, the multiplier, the bandpass filter, the limiter, the lowpass filter, the second local oscillator, the AD converter, A quadrature detection unit, a phase detection unit, a delay detection unit, an AFC unit that corrects a fixed frequency offset, and a BTR unit are provided to use a local oscillator that oscillates at a frequency with a number of digits smaller than that of a conventional oscillator. It becomes possible to demodulate the intermediate frequency signal.
【００１９】第３の発明によれば、固定周波数オフセッ
トを持った第１局所発振器と、乗算器と、バンドパスフ
ィルタと、リミッタと、ローパスフィルタと、第２局所
発振器と、ＡＤ変換器と、直交検波部と、位相検出部
と、遅延検波部と、固定周波数オフセット分の補正を行
う加算器と、ＡＦＣ部と、ＢＴＲ部を備えることで、第
１の発明と同様の効果が得られ、また従来のＡＦＣ部を
そのまま用いることが可能となる。According to the third invention, the first local oscillator having a fixed frequency offset, the multiplier, the bandpass filter, the limiter, the lowpass filter, the second local oscillator, the AD converter, By providing the quadrature detection unit, the phase detection unit, the delay detection unit, the adder for correcting the fixed frequency offset, the AFC unit, and the BTR unit, the same effect as that of the first invention can be obtained. Further, the conventional AFC unit can be used as it is.
【図１】 この発明の実施の形態１における復調装置の
構成を示す図である。FIG. 1 is a diagram showing a configuration of a demodulation device according to a first embodiment of the present invention.
【図２】 この発明の実施の形態２における復調装置の
構成を示す図である。FIG. 2 is a diagram showing a configuration of a demodulation device according to a second embodiment of the present invention.
【図３】 実施の形態１のリミッタをＡＧＣに置き換え
た他の形態の復調装置の構成を示す図である。FIG. 3 is a diagram showing a configuration of a demodulator of another form in which the limiter of the first embodiment is replaced with an AGC.
【図４】 実施の形態２のリミッタをＡＧＣに置き換え
た他の形態の復調装置の構成を示す図である。FIG. 4 is a diagram showing a configuration of a demodulation device of another form in which the limiter of the second embodiment is replaced with an AGC.
【図５】 従来の復調装置の構成を示す図である。FIG. 5 is a diagram showing a configuration of a conventional demodulation device.
１ 従来例における第１局所発振器 ２ 乗算器 ３ 従来例におけるバンドパスフィルタ ４ リミッタ ５ ローパスフィルタ ６ 第２局所発振器 ７ ＡＤ変換器 ８ 直交検波部 ９ 位相検出部 １０ 遅延検波部 １１ 減算器 １２ 積分器 １３ 従来のＡＦＣ部 １４ ＢＴＲ部 １５ 本発明で用いる第１局所発振器 １６ 本発明で用いるバンドパスフィルタ １７ 加算器 １８ 本発明における改良ＡＦＣ部 １９ ＡＧＣ 1 First local oscillator in conventional example 2 multiplier 3 Bandpass filter in conventional example 4 limiter 5 Low pass filter 6 Second local oscillator 7 AD converter 8 Quadrature detector 9 Phase detector 10 Delay detection section 11 Subtractor 12 Integrator 13 Conventional AFC unit 14 BTR section 15 First local oscillator used in the present invention 16 Bandpass filter used in the present invention 17 adder 18 Improved AFC unit in the present invention 19 AGC
Claims (3)
を出力する局所発振器と、受信電波を局所発振器の出力
に基いて中間周波数信号にダウンコンバートさせる乗算
器と、前記乗算器の出力信号をディジタル信号に変換す
るＡＤ変換器と、前記ＡＤ変換器の出力と前記固定周波
数分のオフセットに基いて、周波数オフセット補正を行
う制御器とを備えた復調装置。1. A local oscillator that outputs an oscillation signal offset by a fixed frequency, a multiplier that down-converts a received radio wave into an intermediate frequency signal based on the output of the local oscillator, and an output signal of the multiplier is a digital signal. A demodulation device comprising: an AD converter for converting into a signal, and a controller for performing frequency offset correction based on the output of the AD converter and the offset of the fixed frequency.
を出力する第１の局所発振器と、受信電波を第１の局所
発振器の出力に基いて中間周波数信号にダウンコンバー
トさせる乗算器と、前記乗算器より出力される中間周波
数信号の不要周波数成分または高調波成分を除去するフ
ィルタと、第２の局所発振器と、前記高調波成分が除去
された出力信号を前記第２の局所発振器に基いてサンプ
リングし、ディジタル信号に変換するＡＤ変換器と、前
記ＡＤ変換器の出力を直交検波する直交検波部と、前記
直交検波出力の位相を検出する位相検出部と、前記位相
検出部より出力される位相検出データより遅延検波を行
う遅延検波部と、前記遅延検波部の出力の積分値に前記
固定周波数分のオフセットを加算し、前記遅延検波部の
出力から当該加算値の位相誤差を減算して周波数オフセ
ット補正を行うＡＦＣ部と、前記ＡＦＣ部の出力信号か
ら受信データと再生クロックを出力するＢＴＲ部とを備
えた復調装置。2. A first local oscillator that outputs an oscillation signal offset by a fixed frequency, a multiplier that down-converts a received radio wave into an intermediate frequency signal based on the output of the first local oscillator, and the multiplier. A filter for removing an unnecessary frequency component or a harmonic component of the intermediate frequency signal output from the second local oscillator, and a second local oscillator, and the output signal from which the harmonic component is removed, is sampled based on the second local oscillator. An AD converter for converting into a digital signal, a quadrature detection section for quadrature detection of the output of the AD converter, a phase detection section for detecting the phase of the quadrature detection output, and a phase detection output from the phase detection section A delay detection unit that performs delay detection from data, and an offset of the fixed frequency is added to the integrated value of the output of the delay detection unit, and the added value is output from the output of the delay detection unit. A demodulation device including an AFC unit that performs frequency offset correction by subtracting the phase error of the above, and a BTR unit that outputs received data and a recovered clock from an output signal of the AFC unit.
を出力する第１の局所発振器と、受信電波を第１の局所
発振器の出力に基いて中間周波数信号にダウンコンバー
トさせる乗算器と、前記乗算器より出力される中間周波
数信号の不要周波数成分または高調波成分を除去するフ
ィルタと、第２の局所発振器と、前記高調波成分が除去
された出力信号を前記第２の局所発振器に基いてサンプ
リングし、ディジタル信号に変換するＡＤ変換器と、前
記ＡＤ変換器の出力を直交検波する直交検波部と、前記
直交検波出力の位相を検出する位相検出部と、前記位相
検出部より出力される位相検出データより遅延検波を行
う遅延検波部と、前記遅延検波部の出力に前記固定周波
数分のオフセットを加算する加算器と、前記加算器の出
力から当該加算器の積分値の位相誤差を減算して周波数
オフセット補正を行うＡＦＣ部と、前記ＡＦＣ部の出力
信号から受信データと再生クロックを出力するＢＴＲ部
とを備えた復調装置。3. A first local oscillator that outputs an oscillation signal offset by a fixed frequency, a multiplier that down-converts a received radio wave into an intermediate frequency signal based on the output of the first local oscillator, and the multiplier. A filter for removing an unnecessary frequency component or a harmonic component of the intermediate frequency signal output from the second local oscillator, and a second local oscillator, and the output signal from which the harmonic component is removed, is sampled based on the second local oscillator. An AD converter for converting into a digital signal, a quadrature detection section for quadrature detection of the output of the AD converter, a phase detection section for detecting the phase of the quadrature detection output, and a phase detection output from the phase detection section A delay detection unit that performs delay detection from data, an adder that adds the offset of the fixed frequency to the output of the delay detection unit, and an output of the adder A demodulator provided with an AFC unit for subtracting a phase error of an integrated value to correct a frequency offset, and a BTR unit for outputting received data and a reproduced clock from an output signal of the AFC unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001306006A JP3818112B2 (en) | 2001-10-02 | 2001-10-02 | Demodulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001306006A JP3818112B2 (en) | 2001-10-02 | 2001-10-02 | Demodulator |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2003110641A true JP2003110641A (en) | 2003-04-11 |
| JP2003110641A5 JP2003110641A5 (en) | 2005-06-09 |
| JP3818112B2 JP3818112B2 (en) | 2006-09-06 |
Family
ID=19125711
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001306006A Expired - Lifetime JP3818112B2 (en) | 2001-10-02 | 2001-10-02 | Demodulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3818112B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009055279A (en) * | 2007-08-27 | 2009-03-12 | Iwatsu Electric Co Ltd | Automatic frequency control method and apparatus |
-
2001
- 2001-10-02 JP JP2001306006A patent/JP3818112B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009055279A (en) * | 2007-08-27 | 2009-03-12 | Iwatsu Electric Co Ltd | Automatic frequency control method and apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3818112B2 (en) | 2006-09-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4366808B2 (en) | Timing error detection circuit, demodulation circuit and method thereof | |
| US20050259768A1 (en) | Digital receiver and method for processing received signals | |
| US5757864A (en) | Receiver with filters offset correction | |
| US20070140382A1 (en) | Bandpass sampling receiver and the sampling method | |
| JPH08149166A (en) | Radio communication equipment | |
| JP3077881B2 (en) | Demodulation method and demodulation device | |
| US6731698B1 (en) | Quadrature demodulation circuit capable for canceling offset | |
| US6868129B2 (en) | Demodulator for a radio receiver and method of operation | |
| KR20010063060A (en) | Vsb receiver | |
| WO2005055449A1 (en) | Bandpass sampling receiver and the sampling method | |
| JPH09224059A (en) | Direct conversion fsk receiver | |
| KR100505669B1 (en) | Demodulator circuit of digital television and method thereof | |
| JP2003110641A (en) | Demodulator | |
| JPH0779363B2 (en) | Delay detection circuit | |
| JP2005516514A (en) | Method for detecting an additional DC component contained in an input burst signal | |
| JPH05211535A (en) | Afc circuit for demodulator | |
| JP4722673B2 (en) | FSK demodulation circuit | |
| JP2795761B2 (en) | MSK signal demodulation circuit | |
| JP2001257733A (en) | Carrier recovery apparatus and its method and receiver | |
| JP4637661B2 (en) | Modulation signal demodulator | |
| JP2003110641A5 (en) | ||
| KR0159440B1 (en) | A circuit and method for restorating frequency offset of receiver | |
| JP2007189654A (en) | Afc circuit | |
| JP3366286B2 (en) | Digital receiver | |
| JP3265052B2 (en) | Digital modulation wave demodulator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| RD01 | Notification of change of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7421 Effective date: 20040706 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20040827 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20040827 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20060517 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20060523 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20060605 |
|
| R151 | Written notification of patent or utility model registration |
Ref document number: 3818112 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100623 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100623 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110623 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120623 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130623 Year of fee payment: 7 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |