JP2003110061A - Electronic component for flip-chip packaging and manufacturing method thereof, circuit plate and manufacturing method thereof, and manufacturing method of packaging body - Google Patents

Electronic component for flip-chip packaging and manufacturing method thereof, circuit plate and manufacturing method thereof, and manufacturing method of packaging body

Info

Publication number
JP2003110061A
JP2003110061A JP2001301399A JP2001301399A JP2003110061A JP 2003110061 A JP2003110061 A JP 2003110061A JP 2001301399 A JP2001301399 A JP 2001301399A JP 2001301399 A JP2001301399 A JP 2001301399A JP 2003110061 A JP2003110061 A JP 2003110061A
Authority
JP
Japan
Prior art keywords
conductor
electronic component
circuit board
mounting
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001301399A
Other languages
Japanese (ja)
Inventor
利治 ▼高▲山
Toshiji Takayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
K Tech Devices Corp
Original Assignee
K Tech Devices Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by K Tech Devices Corp filed Critical K Tech Devices Corp
Priority to JP2001301399A priority Critical patent/JP2003110061A/en
Publication of JP2003110061A publication Critical patent/JP2003110061A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To achieve flip-chip packaging that can reduce the distance between bumps 7 in a manufacturing method of an electronic component for flip-chip packaging where a plurality of terminals 3 are interspersed on a packaging surface and a conductor is formed on the terminal 3. SOLUTION: A process for covering the packaging surface with a conductor with a specific thickness, a process for masking the terminal 3 and a conductor surface that is set to be the corresponding position, and a process for removing the conductor other than a mask 6 concerned for treatment. The processes are executed successively. Preferably, a bump is made of copper.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明はフリップチップ実装
用電子部品及びその製造法、回路板及びその製造法、実
装体の製造法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component for flip chip mounting, a method for manufacturing the same, a circuit board, a method for manufacturing the same, and a method for manufacturing a mounting body.

【０００２】[0002]

【従来の技術】近年の電子機器の小型化に伴って電子部
品の高密度実装化が求められており、その求めに応じる
技術の一つとしてフリップチップ実装技術がある。フリ
ップチップ実装用電子部品は、実装される側の面に複数
のはんだバンプが点在しており、その電子部品は、実装
時に当該はんだバンプが溶融して回路板のランドと固着
される。2. Description of the Related Art With the recent miniaturization of electronic equipment, there is a demand for high-density mounting of electronic components, and one of the technologies that meet the demand is flip-chip mounting technology. The flip-chip mounting electronic component has a plurality of solder bumps scattered on the surface on the mounting side, and the electronic bump is fixed to the land of the circuit board by melting the solder bump during mounting.

【０００３】前記はんだバンプの電子部品への形成に
は、はんだボールをフリップチップ実装用電子部品の実
装面の必要箇所に配置し、リフロー工程等を経るのが一
般的である。In order to form the solder bumps on the electronic component, it is general that a solder ball is arranged at a required position on the mounting surface of the electronic component for flip chip mounting, and a reflow process or the like is performed.

【０００４】[0004]

【発明が解決しようとする課題】上記高密度実装化が更
に進行すると、次に求められるのは個々のはんだバンプ
間距離を小さくすることによるフリップチップ実装用電
子部品の小型化であると考えられる。そこで本発明が解
決しようとする課題は、バンプ間距離を小さくしたフリ
ップチップ実装を実現することである。As the high-density mounting progresses further, it is considered that the next demand is to downsize the electronic component for flip-chip mounting by reducing the distance between individual solder bumps. . Therefore, the problem to be solved by the present invention is to realize flip-chip mounting with a reduced distance between bumps.

【０００５】[0005]

【課題を解決するための手段】上記課題を解決するた
め、本発明のフリップチップ実装用電子部品の製造法
は、実装面に複数の端子３が点在し、当該端子３上に導
体が形成されたフリップチップ実装用電子部品の製造法
において、前記実装面を所定厚みの導体で被覆する工程
と、前記端子３部と対応位置となる導体表面をマスクす
る工程と、当該マスク６部以外の導体を除去処理する工
程とを有し、これら工程をこの順に実施することを特徴
とする。In order to solve the above problems, in the method of manufacturing an electronic component for flip-chip mounting of the present invention, a plurality of terminals 3 are scattered on the mounting surface, and conductors are formed on the terminals 3. In the method for manufacturing an electronic component for flip chip mounting described above, a step of covering the mounting surface with a conductor having a predetermined thickness, a step of masking a conductor surface corresponding to the terminal 3 part, and a step other than the mask 6 part And a step of removing the conductor, and these steps are performed in this order.

【０００６】上記実装面を所定厚みの導体で被覆する工
程とは、例えば無電解めっき工程及び電解めっき工程で
ある。例えば図１（ａ）に示す印刷回路板８絶縁部表面
上及び端子３上に銅からなる無電解めっき層４を形成し
（図１（ｂ））、その後更に銅からなる電解めっき層５
を形成する（図１（ｃ））。また上記端子３部と対応位
置となる導体表面をマスクする工程とは、例えば導体で
ある銅からなる電解めっき層５表面であって、端子３と
対応する位置に例えばスクリーン印刷技術等によりマス
ク６を形成する工程である（図１（ｄ））。またマスク
６が配された導体部以外の導体部を除去処理する工程
は、例えばソフトエッチング処理による。するとマスク
６で覆われた以外の前記電解めっき層５及び無電解めっ
き層４が除去される（図１（ｅ））。その後に必要に応
じてマスク６を除去する（図１（ｆ））。前記ソフトエ
ッチング時にゆっくりと溶解する材質からなるマスク６
や、マスク６が残存していても実装時に良好な実装状態
を維持できるのであれば当該除去処理は不要となる。除
去処理法の例としては、酸やアルカリによる処理や剥離
処理、研削処理等である。例えば上記スクリーン印刷の
手法により形成された感光性のインクをマスク６の材質
とした場合、アルカリ性の薬品等により除去される。The step of covering the mounting surface with a conductor having a predetermined thickness is, for example, an electroless plating step or an electrolytic plating step. For example, an electroless plating layer 4 made of copper is formed on the surface of the insulating portion of the printed circuit board 8 and the terminals 3 shown in FIG. 1A (FIG. 1B), and then an electrolytic plating layer 5 made of copper is further formed.
Are formed (FIG. 1C). The step of masking the surface of the conductor corresponding to the terminal 3 portion is, for example, the surface of the electrolytic plating layer 5 made of copper which is a conductor, and the mask 6 is formed at a position corresponding to the terminal 3 by, for example, a screen printing technique. Is a step of forming (FIG. 1D). The step of removing the conductor portion other than the conductor portion on which the mask 6 is arranged is, for example, a soft etching treatment. Then, the electrolytic plating layer 5 and the electroless plating layer 4 other than those covered with the mask 6 are removed (FIG. 1E). After that, the mask 6 is removed as necessary (FIG. 1F). Mask 6 made of a material that slowly dissolves during the soft etching
Alternatively, even if the mask 6 remains, if the good mounting state can be maintained at the time of mounting, the removing process is unnecessary. Examples of the removal treatment method include treatment with acid or alkali, peeling treatment, and grinding treatment. For example, when the photosensitive ink formed by the screen printing method is used as the material of the mask 6, it is removed by an alkaline chemical or the like.

【０００７】以上の図１（ａ）〜（ｆ）に示した工程を
この順に実施すると、導体（銅）であるバンプ７が形成
される。当該工程では、従来に比して非常にバンプ７間
距離を狭くすることができることが明らかである。その
理由は図１（ａ）〜（ｆ）に示した工程は、印刷回路板
のパターニング工程における技術に類似した技術を用い
ているためである。印刷回路板のパターニング技術で
は、いわゆるファインピッチのパターニングが可能であ
り、約０．０５ｍ間隔でのバンプ７形成を可能とする。
これははんだボールを固着させる従来のバンプ形成にお
ける通常のバンプ間最短距離（０．２５〜０．７５ｍ
ｍ）よりも狭い。且つバンプ径が従来０．３〜１．０ｍ
ｍであるところ、本発明により約０．１ｍｍ程度にする
ことが可能となる。従って本発明が解決しようとする課
題であるところの、バンプ７間距離を小さくしたフリッ
プチップ実装が可能となる。またそれによりフリップチ
ップ実装用電子部品の小型化が可能となる。When the steps shown in FIGS. 1A to 1F are carried out in this order, the bumps 7 which are conductors (copper) are formed. It is clear that in this step, the distance between the bumps 7 can be made extremely narrower than in the conventional case. The reason is that the process shown in FIGS. 1A to 1F uses a technique similar to the technique in the patterning process of the printed circuit board. The printed circuit board patterning technique enables so-called fine pitch patterning, and enables formation of the bumps 7 at intervals of about 0.05 m.
This is the shortest distance between normal bumps (0.25 to 0.75 m) in the conventional bump formation for fixing solder balls.
narrower than m). Moreover, the bump diameter is 0.3-1.0m.
However, according to the present invention, it can be about 0.1 mm. Therefore, flip-chip mounting with a small distance between the bumps 7 is possible, which is a problem to be solved by the present invention. Further, it is possible to downsize the electronic component for flip chip mounting.

【０００８】また上記図１（ａ）〜（ｆ）に示した工程
を経て得られたバンプ７は、その先端が略平面となる。
そのため、例えばはんだを用いた実装工程全後に亘りそ
の形状変化をしない材質のバンプ７（例えば銅製）を用
いた場合には、溶融したはんだとバンプ７先端面及びそ
の周辺の側面との接触面積が従来の球形バンプ７を用い
る場合よりも大きくなり、溶融したはんだの表面張力を
大きく受けることから、いわゆるセルフアライメント性
が向上する。また、はんだからなるバンプ７を用いた場
合には、それが溶融・固化する際のバンプ７の形状変化
を極力抑えることができる。これに対し従来のはんだボ
ールを使用すると、その実装時の溶融・固化の過程にお
いて大きな形状変化を伴わざるを得ない。その理由は、
その回路板（厳密に言うとランド）と接触するはんだボ
ールの面が当初球面状であり、その後の前記溶融・固化
の過程で回路板と接触するはんだボール面が平面となる
からである。このような実装時のはんだの形状変化量の
大小によっては、隣合うバンプの前記溶融状態での形状
変化時に両者が接触・一体化した状態で固化するおそれ
がある。いわゆるはんだブリッジに類似した現象の発生
である。その点実装時のはんだの形状変化を小さく抑え
ることができれば、はんだバンプの溶融・固化の過程で
の隣合うはんだバンプとの接触を抑えることができる。
これらのことから、バンプ７が銅などのはんだ以外の材
質であっても、はんだからなるバンプ７であっても、そ
の先端が実質的に平面であることが好ましい。The bump 7 obtained through the steps shown in FIGS. 1A to 1F has a substantially flat tip.
Therefore, for example, when the bump 7 (for example, made of copper) made of a material that does not change its shape after the entire mounting process using solder is used, the contact area between the molten solder and the tip surface of the bump 7 and the side surface around the bump 7 is small. It becomes larger than when the conventional spherical bumps 7 are used, and the surface tension of the molten solder is largely received, so that the so-called self-alignment property is improved. Further, when the bumps 7 made of solder are used, it is possible to suppress the shape change of the bumps 7 when the bumps 7 are melted and solidified. On the other hand, when the conventional solder balls are used, there is no choice but to undergo a large change in shape during the process of melting and solidifying during mounting. The reason is,
This is because the surface of the solder ball that comes into contact with the circuit board (strictly speaking, the land) is initially spherical, and the surface of the solder ball that comes into contact with the circuit board becomes a flat surface during the subsequent melting and solidification process. Depending on the amount of change in the shape of the solder at the time of mounting, there is a possibility that the adjacent bumps may solidify in a contacted / integrated state when the shape of the adjacent bump changes in the molten state. This is a phenomenon similar to a so-called solder bridge. In that respect, if it is possible to suppress the change in the shape of the solder during mounting, it is possible to suppress the contact with the adjacent solder bump during the process of melting and solidifying the solder bump.
From these facts, it is preferable that the tips of the bumps 7 are substantially flat, even if the bumps 7 are made of a material other than solder such as copper or the bumps 7 are made of solder.

【０００９】また上記図１（ａ）〜（ｆ）に示した工程
を経ることにより、実装面に複数の端子が点在し、当該
端子上に形成された導体を有するフリップチップ実装用
電子部品であって、前記導体が成長形成及び除去処理の
残部として形成されてなり、且つ前記端子とその上の導
体高さの和が全てに亘り実質的に等しく、当該導体部先
端が実質的な平面であることを特徴とする本発明のフリ
ップチップ実装用電子部品を得ることができる。Further, through the steps shown in FIGS. 1 (a) to 1 (f), a flip chip mounting electronic component having a plurality of terminals scattered on the mounting surface and having conductors formed on the terminals is formed. The conductor is formed as the remainder of the growth formation and removal process, and the sum of the height of the terminal and the conductor above it is substantially the same, and the tip of the conductor is a substantially flat surface. It is possible to obtain the electronic component for flip-chip mounting according to the present invention.

【００１０】また上記図１（ａ）〜（ｆ）に示した工程
を経ることにより、実装面に複数のフリップチップ実装
用ランドが点在し、当該端子上に形成された導体を有す
る回路板であって、前記導体が成長形成及び除去処理の
残部として形成されてなり、且つ前記ランド高さとその
上の導体高さの和が全てに亘り実質的に等しく、当該導
体部先端が実質的な平面であることを特徴とする本発明
の回路板を得ることができる。Further, through the steps shown in FIGS. 1A to 1F, a circuit board having a plurality of flip chip mounting lands scattered on the mounting surface and having conductors formed on the terminals is formed. The conductor is formed as the remainder of the growth formation and removal process, and the sum of the land height and the conductor height above it is substantially the same, and the tip of the conductor portion is substantially the same. It is possible to obtain the circuit board of the present invention which is a flat surface.

【００１１】また上記本発明に係るバンプ７は、実装の
際にバンプ７を溶融・固化させずに異方性導電物質を介
して回路板と電気接続させることもできる。当該異方性
導電物質は、ペースト状であって、後に固化させること
が可能なものが好ましい。固着機能をも併有しており、
且つはんだのように固体を加熱溶融しなければ流動しな
いという取扱い性の悪さを有していないからである。異
方性導電物質の使用による実装では、はんだを使用する
実装に比べて隣合うバンプ７間距離を小さくすることが
できる。隣合うバンプ７同士が導通される蓋然性がある
部材（例えば従来のはんだ）がないためである。その場
合本発明にかかるバンプ７形成法は特に好ましいといえ
る。その理由は前述の通りファインピッチパターニング
技術で作製されるためであり、隣合うバンプ７間距離を
現状の印刷回路板パターン間隔と同等レベルまで小さく
することが可能だからである。この場合のバンプ７材質
は、例えば銅が好ましい。導電率が高く、且つ安価で入
手が容易だからである。The bump 7 according to the present invention can be electrically connected to a circuit board through an anisotropic conductive material without melting and solidifying the bump 7 during mounting. The anisotropic conductive material is preferably paste-like and capable of being solidified later. It also has a fixing function,
In addition, it does not have the poor handleability that does not flow unless the solid is heated and melted like solder. In the mounting using the anisotropic conductive material, the distance between the adjacent bumps 7 can be reduced as compared with the mounting using the solder. This is because there is no member (for example, conventional solder) having a probability that adjacent bumps 7 are electrically connected to each other. In that case, it can be said that the bump 7 forming method according to the present invention is particularly preferable. The reason is that it is produced by the fine pitch patterning technique as described above, and it is possible to reduce the distance between the adjacent bumps 7 to the same level as the current printed circuit board pattern spacing. In this case, the material of the bumps 7 is preferably copper, for example. This is because they have high conductivity, are inexpensive, and are easily available.

【００１２】また、上記本発明にかかる複数のバンプ７
の高さ（図１（ｆ）においては、端子３と電解めっき層
５との和）は、全て実質的に等しいことが好ましい。そ
の理由は、全てのバンプ７が回路板と同様の接触状態を
形成しつつ実装することにより、全ての電気接続箇所に
おいて均一・確実な電気接続状態を得ることができるた
めである。また上記のように、異方性導電物質を用いて
本発明の実装体を構成する場合には、特にバンプ７の高
さを実質的に等しくすることが重要となる。その理由
は、バンプ７により圧縮される異方性導電物質の当該圧
縮状態が、それぞれのバンプ７により異なることは、そ
れぞれのバンプ７における電気接続状態に直接的にばら
つきを生じさせるためである。上記本発明にかかる電解
めっき層５形成工程では、印刷回路板８及び端子３の全
面に電解めっきを施すこととなる。下地の印刷回路板８
及び端子３の表面状態が極端に均一でない場合を除き、
電解めっき層５の高さが全て実質的に等しくなる。また
端子３厚みは電気めっき工程へ殆ど影響せず無視できる
程度であるし、最終的に不要部分が除去され、バンプ７
が残存する時点では、当該影響部分は既に除去されてい
るため、本発明にかかる複数のバンプ７の高さは全て実
質的に等しくなる。Further, the plurality of bumps 7 according to the present invention described above.
It is preferable that all the heights (in FIG. 1 (f), the sum of the terminal 3 and the electrolytic plating layer 5) are substantially equal. The reason is that by mounting all the bumps 7 while forming a contact state similar to that of the circuit board, a uniform and reliable electric connection state can be obtained at all electric connection points. Further, as described above, particularly when the mounting body of the present invention is formed by using the anisotropic conductive material, it is important that the heights of the bumps 7 are substantially equal. The reason for this is that the difference in the compressed state of the anisotropic conductive material compressed by the bumps 7 varies depending on the bumps 7, which directly causes variations in the electrical connection state of the bumps 7. In the step of forming the electroplated layer 5 according to the present invention, electroplating is performed on the entire surfaces of the printed circuit board 8 and the terminals 3. Base printed circuit board 8
And unless the surface condition of the terminal 3 is extremely uneven,
The heights of the electroplated layers 5 are all substantially the same. Further, the thickness of the terminal 3 has a negligible effect on the electroplating process and can be neglected.
Since the affected portion has already been removed at the time when is left, the heights of the plurality of bumps 7 according to the present invention are all substantially the same.

【００１３】またバンプ７の形状は、その先端側が細く
なる円錐台形又は角錐台形であることが好ましい。その
理由は、全体的なバンプ７強度をその基底部（先端とは
逆側）で維持しつつ、バンプ７先端における隣合うバン
プ７間距離を大きくすることができるためである。その
ことはバンプ７間の導通の防止に更に寄与する。また、
バンプ７形成に際して上記マスク６をスクリーン印刷等
で形成する際に、その位置ずれをある程度許容できる。The shape of the bump 7 is preferably a truncated cone shape or a truncated pyramid shape whose tip side is narrow. The reason is that the distance between adjacent bumps 7 at the tips of the bumps 7 can be increased while maintaining the overall strength of the bumps 7 at the base portion (on the side opposite to the tip). This further contributes to prevention of conduction between the bumps 7. Also,
When forming the bumps 7 when the mask 6 is formed by screen printing or the like, the positional deviation can be allowed to some extent.

【００１４】また、バンプ７先端と、その被接続部とを
熱圧着法にて固着させる場合には、前記バンプ形成（円
錐台形又は角錐台形）が特に好ましい。ここで熱圧着法
とは、加熱状態で加圧することで両者を固着する方法
や、加熱状態で更に加圧し、加えて超音波等で振動を与
えることで両者を固着する方法をいう。かかる熱圧着法
において、前記バンプ形状とすることで、バンプ先端に
は圧力が集中しやすくなり、且つその基底部が幅広とな
っているために、逆に当該圧力が分散されている。かか
る基底部は、バンプ７とその支持部との固着強度が熱圧
着法では特に求められる。このようにバンプ７の基底部
及び先端に求められる事項をそれぞれ具備することとな
るため、当該円錐台形又は角錐台形は熱圧着法に適した
バンプ７の形状であるといえる。当該熱圧着法の採用の
際には、少なくともバンプ７先端部表面には比較的容易
に溶融し、その後即座に硬化する材料が配されているこ
とが好ましい。当該材料は例えばはんだや金などであ
る。Further, when the tips of the bumps 7 and their connected portions are fixed by thermocompression bonding, the bump formation (frustroconical shape or truncated pyramid shape) is particularly preferable. Here, the thermocompression bonding method refers to a method of fixing both by pressing in a heated state, or a method of further pressing in a heated state and additionally applying vibration by ultrasonic waves or the like to fix both. In such a thermocompression bonding method, by forming the bump shape, the pressure is likely to concentrate at the tip of the bump, and the base portion is wide, so that the pressure is dispersed on the contrary. In the base portion, the bonding strength between the bump 7 and its supporting portion is particularly required by the thermocompression bonding method. As described above, since the base portion and the tip end of the bump 7 are provided respectively, the truncated cone shape or the truncated pyramid shape can be said to be the shape of the bump 7 suitable for the thermocompression bonding method. When adopting the thermocompression bonding method, it is preferable that at least the surface of the tip end portion of the bump 7 is provided with a material that melts relatively easily and then hardens immediately. The material is, for example, solder or gold.

【００１５】前記電解めっき層５の形成は、成長形成の
一種である。その他の成長形成の具体例は、ＣＶＤ、ス
パッタリング、噴霧熱分解法等があるが、これらの中で
はめっき法が形成速度や効率、それらに伴う低コスト化
等の点で他に比して優れており好ましい。その中でも電
解めっき法が特に成長速度が速く好ましい。また成長形
成に代えて除去処理の残部としてバンプ７を形成するこ
とも可能である。例えば箔状の導電性物質を印刷回路板
８に貼付し、その後不必要部分をエッチング処理等で除
去する等である。図１に示したパンプ７の形成は、電解
めっきによる成長形成及びソフトエッチング等による除
去処理の双方によってなされている。電気めっき等の成
長形成によって得られた形成物（バンプ７）は、一般に
その基材（印刷回路版８の端子３）表面と強固に固着し
ており、その取扱い性に優れる利点がある。また従来の
はんだボールの使用の場合のように、当初別部材だった
物を固着させるなどという煩雑な工程を要しない利点も
ある。The formation of the electrolytic plating layer 5 is a kind of growth formation. Other specific examples of growth formation include CVD, sputtering, spray pyrolysis, etc. Among these, the plating method is superior to others in terms of formation speed and efficiency, and associated cost reduction. Is preferable. Among them, the electrolytic plating method is preferable because of its high growth rate. It is also possible to form the bumps 7 as the rest of the removal process instead of the growth formation. For example, a foil-shaped conductive material is attached to the printed circuit board 8 and then unnecessary portions are removed by etching or the like. The formation of the pump 7 shown in FIG. 1 is performed by both growth formation by electrolytic plating and removal treatment by soft etching or the like. The formed product (bump 7) obtained by growth formation such as electroplating is generally firmly fixed to the surface of the base material (terminal 3 of the printed circuit board 8) and has an advantage of being easy to handle. Further, there is an advantage that a complicated process such as fixing an object which is originally a separate member is not required unlike the case of using a conventional solder ball.

【００１６】上記バンプ７は、電子部品側に形成しても
よいし、電子部品が搭載される回路板に形成してもよい
し、また電子部品及び回路板の双方に形成してもよい。
またバンプ７の材質は銅以外、例えばはんだとしてもよ
い。その場合において、フリップチップ実装体を構成す
る際の固着用材料として、当該はんだを用いることがで
きる。この点は従来のはんだボールの使用の際と同様で
ある。またその場合において、実装時には回路板と電子
部品との電気接続の更なる確実化、接続強度の向上を図
るため、クリームはんだを補助接続部材として用いても
よい。The bumps 7 may be formed on the electronic component side, on the circuit board on which the electronic component is mounted, or on both the electronic component and the circuit board.
The material of the bumps 7 may be solder, for example, other than copper. In that case, the solder can be used as a fixing material when forming the flip chip mounting body. This point is the same as when using a conventional solder ball. Further, in this case, cream solder may be used as an auxiliary connecting member in order to further secure the electric connection between the circuit board and the electronic component and improve the connection strength during mounting.

【００１７】また、バンプ７が主としてはんだ以外の材
質（例えば銅）からなり、且つ当該バンプ７と、その被
接続部が、はんだの溶融・固化による場合には、当該バ
ンプ表面には、いわゆるはんだくわれを防止する層が形
成されることが好ましい。極力バンプ形状を維持して、
実装状態の安定化を図りたい場合を考慮したものであ
る。このような実装状態の安定化は、特に小型部品の実
装の際に求められる。かかる層の代表例はニッケル層で
ある。このようなはんだと合金化しにくい金属をバンプ
７の主構成材料とするときには、かかるはんだくわれを
防止する層は不要である。はんだくわれされ易い金属と
しては、銀、銅、金が代表例として挙げられる。但し、
以上に述べたことは、はんだが錫を含んでいる場合であ
る。錫を含まないはんだを用いる場合には、そのはんだ
成分に適したはんだくわれ防止層材質を選択する。When the bumps 7 are mainly made of a material other than solder (for example, copper) and the bumps 7 and their connected parts are formed by melting and solidifying the solder, so-called solder is formed on the surface of the bumps. It is preferred that a layer that prevents kinking is formed. Maintain the bump shape as much as possible,
This is in consideration of the case where it is desired to stabilize the mounting state. Such stabilization of the mounting state is required especially when mounting small components. A typical example of such a layer is a nickel layer. When such a metal that is difficult to alloy with solder is used as the main constituent material of the bump 7, a layer for preventing such solder shaving is unnecessary. Representative examples of the metal that is easily soldered include silver, copper, and gold. However,
What has been described above is the case where the solder contains tin. When using a solder that does not contain tin, select a material for the solder curl prevention layer that is suitable for the solder component.

【００１８】また、かかるはんだくわれ防止層の上に
は、はんだとの親和性の良好な層が形成されることが更
に好ましい。かかる層は、当該はんだと同成分のはん
だ、金、銀、銅等である。即ち、はんだと合金化しやす
い金属層である。この層の存在により、はんだとの固着
が強固なものとなるためである。Further, it is more preferable that a layer having a good affinity for solder is formed on the solder anti-corrosion layer. Such a layer is a solder having the same composition as the solder, gold, silver, copper or the like. That is, it is a metal layer that is easily alloyed with solder. This is because the presence of this layer strengthens the fixation with the solder.

【００１９】これらのはんだくわれ防止層とはんだとの
親和性の良好な層は、電解めっきの手法により形成され
るのが好ましい。かかる手法によれば、各金属層の接合
面は非常に緻密な当該各金属層の元素からなる合金層が
形成されるとされており、各層の親和性は非常に優れた
ものとなる。但し、製造の容易さの点からは、無電解め
っきによるのが好ましい。電解めっきに要する各種配線
を要しないためである。ここでの無電解めっき液に要求
される析出反応機構は、被めっき材表面における極部電
池反応により析出が進行することである。このことによ
り、バンプ間の絶縁領域への析出を防ぐことができ、短
絡が発生しない。It is preferable that these layers having a good affinity for the solder shaving prevention layer and the solder are formed by an electrolytic plating method. According to such a method, it is said that a very dense alloy layer made of the element of each metal layer is formed on the bonding surface of each metal layer, and the affinity of each layer is very excellent. However, from the viewpoint of ease of production, electroless plating is preferable. This is because various wiring required for electrolytic plating is not required. The deposition reaction mechanism required for the electroless plating solution here is that the deposition progresses due to the electrode cell reaction on the surface of the material to be plated. As a result, it is possible to prevent deposition between the bumps on the insulating region, and a short circuit does not occur.

【００２０】本発明にかかるバンプを有するフリップチ
ップ実装用電子部品は、高密度実装される実装体を用い
る小型電子機器に好適に用いられることは言うまでもな
い。またＩＣカード等の、多くの場合そのフリップチッ
プ実装用電子部品単体が用いられる機器にもその小型化
の特長を生かして好適に使用することができる。It goes without saying that the flip-chip mounting electronic component having bumps according to the present invention is preferably used for a small electronic device using a mounting body to be mounted at high density. Further, in many cases, it can be suitably used for a device such as an IC card in which a single electronic component for flip-chip mounting is used by taking advantage of its miniaturization.

【００２１】[0021]

【発明の実施の形態】（実施の形態１）まずガラス繊維
が混入したエポキシ樹脂成形体としての板を積層した印
刷回路板８を用意する。当該印刷回路板８は、後述する
電子部品９から導出される多数の端子が一方の面から他
方の面にそれぞれ独立した導電経路が内層を経由して形
成され、当該他方の面には当該多数の端子と対応する多
数のランドが略全面に、互いに絶縁を維持しながら点在
している（図３（ａ）（ｄ））。当該ランドを起点とし
て銅からなるバンプ７を成長形成させる方法を以下に述
べる。DESCRIPTION OF THE PREFERRED EMBODIMENTS (Embodiment 1) First, a printed circuit board 8 is prepared in which boards, which are epoxy resin moldings mixed with glass fibers, are laminated. The printed circuit board 8 has a large number of terminals derived from an electronic component 9 described later, in which independent conductive paths are formed from one surface to the other surface via an inner layer, and the plurality of terminals are formed on the other surface. A large number of lands corresponding to the terminals are scattered over substantially the entire surface while maintaining insulation from each other (FIGS. 3A and 3D). A method for growing and forming the bump 7 made of copper from the land as a starting point will be described below.

【００２２】まず図１（ａ）に示すように印刷回路板８
の絶縁部及び端子３上に銅からなる無電解めっき層４を
形成する（図１（ｂ））。無電解めっきの方法はいわゆ
る非触媒化学めっきであり、銅が溶解しためっき液に、
被めっき材料（印刷回路板８）を浸漬する方法である。
その際のめっき液組成は、銅イオン源、アルカリ源、還
元剤、及びキレート剤等を含むものである。これらは市
販のものを用いることができる。このめっきにより、前
記ランド及び隣合うランド間の絶縁領域にも銅が形成さ
れる。またこのめっき厚は約０．２μｍである。なお、
この無電解めっきに先立って、パラジウム等のめっき触
媒を沈着させてもよい。First, as shown in FIG. 1A, the printed circuit board 8 is formed.
The electroless plating layer 4 made of copper is formed on the insulating portion and the terminal 3 (FIG. 1B). The method of electroless plating is so-called non-catalytic chemical plating, in a plating solution in which copper is dissolved,
In this method, the material to be plated (printed circuit board 8) is immersed.
The plating solution composition at that time contains a copper ion source, an alkali source, a reducing agent, a chelating agent, and the like. These may be commercially available products. By this plating, copper is also formed in the insulating region between the land and the adjacent land. The plating thickness is about 0.2 μm. In addition,
Prior to this electroless plating, a plating catalyst such as palladium may be deposited.

【００２３】その後更に銅からなる電解めっき層５を形
成する（図１（ｃ））。電解めっき条件は、上記無電解
銅めっき工程終了後の印刷回路板を、ピロりん酸銅を含
むめっき液に浸漬しながら印刷回路板８の端子３を陰極
として約２５０μｍのめっき厚となるまで通電する条件
である。After that, an electrolytic plating layer 5 made of copper is further formed (FIG. 1 (c)). The electrolytic plating conditions are such that the printed circuit board after the completion of the electroless copper plating step is dipped in a plating solution containing copper pyrophosphate and energized until the plating thickness of about 250 μm is reached with the terminal 3 of the printed circuit board 8 as a cathode. It is a condition to do.

【００２４】次に上記端子３部と対応位置となる導体表
面をマスクする。前記電解めっき層５表面であって、端
子３と対応位置にスクリーン印刷技術によりエポキシ系
樹脂からなる厚み約２０μｍのマスク６を形成する工程
である（参考：図１（ｄ））。マスクの径は前記ランド
の径の約１／２となるようにした。その後当該ペースト
を加熱硬化させる。前工程の電解めっき工程による電解
めっき層５の表面の微細な凹凸は、当該スクリーン印刷
工程に悪影響を与えなかった。Next, the surface of the conductor at the position corresponding to the terminal 3 is masked. This is a step of forming a mask 6 made of epoxy resin and having a thickness of about 20 μm on the surface of the electrolytic plating layer 5 at a position corresponding to the terminal 3 by a screen printing technique (reference: FIG. 1D). The diameter of the mask was set to be about 1/2 of the diameter of the land. Then, the paste is heat-cured. The fine irregularities on the surface of the electroplated layer 5 due to the electroplating step in the previous step did not adversely affect the screen printing step.

【００２５】またマスク６部以外の導体（電解めっき層
５及び）を除去処理する工程は、塩化鉄水溶液を用いた
ソフトエッチング処理による。するとマスク６で覆われ
た部分の電解めっき層５及び無電解めっき層４が残る
（参考：図１（ｅ））。また隣合う端子間の絶縁も維持
されている。The step of removing the conductor (electrolytic plating layer 5 and the other parts) other than the mask 6 is by soft etching using an iron chloride aqueous solution. Then, the portions of the electrolytic plating layer 5 and the electroless plating layer 4 covered with the mask 6 remain (reference: FIG. 1E). Also, insulation between adjacent terminals is maintained.

【００２６】次いで上記マスク６を除去する（参考：図
１（ｆ））。除去処理法は、表面全体を研磨する処理で
ある。研磨工程とすることにより、仮に電解めっき層５
表面に多少の凹凸があったとしても、その電解めっき層
５及び端子３の高さの和を全てに亘り実質的に等しくす
ることができる。Next, the mask 6 is removed (reference: FIG. 1 (f)). The removal treatment method is a treatment for polishing the entire surface. As a result of the polishing step, the electrolytic plating layer 5
Even if there are some irregularities on the surface, the sum of the heights of the electrolytic plating layer 5 and the terminals 3 can be made substantially the same over all.

【００２７】このようにしてバンプ７が成長形成及び除
去処理の残部として形成される。このように形成された
バンプ７は、印刷回路板８（厳密には端子３）と非常に
強固に固着されている。当該印刷回路板８のバンプ７存
在面が実装面となる。またバンプ７は、その先端が細い
略円錐台形となった。ここでバンプ７の先端の径／基底
部の径は、１／３となっていた。In this way, the bumps 7 are formed as the rest of the growth formation and removal processing. The bumps 7 thus formed are very firmly fixed to the printed circuit board 8 (strictly speaking, the terminals 3). The surface where the bumps 7 are present on the printed circuit board 8 becomes the mounting surface. The bump 7 has a substantially truncated cone shape with a thin tip. Here, the diameter of the tip of the bump 7 / the diameter of the base was 1/3.

【００２８】次いでバンプ表面にのみ無電解ニッケルめ
っきと無電解金めっきとをこの順に実施する。無電解ニ
ッケルめっき及び無電解金めっきはそれぞれ公知の置換
めっきにより実施される。Next, electroless nickel plating and electroless gold plating are carried out in this order only on the bump surface. The electroless nickel plating and the electroless gold plating are each performed by known displacement plating.

【００２９】次にこの印刷回路板の実装面とは逆の面に
電子部品９を取り付ける方法について述べる。図３
（ａ）に示すペースト状のダイ接着剤１０（例えば東芝
ケミカル株式会社製「ケミタイトＣＴ２００シリーズ」
等）を用いて印刷回路板８の実装面とは逆の面に扁平な
立方体形状の電子部品９（ＩＣチップ）を固定する。そ
して多数本の金線１１により電子部品９とその周囲の印
刷回路板８のランドとを電気接続する。当該接続には公
知のワイヤーボンディング技術を用いる。更に金線１１
全体と電子部品９とをエポキシ樹脂からなる充填剤１２
により封止する。これで電子部品９が印刷回路板８へ取
り付けられ、意図する電気接続状態を維持しつつ固定さ
れる。またこのようにして得られた電子部品が、本発明
のフリップチップ実装用電子部品となる。Next, a method of mounting the electronic component 9 on the surface opposite to the mounting surface of the printed circuit board will be described. Figure 3
A paste-like die adhesive 10 shown in (a) (for example, "Chemite CT200 series" manufactured by Toshiba Chemical Co., Ltd.)
Etc.) is used to fix the flat cubic electronic component 9 (IC chip) to the surface opposite to the mounting surface of the printed circuit board 8. Then, the plurality of gold wires 11 electrically connect the electronic component 9 and the lands of the printed circuit board 8 around the electronic component 9. A known wire bonding technique is used for the connection. Gold wire 11
Filler 12 made of epoxy resin for the whole and electronic parts 9
To seal. Thus, the electronic component 9 is attached to the printed circuit board 8 and fixed while maintaining the intended electrical connection state. The electronic component thus obtained is the electronic component for flip chip mounting of the present invention.

【００３０】次に回路板へ印刷回路板８へ取り付けられ
た電子部品９を実装する方法（実装体の製造法）につい
て述べる。図２（ａ）に示す回路板のランド（銅製）に
クリームはんだをスクリーン印刷し、リフローに供して
クリームはんだを溶融・固化させ、当該はんだをランド
と固着する。その際溶融したクリームはんだは、バンプ
７表面のＡｕ層全面に行き渡り、バンプ７全体を保持し
ながら固化した。すると図２（ａ）に示すようはんだの
フィレットが形成され、固着強度的にも問題なかった。
かかるフィレットは、円錐台形のバンプ７の細い部分に
主に形成されるため、溶融したはんだはランド領域から
外側へは流動することなく固化し、隣合うランド間では
んだブリッジが形成されることはなかった。またはんだ
とランドとの親和性からも、隣合うランド間でのはんだ
ブリッジ形成が防止されている。このような実装体の製
造法が、本発明の実装体の製造法の一例である。Next, a method of mounting the electronic component 9 attached to the printed circuit board 8 on the circuit board (a method of manufacturing a mounting body) will be described. Cream solder is screen-printed on the land (made of copper) of the circuit board shown in FIG. 2A, and the solder is fixed to the land by reflowing to melt and solidify the cream solder. At that time, the melted cream solder spread over the entire Au layer on the surface of the bumps 7 and solidified while holding the entire bumps 7. As a result, solder fillets were formed as shown in FIG. 2A, and there was no problem in terms of fixing strength.
Since such a fillet is mainly formed in a thin portion of the truncated cone-shaped bump 7, the molten solder is solidified without flowing from the land region to the outside, and a solder bridge is not formed between adjacent lands. There wasn't. Further, due to the affinity between the solder and the land, formation of a solder bridge between adjacent lands is prevented. Such a method of manufacturing a mounting body is an example of a method of manufacturing the mounting body of the present invention.

【００３１】（実施の形態２）次に電子部品が搭載（実
装）される回路板側にバンプ７を形成する実施の形態に
ついて述べる。実施の形態１では、ペースト状のダイ接
着剤１０を用いてバンプ７が形成された印刷回路板８面
とは逆の面に電子部品９（ＩＣチップ）を固定すること
により、バンプ７を有する電子部品９の製造を実現して
いた。本例では、実施の形態１での印刷回路板８へのバ
ンプ７の形成をそのまま採用する。その上でバンプ７が
形成されていない電子部品と、バンプ７が形成された印
刷回路板８とをはんだ等によって固着するものである。(Embodiment 2) Next, an embodiment in which bumps 7 are formed on the side of a circuit board on which electronic components are mounted (mounted) will be described. In the first embodiment, the bumps 7 are provided by fixing the electronic component 9 (IC chip) on the surface opposite to the surface of the printed circuit board 8 on which the bumps 7 are formed using the paste die adhesive 10. The manufacture of the electronic component 9 has been realized. In this example, the formation of the bumps 7 on the printed circuit board 8 in the first embodiment is adopted as it is. Then, the electronic component on which the bumps 7 are not formed and the printed circuit board 8 on which the bumps 7 are formed are fixed by soldering or the like.

【００３２】図１と同様の過程を経て得られた印刷回路
板８のバンプ７上に少量のクリームはんだをスクリーン
印刷する。当該クリームはんだはバンプ７の頂面のみに
配される。この状態で、電子部品の銅からなる端子（ラ
ンド）に当該クリームはんだを接触させる。具体的には
電子部品をバンプ７上に載置する。その後リフロー工程
を経てクリームはんだ及びバンプ７を溶融・固化させて
実装体を構成する。又は、クリームはんだに代えてフラ
ックスのみをランド表面及びバンプ表面に塗布してその
後リフローに供し、はんだからなるバンプを溶融・固化
させ、当該はんだをランドと固着する。溶融したはんだ
はそのランドとの親和性から、ランド領域から外側へは
流動することなく固化したため、隣合うランド間ではん
だブリッジが形成されることはなかった。このような実
装体の製造法が、本発明の実装体の製造法の一例であ
る。A small amount of cream solder is screen-printed on the bumps 7 of the printed circuit board 8 obtained through the same process as in FIG. The cream solder is arranged only on the top surface of the bump 7. In this state, the cream solder is brought into contact with the terminal (land) made of copper of the electronic component. Specifically, the electronic component is placed on the bump 7. Then, the solder paste and the bumps 7 are melted and solidified through a reflow process to form a mounting body. Alternatively, instead of the cream solder, only the flux is applied to the land surface and the bump surface and then subjected to reflow to melt and solidify the bump made of solder and fix the solder to the land. Due to the affinity with the land, the molten solder solidified without flowing from the land region to the outside, so that a solder bridge was not formed between adjacent lands. Such a method of manufacturing a mounting body is an example of a method of manufacturing the mounting body of the present invention.

【００３３】（実施の形態３）次にバンプ７をはんだと
した場合の例を述べる。本例では、実施の形態１、又は
実施の形態２での印刷回路板８へのバンプ７の形成に際
し、電解めっき層５（図１）をアルカノールスルホン酸
と、アルカノールスルホン酸第一スズと、アルカノール
スルホン酸鉛とを溶解した水溶液をめっき浴とし、印刷
回路板８を陰極として電解することにより形成する。そ
れ以外は実施の形態１及び実施の形態２と同様の過程を
経てバンプ７が形成される。但しバンプ７表面にはニッ
ケルめっき及び金めっきを施さない。またソフトエッチ
ング処理のための溶液は、実施の形態１の場合と同様に
塩化鉄水溶液とした。(Third Embodiment) Next, an example in which the bumps 7 are made of solder will be described. In this example, when the bumps 7 are formed on the printed circuit board 8 according to the first or second embodiment, the electrolytic plating layer 5 (FIG. 1) is provided with alkanolsulfonic acid and stannous alkanolsulfonate. It is formed by using an aqueous solution in which lead alkanol sulfonate is dissolved as a plating bath and electrolyzing the printed circuit board 8 as a cathode. Other than that, the bump 7 is formed through the same steps as those in the first and second embodiments. However, the surface of the bump 7 is not plated with nickel or gold. Further, the solution for the soft etching treatment was an aqueous iron chloride solution as in the case of the first embodiment.

【００３４】実装に際しては、クリームはんだを用い
て、リフロー工程を経て当該はんだからなるバンプ７を
溶融・固化させることにより、電子部品９と印刷回路板
８とを固着させる。上記クリームはんだ量はバンプ７頂
面のみを覆う程度の極少量で足りる。但し仮に多少の過
剰のクリームはんだの存在により溶融したはんだは、そ
のランドとの親和性から、ランド領域から外側へは流動
することなく固化したため、隣合うランド間ではんだブ
リッジが形成されることはなかった。At the time of mounting, cream solder is used to melt and solidify the bumps 7 made of the solder through a reflow process to fix the electronic component 9 and the printed circuit board 8 to each other. The amount of cream solder is sufficient to cover only the top surface of the bump 7. However, if the solder melted due to the presence of some excess cream solder solidified without flowing from the land region to the outside due to its affinity with the land, a solder bridge may not be formed between adjacent lands. There wasn't.

【００３５】また、クリームはんだに代えてフラックス
のみをランド表面及びバンプ表面に塗布してその後リフ
ローに供し、はんだからなるバンプを溶融・固化させ、
当該はんだをランドと固着する。その場合であっても溶
融したはんだは、そのランドとの親和性から、ランド領
域から外側へは流動することなく固化したため、隣合う
ランド間ではんだブリッジが形成されることはなかっ
た。Further, instead of the cream solder, only flux is applied to the land surface and the bump surface and then subjected to reflow to melt and solidify the bump made of solder,
The solder is fixed to the land. Even in that case, the melted solder solidified without flowing from the land region to the outside due to the affinity with the land, so that a solder bridge was not formed between adjacent lands.

【００３６】実施の形態１〜３では、バンプ７とランド
とをはんだにより固着することにより電気接続を得てい
たが、ペースト状又はシート状の異方性導電物質（例え
ば東芝ケミカル株式会社製「ＴＡＰ／ＴＮＰシリーズ」
等）を用いて、電子部品９と印刷回路板８とを固着させ
てもよい（図２（ｂ）（ｃ））。ペースト状のものを用
いる場合は、当該ペーストを加熱等で半硬化状態とし、
その後電子部品９端子と印刷回路板８のランドとの間の
当該ペースト部分を加圧圧縮することにより、バンプ７
の突起部形状に起因した部分が特に圧縮され、良導電領
域となり、他の部分がそれと相対的に導電性に乏しい領
域となる（図２（ｃ）：圧縮部分の点を密に描画してい
る。）。また異方性導電物質にシート状のものを用いる
場合は、バンプ７とランドとの間で当該異方性導電物質
を圧縮した状態で隙間を樹脂等で封止（図示しない）す
ることでその状態を維持しながら両者が固着される（図
２（ｂ））。当該圧接箇所が良導電領域となり、他の部
分がそれと相対的に導電性に乏しい領域となる。当該導
電性に乏しい領域の存在により、隣合うバンプ間の導通
（短絡）が回避される。また前記良導電領域の存在によ
り電子部品端子と印刷回路版８のランドとの接続が実現
される。このような実装体の製造法が、本発明の実装体
の製造法の一例である。In the first to third embodiments, the bumps 7 and the lands are fixed to each other by solder to obtain the electrical connection. However, a paste-like or sheet-like anisotropic conductive material (for example, manufactured by Toshiba Chemical Co., Ltd. TAP / TNP series "
Etc.) may be used to fix the electronic component 9 and the printed circuit board 8 (FIGS. 2B and 2C). When using a paste, heat the paste to a semi-cured state,
Thereafter, the paste portion between the terminal of the electronic component 9 and the land of the printed circuit board 8 is pressed and compressed, whereby the bump 7
The portion due to the shape of the protruding portion is particularly compressed to become a good conductive region, and the other portion becomes a region having relatively poor conductivity (FIG. 2 (c): densely draw the points of the compressed portion). .). When a sheet-shaped anisotropic conductive material is used, the anisotropic conductive material is compressed between the bumps 7 and the land by sealing the gap with resin or the like (not shown). Both are fixed while maintaining the state (FIG. 2B). The pressure contact portion becomes a good conductive region, and the other portion becomes a region relatively poor in conductivity. Due to the existence of the region having poor conductivity, conduction (short circuit) between adjacent bumps is avoided. Further, the existence of the good conductive region realizes the connection between the electronic component terminal and the land of the printed circuit board 8. Such a method of manufacturing a mounting body is an example of a method of manufacturing the mounting body of the present invention.

【００３７】実施の形態１〜３では、ワイヤーボンディ
ングによって内部配線がなされる形態の電子部品を用い
ているが、これに限定されない。例えば図３（ｂ）に示
すような、内部配線を内部配線用バンプで実現する形
態、又は内部配線を省略して図３（ｂ）に示す内部配線
用バンプをそのまま本発明にかかるバンプとして外部配
線のために使用する形態（図３（ｃ））などとすること
ができる。In the first to third embodiments, the electronic component in which the internal wiring is formed by wire bonding is used, but the present invention is not limited to this. For example, as shown in FIG. 3B, the internal wiring is realized by bumps for internal wiring, or the internal wiring is omitted and the internal wiring bumps shown in FIG. 3B are directly used as the bumps according to the present invention. The form (FIG. 3C) used for wiring can be adopted.

【００３８】[0038]

【発明の効果】本発明により、バンプ間距離を小さくし
たフリップチップ実装を実現することができた。またそ
れによりフリップチップ実装用電子部品の小型化が可能
となる。According to the present invention, flip-chip mounting in which the distance between bumps is reduced can be realized. Further, it is possible to downsize the electronic component for flip chip mounting.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明にかかるバンプの成長形成の様子の一例
を示す図である。FIG. 1 is a diagram showing an example of a state of growth and formation of bumps according to the present invention.

【図２】本発明にかかる実装要部を示す図である。FIG. 2 is a view showing a main part of mounting according to the present invention.

【図３】本発明の電子部品の概要図である。FIG. 3 is a schematic diagram of an electronic component of the present invention.

【符号の説明】[Explanation of symbols]

３．端子 ４．無電解めっき層 ５．電解めっき層 ６．マスク ７．バンプ ８．印刷回路板 ９．電子部品 １０．ダイ接着剤 １１．金線 １２．充填剤 3. Terminal 4. Electroless plating layer 5. Electrolytic plating layer 6. mask 7. bump 8. Printed circuit board 9. Electronic parts 10. Die adhesive 11. Gold wire 12. filler

フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０５Ｋ 3/34 ５０７ Ｈ０５Ｋ 3/34 ５０７Ｃ Front page continuation (51) Int.Cl. 7 Identification code FI theme code (reference) H05K 3/34 507 H05K 3/34 507C

Claims (8)

【特許請求の範囲】[Claims] 【請求項１】実装面に複数の端子が点在し、当該端子上
に形成された導体を有するフリップチップ実装用電子部
品において、 前記導体が成長形成及び／又は除去処理の残部として形
成されてなり、且つ前記端子とその上の導体高さの和が
全てに亘り実質的に等しく、当該導体部先端が実質的な
平面であることを特徴とするフリップチップ実装用電子
部品。1. A flip-chip mounting electronic component having a plurality of terminals scattered on a mounting surface and having conductors formed on the terminals, wherein the conductors are formed as the rest of growth formation and / or removal processing. The flip chip mounting electronic component is characterized in that the sum of the heights of the terminals and the conductors on the terminals is substantially the same, and the tips of the conductors are substantially flat. 【請求項２】導体が、先端の細い円錐台形又は角錐台形
であることを特徴とする請求項１記載のフリップチップ
実装用電子部品。2. The electronic component for flip chip mounting according to claim 1, wherein the conductor has a truncated cone shape with a thin tip or a truncated pyramid shape. 【請求項３】実装面に複数の端子が点在し、当該端子上
に導体が形成されるフリップチップ実装用電子部品の製
造法において、 前記実装面を所定厚みの導体で被覆する工程と、前記端
子部と対応位置となる導体表面をマスクする工程と、当
該マスク部以外の導体を除去処理する工程とを有し、こ
れら工程をこの順に実施することを特徴とするフリップ
チップ実装用電子部品の製造法。3. A method of manufacturing an electronic component for flip-chip mounting in which a plurality of terminals are scattered on a mounting surface and conductors are formed on the terminals, in the step of covering the mounting surface with a conductor having a predetermined thickness, An electronic component for flip-chip mounting, comprising a step of masking a conductor surface at a position corresponding to the terminal portion, and a step of removing the conductor other than the mask portion, and performing these steps in this order. Manufacturing method. 【請求項４】実装面に複数のフリップチップ実装用ラン
ドが点在し、当該端子上に形成された導体を有する回路
板において、 前記導体が成長形成及び／又は除去処理の残部として形
成されてなり、且つ前記ランド高さとその上の導体高さ
の和が全てに亘り実質的に等しく、当該導体部先端が実
質的な平面であることを特徴とする回路板。4. A circuit board having a plurality of flip-chip mounting lands scattered on a mounting surface and having a conductor formed on the terminal, wherein the conductor is formed as a remainder of growth formation and / or removal processing. And the sum of the land height and the conductor height above the land is substantially the same, and the tip of the conductor portion is a substantially flat surface. 【請求項５】導体が、先端の細い円錐台形又は角錐台形
であることを特徴とする請求項４記載の回路板。5. The circuit board according to claim 4, wherein the conductor has a truncated cone shape with a thin tip or a truncated pyramid shape. 【請求項６】実装面に複数のフリップチップ実装用ラン
ドが点在する回路板の製造法において、 前記実装面を所定厚みの導体で被覆する工程と、前記ラ
ンド部と対応位置となる導体表面をマスクする工程と、
当該マスク部以外の導体を除去処理する工程とを有し、
これら工程をこの順に実施することを特徴とする回路板
の製造法。6. A method of manufacturing a circuit board, wherein a plurality of flip chip mounting lands are scattered on the mounting surface, a step of coating the mounting surface with a conductor having a predetermined thickness, and a conductor surface corresponding to the land portion. A step of masking
A step of removing the conductor other than the mask portion,
A method for manufacturing a circuit board, which comprises performing these steps in this order. 【請求項７】フリップチップ実装用電子部品の実装面端
子部、及び／又は回路板実装面のフリップチップ実装用
ランドが導体を有し、当該導体が成長形成及び／又は除
去処理の残部として形成されてなり、はんだ又は異方性
導電物質により回路板の導体と電子部品、若しくは電子
部品の導体と回路板とを固定することを特徴とする実装
体の製造法。7. A mounting surface terminal portion of an electronic component for flip-chip mounting and / or a land for flip-chip mounting on a circuit board mounting surface has a conductor, and the conductor is formed as the rest of growth formation and / or removal processing. A method for manufacturing a mounting body, characterized in that a conductor of a circuit board and an electronic component, or a conductor of an electronic component and a circuit board are fixed by solder or an anisotropic conductive material. 【請求項８】導体が銅からなり、その表面にニッケル層
と金層とをこの順に形成し、はんだの固着力により固定
を実現することを特徴とする請求項７記載の実装体の製
造法。8. The method for manufacturing a mounting body according to claim 7, wherein the conductor is made of copper, and a nickel layer and a gold layer are formed in this order on the surface of the conductor, and the fixing is realized by a fixing force of solder. .
JP2001301399A 2001-09-28 2001-09-28 Electronic component for flip-chip packaging and manufacturing method thereof, circuit plate and manufacturing method thereof, and manufacturing method of packaging body Pending JP2003110061A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001301399A JP2003110061A (en) 2001-09-28 2001-09-28 Electronic component for flip-chip packaging and manufacturing method thereof, circuit plate and manufacturing method thereof, and manufacturing method of packaging body

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001301399A JP2003110061A (en) 2001-09-28 2001-09-28 Electronic component for flip-chip packaging and manufacturing method thereof, circuit plate and manufacturing method thereof, and manufacturing method of packaging body

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Publication Number Publication Date
JP2003110061A true JP2003110061A (en) 2003-04-11

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100608360B1 (en) 2004-04-16 2006-08-08 주식회사 하이닉스반도체 method of forming a solder structure in a semiconductor device
US7753489B2 (en) 2004-09-27 2010-07-13 Brother Kogyo Kabushiki Kaisha Connection structure of flexible wiring substrate and connection method using same
JP2014090185A (en) * 2013-11-29 2014-05-15 Sekisui Chem Co Ltd Manufacturing method of connection structure

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06342794A (en) * 1993-06-01 1994-12-13 Mitsubishi Electric Corp Resin-sealed type semiconductor package and manufacture thereof
JPH07201864A (en) * 1993-12-28 1995-08-04 Fujitsu Ltd Projection electrode formation method
JPH1117309A (en) * 1997-06-19 1999-01-22 Hitachi Ltd Electronic parts connecting mechanism, electronic circuit board using it, and its manufacture
JPH11177016A (en) * 1997-12-15 1999-07-02 Denso Corp Composite integrated circuit device
JP2001044319A (en) * 1999-07-27 2001-02-16 Kyocera Corp Wiring board and mounting structure thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06342794A (en) * 1993-06-01 1994-12-13 Mitsubishi Electric Corp Resin-sealed type semiconductor package and manufacture thereof
JPH07201864A (en) * 1993-12-28 1995-08-04 Fujitsu Ltd Projection electrode formation method
JPH1117309A (en) * 1997-06-19 1999-01-22 Hitachi Ltd Electronic parts connecting mechanism, electronic circuit board using it, and its manufacture
JPH11177016A (en) * 1997-12-15 1999-07-02 Denso Corp Composite integrated circuit device
JP2001044319A (en) * 1999-07-27 2001-02-16 Kyocera Corp Wiring board and mounting structure thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100608360B1 (en) 2004-04-16 2006-08-08 주식회사 하이닉스반도체 method of forming a solder structure in a semiconductor device
US7753489B2 (en) 2004-09-27 2010-07-13 Brother Kogyo Kabushiki Kaisha Connection structure of flexible wiring substrate and connection method using same
JP2014090185A (en) * 2013-11-29 2014-05-15 Sekisui Chem Co Ltd Manufacturing method of connection structure

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