JP2003092489A - Printed board - Google Patents
Printed boardInfo
- Publication number
- JP2003092489A JP2003092489A JP2001283874A JP2001283874A JP2003092489A JP 2003092489 A JP2003092489 A JP 2003092489A JP 2001283874 A JP2001283874 A JP 2001283874A JP 2001283874 A JP2001283874 A JP 2001283874A JP 2003092489 A JP2003092489 A JP 2003092489A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- insulating substrate
- circuit board
- printed circuit
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、絶縁基板上に複数
の導体パターンを設けたプリント基板の改良に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a printed board having a plurality of conductor patterns provided on an insulating board.
【０００２】[0002]
【従来の技術】プリント基板上に形成される導体パター
ン同士を電気的に接続した配線においては、ＥＭＩ、す
なわち、電磁妨害によりノイズが発生するが、その対策
として、従来では、基板上に中空のフェライトコアを実
装させ、このコアに配線を複数回、巻き回していた。2. Description of the Related Art Noise is generated by EMI, that is, electromagnetic interference in a wiring in which conductor patterns are electrically connected to each other formed on a printed circuit board. A ferrite core was mounted, and wiring was wound around this core multiple times.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、このよ
うな対策においては、基板上にフェライトコアを実装す
るためのエリアを確保させる必要があり、そのため、基
板の高密度化が阻害されていた。However, in such measures, it is necessary to secure an area for mounting the ferrite core on the substrate, which hinders the high density of the substrate.
【０００４】本発明は、上記事情を考慮したものであ
り、基板の高密度化を阻害することなく、導体パターン
を電気的接続した際に生じる電磁妨害を防止することの
できるプリント基板を提供することを目的としている。The present invention has been made in view of the above circumstances, and provides a printed circuit board capable of preventing electromagnetic interference generated when electrically connecting conductor patterns without impeding the densification of the circuit board. Is intended.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するため
に、本発明の請求項１に記載のプリント基板では、絶縁
基板を厚み方向に貫通するスルーホールを、絶縁基板と
の間で中空部を設けて構成し、この中空部には、中空の
コア部材を設けたことを特徴とする。In order to achieve the above object, in a printed circuit board according to a first aspect of the present invention, a through hole penetrating the insulating substrate in the thickness direction has a hollow portion between the through hole and the insulating substrate. Is provided, and a hollow core member is provided in the hollow portion.
【０００６】請求項２に記載のプリント基板では、スル
ーホールには、絶縁基板上の表面と裏面とに設けた導体
パターンがそれぞれ接続されており、スルーホール内に
埋め込んだ導体層によって、表面と裏面の導体パターン
を電気的に接続していることを特徴とする。In the printed circuit board according to the second aspect, conductor patterns provided on the front surface and the back surface of the insulating substrate are respectively connected to the through holes, and the front surface and the back surface are formed by the conductor layers embedded in the through holes. It is characterized in that the conductor pattern on the back surface is electrically connected.
【０００７】請求項３に記載のプリント基板では、絶縁
基板上に実装させる配線を、スルーホールに挿通させた
ことを特徴とする。According to a third aspect of the printed circuit board, the wiring to be mounted on the insulating substrate is inserted through the through hole.
【０００８】[0008]
【発明の実施の形態】以下に、本発明の実施の形態につ
いて、図面とともに説明する。図１は、本発明のプリン
ト基板の縦断面構造の一例を示す図である。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an example of a vertical sectional structure of a printed circuit board of the present invention.
【０００９】このプリント基板１は、絶縁基板２を厚み
方向に貫通するスルーホール４を設けており、このスル
ーホール４と絶縁基板２の内壁面４０との間には中空部
を設けており、この中空部には、中空のコア部材５を挿
通している。また、スルーホール４には、基板２の表面
と裏面とに設けた導体パターン３Ａ，３Ｂを接続してお
り、スルーホール４に、導体層６を、例えば、はんだを
流し込むことによって形成して、表面と裏面の導体パタ
ーン３Ａ，３Ｂを電気的に接続している。The printed circuit board 1 is provided with a through hole 4 penetrating the insulating substrate 2 in the thickness direction, and a hollow portion is provided between the through hole 4 and the inner wall surface 40 of the insulating substrate 2. A hollow core member 5 is inserted into this hollow portion. The conductor patterns 3A and 3B provided on the front surface and the back surface of the substrate 2 are connected to the through hole 4, and a conductor layer 6 is formed in the through hole 4 by pouring solder, for example. The conductor patterns 3A and 3B on the front surface and the back surface are electrically connected.
【００１０】このような構成のプリント基板１は、例え
ば、以下に示す回路に適用される。図２は、本発明をク
ロック処理回路に適用したものを示しており、クロック
発生回路７より出力されるクロックは、導体パターン３
Ａ，３Ｂを通じてＩＣ８に入力される。The printed circuit board 1 having such a structure is applied to, for example, a circuit shown below. FIG. 2 shows that the present invention is applied to a clock processing circuit. The clock output from the clock generation circuit 7 is a conductor pattern 3
Input to IC8 through A and 3B.
【００１１】この回路では、クロック発生回路７より出
力されるクロックは、一般的に３０ＭＨｚ以上の高周波
数であるが、導体パターン３Ａ，３Ｂを電気的接続する
導体層６がスルーホール４に埋め込まれているため、導
体層６周辺で電磁障害が生じないという利点がある。In this circuit, the clock output from the clock generation circuit 7 has a high frequency of generally 30 MHz or more, but the conductor layer 6 for electrically connecting the conductor patterns 3A and 3B is embedded in the through hole 4. Therefore, there is an advantage that electromagnetic interference does not occur around the conductor layer 6.
【００１２】また、図３は、本発明をビデオ信号処理回
路に適用したものであり、ＣＣＤ９より出力されるビデ
オ信号は、導体パターン３Ａ，３Ｂを通じて画処理ＩＣ
１０に入力される。FIG. 3 shows a video signal processing circuit to which the present invention is applied. The video signal output from the CCD 9 is image-processed through the conductor patterns 3A and 3B.
Input to 10.
【００１３】この回路では、ＣＣＤ９より出力されるビ
デオ信号は、一般的に３０ＭＨｚ以上の高周波数である
が、導体パターン３Ａ，３Ｂを電気的接続する導体層６
がスルーホール４に埋め込まれているため、導体層６周
辺で電磁障害が生じないという利点がある。In this circuit, the video signal output from the CCD 9 has a high frequency of generally 30 MHz or more, but the conductor layer 6 for electrically connecting the conductor patterns 3A and 3B is used.
Embedded in the through hole 4, there is an advantage that electromagnetic interference does not occur around the conductor layer 6.
【００１４】図４は、本発明のプリント基板の他例を示
す図である。このプリント基板１’は、導体パターン３
Ａ，３Ｂは、導体層６で電気的接続せずに、配線Ｌで電
気的接続した構成としている。FIG. 4 is a diagram showing another example of the printed circuit board of the present invention. This printed circuit board 1'has a conductor pattern 3
A and 3B are not electrically connected by the conductor layer 6 but are electrically connected by the wiring L.
【００１５】プリント基板１’では、スルーホール４の
周囲に、配線Ｌを貫通させる貫通孔Ｈを複数設けてお
り、各々の貫通孔Ｈとスルーホール４との間で配線Ｌを
巻き回すことによって、配線Ｌを複数ターンにわたっ
て、スルーホール４内を挿通させている。In the printed circuit board 1 ', a plurality of through holes H for penetrating the wiring L are provided around the through hole 4, and the wiring L is wound between each through hole H and the through hole 4. The wiring L is inserted through the through hole 4 over a plurality of turns.
【００１６】これにより、導体パターン３Ａ，３Ｂ同士
を配線Ｌにより電気的接続する場合に、スルーホール４
内のコア部材５によって、配線Ｌから生じる電磁障害の
発生を防止することができる。As a result, when the conductor patterns 3A and 3B are electrically connected to each other by the wiring L, the through hole 4 is formed.
The inner core member 5 can prevent the occurrence of electromagnetic interference caused by the wiring L.
【００１７】[0017]
【発明の効果】以上の説明からも理解できるように、本
発明の請求項１に記載のプリント基板では、絶縁基板を
厚み方向に貫通するスルーホールを、絶縁基板との間で
中空部を設けて構成し、この中空部には、中空のコア部
材を設けているので、このスルーホールを使用して導体
パターンを電気的接続すれば、基板の高密度化を阻害す
ることなく、電磁障害の発生を防止することができる。As can be understood from the above description, in the printed circuit board according to the first aspect of the present invention, a through hole penetrating the insulating substrate in the thickness direction and a hollow portion are provided between the insulating substrate and the through hole. Since a hollow core member is provided in this hollow portion, if the conductor pattern is electrically connected using this through hole, electromagnetic interference is prevented without impeding the densification of the substrate. Occurrence can be prevented.
【００１８】請求項２に記載のプリント基板では、スル
ーホールには、絶縁基板上の表面と裏面とに設けた導体
パターンがそれぞれ接続されており、スルーホール内に
埋め込んだ導体層によって、表面と裏面の導体パターン
を電気的に接続しているので、基板の表面と裏面の導体
パターンを電気的接続する導体層についても、効果的に
電磁障害の発生を防止することができる。In the printed circuit board according to the present invention, conductor patterns provided on the front surface and the back surface of the insulating substrate are respectively connected to the through holes, and the front surface and the back surface are formed by the conductor layers embedded in the through holes. Since the conductor patterns on the back surface are electrically connected, it is possible to effectively prevent electromagnetic interference even in the conductor layer that electrically connects the conductor patterns on the front surface and the back surface of the substrate.
【００１９】請求項３に記載のプリント基板では、絶縁
基板上に実装させる配線を、スルーホールに挿通させた
ので、基板上に実装させる配線についても、効果的に電
磁障害の発生を防止することができる。In the printed circuit board according to the third aspect, the wiring to be mounted on the insulating substrate is inserted into the through hole, so that the wiring to be mounted on the substrate can be effectively prevented from causing electromagnetic interference. You can
【図１】本発明のプリント基板の縦断面構造の一例を示
す図である。FIG. 1 is a diagram showing an example of a vertical sectional structure of a printed circuit board of the present invention.
【図２】クロック処理回路に適用した本発明について説
明するための図である。FIG. 2 is a diagram for explaining the present invention applied to a clock processing circuit.
【図３】ビデオ信号処理回路に適用した本発明について
説明するための図である。FIG. 3 is a diagram for explaining the present invention applied to a video signal processing circuit.
【図４】本発明のプリント基板の他例を示す図である。FIG. 4 is a diagram showing another example of the printed circuit board of the present invention.
１、１’・・・プリント基板 ２・・・絶縁基板 ３Ａ，３Ｂ・・・導体パターン ４・・・スルーホール ５・・・コア部材 ６・・・導体層 Ｌ・・・配線 1, 1 '... Printed circuit board 2 ... Insulating substrate 3A, 3B ... Conductor pattern 4 ... Through hole 5: Core member 6 ... Conductor layer L: Wiring
Claims (3)
プリント基板において、 上記絶縁基板を厚み方向に貫通するスルーホールを、上
記絶縁基板との間で中空部を設けて構成し、この中空部
には、中空のコア部材を設けたことを特徴とするプリン
ト基板。1. A printed circuit board having a plurality of conductor patterns provided on an insulating substrate, wherein a through hole penetrating the insulating substrate in the thickness direction is formed with a hollow portion between the insulating substrate and the through hole. A printed circuit board, wherein a hollow core member is provided in the portion.
に設けた導体パターンがそれぞれ接続されており、 上記スルーホール内に埋め込んだ導体層によって、表面
と裏面の導体パターンを電気的に接続していることを特
徴とするプリント基板。2. The conductor pattern provided on the front surface and the back surface of the insulating substrate are connected to the through hole, and the conductor pattern is embedded in the through hole to form a surface. A printed circuit board characterized in that the conductor pattern on the back surface is electrically connected.
に挿通させたことを特徴とするプリント基板。3. The printed circuit board according to claim 1, wherein wiring to be mounted on the insulating substrate is inserted through the through hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001283874A JP2003092489A (en) | 2001-09-18 | 2001-09-18 | Printed board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001283874A JP2003092489A (en) | 2001-09-18 | 2001-09-18 | Printed board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003092489A true JP2003092489A (en) | 2003-03-28 |
Family
ID=19107303
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001283874A Pending JP2003092489A (en) | 2001-09-18 | 2001-09-18 | Printed board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003092489A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009087689A (en) * | 2007-09-28 | 2009-04-23 | Kawamura Electric Inc | Ground-fault circuit interrupter |
| US7812702B2 (en) | 2006-05-08 | 2010-10-12 | Ibiden Co., Ltd. | Inductor and electric power supply using it |
-
2001
- 2001-09-18 JP JP2001283874A patent/JP2003092489A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7812702B2 (en) | 2006-05-08 | 2010-10-12 | Ibiden Co., Ltd. | Inductor and electric power supply using it |
| US7843302B2 (en) | 2006-05-08 | 2010-11-30 | Ibiden Co., Ltd. | Inductor and electric power supply using it |
| US7855626B2 (en) | 2006-05-08 | 2010-12-21 | Ibiden Co., Ltd. | Inductor and electric power supply using it |
| US7868728B2 (en) | 2006-05-08 | 2011-01-11 | Ibiden Co., Ltd. | Inductor and electric power supply using it |
| US8207811B2 (en) | 2006-05-08 | 2012-06-26 | Ibiden Co., Ltd. | Inductor and electric power supply using it |
| JP2009087689A (en) * | 2007-09-28 | 2009-04-23 | Kawamura Electric Inc | Ground-fault circuit interrupter |
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Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20051115 |
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