JP2003086627A - Method for assembling semiconductor device and semiconductor device - Google Patents
Method for assembling semiconductor device and semiconductor deviceInfo
- Publication number
- JP2003086627A JP2003086627A JP2001280920A JP2001280920A JP2003086627A JP 2003086627 A JP2003086627 A JP 2003086627A JP 2001280920 A JP2001280920 A JP 2001280920A JP 2001280920 A JP2001280920 A JP 2001280920A JP 2003086627 A JP2003086627 A JP 2003086627A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- circuit board
- semiconductor device
- assembling
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、バンプ接合方式で
基板と接合する半導体素子の組立方法に関するものであ
り、その製造方法を用いて製作された半導体装置であ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of assembling a semiconductor element that is bonded to a substrate by a bump bonding method, and a semiconductor device manufactured by the manufacturing method.
【０００２】[0002]
【従来の技術】近年半導体パッケージの小型化や薄型化
に対する技術革新は目覚しいものがあり、様々なパッケ
ージ構造が提唱され、製品化されている。従来のリード
フレーム接合に変わり、半田バンプのような突起電極に
より、回路基板（マザーボード）に電気的に接合させる
エリア実装方式は特に重要である。2. Description of the Related Art In recent years, technological innovations toward miniaturization and thinning of semiconductor packages have been remarkable, and various package structures have been proposed and commercialized. In place of the conventional lead frame bonding, an area mounting method of electrically bonding to a circuit board (motherboard) by a protruding electrode such as a solder bump is particularly important.
【０００３】その中で半導体チップの回路面に直接突起
電極が具備されたフリップチップはパッケージをチップ
スケールへ最小化できる方法の一つである。フリップチ
ップ実装は、半田電極の場合、半田電極表面の酸化膜を
除去する為にフラックスで処理した後、リフロー等の方
法で接合する。その為、半田電極や回路基板等の周囲に
フラックスが残存し、不純物として問題となるためにフ
ラックスを除去する洗浄を行った後液状封止を行う。そ
の理由としては、直接回路基板（マザーボード）に突起
電極で接合する為、温度サイクル試験のような信頼性試
験を行うと、半導体チップと回路板の線膨張係数の差に
より電極接合部の電気的不良が発生する為であるAmong them, the flip chip in which the projecting electrodes are directly provided on the circuit surface of the semiconductor chip is one of the methods for minimizing the package to a chip scale. In the flip-chip mounting, in the case of a solder electrode, a flux is used to remove an oxide film on the surface of the solder electrode, and then the solder electrode is joined by a method such as reflow. Therefore, the flux remains around the solder electrodes, the circuit board, etc. and becomes a problem as impurities. Therefore, cleaning is performed to remove the flux, and then liquid sealing is performed. The reason is that the circuit board (motherboard) is directly bonded with the protruding electrodes. Therefore, when a reliability test such as a temperature cycle test is performed, the electrical connection of the electrode bonding part is caused by the difference in the linear expansion coefficient between the semiconductor chip and the circuit board. This is because a defect occurs
【０００４】液状樹脂による封止は、半導体チップの一
辺又は複数面にアンダーフィル材と呼ばれる液状封止樹
脂を塗布し、毛細管現象を利用して樹脂を回路基板と半
導体チップの間隙に流し込ませる。しかしこの方法はフ
ラックス処理工程、フラックス洗浄工程を行う為工程が
長くなり、且つ洗浄廃液の処理問題等環境管理を厳しく
しなければならない等の問題がある。更に液状封止を毛
細管現象で行う為、封止時間が長く、通常後硬化工程も
行わなければらないため、生産性に問題があった。In the liquid resin sealing, a liquid sealing resin called an underfill material is applied to one side or a plurality of surfaces of the semiconductor chip, and the resin is poured into the gap between the circuit board and the semiconductor chip by utilizing the capillary phenomenon. However, this method has problems that the steps are long because the flux processing step and the flux cleaning step are performed, and the environmental management such as the processing problem of the cleaning waste liquid must be strict. Further, since the liquid sealing is performed by the capillary phenomenon, the sealing time is long and the post-curing step is usually required, which causes a problem in productivity.
【０００５】そこで、直接回路基板に樹脂組成物を塗布
し、半田電極を持った半導体チップをその上から搭載
し、半田接合と樹脂封止を同時に行う方法が考案された
（米国特許第 5,128,746号公報）。この場合、半田を回
路基板に接合させる為に、熱硬化性樹脂、硬化剤からな
る樹脂組成物にフラックス作用を有する成分を添加する
ことが特徴である。Therefore, a method has been devised in which a resin composition is directly applied to a circuit board, a semiconductor chip having a solder electrode is mounted thereon, and solder bonding and resin sealing are simultaneously performed (US Pat. No. 5,128,746). Gazette). In this case, in order to bond the solder to the circuit board, a component having a flux function is added to the resin composition including the thermosetting resin and the curing agent.
【０００６】しかし、一般的には回路基板側に樹脂組成
物が塗布され、多くの突起電極を有する半導体素子を圧
接すること、または回路基板面が複雑なパターンが形成
され、それによる凹凸が多いことから、圧接時の樹脂組
成物の拡がりに伴う巻き込みエアを内包し、信頼性に悪
影響を及ぼしてしまう可能性があった。また、半導体チ
ップ側に塗布する方法は、樹脂ダレが発生する可能性が
あり採用されていなかった。However, in general, a resin composition is applied to the circuit board side to press-contact a semiconductor element having many protruding electrodes, or a complicated pattern is formed on the surface of the circuit board, resulting in many irregularities. Therefore, there is a possibility that the air entrapped due to the spread of the resin composition at the time of pressure contact may be included and the reliability may be adversely affected. Further, the method of coating on the semiconductor chip side has not been adopted because the resin sagging may occur.
【０００７】また、封止樹脂組成物をより高信頼性にす
るため、フィラーを添加する場合があるが、複雑な回路
面が形成されているため、フィラーが微小な凹凸や、接
合部であるパッドにトラップされ、バンプとの間に噛み
込まれ、接合不良を起こす可能性があった。Further, a filler may be added in order to make the encapsulating resin composition more reliable, but since the complicated circuit surface is formed, the filler is a minute unevenness or a joint portion. There was a possibility of being trapped by the pad and being caught between the bumps and causing a bonding failure.
【０００８】[0008]
【発明が解決しようとする課題】本発明の課題は、液状
樹脂封止組成物を用いて半導体チップ、特に回路面に突
起電極を有する半導体チップを封止する圧接実装法にお
いて、封止時間が短く、且つ圧接時の巻き込みエアやフ
ィラーのような固形物の圧接時の噛み込みを低減可能な
半導体装置の組立方法である。SUMMARY OF THE INVENTION An object of the present invention is to provide a sealing time in a pressure contact mounting method for sealing a semiconductor chip, particularly a semiconductor chip having a protruding electrode on a circuit surface, using a liquid resin sealing composition. It is a method of assembling a semiconductor device that is short and can reduce entrapment of solid matter such as entrapped air or filler during pressure contact during pressure contact.
【０００９】[0009]
【課題を解決するための手段】本発明は、（１）回路基
板と電気的接合させる為の半田バンプを有する多数個の
半導体素子が形成された半導体チップ上にあらかじめフ
ラックス作用を有するノンフローアンダーフィル材料を
塗布する工程、（２）半導体チップと半導体チップ上の
半田バンプに対応したパッド部を有する回路基板とを位
置合わせする工程、（３）半導体チップと該回路基板を
圧接する工程、（４）チップと回路基板を熱圧着する工
程からなる半導体装置の組立方法である。According to the present invention, (1) a non-flow under having a flux function is previously formed on a semiconductor chip on which a large number of semiconductor elements having solder bumps for electrically connecting to a circuit board are formed. A step of applying a fill material, (2) a step of aligning the semiconductor chip with a circuit board having a pad portion corresponding to a solder bump on the semiconductor chip, (3) a step of press-contacting the semiconductor chip with the circuit board, 4) A method of assembling a semiconductor device, which comprises a step of thermocompression bonding a chip and a circuit board.
【００１０】更に好ましい形態としては、ノンフローア
ンダーフィル材料を塗布する方法が、ディスペンスもし
くはスクリーン印刷により行われ、ノンフローアンダー
フィル材料を塗布する工程の後に、ノンフローアンダー
フィル材料の樹脂中の空気を脱泡除去する工程を含み、
チップと回路基板を熱圧着する方法がリフロー又はパル
スヒートにより行われ、ノンフローアンダーフィル材料
がエポキシ樹脂系、またはシアネート樹脂系である半導
体装置の組立方法である。また、上記に記載の半導体装
置の組立方法を用いて作製された半導体装置である。In a further preferred form, the method of applying the non-flow underfill material is performed by dispensing or screen printing, and after the step of applying the non-flow underfill material, air in the resin of the non-flow underfill material is applied. Defoaming and removing,
The method of thermocompression bonding the chip and the circuit board is performed by reflow or pulse heating, and the non-flow underfill material is an epoxy resin-based or cyanate resin-based semiconductor device assembling method. Further, the semiconductor device is manufactured by using the method for assembling the semiconductor device described above.
【００１１】[0011]
【発明の実施の形態】本発明について詳細に説明する。
本発明において用いられる封止樹脂材料は、熱硬化性樹
脂が好ましく、更には常温で液状のものが好ましい。例
としては、エポキシ樹脂、シアネート樹脂、ウレタン樹
脂、ポリブタジエン樹脂、シリコーン樹脂、フェノール
樹脂等公知の熱硬化性樹脂を適用することが出来るが、
より好ましくはエポキシ樹脂、シアネート樹脂である。
半導体素子の封止目的のため不純物、特にイオン性不純
物が少ないものが好ましい。BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described in detail.
The encapsulating resin material used in the present invention is preferably a thermosetting resin, and more preferably liquid at room temperature. As an example, a known thermosetting resin such as an epoxy resin, a cyanate resin, a urethane resin, a polybutadiene resin, a silicone resin, a phenol resin can be applied,
Epoxy resin and cyanate resin are more preferable.
For the purpose of encapsulating a semiconductor element, an impurity, particularly an ionic impurity, is preferable.
【００１２】エポキシ樹脂を用いる場合、エポキシ樹脂
の種類として特に限定されず、例えば、ビスフェノール
Ｆ型エポキシ樹脂、ビスフェノールＡ型エポキシ樹脂、
ナフタレン型エポキシ樹脂、ビフェニル型エポキシ樹
脂、多官能型エポキシ樹脂等を用いることができるが、
常温で液状のものが好ましい。常温で液状ではないもの
に関しては、既存の液状エポキシ樹脂にあらかじめ溶解
させて使用することもできる。エポキシ樹脂の硬化剤と
しては、公知のものを用いることができ、例えば、酸無
水物系硬化剤、アミン系硬化剤、フェノール樹脂系硬化
剤等を用いることができる。エポキシ樹脂の硬化促進剤
としては、公知のものを用いることができ、例えば、イ
ミダゾール類、ＤＢＵ、リン系触媒、金属アセチルアセ
トナートや金属ナフテン酸等の金属錯体等を用いること
ができる。When an epoxy resin is used, the type of epoxy resin is not particularly limited, and examples thereof include bisphenol F type epoxy resin, bisphenol A type epoxy resin,
Although naphthalene type epoxy resin, biphenyl type epoxy resin, polyfunctional type epoxy resin, etc. can be used,
It is preferably liquid at room temperature. Those that are not liquid at room temperature can be dissolved in the existing liquid epoxy resin in advance before use. As the curing agent for the epoxy resin, known ones can be used, and for example, an acid anhydride-based curing agent, an amine-based curing agent, a phenol resin-based curing agent and the like can be used. As the curing accelerator for the epoxy resin, known compounds can be used, and for example, imidazoles, DBU, phosphorus-based catalysts, metal complexes such as metal acetylacetonate and metal naphthenic acid, and the like can be used.
【００１３】本発明において用いられる封止樹脂材料
は、ノンフローアンダーフィル材料であり、フラックス
作用を有することが必要である。封止樹脂材料にノンフ
ローが必要となるのは、半田バンプ接続をリフローやパ
ルスヒート方式により一括で行う為であり、そのために
は半田の酸化膜を還元除去できるようなフラックス特性
が必要なためである。フラックス作用を有するとは共晶
半田の表面の酸化膜を還元除去し、基板と接合できるよ
うにする作用のことをいい、その様な作用を有する物質
を封止樹脂材料に含むことが必要である。その様な作用
を有する物質としては、例えば、有機カルボン酸類（ポ
リマー、モノマー含む）、ハイドロキノン、ナフトキノ
ンのような還元作用を示す物質または該構造を有する化
合物がある。また、例えば、エポキシ樹脂の硬化剤とし
ての作用とフラックス作用の両方を有する物質を用いて
も良い。そのような例としては、１分子あたり少なくと
も２個以上のフェノール性水酸基と１分子当たり少なく
とも１個以上の芳香族カルボン酸を有する化合物であ
り、この様な化合物の例としては、例えば、ジヒドロキ
シ安息香酸、フェノールフタリン、ジヒドロキシナフト
エ酸等がある。The sealing resin material used in the present invention is a non-flow underfill material and is required to have a flux function. Non-flow is required for the encapsulating resin material because solder bump connection is performed collectively by reflow or pulse heating method, and for that purpose, flux characteristics that can reduce and remove the oxide film of solder are required. is there. Having a flux function means a function of reducing and removing the oxide film on the surface of the eutectic solder to enable bonding with the substrate, and it is necessary to include a substance having such a function in the encapsulating resin material. is there. Examples of the substance having such an action include substances having a reducing action such as organic carboxylic acids (including polymers and monomers), hydroquinone, naphthoquinone, and compounds having the structure. Further, for example, a substance having both an action as a curing agent for the epoxy resin and a flux action may be used. Examples of such compounds are compounds having at least two or more phenolic hydroxyl groups per molecule and at least one or more aromatic carboxylic acid per molecule. Examples of such compounds include, for example, dihydroxybenzoic acid. Acid, phenolphthaline, dihydroxynaphthoic acid and the like.
【００１４】これらフラックス作用を有する物質の添加
量は、主剤となる液状の熱硬化性樹脂１００重量部に対
し、１０〜５０重量部であることが望ましい。１０重量
部未満であると十分なフラックス活性が得られず、半田
バンプの接合性が低下するという不具合が生じ、５０重
量部を越えるとマイグレーションや耐湿劣化などにつな
がる可能性があるためである。The amount of the substance having the flux action added is preferably 10 to 50 parts by weight with respect to 100 parts by weight of the liquid thermosetting resin as the main component. This is because if the amount is less than 10 parts by weight, sufficient flux activity cannot be obtained and the bondability of the solder bumps deteriorates, and if it exceeds 50 parts by weight, migration or moisture resistance deterioration may occur.
【００１５】また、特性を向上させるためにフィラーを
添加することが出来る。その例としては、シリカ、炭酸
カルシウム、アルミナ、窒化アルミ等が挙げられる。ま
た熱硬化性樹脂が固形の場合、予め溶剤に溶かして使用
することも出来る。更に低応力剤等添加することが出来
る。A filler may be added to improve the characteristics. Examples thereof include silica, calcium carbonate, alumina, aluminum nitride and the like. When the thermosetting resin is solid, it can be used by dissolving it in a solvent in advance. Further, a low stress agent or the like can be added.
【００１６】本発明で特徴的なのは、比較して凹凸が多
い半導体チップ側に封止樹脂材料を塗布することであ
り、これにより、回路基板側の半導体素子接合部に多少
の凹凸が存在しても、エアの巻き込みの低減やフィラー
の噛み込みを低減できることになる。半導体チップ側に
封止樹脂材料を塗布する方法は、ディスペンサーによる
塗布、スクリーン印刷法、スピンコート法等通常の塗布
方法を用いることができる。半導体チップ側に塗布する
封止樹脂材料の量としては、半導体素子を覆う程度、例
えば、平均塗布量が０．５〜４ｍｇ/ｍｍ2となるのが好
ましい。塗布量が少なく、０．５ｍｇ/ｍｍ2未満である
と半導体素子が全て封止樹脂材料で覆われず、樹脂材料
封止部に未充填部が生じたり信頼性に悪影響を及ぼす可
能性があり、また、塗布量が多く、４ｍｇ/ｍｍ2を越え
ると封止樹脂材料の圧接時のはみ出しや半導体チップへ
の這い上がりを生じてしまう可能性がある。A feature of the present invention is that the encapsulating resin material is applied on the side of the semiconductor chip which has more irregularities than that of the semiconductor chip. Also, it is possible to reduce air entrapment and filler entrapment. As a method of applying the sealing resin material to the semiconductor chip side, a usual application method such as application with a dispenser, screen printing method, spin coating method or the like can be used. The amount of the sealing resin material applied to the semiconductor chip side is preferably such that the semiconductor element is covered, for example, the average applied amount is 0.5 to 4 mg / mm 2 . If the coating amount is small and less than 0.5 mg / mm 2 , the semiconductor element may not be entirely covered with the encapsulating resin material, which may cause an unfilled portion in the resin material encapsulating portion and adversely affect reliability. Further, if the coating amount is large and exceeds 4 mg / mm 2 , there is a possibility that the sealing resin material may squeeze out during pressure contact and may crawl onto the semiconductor chip.
【００１７】封止樹脂材料を塗布する工程の後、エアの
巻き込みを少なくする為に、塗布後、接合の工程前に、
封止樹脂材料を減圧下に置き材料中に含まれるエアをあ
らかじめ脱泡除去する工程を含んでいても差し支えな
い。減圧の条件としては、例えば、５Ｔｏｒｒ以下で、
０．５時間程度行う。After the step of applying the sealing resin material, in order to reduce the entrainment of air, after application and before the step of joining,
The step of placing the sealing resin material under reduced pressure and removing the air contained in the material in advance may be included. The depressurization condition is, for example, 5 Torr or less,
Perform for about 0.5 hours.
【００１８】次ぎに半導体チップと半導体チップ上の半
田バンプに対応したパッド部を有する回路基板とを位置
合わせする。位置合わせに用いる装置としては、通常の
フリップチップボンダーを用いることができる。本発明
をフリップチップボンダーを用いて実施する際、通常回
路基板を設置するステージ側にチップを設置しても差し
支えない。Next, the semiconductor chip and the circuit board having the pad portions corresponding to the solder bumps on the semiconductor chip are aligned. A normal flip chip bonder can be used as the device used for the alignment. When the present invention is carried out using the flip chip bonder, the chip may be installed on the stage side where the circuit board is normally installed.
【００１９】次ぎにフリップチップボンダーを用いて圧
接する。圧接時の条件としては、通常圧力が２ｇ〜３０
ｇ/ｂｕｍｐ、時間が２〜１０秒である。圧力が２ｇ未
満であると、十分にチップと基板が接触せず、接合不良
を及ぼす懸念があり、３０ｇを越えると、バンプがつぶ
れてしまうという懸念がある。また時間が２秒未満であ
ると圧力が十分にかからない可能性があり、１０秒を越
えると過剰な圧力がかかる可能性がある。Next, pressure welding is performed using a flip chip bonder. As the condition for pressure welding, the normal pressure is 2 g to 30
g / bump, time is 2 to 10 seconds. If the pressure is less than 2 g, the chip and the substrate may not be sufficiently contacted with each other, which may result in defective bonding, and if the pressure exceeds 30 g, the bump may be crushed. If the time is less than 2 seconds, sufficient pressure may not be applied, and if it exceeds 10 seconds, excessive pressure may be applied.
【００２０】次ぎにチップと回路基板を加熱工程により
加熱接合する。加熱接合する方法としては、例えば、リ
フロー、パルスヒート等により行われる。加熱接合の条
件として、例えばリフローであれば、半田の組成により
適切な温度は異なるが、組成が共晶半田の場合、ピーク
温度２００〜２４０℃で、２〜８分間加熱を行う。パル
スヒートであれば、ピーク温度２００〜２４０℃で２〜
１５秒程度行う。本発明の組立方法以外の半導体装置の
組立方法は公知の方法を用いることができる。Next, the chip and the circuit board are heat-bonded by a heating process. The method of heating and joining is performed by, for example, reflow, pulse heating, or the like. As a condition for heat bonding, for example, in the case of reflow, an appropriate temperature differs depending on the composition of the solder, but when the composition is eutectic solder, heating is performed at a peak temperature of 200 to 240 ° C. for 2 to 8 minutes. If it is pulse heat, the peak temperature is 200 to 240 ° C.
Do it for about 15 seconds. As a method of assembling a semiconductor device other than the assembling method of the present invention, a known method can be used.
【００２１】[0021]
【実施例】＜実施例１−３、比較例１−２＞使用する液
状封止樹脂に関しては、表１の処方に従って秤量し、ミ
キサーにて混練し、真空脱泡後、液状樹脂組成物を作製
した。次に特性を把握するため以下の代用特性を評価し
た。
（１）常態粘度：２５℃において東機産業（株）製Ｅ型
粘度計で初期粘度（コーン回転数２．５ｒｐｍ）及び２
５℃における０．５ｒｐｍ/２．５ｒｐｍという比をチ
キソ比とした。
（２）半田濡れ性：樹脂組成物のフラックス活性を判断
する目安として、厚さ２５０μｍのベア銅フレームに作
製した液状樹脂組成物を滴下し、その上に直径０．８５
ｍｍの共晶半田ボールを静置した。それを２００℃に加
熱したホットプレート上に静置し、半田ボールのつぶれ
方を観測した。そのサンプルよりつぶれた半田高さと広
がり幅の比をアスペクト比として計算した。Examples <Example 1-3, Comparative Example 1-2> Regarding the liquid encapsulating resin to be used, the liquid resin composition was weighed according to the formulation in Table 1, kneaded with a mixer, and vacuum degassed to obtain a liquid resin composition. It was made. Next, the following substitute characteristics were evaluated in order to grasp the characteristics. (1) Normal viscosity: at 25 ° C., using an E-type viscometer manufactured by Toki Sangyo Co., Ltd., an initial viscosity (cone rotation speed: 2.5 rpm) and 2
The ratio of 0.5 rpm / 2.5 rpm at 5 ° C was defined as the thixo ratio. (2) Solder wettability: As a standard for determining the flux activity of the resin composition, the liquid resin composition prepared was dropped on a bare copper frame having a thickness of 250 μm, and a diameter of 0.85 was applied onto it.
The mm eutectic solder balls were left to stand. It was left standing on a hot plate heated to 200 ° C., and how the solder balls were crushed was observed. The aspect ratio was calculated as the ratio of the solder height and spread width that were crushed from the sample.
【００２２】（３）半田バンプ接合率：住商化成社製の
バンプ付きチップ（サイズ：１０ｍｍ×１０ｍｍ，バン
プ数：９００）、また対となる厚み０．７５ｍｍの回路
基板（サイズ：２０ｍｍ×２０ｍｍ）を用い、チップ又
は回路基板上にオートディスペンサーを用いて液状封止
樹脂組成物を塗布した。塗布量は２．５ｍｇ/ｍｍ2とし
た。次ぎにチップと回路基板の位置合わせを澁谷工業社
製フリップチップボンダーを用いて行った後、両者を圧
接させた。圧接の条件としては、圧力２０ｇ／ｂｕｍ
ｐ、圧接時間３秒で行った。マウントスピードは５００
μｍ／秒で行った。圧接したサンプルをピーク温度２３
０℃、１８３℃以上の時間が６０ｓｅｃ、トータル時間
が３００ｓｅｃのプロファイルを有するリフローに通し
てバンプの熱圧着を行った。その後、バンプの接合性を
テスターにより観察した。
（４）内部ボイド観察：日立製作所社製のＳＡＴを用い
て内部ボイドの観察を行った。(3) Solder bump bonding rate: Chips with bumps (size: 10 mm x 10 mm, number of bumps: 900) manufactured by Sumisho Chemical Co., Ltd., and a pair of 0.75 mm thick circuit boards (size: 20 mm x 20 mm) And the liquid encapsulating resin composition was applied onto the chip or the circuit board using an auto dispenser. The coating amount was 2.5 mg / mm 2 . Next, the chip and the circuit board were aligned with each other by using a Flip Chip Bonder manufactured by Shibuya Kogyo Co., Ltd., and then the two were pressed against each other. The pressure welding condition is a pressure of 20 g / bum.
p and pressure contact time was 3 seconds. Mount speed is 500
μm / sec. The peak temperature of the pressed sample is 23
The bumps were thermocompression bonded through a reflow process having a profile in which the time was 0 ° C., 183 ° C. or higher for 60 seconds, and the total time was 300 seconds. Then, the bondability of the bumps was observed with a tester. (4) Observation of internal voids: The internal voids were observed using Hitachi's SAT.
【００２３】＜実施例３＞表１の処方に従い実施例２と
同様にして液状樹脂組成物を作製した。この液状樹脂組
成物は実施例２と同様に評価を行ったが、半田バンプ接
合率のみ次のように試料を作成し、評価を行った。液状
樹脂組成物を実施例２と同様に基板側に塗布した後、真
空圧５Ｔｏｒｒ以下、０．５時間の条件下で液状樹脂組
成物中の空気を脱泡除去する工程を実施した。その後の
工程は実施例２と同様に実施して半導体装置を組み立て
た。Example 3 A liquid resin composition was prepared in the same manner as in Example 2 according to the formulation shown in Table 1. This liquid resin composition was evaluated in the same manner as in Example 2, but a sample was prepared in the following manner only for the solder bump bonding rate and evaluated. After the liquid resin composition was applied to the substrate side in the same manner as in Example 2, a step of removing air from the liquid resin composition by defoaming was carried out under a vacuum pressure of 5 Torr or less and 0.5 hour. Subsequent steps were carried out in the same manner as in Example 2 to assemble a semiconductor device.
【００２４】実施例に用いた原材料の内容は下記のとお
りである。
・ビスフェーノールＦ型エポキシ樹脂：粘度；２，００
０ｍＰａ・ｓ（２５℃）
・フェノール樹脂系硬化剤：フラックス特性を有するフ
ェノール性硬化剤として、２，５-ヒドロキシ安息香酸
を用いた。The contents of the raw materials used in the examples are as follows. -Bisphenol F type epoxy resin: viscosity; 2,000
0 mPa · s (25 ° C.) Phenolic resin curing agent: 2,5-hydroxybenzoic acid was used as a phenolic curing agent having flux characteristics.
【００２５】上記の測定結果を表１に示す。Table 1 shows the above measurement results.
【表１】
＊１ 球状シリカ：平均粒径：２μｍ、最大粒径：１０
μｍ[Table 1] * 1 Spherical silica: average particle size: 2 μm, maximum particle size: 10
μm
【００２６】表１に示したように、実施例１〜３ではバ
ンプ付きチップ搭載時にミクロエアを巻き込みやすい半
導体チップ側にあらかじめ封止樹脂材料を塗布すること
でミクロエアの巻き込みが原因であるＰＫＧ（パッケー
ジ）内のボイドが少なくることが分かり、それは実施例
２のように高粘度でミクロエアを抱き込みやすい材料に
も有効であることが分かった。更に、実施例３で示す様
に、脱泡工程を加えることによってより効果があること
が分かった。一方、比較例１では通常の回路基板側に塗
布を行ったが、実施例１と同一条件にもかかわらずマウ
ントスピードが速い為か、ミクロエアの抱きこみと考え
られるＰＫＧ内ボイドが多く観察された。これらの誘発
により、チップリフティングが起こったため、半田バン
プ接合率も低下してしまうことが分かった。また比較例
２ではフィラーの噛み込みと思われる接合不良も確認さ
れ、半田バンプ接合率も低いという結果が得られた。こ
れらを解決する為には、マウントスピードを下げること
も解決の１つだと考えられるが、生産性を考えれば、マ
ウントスピードは速い方が望ましいと考えられるため、
好ましくない。As shown in Table 1, in Examples 1 to 3, the encapsulation resin material is applied in advance to the semiconductor chip side where the micro-air is likely to be entrapped when the chip with bumps is mounted. It was found that the number of voids in () was small, and it was also found to be effective for a material having a high viscosity and easily containing micro air as in Example 2. Further, as shown in Example 3, it was found that the addition of the defoaming step was more effective. On the other hand, in Comparative Example 1, the coating was performed on the normal circuit board side, but despite the same conditions as in Example 1, many voids in the PKG which were considered to be the inclusion of micro air were observed, probably because the mount speed was high. . It was found that the chip lifting occurred due to these inductions, and the solder bump bonding rate also decreased. Further, in Comparative Example 2, a joining defect that was considered to be a biting of the filler was also confirmed, and the result that the solder bump joining rate was low was obtained. In order to solve these problems, lowering the mount speed is considered to be one of the solutions, but from the viewpoint of productivity, it is considered that higher mount speed is desirable,
Not preferable.
【００２７】[0027]
【発明の効果】本発明の半導体装置の組立方法を用いる
ことにより、非常に高い半田バンプ接合率、ボイドレス
のパッケージを得ることができ、その工業的メリットは
大きい。By using the method for assembling a semiconductor device according to the present invention, a package having a very high solder bump bonding rate and voidless can be obtained, and its industrial merit is great.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０５Ｋ 3/34 ５０３ Ｈ０１Ｌ 23/30 Ｒ ５０７ ─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. 7 Identification Code FI Theme Coat (Reference) H05K 3/34 503 H01L 23/30 R 507
Claims (6)
半田バンプを有する多数個の半導体素子が形成された半
導体チップ上にあらかじめフラックス作用を有するノン
フローアンダーフィル材料を塗布する工程、（２）該半
導体チップと該半導体チップ上の半田バンプに対応した
パッド部を有する回路基板とを位置合わせする工程、
（３）該半導体チップと該回路基板を圧接する工程、
（４）該半導体チップと該回路基板を熱圧着する工程よ
りなることを特徴とする半導体装置の組立方法。(1) A step of applying a non-flow underfill material having a flux function in advance on a semiconductor chip on which a large number of semiconductor elements having solder bumps for electrically connecting to a circuit board are formed, 2) a step of aligning the semiconductor chip with a circuit board having pad portions corresponding to solder bumps on the semiconductor chip,
(3) a step of press-contacting the semiconductor chip and the circuit board,
(4) A method of assembling a semiconductor device, which comprises a step of thermocompression bonding the semiconductor chip and the circuit board.
る方法が、ディスペンスもしくはスクリーン印刷により
行われる請求項１記載の半導体装置の組立方法。2. The method for assembling a semiconductor device according to claim 1, wherein the method of applying the non-flow underfill material is performed by dispensing or screen printing.
る工程の後に、該ノンフローアンダーフィル材料の樹脂
中の空気を脱泡除去する工程を含む請求項１記載の半導
体装置の組立方法。3. The method for assembling a semiconductor device according to claim 1, further comprising a step of degassing and removing air in the resin of the non-flow underfill material after the step of applying the non-flow underfill material.
法が、リフロー又はパルスヒートにより行われる請求項
１記載の半導体装置の組立方法。4. The method of assembling a semiconductor device according to claim 1, wherein the method of thermocompression bonding the semiconductor chip and the circuit board is performed by reflow or pulse heating.
キシ樹脂系、またはシアネート樹脂系である請求項１記
載の半導体装置の組立方法。5. The method of assembling a semiconductor device according to claim 1, wherein the non-flow underfill material is an epoxy resin type or a cyanate resin type.
装置の組立方法を用いて作製された半導体装置。6. A semiconductor device manufactured by using the method for assembling a semiconductor device according to claim 1.
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|---|---|---|---|
| JP2001280920A JP2003086627A (en) | 2001-09-17 | 2001-09-17 | Method for assembling semiconductor device and semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001280920A JP2003086627A (en) | 2001-09-17 | 2001-09-17 | Method for assembling semiconductor device and semiconductor device |
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|---|---|
| JP2003086627A true JP2003086627A (en) | 2003-03-20 |
Family
ID=19104835
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001280920A Pending JP2003086627A (en) | 2001-09-17 | 2001-09-17 | Method for assembling semiconductor device and semiconductor device |
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| JP (1) | JP2003086627A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019208614A1 (en) * | 2018-04-26 | 2019-10-31 | 三菱瓦斯化学株式会社 | Resin composition, laminate, resin composition layer-attached semiconductor wafer, substrate for mounting resin composition layer-attached semiconductor, and semiconductor device |
-
2001
- 2001-09-17 JP JP2001280920A patent/JP2003086627A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019208614A1 (en) * | 2018-04-26 | 2019-10-31 | 三菱瓦斯化学株式会社 | Resin composition, laminate, resin composition layer-attached semiconductor wafer, substrate for mounting resin composition layer-attached semiconductor, and semiconductor device |
| JPWO2019208614A1 (en) * | 2018-04-26 | 2021-05-20 | 三菱瓦斯化学株式会社 | Resin composition, laminate, semiconductor wafer with resin composition layer, semiconductor mounting substrate with resin composition layer, and semiconductor device |
| JP7344471B2 (en) | 2018-04-26 | 2023-09-14 | 三菱瓦斯化学株式会社 | Resin composition, laminate, semiconductor wafer with resin composition layer, semiconductor mounting substrate with resin composition layer, and semiconductor device |
| US11935803B2 (en) | 2018-04-26 | 2024-03-19 | Mitsubishi Gas Chemical Company, Inc. | Resin composition, laminate, semiconductor wafer with resin composition layer, substrate for mounting semiconductor with resin composition layer and semiconductor device |
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