JP2003078069A - Pseudo wafer for multichip module production and production method therefor - Google Patents

Pseudo wafer for multichip module production and production method therefor

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Publication number
JP2003078069A
JP2003078069A JP2001269051A JP2001269051A JP2003078069A JP 2003078069 A JP2003078069 A JP 2003078069A JP 2001269051 A JP2001269051 A JP 2001269051A JP 2001269051 A JP2001269051 A JP 2001269051A JP 2003078069 A JP2003078069 A JP 2003078069A
Authority
JP
Japan
Prior art keywords
resin layer
chip
wafer
pseudo wafer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001269051A
Other languages
Japanese (ja)
Other versions
JP4724988B2 (en
Inventor
Yuji Takaoka
裕二 高岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
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Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2001269051A priority Critical patent/JP4724988B2/en
Publication of JP2003078069A publication Critical patent/JP2003078069A/en
Application granted granted Critical
Publication of JP4724988B2 publication Critical patent/JP4724988B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a pseudo wafer with which handling can be easy by a conventional wafer handling device without deformation such as warping. SOLUTION: A pseudo wafer 70 is provided with a silicon wafer 72, a resin layer 74 with a circular cross section adhered on the silicon wafer 72 by an adhesive agent, and a plurality of semiconductor chips 76 buried in the resin layer 74 while exposing electrode planes on the surface of the resin layer 74 on the side opposed to the silicon wafer 72. Each of semiconductor chips is one already confirmed as a good product by an examination. Since this pseudo wafer is lined on the rear side of the resin layer by the silicon wafer, deformation such as warping is suppressed differently from a conventional pseudo wafer. Further, since the outer form of the pseudo wafer is specified by the silicon wafer in the case of handling the pseudo wafer, the conventional wafer handling device can be used as it is.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、マルチチップモジ
ュール作製用の疑似ウエハ、及びその作製方法に関し、
更に詳細には、反り等の変形が発生せず、従来のウエハ
・ハンドリング装置により容易にハンドリングできるよ
うにした疑似ウエハ、及びその作製方法に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo wafer for manufacturing a multi-chip module and a method for manufacturing the same.
More specifically, the present invention relates to a pseudo wafer which is not deformed such as warped and can be easily handled by a conventional wafer handling apparatus, and a manufacturing method thereof.

【０００２】[0002]

【従来の技術】半導体装置の高密度実装の要求に伴い、
パッケージＩＣの小型化を図るために、ＱＦＰ（Quad F
lat Package）等の従来のパッケージＩＣに代る新しい
パッケージＩＣの開発が求められている。そして、新し
いパッケージＩＣの一つとして、ＣＳＰ（Chip Scale P
ackage）が開発され、一部実用化されつつあるものの、
ベアチップでフリップチップ方式による実装が可能なＩ
Ｃが求められている。2. Description of the Related Art With the demand for high-density mounting of semiconductor devices,
QFP (Quad F
It is required to develop a new package IC such as a lat package) that replaces the conventional package IC. And as one of the new package ICs, CSP (Chip Scale P
ackage) has been developed and is partly in practical use,
I can be mounted by flip chip method with bare chip
C is required.

【０００３】そこで、デジタル電子機器の回路ブロック
が、特定の回路構成の特定回路ブロックと、他のデジタ
ル電子機器と共通の回路構成の共通回路ブロックとで構
成されていることが多いことに注目して、半導体装置を
構成する回路ブロックをマルチチップパッケージ化、つ
まりマルチチップモジュール（ＭＣＭ：Multi Chip Mod
ule）化することが試みられている。例えば、デジタル
携帯電話では、ＳＲＡＭ（スタティック・ラム）、フラ
ッシュメモリー、マイクロコンピュータ等の各半導体素
子を１個のパッケージとしたマルチチップモジュール化
が進められている。Therefore, it is noted that the circuit block of the digital electronic device is often composed of a specific circuit block having a specific circuit configuration and a common circuit block having a circuit configuration common to other digital electronic devices. Circuit blocks that form a semiconductor device are packaged in a multi-chip package, that is, a multi-chip module (MCM: Multi Chip Module).
ule) is being attempted. For example, in digital mobile phones, a multi-chip module is being developed in which each semiconductor element such as SRAM (static RAM), flash memory, and microcomputer is packaged in one package.

【０００４】特に、最近の１チップシステムＬＳＩの分
野では、ＭＣＭ技術は、システムＬＳＩの１チップパッ
ケージ化にとって極めて有力で効果的な技術である。例
えば、メモリー素子、ロジック素子、更にはアナログＬ
ＳＩを１チップ化する場合、従来のやり方で１チップ化
しようとすると、各素子の構成に対応する異なったＬＳ
Ｉ加工プロセスを同一ウエハに施すことが必要になるの
で、マスク数やプロセス工程数が著しく増加してコスト
の増大を招き、また開発ＴＡＴ（Turnaround time）の
長期化が問題となり、製品歩留りの低下も懸念される。
そこで、各素子、ＬＳＩを個別に作り、ワイヤボンディ
ング方式により、或いはフリップチップ方式により、Ｍ
ＣＭ化する方式が提案されている。Particularly, in the field of recent one-chip system LSI, the MCM technology is a very effective and effective technology for one-chip packaging of the system LSI. For example, memory element, logic element, and analog L
When SI is integrated into one chip, if the conventional method is to be integrated into one chip, different LS corresponding to the configuration of each element is required.
Since it is necessary to perform the I machining process on the same wafer, the number of masks and the number of process steps increase remarkably, resulting in an increase in cost. Further, the development TAT (Turnaround time) becomes a problem and the product yield decreases. Is also concerned.
Therefore, each element and LSI are individually manufactured, and the M
A method of creating a commercial has been proposed.

【０００５】ここで、図３を参照して、ワイヤボンディ
ング方式のＭＣＭの構成を説明する。図３（ａ）及び
（ｂ）は、それぞれ、ワイヤボンディング方式のＭＣＭ
の構成を示す斜視図及び断面図である。ワイヤボンディ
ング方式のＭＣＭ１０は、図３に示すように、裏面に電
極１１を有し、表面に電極１１と接続する配線パターン
（図示せず）を有する回路基板１２と、回路基板１２上
にダイボンディングされ、かつ回路基板１２上の配線パ
ターンに金線等のワイヤ１３によりワイヤボンディング
された半導体チップ１４Ａ〜Ｃとから構成されている。The configuration of the wire bonding type MCM will be described with reference to FIG. 3A and 3B are wire bonding type MCMs, respectively.
3 is a perspective view and a cross-sectional view showing the configuration of FIG. As shown in FIG. 3, the wire bonding type MCM 10 has a circuit board 12 having an electrode 11 on the back surface and a wiring pattern (not shown) connected to the electrode 11 on the front surface, and die bonding on the circuit board 12. And the semiconductor chips 14A to 14C which are wire-bonded to the wiring pattern on the circuit board 12 by the wires 13 such as gold wires.

【０００６】次に、図４を参照して、フリップチップ方
式のＭＣＭの構成を説明する。図４（ａ）及び（ｂ）
は、それぞれ、フリップチップ方式のＭＣＭの構成を示
す斜視図及び断面図である。フリップチップ方式のＭＣ
Ｍ２０は、図４に示すように、裏面に電極２２、電極２
２と電気的に接続する接合電極２４を接合面に有する回
路基板２６と、回路基板２６の接合電極２４にバンプ２
８を介してフリップチップ方式でフェイスダウンで接合
させた半導体チップ３０Ａ〜Ｃとから構成され、半導体
チップ３０Ａ〜Ｃと回路基板２６との間はアンダーフィ
ル材３２で充填されている。ＭＣＭの薄型化及び小型化
のためには、フリップチップ方式が、ワイヤボンディン
グ方式に比べて有利であって、今後、フリップチップ方
式が主流となると思われる。Next, the structure of the flip-chip type MCM will be described with reference to FIG. 4 (a) and (b)
FIG. 3A is a perspective view and a cross-sectional view, respectively, showing the configuration of a flip-chip type MCM. Flip chip MC
As shown in FIG. 4, M20 includes electrodes 22, 2 on the back surface.
Circuit board 26 having a bonding electrode 24 electrically connected to the bonding surface 24 on the bonding surface, and bump 2 on bonding electrode 24 of circuit board 26.
8 and the semiconductor chips 30A to 30C that are joined face down by a flip chip method, and an underfill material 32 is filled between the semiconductor chips 30A to 30C and the circuit board 26. The flip chip method is more advantageous than the wire bonding method for making the MCM thinner and smaller, and the flip chip method is expected to become the mainstream in the future.

【０００７】[0007]

【発明が解決しようとする課題】ところで、フリップチ
ップ方式のＭＣＭを作製するには、各半導体チップにバ
ンプを形成することが必要であるが、ベアチップの形態
の個々の半導体チップにバンプを形成するやり方は、ウ
エハ単位でウエハの各半導体チップにバンプを形成する
やり方に比べて、著しくコスト高になる。つまり、ウエ
ハ上に形成されている半導体チップにウエハ毎に一括し
てバンプを形成するやり方が、技術的にもコスト的にも
好ましい。しかし、ウエハ毎に一括してバンプを形成す
る際には、ウエハ上の半導体チップが良品であろうと不
良品であろうと、全半導体チップを一括して処理するの
で、最終的な製品であるＭＣＭの製品歩留りが悪いとい
う問題があった。ここでは、バンプ形成を例に上げて説
明しているが、ＭＣＭに配線構造を形成する際にも、同
様のことが該当する。By the way, in order to manufacture a flip-chip type MCM, it is necessary to form bumps on each semiconductor chip. However, bumps are formed on individual semiconductor chips in the form of bare chips. The method is significantly more expensive than the method of forming bumps on each semiconductor chip of the wafer on a wafer-by-wafer basis. That is, it is technically and cost-effective to collectively form bumps for each wafer on the semiconductor chips formed on the wafer. However, when the bumps are collectively formed on each wafer, all semiconductor chips are collectively processed regardless of whether the semiconductor chips on the wafer are good products or defective products. There was a problem that the product yield was poor. Here, the bump formation is described as an example, but the same applies when the wiring structure is formed on the MCM.

【０００８】そこで、合格率の低い最先端のＬＳＩであ
っても、ウエハ一括処理の利点を活かしつつ、複数個の
最先端のＬＳＩからなるＭＣＭを高い信頼性、高歩留
り、低コストで作製するために、いわゆる疑似ウエハを
形成する方法が、提案されている。即ち、少なくとも電
極が一方の面上にのみ設けられ、この一方の面以外の全
面が連続した保護物質で覆われている半導体チップ等の
チップ状電子部品の複数個又は複数種が、これらのチッ
プ状電子部品の間及びその裏面に連続して被着された保
護物質によって互いに固着されている疑似ウエハであ
る。Therefore, even for the most advanced LSI with a low pass rate, an MCM composed of a plurality of the most advanced LSIs can be manufactured with high reliability, high yield, and low cost while taking advantage of the wafer batch processing. Therefore, a method of forming a so-called pseudo wafer has been proposed. That is, at least an electrode is provided only on one surface, and a plurality or a plurality of kinds of chip-shaped electronic components such as a semiconductor chip in which the entire surface other than this one surface is covered with a continuous protective substance is used. It is a pseudo wafer fixed to each other by a protective substance continuously applied between the electronic components and the back surface thereof.

【０００９】ここで、図５を参照して、上述の疑似ウエ
ハの構成を更に説明する。図５（ａ）及び（ｂ）は、そ
れぞれ、疑似ウエハの構成を示す斜視図である。疑似ウ
エハ４０は、図５（ａ）に示すように、良品の半導体ベ
アチップ４２のみを、電極面を露出させて、円形の樹脂
製基板４４に埋め込んだものである。半導体チップ４２
は、集積回路を形成したウエハをダイシングし、チップ
化して得た、ＬＳＩチップ、メモリチップ等の半導体チ
ップにオープン／ショート検査、ＤＣ（直流）電圧測定
試験等の検査を施し、良品と確認された半導体チップで
ある。また、疑似基板４０は、図５（ｂ）に示すよう
に、円形の樹脂基板ではなく、方形の樹脂製基板４６に
埋め込んだ形でも良い。The structure of the above pseudo wafer will be further described with reference to FIG. 5A and 5B are perspective views showing the structure of the pseudo wafer. As shown in FIG. 5A, the pseudo wafer 40 is formed by embedding only a good semiconductor bare chip 42 in a circular resin substrate 44 with its electrode surface exposed. Semiconductor chip 42
Is a good product after the semiconductor chips such as LSI chips and memory chips obtained by dicing the wafer on which the integrated circuit is formed are subjected to inspections such as open / short inspection and DC (direct current) voltage measurement test. It is a semiconductor chip. Further, as shown in FIG. 5B, the pseudo substrate 40 may be embedded in a rectangular resin substrate 46 instead of the circular resin substrate.

【００１０】以下に、図６から図８を参照して、疑似ウ
エハ４０の作製方法及びその利用方法を説明する。図６
（ａ）から（ｄ）は、それぞれ、疑似ウエハを作製する
際の工程毎の断面図であり、図７（ｅ）から（ｇ）、及
び図８（ｈ）から（ｊ）は、疑似ウエハを利用する際の
工程毎の断面図である。図６（ａ）に示すように、仮の
支持基板となる石英基板４８上に、紫外線が照射される
と、粘着力が低下する粘着シート５０を貼り付ける。粘
着シート５０は、例えば、ウエハプロセスの通常のダイ
シング工程で用いられている、例えばアクリル系の粘着
シートである。尚、石英基板に代えて、安価なガラス基
板を使用することもできる。A method of manufacturing the pseudo wafer 40 and a method of using the pseudo wafer 40 will be described below with reference to FIGS. 6 to 8. Figure 6
FIGS. 7A to 7D are cross-sectional views of respective steps in manufacturing the pseudo wafer, and FIGS. 7E to 7G and FIGS. 8H to 8J are pseudo wafers. It is sectional drawing for every process at the time of utilizing. As shown in FIG. 6A, an adhesive sheet 50 whose adhesive strength decreases when irradiated with ultraviolet rays is adhered onto a quartz substrate 48 serving as a temporary support substrate. The pressure-sensitive adhesive sheet 50 is, for example, an acrylic pressure-sensitive adhesive sheet used in a normal dicing process of a wafer process. Note that an inexpensive glass substrate can be used instead of the quartz substrate.

【００１１】次に、図６（ｂ）に示すように、良品と確
認した複数個の半導体チップ４２を、チップ表面（電極
面）を下にして所定の配列で粘着シート５０に貼り付け
る。ここで重要なことは、良品の半導体チップのみを石
英基板４８上に貼り付けることである。次に、図６
（ｃ）のように、半導体チップ４２上から有機系絶縁性
樹脂、例えばアクリル系等の樹脂をスピンコート法又は
印刷法等で均一に塗布して樹脂層５２を形成する。次
に、図６（ｄ）に示すように、石英基板４８の裏側４８
ａから紫外線を照射して、粘着シート５０の粘着力を低
下させて、粘着シート５０の粘着面５０ａから樹脂層５
２及び半導体チップ４２を剥離して、樹脂層５２によっ
て側面及び裏面が固められた複数の半導体チップ４２か
らなる疑似ウエハ４０を作製することができる。Next, as shown in FIG. 6B, a plurality of semiconductor chips 42 confirmed to be non-defective are attached to the adhesive sheet 50 in a predetermined arrangement with the chip surface (electrode surface) facing down. What is important here is that only good semiconductor chips are attached onto the quartz substrate 48. Next, FIG.
As shown in (c), an organic insulating resin, such as an acrylic resin, is uniformly applied on the semiconductor chip 42 by a spin coating method or a printing method to form a resin layer 52. Next, as shown in FIG. 6D, the back side 48 of the quartz substrate 48 is
a to irradiate the resin layer 5 from the adhesive surface 50a of the adhesive sheet 50 to reduce the adhesive force of the adhesive sheet 50.
2 and the semiconductor chip 42 can be peeled off, and the pseudo wafer 40 including the plurality of semiconductor chips 42 whose side surface and back surface are solidified by the resin layer 52 can be manufactured.

【００１２】次に、図７（ｅ）のように、半導体チップ
４２の表面４２ａ（電極面）が上向きになるように疑似
ウエハ４０をひっくり返して、表裏を逆にする。疑似ウ
エハ４０に保持されている半導体チップ４２は、図７
（ｅ）の拡大図に示すように、Ｓｉ基板上にＳｉＯ2膜
４２ｄを介してＡｌ電極パッド４２ｂが形成され、更
に、Ａｌ電極パッド４２ｂ及びＳｉＯ2 膜４２ｄは、Ａ
ｌ電極パッド４２ｂの上面を除いて、パッシベーション
膜４２ｃで被覆されている。次に、図７（ｆ）に示すよ
うに、Ａｌ電極パッド４２ｂの露出した上面のみに、Ｎ
ｉ無電解めっき法により選択的にＮｉ無電解めっき層
（ＵＢＭ、Under BumpMetal）５３を形成する。次い
で、図７（ｇ）に示すように、印刷マスク５４を当て
て、はんだペースト５６を印刷法によりＮｉ無電解めっ
き層（ＵＢＭ）５３上に転写する。Next, as shown in FIG. 7E, the pseudo wafer 40 is turned over so that the surface 42a (electrode surface) of the semiconductor chip 42 faces upward, and the front and back are turned upside down. The semiconductor chip 42 held on the pseudo wafer 40 is shown in FIG.
As shown in the enlarged view of (e), the Al electrode pad 42b is formed on the Si substrate via the SiO 2 film 42d, and the Al electrode pad 42b and the SiO 2 film 42d are
The l electrode pad 42b is covered with a passivation film 42c except the upper surface. Next, as shown in FIG. 7F, N is formed only on the exposed upper surface of the Al electrode pad 42b.
An Ni electroless plating layer (UBM, Under Bump Metal) 53 is selectively formed by an i electroless plating method. Next, as shown in FIG. 7G, a printing mask 54 is applied and the solder paste 56 is transferred onto the Ni electroless plating layer (UBM) 53 by a printing method.

【００１３】続いて、図８（ｈ）に示すように、ウエッ
トバック（加熱溶融）法ではんだペースト５６を溶融し
て、はんだバンプ５８を形成する。このように、Ｎｉ無
電解めっき法及びはんだペーストスクリーン印刷法等を
用いることにより、フォトプロセスを用いることなく、
容易にはんだバンプ５８を形成することができる。な
お、このＮｉ無電解めっき層（ＵＢＭ）５３は、Ａｌ電
極パッド４２ｂの上面をリン酸系エッチ液で前処理した
後に、Ｚｎ処理によりＺｎを置換析出させ、さらにＮｉ
−Ｐめっき層に浸漬させることにより、容易に形成で
き、Ａｌ電極パッド４２ｂとはんだバンプとの接続を助
けるＵＢＭ（Under Bump Metal）として作用する。Subsequently, as shown in FIG. 8H, the solder paste 56 is melted by a wet back (heating and melting) method to form solder bumps 58. Thus, by using the Ni electroless plating method and the solder paste screen printing method, etc., without using a photo process,
The solder bumps 58 can be easily formed. The Ni electroless plating layer (UBM) 53 is formed by pre-treating the upper surface of the Al electrode pad 42b with a phosphoric acid-based etchant, and then Zn-displacement by Zn treatment.
It can be easily formed by immersing it in the -P plating layer, and acts as a UBM (Under Bump Metal) that helps the connection between the Al electrode pad 42b and the solder bump.

【００１４】次いで、図８（ｉ）に示すように、疑似ウ
エハ４０をスクライブライン６０に沿ってブレード６４
等でダイシングして、複数個の半導体チップ４２を有す
るマルチチップモジュール（ＭＣＭ）６６を作製する。
続いて、図８（ｊ）に示すように、フリップチップ方式
によりＭＣＭ６６をフェイスダウンで、ソルダー（はん
だ）ペーストを有する配線基板６８上に位置決めし、リ
フロー法等によりはんだ接合する。Next, as shown in FIG. 8 (i), the dummy wafer 40 is moved along the scribe line 60 by the blade 64.
Etc., dicing is performed to produce a multi-chip module (MCM) 66 having a plurality of semiconductor chips 42.
Subsequently, as shown in FIG. 8J, the MCM 66 is positioned face down by the flip chip method on the wiring board 68 having the solder (solder) paste, and soldered by the reflow method or the like.

【００１５】しかし、上述した方法のように、スピンコ
ート法又は印刷法により樹脂を塗布し、半導体チップを
樹脂で埋め固め、いわゆる疑似ウエハするやり方には、
以下の問題があった。第１の問題は、樹脂層を硬化させ
る再、樹脂層の収縮等によって疑似ウエハに反り等の変
形が発生するということである。第２の問題は、スピン
コート法又は印刷方法により樹脂層を形成すると、樹脂
層の裏面（半導体チップとは反対側の面）の状態が安定
しない、つまり凹凸が生じてフラットにならないという
ことから、どうしても裏面研磨の導入が必要になって、
コスト高になるということである。第３の問題は、上述
の疑似ウエハでは、基板が樹脂基板であるので、通常の
ウエハプロセス装置の搬送系では、樹脂基板の変形、摩
擦等によって疑似ウエハを円滑に搬送できなかったり、
また、搬送系に設けられている静電チャック、センサ等
が円滑に動作しなかったりして搬送を制御できないとい
うことである。However, as in the above-mentioned method, a method of applying a resin by a spin coating method or a printing method, embedding a semiconductor chip in the resin, and so-called pseudo wafer is
There were the following problems. The first problem is that the pseudo wafer is deformed, such as warped, due to re-curing of the resin layer, contraction of the resin layer, or the like. The second problem is that when the resin layer is formed by the spin coating method or the printing method, the state of the back surface of the resin layer (the surface opposite to the semiconductor chip) is not stable, that is, unevenness does not make it flat. By all means, it became necessary to introduce backside polishing,
The cost is high. A third problem is that, in the above-mentioned pseudo wafer, the substrate is a resin substrate, so that the transfer system of a normal wafer process apparatus cannot smoothly transfer the pseudo wafer due to deformation, friction, etc. of the resin substrate.
In addition, the electrostatic chuck, the sensor, and the like provided in the transfer system do not operate smoothly, and the transfer cannot be controlled.

【００１６】そこで、本発明の目的は、反り等の変形が
発生せず、従来のウエハ・ハンドリング装置により容易
にハンドリングできるようにした疑似ウエハ及びその作
製方法を提供することである。SUMMARY OF THE INVENTION An object of the present invention is to provide a pseudo wafer and its manufacturing method which can be easily handled by a conventional wafer handling apparatus without deformation such as warpage.

【００１７】[0017]

【課題を解決するための手段】本発明者は、上記の問題
を解決するために、半導体チップを埋め込んだ樹脂層の
裏面にシリコンウエハを貼り付けて、樹脂硬化時に発生
する反り等の変形を防止し、且つ疑似ウエハの裏面を平
滑、平坦にすることにより、疑似ウエハの搬送の安定
化、円滑化を実現することを着想し、実験の末に、本発
明を発明するに到った。In order to solve the above problems, the present inventor has attached a silicon wafer to the back surface of a resin layer in which a semiconductor chip is embedded to prevent deformation such as warpage that occurs during resin curing. The present invention has been invented after experiments, with the idea of stabilizing and smoothing the transfer of the pseudo wafer by preventing it and making the back surface of the pseudo wafer smooth and flat.

【００１８】上記目的を達成するために、本発明に係る
マルチチップモジュール作製用の疑似ウエハは、基板
と、基板上に接着されている樹脂層と、基板と反対側の
樹脂層の表面に電極面を露出して樹脂層に埋め込まれて
いる複数個の、半導体チップ及び半導体チップと実質的
に同じ形状のチップ状電子部品（以下、半導体チップと
言う）とを備えていることを特徴としている。In order to achieve the above object, a pseudo wafer for producing a multi-chip module according to the present invention comprises a substrate, a resin layer adhered on the substrate, and an electrode on the surface of the resin layer opposite to the substrate. It is characterized in that it is provided with a plurality of semiconductor chips and chip-shaped electronic components (hereinafter, referred to as semiconductor chips) having substantially the same shape as the semiconductor chips, the surfaces of which are exposed and embedded in the resin layer. .

【００１９】本発明で使用する基板は、耐熱温度が４０
０℃以上である限り、形状、材質等に制約なく使用でき
るものの、好適には、疑似ウエハのハンドリングに際
し、通常のウエハ・ハンドリング装置を使用することが
できるので、半導体装置の作製に使用する６インチ、８
インチ、１２インチ等のシリコン・ウエハである。本発
明で、半導体チップは、チップ状の半導体装置、いわゆ
る半導体チップのみならず、チップ状の電子部品、例え
ば抵抗等も含む概念である。半導体チップの個数、種類
には制約は無く、例えば半導体チップは、ＤＲＡＭメモ
リチップ、フラッシュメモリーチップ、ＳＲＡＭチッ
プ、マイクロコンピュータチップ、更にＣＰＵ（中央演
算処理ユニット）等である。樹脂層は、好適には、絶縁
性樹脂、例えばシリコン系樹脂、セラミック系樹脂等で
形成されている。これにより、疑似ウエハの後続処理が
容易になる。半導体チップの配列は、制約は無く、任意
の配列で良い。The substrate used in the present invention has a heat resistant temperature of 40.
As long as the temperature is 0 ° C. or higher, it can be used without limitation in shape, material, etc., but it is preferably used for manufacturing a semiconductor device because a normal wafer handling device can be used for handling a pseudo wafer. Inch, 8
It is a silicon wafer such as inch or 12 inch. In the present invention, the semiconductor chip is a concept including not only chip-shaped semiconductor devices, so-called semiconductor chips, but also chip-shaped electronic parts such as resistors. There are no restrictions on the number and type of semiconductor chips. For example, the semiconductor chips are DRAM memory chips, flash memory chips, SRAM chips, microcomputer chips, and CPU (central processing unit). The resin layer is preferably formed of an insulating resin such as a silicon resin or a ceramic resin. This facilitates subsequent processing of the pseudo wafer. There is no restriction on the arrangement of the semiconductor chips, and any arrangement may be used.

【００２０】本発明に係る疑似ウエハでは、裏面が基板
で裏打ちされているので、従来の疑似ウエハのように樹
脂層の硬化に際して反り、撓み等の変形が生じない。ま
た、半導体チップ等のチップ状電子部品が電極面を除い
て樹脂層によって被覆されているので、疑似ウエハから
チップ化して得たマルチチップモジュールをハンドリン
グする際、半導体チップが樹脂層で保護された形になる
ので、半導体チップの損傷が少ない。また、マルチチッ
プモジュールの裏面が基板で裏打ちされているので、マ
ルチチップモジュールの機械的強度が増し、マルチチッ
プモジュールのハンドリングが容易となり、良好な実装
信頼性が得られる。Since the back surface of the pseudo wafer according to the present invention is lined with the substrate, there is no deformation such as warping or bending when the resin layer is cured, unlike the conventional pseudo wafer. In addition, since chip-shaped electronic components such as semiconductor chips are covered with a resin layer excluding the electrode surface, the semiconductor chip is protected by the resin layer when handling a multi-chip module obtained by forming a chip from a pseudo wafer. Since it is shaped, there is little damage to the semiconductor chip. Further, since the back surface of the multi-chip module is lined with the substrate, the mechanical strength of the multi-chip module is increased, the handling of the multi-chip module is facilitated, and good mounting reliability is obtained.

【００２１】本発明に係る疑似ウエハの作製方法は、基
板上に接着されている樹脂層に電極面を露出して埋め込
まれている複数個の、半導体チップ及び半導体チップと
実質的に同じ形状のチップ状電子部品（以下、半導体チ
ップと言う）を備えている、マルチチップモジュール作
製用の疑似ウエハを作製する方法であって、所定の処理
を施すことにより粘着力が低下する粘着手段上に、良品
として確認された半導体チップのみを、半導体チップの
電極面を下にして、接着させる工程と、半導体チップの
電極面を露出させて半導体チップを埋め込みつつ粘着手
段上に樹脂層を形成する工程と、樹脂層の平面的寸法よ
り大きな基板を樹脂層上に貼り付ける工程と、樹脂層を
硬化させる工程と、所定の処理を施して粘着手段の粘着
力を低下させ、粘着手段を樹脂層及び半導体チップから
剥離させる工程とを有することを特徴としている。According to the method of manufacturing a pseudo wafer according to the present invention, a plurality of semiconductor chips embedded in a resin layer adhered on a substrate with the electrode surface exposed and having substantially the same shape as the semiconductor chip. A method for producing a pseudo wafer for producing a multi-chip module, which comprises a chip-shaped electronic component (hereinafter referred to as a semiconductor chip), wherein an adhesive means whose adhesive force is reduced by performing a predetermined process, Only a semiconductor chip confirmed as a good product is bonded with the semiconductor chip electrode surface facing down, and a step of exposing the electrode surface of the semiconductor chip to embed the semiconductor chip and forming a resin layer on the adhesive means. , A step of sticking a substrate larger than the planar dimension of the resin layer on the resin layer, a step of curing the resin layer, and a predetermined treatment to reduce the adhesive force of the adhesive means, It is characterized by a step for peeling means from the resin layer, and the semiconductor chip.

【００２２】樹脂層を形成する工程では、射出成形法又
は型成形法により樹脂を成形することにより、樹脂層を
形成する。これにより、表面が平滑で平坦な樹脂層を形
成することができるので、基板の貼り付けが容易にな
り、接着性が向上する。半導体チップを接着させる工程
では、半導体チップを所定の配列で粘着手段上に接着さ
せる。また、粘着手段として、紫外光の照射により粘着
力が低下する粘着テープ、又は加熱により発泡して粘着
力が低下する熱発泡性テープを使用する。In the step of forming the resin layer, the resin layer is formed by molding the resin by injection molding or molding. This makes it possible to form a resin layer having a smooth and flat surface, which facilitates the attachment of the substrate and improves the adhesiveness. In the step of adhering the semiconductor chips, the semiconductor chips are adhered on the adhesive means in a predetermined arrangement. Further, as the adhesive means, an adhesive tape whose adhesive strength is reduced by irradiation with ultraviolet light, or a heat-foamable tape which is foamed by heating and whose adhesive strength is reduced is used.

【００２３】本発明方法では、良品と確認された半導体
チップのみを粘着テープに貼り付けているので、あたか
も全チップが良品チップであるウエハとして疑似ウエハ
を作製することができる。また、良品の半導体チップの
みを有する疑似ウエハに、ウエハ一括で、バンプ処理、
再配線処理等を施すことが可能となり、マルチチップモ
ジュールの製品歩留りが向上する。更には、疑似ウエハ
をダイシングして、複数個の半導体チップを有するマル
チチップモジュールを作製する際、半導体チップ間の樹
脂層部分及び基板部分を切断することになるので、半導
体チップ本体に歪み、バリ、亀裂等のダメージを与えな
いようにして、容易に疑似ウエハを切断することができ
る。In the method of the present invention, since only the semiconductor chips confirmed to be non-defective are attached to the adhesive tape, it is possible to manufacture a pseudo wafer as a wafer in which all the chips are non-defective chips. Also, on a pseudo wafer having only non-defective semiconductor chips, the wafer is subjected to bump processing,
The rewiring process and the like can be performed, and the product yield of the multichip module is improved. Furthermore, when a multi-chip module having a plurality of semiconductor chips is manufactured by dicing the pseudo wafer, the resin layer portion and the substrate portion between the semiconductor chips are cut, so that the semiconductor chip body is distorted and burrs The pseudo wafer can be easily cut without causing damage such as cracks.

【００２４】[0024]

【発明の実施の形態】以下に、実施形態例を挙げ、添付
図面を参照して、本発明の実施の形態を具体的かつ詳細
に説明する。疑似ウエハの実施形態例 本実施形態例は、本発明に係る疑似ウエハの実施形態の
一例であって、図１（ａ）及び（ｂ）は、それぞれ、本
実施形態例の疑似ウエハの平面図及び図１（ａ）の線Ｉ
−Ｉでの断面図である。本実施形態例の疑似ウエハ７０
は、図１に示すように、シリコン基板７２と、シリコン
基板７２上に接着剤により接着されている断面円形の樹
脂層７４と、シリコン基板７２と反対側の樹脂層７４の
表面に電極面を露出して樹脂層７４に埋め込まれている
複数個の半導体チップ７６とを備えている。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described specifically and in detail with reference to the accompanying drawings. Embodiment Example of Pseudo Wafer This embodiment example is an example of the embodiment of the pseudo wafer according to the present invention, and FIGS. 1A and 1B are plan views of the pseudo wafer of the present embodiment example, respectively. And line I in FIG. 1 (a)
It is sectional drawing in -I. Pseudo wafer 70 of the present embodiment example
As shown in FIG. 1, a silicon substrate 72, a resin layer 74 having a circular cross section adhered to the silicon substrate 72 with an adhesive, and an electrode surface on the surface of the resin layer 74 opposite to the silicon substrate 72 are provided with electrode surfaces. A plurality of semiconductor chips 76 exposed and embedded in the resin layer 74 are provided.

【００２５】シリコン基板７２は、半導体装置の作製に
際し、通常使用している８インチのシリコン半導体基板
であって、樹脂層７４の直径より僅かに、例えば１００
μｍ程度大きな直径を有する。シリコン基板７２は、８
インチである必要はなく、６インチ、或いは１２インチ
でも良い。シリコン基板７２は、８インチ基板のときは
基板厚さが６００〜６２５μｍであり、６インチ基板の
ときは基板厚さが５００〜５２５μｍである。樹脂層７
４は、シリコン系、セラミック系のモールド樹脂であっ
て、シリコン基板７２が８インチのときには、樹脂層７
４の厚さは約５００μｍである。半導体チップ７６は、
例えばＤＲＡＭメモリチップ、フラッシュメモリーチッ
プ、ＳＲＡＭチップ、マイクロコンピュータチップ、更
にＣＰＵ（中央演算処理ユニット）等であって、それぞ
れが既に検査により良品であると確認されているもので
ある。The silicon substrate 72 is an 8-inch silicon semiconductor substrate which is usually used in manufacturing a semiconductor device, and is slightly smaller than the diameter of the resin layer 74, for example, 100.
It has a large diameter of about μm. The silicon substrate 72 is 8
It need not be inches, and may be 6 inches or 12 inches. The silicon substrate 72 has a substrate thickness of 600 to 625 μm when it is an 8-inch substrate, and a substrate thickness of 500 to 525 μm when it is a 6-inch substrate. Resin layer 7
Reference numeral 4 denotes a silicon-based or ceramic-based mold resin, and when the silicon substrate 72 is 8 inches, the resin layer 7
The thickness of 4 is about 500 μm. The semiconductor chip 76 is
For example, a DRAM memory chip, a flash memory chip, an SRAM chip, a microcomputer chip, a CPU (central processing unit), etc., each of which has already been confirmed to be non-defective by inspection.

【００２６】本実施形態例の疑似ウエハ７０は、樹脂層
７４の裏面にシリコン基板７２で裏打ちされているの
で、従来の疑似ウエハとは異なり、反り、撓み等の変形
が抑制されている。また、疑似ウエハ７０の外形がシリ
コン基板７２で規定されているので、疑似ウエハ７０の
ハンドリングに際し、従来のウエハ・ハンドリング装置
をそのまま使用することができる。Since the pseudo wafer 70 of the present embodiment is lined with the silicon substrate 72 on the back surface of the resin layer 74, unlike the conventional pseudo wafer, deformation such as warpage and bending is suppressed. Further, since the outer shape of the pseudo wafer 70 is defined by the silicon substrate 72, when the pseudo wafer 70 is handled, the conventional wafer handling device can be used as it is.

【００２７】疑似ウエハの作製方法の実施形態例 本実施形態例は、本発明に係る疑似ウエハの作製方法を
上述の疑似ウエハ７０の作製に適用した実施形態の一例
である。図２（ａ）から図２（ｄ）は、それぞれ、本実
施形態例の方法に従って疑似ウエハを作製する際の工程
毎の断面図である。先ず、図２（ａ）に示すように、粘
着テープ７８上に半導体チップ７６を所定の配列で貼り
付ける。半導体チップ７６は、例えばＤＲＡＭメモリチ
ップ、フラッシュメモリーチップ、ＳＲＡＭチップ、マ
イクロコンピュータチップ、更にＣＰＵ（中央演算処理
ユニット）等であって、それぞれが既に検査により良品
であると確認されているものである。粘着テープ７８
は、例えば約２００℃に加熱すると、発泡して、粘着力
が低下する性質を有する粘着テープであって、市販品を
使用することができる。また、従来と同様に、紫外光を
照射すると、粘着力が低下する性質を有する粘着テープ
を使用しても良い。 Embodiment Example of Pseudo Wafer Manufacturing Method This embodiment example is an example of an embodiment in which the pseudo wafer manufacturing method according to the present invention is applied to manufacture of the above-described pseudo wafer 70. FIG. 2A to FIG. 2D are cross-sectional views of respective steps when manufacturing a pseudo wafer according to the method of the present embodiment. First, as shown in FIG. 2A, the semiconductor chips 76 are attached on the adhesive tape 78 in a predetermined arrangement. The semiconductor chip 76 is, for example, a DRAM memory chip, a flash memory chip, an SRAM chip, a microcomputer chip, a CPU (central processing unit), etc., each of which has already been confirmed as a non-defective product by inspection. . Adhesive tape 78
Is a pressure-sensitive adhesive tape having a property that when heated to, for example, about 200 ° C., it foams and its adhesive strength is reduced, and a commercially available product can be used. In addition, as in the conventional case, an adhesive tape having a property of lowering the adhesive force when irradiated with ultraviolet light may be used.

【００２８】次いで、図２（ｂ）に示すように、粘着テ
ープ７８上の半導体チップ７６を埋め込みつつ粘着テー
プ７８上に、直径が８インチのウエハより僅かに小さ
く、膜厚が５００μｍのシリコン系樹脂からなる樹脂層
７４を形成する。樹脂層７４の形成は、例えば射出成形
法又は型成形法により行う。これにより、印刷法、スピ
ンコート法に比べて、樹脂面が平滑で平坦な樹脂層７４
を成形でき、樹脂層７４上へのシリコン基板７２の接着
が容易になると共に疑似ウエハ７０のハンドリングが円
滑になる。Then, as shown in FIG. 2 (b), the semiconductor chip 76 on the adhesive tape 78 is embedded on the adhesive tape 78, which is slightly smaller than a wafer having a diameter of 8 inches and a film thickness of 500 μm. A resin layer 74 made of resin is formed. The resin layer 74 is formed by, for example, an injection molding method or a molding method. As a result, the resin layer 74 having a smoother and smoother resin surface than the printing method and the spin coating method.
Can be molded, the silicon substrate 72 can be easily adhered to the resin layer 74, and the pseudo wafer 70 can be handled smoothly.

【００２９】次に、図２（ｃ）に示すように、樹脂層７
４の粘着テープ７８とは反対側の面に、樹脂層７４より
直径が僅かに大きな８インチのシリコン基板７２を接着
剤によって貼り付ける。続いて、樹脂層７４を２００℃
以下の所定温度まで加熱して、樹脂層７４を硬化させ
る。次いで、図２（ｄ）に示すように、粘着テープ７８
を約２００℃に加熱して発泡させ、粘着力を低下させ
る。そして、樹脂層７４及び半導体チップ７６から剥離
して、上下逆にすると、図１に示すような疑似ウエハ７
０を作製することができる。Next, as shown in FIG. 2C, the resin layer 7
An 8-inch silicon substrate 72 having a diameter slightly larger than that of the resin layer 74 is attached to the surface opposite to the adhesive tape 78 of No. 4 by an adhesive agent. Then, the resin layer 74 is heated to 200 ° C.
The resin layer 74 is cured by heating to the following predetermined temperature. Then, as shown in FIG. 2D, the adhesive tape 78
Is heated to about 200 ° C. to foam and reduce the adhesive strength. Then, when peeled from the resin layer 74 and the semiconductor chip 76 and turned upside down, the pseudo wafer 7 as shown in FIG.
0 can be created.

【００３０】以下、本実施形態例の疑似ウエハ７０を使
って、従来の疑似ウエハ４０と同様にして、はんだバン
プを形成し、配線基板上に実装することができる。ま
た、従来の半導体装置の配線構造の形成と同様にして、
疑似ウエハ７０上の半導体チップ７６に配線構造を形成
することもできる。Hereinafter, using the pseudo wafer 70 of this embodiment, solder bumps can be formed and mounted on a wiring board in the same manner as the conventional pseudo wafer 40. Further, in the same manner as in the formation of the wiring structure of the conventional semiconductor device,
A wiring structure may be formed on the semiconductor chip 76 on the pseudo wafer 70.

【００３１】[0031]

【発明の効果】本発明によれば、基板と、基板上に接着
されている樹脂層と、基板と反対側の樹脂層の表面に電
極面を露出して樹脂層に埋め込まれている複数個の半導
体チップとを備える、マルチチップモジュール作製用の
疑似ウエハを実現している。これにより、従来の疑似ウ
エハとは異なり、疑似ウエハの反り、撓み等の変形が抑
制され、疑似ウエハの後続処理が容易になる。また、疑
似ウエハの裏面を基板とすることにより、疑似ウエハの
裏面が、平滑、平坦になり、疑似ウエハのハンドリング
が容易になり、後続処理の製品歩留りが向上する。更に
は、基板としてシリコンウエハを使用することにより、
通常のウエハプロセス装置の搬送系をそのまま使用する
ことができる。本発明方法は、本発明に係る疑似ウエハ
の好適な作製方法を実現している。According to the present invention, a substrate, a resin layer adhered to the substrate, and a plurality of electrodes whose electrode surfaces are exposed on the surface of the resin layer opposite to the substrate and which are embedded in the resin layer. , And a pseudo wafer for manufacturing a multi-chip module. As a result, unlike the conventional pseudo wafer, deformation of the pseudo wafer such as warpage and bending is suppressed, and subsequent processing of the pseudo wafer is facilitated. Further, by using the back surface of the pseudo wafer as the substrate, the back surface of the pseudo wafer becomes smooth and flat, the handling of the pseudo wafer is facilitated, and the product yield of the subsequent processing is improved. Furthermore, by using a silicon wafer as the substrate,
The transfer system of a normal wafer processing apparatus can be used as it is. The method of the present invention realizes a preferable method of manufacturing a pseudo wafer according to the present invention.

【図面の簡単な説明】[Brief description of drawings]

【図１】図１（ａ）及び（ｂ）は、それぞれ、実施形態
例の疑似ウエハの平面図及び図１（ａ）の線Ｉ−Ｉでの
断面図である。1A and 1B are a plan view and a cross-sectional view taken along the line I-I of FIG. 1A, respectively, of a pseudo wafer according to an exemplary embodiment.

【図２】図２（ａ）から（ｄ）は、それぞれ、実施形態
例の方法に従って疑似ウエハを作製する際の工程毎の断
面図である。FIG. 2A to FIG. 2D are cross-sectional views of respective steps in manufacturing a pseudo wafer according to the method of the embodiment.

【図３】図３（ａ）及び（ｂ）は、それぞれ、ワイヤボ
ンディング方式のＭＣＭの構成を示す斜視図及び断面図
である。3A and 3B are respectively a perspective view and a cross-sectional view showing the configuration of a wire bonding type MCM.

【図４】図４（ａ）及び（ｂ）は、それぞれ、フリップ
チップ方式のＭＣＭの構成を示す斜視図及び断面図であ
る。FIG. 4A and FIG. 4B are a perspective view and a cross-sectional view showing a configuration of a flip-chip type MCM, respectively.

【図５】図５（ａ）及び（ｂ）は、それぞれ、疑似ウエ
ハの構成を示す斜視図である。5 (a) and 5 (b) are perspective views showing a structure of a pseudo wafer, respectively.

【図６】図６（ａ）から（ｄ）は、それぞれ、従来の方
法で疑似ウエハを作製する際の工程毎の断面図である。6 (a) to 6 (d) are cross-sectional views of respective steps in manufacturing a pseudo wafer by a conventional method.

【図７】図７（ｅ）から（ｇ）は、それぞれ、疑似ウエ
ハを利用する際の工程毎の断面図である。FIGS. 7 (e) to 7 (g) are cross-sectional views of respective steps when using a pseudo wafer.

【図８】図８（ｈ）から（ｊ）は、それぞれ、図７
（ｇ）に続いて、疑似ウエハを利用する際の工程毎の断
面図である。8 (h) to (j) are respectively FIG.
It is sectional drawing for every process at the time of utilizing a pseudo wafer following (g).

【符号の説明】[Explanation of symbols]

１０……ワイヤボンディング方式のＭＣＭ、１１……電
極、１２……回路基板、１３……ワイヤ、１４……半導
体チップ、２０……フリップチップ方式のＭＣＭ、２２
……電極、２４……接合電極、２６……回路基板、２８
……バンプ、３０……半導体チップ、３２……アンダー
フィル材、４０……疑似ウエハ、４２……良品の半導体
ベアチップ、円形の樹脂製基板、４６……方形の樹脂製
基板、４８……石英基板、５０……粘着シート、５２…
…樹脂層、５３……Ｎｉ無電解めっき層（ＵＢＭ、Unde
r Bump Metal）、５４……印刷マスク、５６……はんだ
ペースト、５８……はんだバンプ、６０……スクライブ
ライン、６４……ブレード、６６……マルチチップモジ
ュール（ＭＣＭ）、６８……配線基板、７０……実施形
態例の疑似ウエハ、７２……シリコン基板、７４……樹
脂層、７６……半導体チップ、７８……粘着テープ。10 ... Wire bonding type MCM, 11 ... Electrode, 12 ... Circuit board, 13 ... Wire, 14 ... Semiconductor chip, 20 ... Flip chip type MCM, 22
...... Electrodes, 24 ...... Joint electrodes, 26 ...... Circuit board, 28
... bumps, 30 semiconductor chips, 32 underfill material, 40 pseudo wafers, 42 good semiconductor bare chips, circular resin substrate, 46 square resin substrate, 48 quartz Substrate, 50 ... Adhesive sheet, 52 ...
... Resin layer, 53 ... Ni electroless plating layer (UBM, Unde
r Bump Metal), 54 ... Printing mask, 56 ... Solder paste, 58 ... Solder bump, 60 ... Scribe line, 64 ... Blade, 66 ... Multi-chip module (MCM), 68 ... Wiring board, 70 ... Pseudo wafer of embodiment, 72 ... Silicon substrate, 74 ... Resin layer, 76 ... Semiconductor chip, 78 ... Adhesive tape.

Claims (9)

【特許請求の範囲】[Claims] 【請求項１】 基板と、 前記基板上に接着されている樹脂層と、 前記基板と反対側の樹脂層の表面に電極面を露出して前
記樹脂層に埋め込まれている複数個の、半導体チップ及
び前記半導体チップと実質的に同じ形状のチップ状電子
部品（以下、半導体チップと言う）とを備えていること
を特徴とするマルチチップモジュール作製用の疑似ウエ
ハ。1. A substrate, a resin layer adhered onto the substrate, and a plurality of semiconductors having electrode surfaces exposed on the surface of the resin layer opposite to the substrate and embedded in the resin layer. A pseudo wafer for producing a multi-chip module, comprising a chip and a chip-shaped electronic component having substantially the same shape as the semiconductor chip (hereinafter referred to as a semiconductor chip). 【請求項２】 前記基板は、半導体装置の作製に使用す
るウエハであることを特徴とする請求項１に記載のマル
チチップモジュール作製用の疑似ウエハ。2. The pseudo wafer for manufacturing a multi-chip module according to claim 1, wherein the substrate is a wafer used for manufacturing a semiconductor device. 【請求項３】 前記複数個の半導体チップは、複数種の
半導体チップで構成されていることを特徴とする請求項
１に記載のマルチチップモジュール作製用の疑似ウエ
ハ。3. The pseudo wafer for manufacturing a multi-chip module according to claim 1, wherein the plurality of semiconductor chips are composed of a plurality of types of semiconductor chips. 【請求項４】 前記樹脂層が絶縁性樹脂で形成されてい
ることを特徴とする請求項１に記載のマルチチップモジ
ュール作製用の疑似ウエハ。4. The pseudo wafer for producing a multi-chip module according to claim 1, wherein the resin layer is formed of an insulating resin. 【請求項５】 前記半導体チップが、所定の配列で前記
樹脂層内に埋め込まれていることを特徴とする請求項１
から４のうちのいずれか１項に記載のマルチチップモジ
ュール作製用の疑似ウエハ。5. The semiconductor chips are embedded in the resin layer in a predetermined arrangement.
5. A pseudo wafer for producing a multi-chip module according to any one of items 1 to 4. 【請求項６】 基板上に接着されている樹脂層に電極面
を露出して埋め込まれている複数個の、半導体チップ及
び半導体チップと実質的に同じ形状のチップ状電子部品
（以下、半導体チップと言う）を備えている、マルチチ
ップモジュール作製用の疑似ウエハを作製する方法であ
って、 所定の処理を施すことにより粘着力が低下する粘着手段
上に、良品として確認された半導体チップのみを、前記
半導体チップの電極面を下にして、接着させる工程と、 前記半導体チップの電極面を露出させて前記半導体チッ
プを埋め込みつつ前記粘着手段上に樹脂層を形成する工
程と、 前記樹脂層の平面的寸法より大きな基板を前記樹脂層上
に貼り付ける工程と、 前記樹脂層を硬化させる工程と、 所定の処理を施して前記粘着手段の粘着力を低下させ、
前記粘着手段を前記樹脂層及び前記半導体チップから剥
離させる工程とを有することを特徴とする疑似ウエハの
作製方法。6. A plurality of semiconductor chips embedded in a resin layer adhered on a substrate with its electrode surface exposed and chip-shaped electronic components having substantially the same shape as the semiconductor chip (hereinafter, semiconductor chip). A method for producing a pseudo wafer for multi-chip module production, in which only the semiconductor chips confirmed as non-defective are placed on the adhesive means whose adhesive strength is reduced by performing a predetermined process. A step of adhering the semiconductor chip with the electrode surface facing down, a step of exposing the electrode surface of the semiconductor chip to form a resin layer on the adhesive means while embedding the semiconductor chip, and a step of forming the resin layer A step of sticking a substrate having a size larger than a plane size on the resin layer, a step of curing the resin layer, and a predetermined treatment to reduce the adhesive force of the adhesive means,
And a step of peeling the adhesive means from the resin layer and the semiconductor chip. 【請求項７】 前記樹脂層を形成する工程では、射出成
形法又は型成形法によって樹脂を成形することにより、
前記樹脂層を形成することを特徴とする請求項６に記載
の疑似ウエハの作製方法。7. In the step of forming the resin layer, the resin is molded by an injection molding method or a molding method,
The method for manufacturing a pseudo wafer according to claim 6, wherein the resin layer is formed. 【請求項８】 前記粘着手段が、紫外光の照射により粘
着力が低下する粘着テープ、又は加熱により発泡して粘
着力が低下する熱発泡性テープであることを特徴とする
請求項６に記載の疑似ウエハの作製方法。8. The adhesive tape according to claim 6, wherein the adhesive means is an adhesive tape whose adhesive strength is reduced by irradiation with ultraviolet light, or a heat-foamable tape which is foamed by heating to reduce the adhesive strength. Method for manufacturing pseudo wafer. 【請求項９】 前記半導体チップを接着させる工程で
は、前記半導体チップを所定の配列で前記粘着手段上に
接着させることを特徴とする請求項６に記載の疑似ウエ
ハの作製方法。9. The method of manufacturing a pseudo wafer according to claim 6, wherein in the step of adhering the semiconductor chips, the semiconductor chips are adhered on the adhesive means in a predetermined arrangement.
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Publication number Priority date Publication date Assignee Title
DE102004027489B4 (en) * 2004-06-04 2017-03-02 Infineon Technologies Ag A method of arranging chips of a first substrate on a second substrate
US7652493B2 (en) 2004-06-04 2010-01-26 Infineon Technologies Ag Test arrangement having chips of a first substrate on a second substrate and chips of the second substrate on a third substrate
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DE102004027489A1 (en) * 2004-06-04 2005-12-29 Infineon Technologies Ag A method of arranging chips of a first substrate on a second substrate
JP2006198450A (en) * 2005-01-18 2006-08-03 Disco Abrasive Syst Ltd Coating method of protective coating film
JP4666583B2 (en) * 2005-01-18 2011-04-06 株式会社ディスコ Protective coating method
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JP2012188555A (en) * 2011-03-10 2012-10-04 Sumitomo Bakelite Co Ltd Semiconductor device and method of manufacturing semiconductor device
WO2014178266A1 (en) * 2013-04-30 2014-11-06 日東電工株式会社 Sealing sheet application method and sealing sheet application device
WO2018179819A1 (en) * 2017-03-30 2018-10-04 日本碍子株式会社 Temporary-fixing substrate and method for molding electronic component
JP6420023B1 (en) * 2017-03-30 2018-11-07 日本碍子株式会社 Temporary fixing substrate and electronic component molding method
CN110494956A (en) * 2017-03-30 2019-11-22 日本碍子株式会社 The molding methods of temporary fixed substrate and electronic component
CN110494956B (en) * 2017-03-30 2023-04-28 日本碍子株式会社 Temporary fixing substrate and molding method of electronic component

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