JP2003009412A - Polarity inversion equipment for layered electric double layer capacitor - Google Patents
Polarity inversion equipment for layered electric double layer capacitorInfo
- Publication number
- JP2003009412A JP2003009412A JP2001193962A JP2001193962A JP2003009412A JP 2003009412 A JP2003009412 A JP 2003009412A JP 2001193962 A JP2001193962 A JP 2001193962A JP 2001193962 A JP2001193962 A JP 2001193962A JP 2003009412 A JP2003009412 A JP 2003009412A
- Authority
- JP
- Japan
- Prior art keywords
- double layer
- electric double
- voltage
- layer capacitor
- polarity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/13—Energy storage using capacitors
Landscapes
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、積層型電気二重層
キャパシタ用極性反転装置に関する。詳しくは、積層型
電気二重層キャパシタの自己放電改善に関する技術であ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polarity reversal device for a laminated electric double layer capacitor. Specifically, it is a technique relating to improvement of self-discharge of a laminated electric double layer capacitor.
【０００２】[0002]
【従来の技術】電気二重層キャパシタ（ＥＤＬＣ）は、
電解液を含浸したセパレータやゲル電解質と、そしてそ
れを対向して挟む電極と、電気を取り出すための集電極
とを主な構成物としてなるものである。電気二重層キャ
パシタは、セル当たりの耐電圧が２．５〜３．０Ｖ程度
であり、電気二重層キャパシタを用いて１セル当たりの
耐電圧以上に充電するためには電気二重層キャパシタを
複数個直列接続する必要がある。巻き回い型電気二重層
キャパシタの場合、直列接続は電気回路を付加して行
う。一方、積層型電気二重層キャパシタは一対の集電用
電極の他に（所用積層数−１）個だけバイポーラ型電極
を用いて積層している。2. Description of the Related Art Electric double layer capacitors (EDLC) are
The main components are a separator or a gel electrolyte impregnated with an electrolytic solution, electrodes sandwiching the electrolyte and a gel electrolyte, and a collecting electrode for taking out electricity. The electric double layer capacitor has a withstand voltage of about 2.5 to 3.0 V per cell, and in order to charge the electric double layer capacitor at a voltage higher than the withstand voltage per cell, a plurality of electric double layer capacitors are used. Must be connected in series. In the case of a wound type electric double layer capacitor, series connection is performed by adding an electric circuit. On the other hand, the laminated type electric double layer capacitor is laminated by using only a pair of current collecting electrodes (the required number of laminated layers-1) and bipolar type electrodes.
【０００３】[0003]
【発明が解決しようとする課題】直列接続した個々の電
気二重層キャパシタは、理想的には、充電電圧を直列接
続数で除した電圧（＝充電電圧／直列接続数）を分担す
ることになる。しかし、現実には各電気二重層キャパシ
タ毎に静電容量と内部抵抗、そして自己放電特性にばら
つきがあり、特に自己放電特性のばらつきは、課電（一
定電圧での充電）したに電圧分担の差を生じさせること
になる。そのため、分担した電圧が高い電気二重層キャ
パシタセルから順番に劣化が進み、電気二重層キャパシ
タが持つ本来の寿命を短くする原因となっている。他に
は、以下に示すような問題点がある。Ideally, the individual electric double layer capacitors connected in series share a voltage (= charging voltage / number of series connections) obtained by dividing the charging voltage by the number of series connections. . However, in reality, there are variations in capacitance, internal resistance, and self-discharge characteristics for each electric double layer capacitor. Especially, variations in self-discharge characteristics are due to voltage sharing after charging (charging at a constant voltage). It will make a difference. Therefore, the electric double layer capacitor cells having a higher shared voltage are sequentially deteriorated, which causes a reduction in the original life of the electric double layer capacitor. In addition, there are the following problems.
【０００４】（１）積層した電気二重層キャパシタが持
つ自己放電特性による分担電圧のばらつきを抑えるため
に充電した電気二重層キャパシタを一回放電させ、陽極
と陰極を反転させて（以下、極性反転とよぶ）再び充電
することを繰り返すことによって分担電圧の上昇を抑え
ることが可能になる。但し、自己放電が大きいセルは一
定電圧での充電を行った後に他のセルよりも相対的に分
担電圧が下がり、極性反転したときにおよそ数時間の
間、所定の分担電圧よりも高い電圧を分担することにな
り、寿命が短くなるおそれがある。(1) In order to suppress the variation in the shared voltage due to the self-discharge characteristics of the laminated electric double layer capacitors, the charged electric double layer capacitors are discharged once and the anode and the cathode are inverted (hereinafter, polarity inversion). It is possible to suppress the rise in the shared voltage by repeating charging again. However, a cell with a large self-discharge has a relatively lower sharing voltage than other cells after being charged at a constant voltage, and when the polarity is reversed, a voltage higher than the predetermined sharing voltage is maintained for about several hours. It will be shared and the life may be shortened.
【０００５】例えば、４セルを直列に接続して構成され
た電気二重層キャパシタの充電電圧を１０ボルトとする
と、各セルの分担電圧は、理想的には、２．５Ｖ（＝１
０／４）となる。そのため、図７（ａ）に示すように、
電気二重層キャパシタを一定電圧（１０Ｖ）で充電する
と、各セルには２．５Ｖまで印加されることになる。充
電後、時間の経過に伴い、自己放電が大きいセルについ
ては、図７（ａ）中に破線で示すように、同図中実線で
示す他のセルに比較し、電圧値が低下することになる。
例として、約０．５Ｖ低下するものとした。For example, assuming that the charging voltage of an electric double layer capacitor constituted by connecting four cells in series is 10 V, the shared voltage of each cell is ideally 2.5 V (= 1.
0/4). Therefore, as shown in FIG.
When the electric double layer capacitor is charged with a constant voltage (10V), 2.5V is applied to each cell. After charging, with time, for cells with large self-discharge, as indicated by the broken line in FIG. 7A, the voltage value decreases as compared with other cells indicated by the solid line in the figure. Become.
As an example, it is assumed that the voltage drops by about 0.5V.
【０００６】その後、電気二重層キャパシタを放電する
と、図７（ａ）中に示すように、他のセルは０Ｖになる
のに比較し、自己放電が大きいセルは−０．５Ｖとな
る。そして、図７（ａ）中に示すように、極性反転して
電気二重層キャパシタに充電すると、他のセルは−２．
５Ｖになるのに比較し、自己放電が大きいセルは−３．
０Ｖとなる。前述したように、各セル当たりの耐電圧は
２．５〜３．０ボルトであるので、、仮に、耐電圧が
２．５Ｖであるとすると、２．５Ｖを越えた時間に応
じ、図７（ａ）中斜線で入れて示す領域に比例して、寿
命が短くなることになる。しかも、このような、充電、
放電及び極性反転のサイクルを繰り返すと、上記傾向が
著しくなる。After that, when the electric double layer capacitor is discharged, as shown in FIG. 7 (a), the self-discharge is large at -0.5V as compared with 0V at other cells. Then, as shown in FIG. 7 (a), when the electric double layer capacitor is charged by reversing the polarity, other cells are -2.
As compared with the case where the voltage becomes 5 V, the cell having a large self-discharge is -3.
It becomes 0V. As described above, the withstand voltage of each cell is 2.5 to 3.0 V. Therefore, assuming that the withstand voltage is 2.5 V, the voltage of FIG. (A) The life is shortened in proportion to the area indicated by the shaded area. Moreover, such charging,
The above tendency becomes remarkable when the cycle of discharge and polarity inversion is repeated.
【０００７】（２）ゲル電解質を用いた積層型電気二重
層キャパシタでは製造時の不具合として、ゲル電解質
（電解質にポリマーを混ぜてゲル化したもの）にピンホ
ール（微小な貫通穴）が存在する場合には、セルは短絡
したような挙動を示すおそれがある。そのとき、セル内
部では電荷集中が発生し、異常に発熱することで、電気
二重層キャパシタの劣化が加速され、内部抵抗が上昇し
たり、発火したりする可能性がある。(2) In a laminated type electric double layer capacitor using a gel electrolyte, there is a pinhole (a minute through hole) in the gel electrolyte (a gel obtained by mixing a polymer with an electrolyte) as a defect during manufacturing. In some cases, the cell may behave like a short circuit. At that time, electric charge concentration occurs inside the cell and abnormal heat is generated, which may accelerate deterioration of the electric double layer capacitor, increase internal resistance, or cause ignition.
【０００８】[0008]
【課題を解決するための手段】上記課題を解決する本発
明の請求項１に係る積層型電気二重層キャパシタ用極性
反転装置は、電気二重層キャパシタの分担電圧をボルテ
ージセンサー及びリレーにより測定すると共に分担電圧
の中でも電圧最小値を監視し、該電圧最小値が所定値以
下となるときに前記電気二重層キャパシタの極性反転を
行う極性反転指示回路を用いることを特徴とする。A polarity reversal device for a laminated type electric double layer capacitor according to claim 1 of the present invention which solves the above problems measures the shared voltage of the electric double layer capacitor by a voltage sensor and a relay. It is characterized by using a polarity reversal instruction circuit that monitors the minimum voltage value among the shared voltages and performs the polarity reversal of the electric double layer capacitor when the minimum voltage value becomes a predetermined value or less.
【０００９】上記課題を解決する本発明の請求項２に係
る積層型電気二重層キャパシタ用極性反転装置は、電気
二重層キャパシタの放電時間を管理するタイマーを設け
ると共に前記電気二重層キャパシタの分担電圧の電圧最
小値となる時間が予め実験的又は経験的に求めて該タイ
マーに設定され、該タイマーにより前記電気二重層キャ
パシタの極性反転を行う極性反転指示回路を用いること
を特徴とする。A polarity reversal device for a laminated electric double layer capacitor according to a second aspect of the present invention which solves the above-mentioned problems is provided with a timer for managing the discharge time of the electric double layer capacitor and the shared voltage of the electric double layer capacitor. The time when the voltage becomes the minimum value is experimentally or empirically obtained in advance and set in the timer, and a polarity reversal instruction circuit for reversing the polarity of the electric double layer capacitor is used by the timer.
【００１０】上記課題を解決する本発明の請求項３に係
る積層型電気二重層キャパシタ用極性反転装置は、請求
項１におけるボルテージセンサー及びリレーに代えて、
コンピュータ及びリレーボードを用いることで、遠隔地
や別室での分担電圧の監視、制御を可能としたことを特
徴とする。A polarity reversal device for a laminated electric double layer capacitor according to a third aspect of the present invention, which solves the above-mentioned problems, replaces the voltage sensor and the relay according to the first aspect,
By using a computer and a relay board, it is possible to monitor and control the shared voltage in a remote place or a separate room.
【００１１】[0011]
【発明の実施の形態】上述の問題点を解決するため、分
担電圧が測定できる積層型電気二重層キャパシタを用
い、各セルの分担電圧を測定しながら一定電圧の充電を
行った。電気二重層キャパシタは、電解液が四級アンモ
ニウム塩であるテトラエチルアンモニウムテトラフロロ
ボレート、溶媒はプロピレンカーボネートであり、濃度
は０．９７ｍｏｌ／Ｌとした。DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to solve the above problems, a laminated electric double layer capacitor whose shared voltage can be measured was used to charge a constant voltage while measuring the shared voltage of each cell. In the electric double layer capacitor, the electrolytic solution was tetraethylammonium tetrafluoroborate, which is a quaternary ammonium salt, the solvent was propylene carbonate, and the concentration was 0.97 mol / L.
【００１２】電極はフェノール樹脂繊維を原料とし、平
織りした後、賦活処理を施した比表面積１５００〜２５
００ｍ2／ｇの活性炭繊維布である。活性炭繊維布は導
電性ペーストを用いて、集電用アルミ板の片面とバイポ
ーラ用アルミニウム箔の両面に接着し、集電極とした。
電極間のショートを防ぐための支持電解質は、電解液に
ポリアクリロニトリルを混合し、加熱溶解したゲル電解
質を用いた。溶解したゲル電解質は、放冷によりゲル化
する前にドクターブレードを用いて一定の厚さに成形し
た。The electrode is made of phenolic resin fiber as a raw material, plain-woven, and then activated to give a specific surface area of 1500 to 25.
It is an activated carbon fiber cloth of 00 m 2 / g. A conductive paste was used as the activated carbon fiber cloth, and it was bonded to one side of the current collecting aluminum plate and both sides of the bipolar aluminum foil to form a collecting electrode.
As a supporting electrolyte for preventing a short circuit between electrodes, a gel electrolyte prepared by mixing polyacrylonitrile in an electrolytic solution and heating and dissolving it was used. The melted gel electrolyte was formed into a uniform thickness by using a doctor blade before being gelled by cooling.
【００１３】〔実施例１〕本発明の第１の実施例を図１
に示す。本実施例は、ボルテージセンサーＶＳ１〜ＶＳ
５と絶対値出力アイソレータ１０を用いた極性反転回路
であり、測定中の分担電圧は電圧指示をボルテージセン
サーＶＳ１〜ＶＳ５で取得し、分担電圧が一定値以下に
なったときに抵抗放電と極性切替えを指令できるように
した極性反転指示回路である。[Embodiment 1] A first embodiment of the present invention is shown in FIG.
Shown in. In this embodiment, the voltage sensors VS1 to VS are used.
5 is a polarity reversal circuit using the absolute value output isolator 10. The shared voltage during measurement is obtained by the voltage sensors VS1 to VS5 for the shared voltage during measurement, and when the shared voltage becomes a certain value or less, resistance discharge and polarity switching. Is a polarity reversal instruction circuit capable of instructing.
【００１４】ここで、主電源線Ｐ，Ｎには常に所定の電
圧がかかっているものとし、制御回路へ制御電線Ｌ１，
Ｌ２を用いて電気を供給したときは正極性回路がＯＮし
ている状態とする。絶対値出力アイソレータ１０は、電
圧の絶対値を検出するものであり、逆方向からの電流の
流れを遮断する機能を持つ。制御回路は主電源線Ｐ，Ｎ
のＯＮと連動するものとする。電源投入時は、５セル積
層品の電気二重層キャパシタＣには所定の電圧で充電が
なされる。Here, it is assumed that a predetermined voltage is always applied to the main power supply lines P and N, and the control wires L1 and
When electricity is supplied using L2, the positive polarity circuit is in the ON state. The absolute value output isolator 10 detects the absolute value of the voltage, and has a function of interrupting the current flow from the opposite direction. The control circuit is the main power line P, N
Shall be interlocked with ON. When the power is turned on, the electric double layer capacitor C of the 5-cell laminated product is charged with a predetermined voltage.
【００１５】ボルテージセンサーＶＳ１〜ＶＳ５は、電
気二重層キャパシタＣの分担電圧の絶対値を絶対値出力
アイソレータ１０からモニターしており、論理和接続さ
れている。ボルテージセンサーＶＳ１〜ＶＳ５は、分担
電圧が設定値以下になるとＯＮするスイッチを有する。
自己放電特性の悪いセルの電圧が降下して、ボルテージ
センサーＶＳ１〜ＶＳ５のいずれかがスイッチＯＮの指
令を出すと、放電抵抗を駆動するスイッチＳＷ１がＯＮ
になる。すると抵抗放電用リレーＣＲ１がＯＮし、抵抗
Ｒに電気二重層キャパシタＣの電気を流すスイッチＳＷ
８がＯＮになって抵抗放電が始まる。The voltage sensors VS1 to VS5 monitor the absolute value of the shared voltage of the electric double layer capacitor C from the absolute value output isolator 10 and are logically connected. Each of the voltage sensors VS1 to VS5 has a switch that is turned on when the shared voltage becomes equal to or lower than a set value.
When the voltage of a cell with poor self-discharge characteristics drops and any of the voltage sensors VS1 to VS5 issues a command to turn on the switch, the switch SW1 that drives the discharge resistance turns on.
become. Then, the resistance discharge relay CR1 is turned on, and the switch SW for flowing the electricity of the electric double layer capacitor C to the resistor R
8 is turned on and resistance discharge starts.
【００１６】スイッチＳＷ１のＯＮに連動してインター
ロック用リレーＸＲ１，ＸＲ２がＯＦＦになる。インタ
ーロック用リレーＸＲ１，ＸＲ２は正極性、逆極性を決
めるリレーＣＲ２，ＣＲ３を強制的にＯＦＦにするた
め、リレーＣＲ２に接続れさた逆極性用スイッチＳＷ
５，ＳＷ６がＯＮとなり、また、リレーＣＲ３に接続さ
れた正極性用スイッチＳＷ４，ＳＷ７がＯＦＦとなり、
その結果、主電源線Ｐ，Ｎを通じて電気二重層キャパシ
タＣに供給される電気を遮断する。The interlock relays XR1 and XR2 are turned off in conjunction with the turning on of the switch SW1. The interlock relays XR1 and XR2 are forced to turn off the relays CR2 and CR3 that determine the positive polarity and the reverse polarity, so the reverse polarity switch SW connected to the relay CR2.
5, SW6 is turned on, and the positive polarity switches SW4, SW7 connected to the relay CR3 are turned off,
As a result, electricity supplied to the electric double layer capacitor C through the main power supply lines P and N is cut off.
【００１７】抵抗放電時の電気二重層キャパシタ電圧は
ボルテージセンサーＶＳ６で監視しており、電気二重層
キャパシタＣの電圧が一定値以下になるとＯＮ指令をだ
す機能とボルテージセンサーＶＳ６自身をリセットする
機能を持つ。抵抗放電により電気二重層キャパシタ電圧
が所定電圧値以下になるとボルテージセンサーＶＳ６が
ＯＮし、ボルテージセンサーＶＳ１〜ＶＳ５にリセット
をかける。リセットをかけられたボルテージセンサーＶ
Ｓ１〜ＶＳ５は、抵抗放電をやめるためにスイッチＳＷ
１をＯＦＦにし、抵抗Ｒによる放電をやめるのと同時に
インターロック用リレーＸＲ１，ＸＲ２をＯＮする。ボ
ルテージセンサーＶＳ６からは、遅延回路２０をはさん
で同時にＯＮとＯＦＦできないスイッチＳＷ２，ＳＷ３
を切り替える指令を与える。そして、極性反転した状態
で再び充電を開始する。The voltage of the electric double layer capacitor during resistance discharge is monitored by the voltage sensor VS6. When the voltage of the electric double layer capacitor C becomes a certain value or less, it has a function of issuing an ON command and a function of resetting the voltage sensor VS6 itself. To have. When the electric double layer capacitor voltage becomes equal to or lower than a predetermined voltage value due to resistance discharge, the voltage sensor VS6 is turned on, and the voltage sensors VS1 to VS5 are reset. Reset voltage sensor V
S1 to VS5 are switches SW to stop resistance discharge
When 1 is turned off and the discharge by the resistor R is stopped, the interlock relays XR1 and XR2 are turned on at the same time. From the voltage sensor VS6, switches SW2 and SW3 that cannot be turned on and off at the same time with the delay circuit 20 in between.
Give a command to switch. Then, charging is started again in the state where the polarity is reversed.
【００１８】このように説明したように、本実施例で
は、積層型電気二重層キャパシタの分担電圧における下
限電圧が検出できるようになり、また、極性反転リレー
の動作間隔を変更することも可能である。そのため、極
性反転時の過電圧を防ぐことができ、一定時間で極性反
転を行う従来技術と比較し、電気二重層キャパシタの長
寿命化が可能になる。例えば、図７（ｂ）に示すよう
に、各セルの分担電圧が、２．５Ｖであるとしたとき、
充電後時間の経過に伴い、自己放電が大きいセルについ
ては、図中に破線で示すように、同図中実線で示す他の
セルに比較し、電圧値が低下することになる。As described above, in this embodiment, the lower limit voltage in the shared voltage of the laminated electric double layer capacitor can be detected, and the operation interval of the polarity reversal relay can be changed. is there. Therefore, overvoltage at the time of polarity reversal can be prevented, and the life of the electric double layer capacitor can be extended as compared with the conventional technique in which the polarity reversal is performed in a fixed time. For example, as shown in FIG. 7B, when the shared voltage of each cell is 2.5V,
As the time after charging elapses, the cell having a large self-discharge has a voltage value lower than that of other cells indicated by the solid line in the figure, as indicated by the broken line in the figure.
【００１９】ここで、ボルテージセンサーＶＳ１〜ＶＳ
５に対して、設定電圧として０．２Ｖを設定しておけ
ば、分担電圧の電圧最小値が２．３Ｖ（＝２．５−０．
２）となったときに、放電を開始することとなる。その
ため、図７（ｂ）中に示すように、自己放電が大きいセ
ルは放電時に−０．２Ｖとなり、そして、極性反転時に
は−２．７Ｖとなる。Here, the voltage sensors VS1 to VS
5, if 0.2V is set as the set voltage, the minimum voltage value of the shared voltage is 2.3V (= 2.5-0.
When the condition 2) is reached, discharging will be started. Therefore, as shown in FIG. 7B, a cell having a large self-discharge has a voltage of −0.2V at the time of discharging and a voltage of −2.7V at the time of polarity reversal.
【００２０】ここで、仮に、耐電圧が２．５Ｖであると
すると、２．５Ｖを越えた時間に応じ、図７（ｂ）中斜
線で入れて示す領域に比例して、本来の寿命が短くなる
ことになることは避けられない。但し、図７（ａ）に示
す従来技術に比較し、本実施例では、２．５Ｖを越えた
時間が少なくなり、図中破線で示す領域が減少する結
果、電気二重層キャパシタの寿命が延長するという利点
がある。従って、本実施例に係る電気二重層キャパシタ
は、従来技術に係る比較例に対して、図６に示すよう
に、課電時間に対する容量変化の減少が低減するという
メリットがある。Here, assuming that the withstand voltage is 2.5 V, the original life is proportional to the area shown by the hatched area in FIG. It is inevitable that it will become shorter. However, as compared with the conventional technique shown in FIG. 7A, in this embodiment, the time over 2.5 V is reduced, and the area shown by the broken line in the figure is reduced, resulting in extension of the life of the electric double layer capacitor. There is an advantage of doing. Therefore, the electric double layer capacitor according to the present embodiment has an advantage over the comparative example according to the related art in that the decrease in capacitance change with respect to the voltage application time is reduced as shown in FIG.
【００２１】〔実施例２〕本発明の第２の実施例を図２
に示す。本実施例は、リレーＡ接点とＢ接点を用いた極
性反転指示回路である。即ち、実施例１では正極性と逆
極性の切替えは独立したスイッチＳＷ２、ＳＷ３を用い
たが、本実施例では、図２に示すように、一つのリレー
ＴＲ１のＡ接点とＢ接点に接続するものである。リレー
ＴＲ１は中性点で０．１秒〜０．５秒程度静止すること
ができるものを用いる。その他の構成は、前述した実施
例１と同様であり、同様な効果を奏する。[Embodiment 2] A second embodiment of the present invention is shown in FIG.
Shown in. The present embodiment is a polarity reversal instruction circuit using relay A contacts and B contacts. That is, in the first embodiment, the switches SW2 and SW3 which are independent of each other are used to switch between the positive polarity and the reverse polarity, but in the present embodiment, as shown in FIG. 2, the relays are connected to the A contact and the B contact of the relay TR1. It is a thing. As the relay TR1, a relay TR1 which can stand still for about 0.1 to 0.5 seconds at a neutral point is used. Other configurations are similar to those of the above-described first embodiment, and have similar effects.
【００２２】このように説明したように、本実施例で
は、実施例１と同様な効果を奏する他、極性反転リレー
の動作間隔に特別な条件指定がない場合には、二つのス
イッチＳＷ２、ＳＷ３に代えて一つのリレーＴＲ１を用
いるため、部品点数を減らすことができる。As described above, in this embodiment, in addition to the same effect as that of the first embodiment, two switches SW2 and SW3 are provided if no special condition is specified for the operation interval of the polarity reversing relay. Instead of using one relay TR1, the number of parts can be reduced.
【００２３】〔実施例３〕本発明の第３の実施例を図３
に示す。本実施例はシーケンサ３０による極性反転指示
回路である。即ち、実施例１及び２では外部リレー回路
を組んだが、本実施例では、図３に示すようなリレーシ
ーケンスの代替としてシーケンサ３０を用いて実現し
た。その他の構成は、実施例１及び２と同様である。[Embodiment 3] A third embodiment of the present invention is shown in FIG.
Shown in. The present embodiment is a polarity inversion instruction circuit by the sequencer 30. That is, although the external relay circuit is assembled in the first and second embodiments, the present embodiment is realized by using the sequencer 30 as an alternative to the relay sequence shown in FIG. Other configurations are similar to those of the first and second embodiments.
【００２４】従って、本実施例では、実施例１，２と同
様な効果を奏する他、積層数が多い電気二重層キャパシ
タを製造したときの分担電圧測定に必要な部品点数が大
幅に減り、その結果極性反転回路を含めた電気二重層キ
ャパシタユニットや電力変換盤を小型化することが可能
になる。Therefore, in this embodiment, in addition to the same effects as in the first and second embodiments, the number of components required for measuring the shared voltage when an electric double layer capacitor having a large number of laminated layers is manufactured is significantly reduced. As a result, the electric double layer capacitor unit including the polarity reversing circuit and the power conversion board can be downsized.
【００２５】〔実施例４〕本発明の第４の実施例を図４
に示す。本実施例は、シーケンサ内部タイマー回路を用
いた極性反転指示回路である。即ち、図４に示すよう
に、各セル用のボルテージセンサーの代わりに所定時間
が経過したときにＯＮ指令をだし、ホールドできるタイ
マーＴＭ１〜３をつけて極性反転指令とするものであ
る。[Embodiment 4] A fourth embodiment of the present invention is shown in FIG.
Shown in. The present embodiment is a polarity reversal instruction circuit using a sequencer internal timer circuit. That is, as shown in FIG. 4, an ON command is issued instead of the voltage sensor for each cell when a predetermined time has elapsed, and timers TM1 to TM3 that can hold the signals are attached to give a polarity reversal command.
【００２６】そのとき、タイマーＴＭ１〜３か同時に動
作することがないように一つのタイマーがＯＮしたとき
に、他のタイマーをＯＦＦするようなインターロックを
かけて誤動作を防止している。各タイマーＴＭ１〜３に
は、電気二重層キャパシタの分担電圧の電圧最小値が設
定値以下となる時間として、実験的又は経験的に求めた
値が設定されている。At this time, when one of the timers TM1 to TM3 is turned on so that the timers TM1 to TM3 do not operate at the same time, the other timers are turned off to prevent an erroneous operation. In each of the timers TM1 to TM3, an experimentally or empirically obtained value is set as the time during which the minimum voltage value of the shared voltage of the electric double layer capacitor is equal to or less than the set value.
【００２７】従って、本実施例では、ボルテージセンサ
ーとそれに付随する分担電圧測定回路を減らすことがで
き、その結果、部品点数が減少するため電気二重層キャ
パシタユニット全体の小型化が可能になる。即ち、実施
例１〜３までは各セルの分担電圧をモニターして極性反
転指令を出していたが、定電圧課電試験等により分担電
圧の時間変化が明確化されていれば、分担電圧の代わり
に時間を管理することで極性反転指令を出すこともでき
る。Therefore, in this embodiment, it is possible to reduce the voltage sensor and the shared voltage measuring circuit associated therewith, and as a result, the number of parts is reduced, so that the electric double layer capacitor unit as a whole can be downsized. That is, in Examples 1 to 3, the shared voltage of each cell was monitored and the polarity reversal command was issued, but if the time change of the shared voltage is clarified by the constant voltage charging test, the shared voltage Alternatively, the polarity reversal command can be issued by managing the time.
【００２８】〔実施例５〕本発明の第５の実施例を図５
に示す。本実施例は、データロガーとコンピュータを用
いた極性反転指示回路である。本実施例では、実施例１
〜４におけるシーケンサやタイマー等の外部機器の代わ
りに、図５に示すようなパソコン及びオンボードマイコ
ンのようなコンピュータ４０とそれに付属のパラレルＩ
Ｏポート、そしてリレーを組み合わせて極性反転ができ
るようにした。[Embodiment 5] A fifth embodiment of the present invention is shown in FIG.
Shown in. The present embodiment is a polarity reversal instruction circuit using a data logger and a computer. In this embodiment, the first embodiment
4 instead of an external device such as a sequencer or a timer, a computer 40 such as a personal computer and an on-board microcomputer as shown in FIG.
The polarity can be reversed by combining O port and relay.
【００２９】従って、本実施例では、電気二重層キャパ
シタユニットと極性反転制御部を分離することができ、
その結果、遠隔地での分担電圧測定と極性反転の制御が
可能になることに加え電源操作室等での監視、制御が可
能になる。Therefore, in this embodiment, the electric double layer capacitor unit and the polarity reversal control section can be separated.
As a result, it becomes possible to measure the shared voltage and control the polarity reversal at a remote place, and also to monitor and control the power supply operating room.
【００３０】[0030]
【発明の効果】以上、実施例に基づいて具体的に説明し
たように、本発明の請求項１に係る電気二重層キャパシ
タ用極性反転装置では、電気二重層キャパシタの分担電
圧をボルテージセンサー及びリレーにより測定すると共
に分担電圧の中でも電圧最小値を監視し、該電圧最小値
が所定値以下となるときに極性反転指示回路により前記
電気二重層キャパシタの極性反転を行うため、極性反転
したときに自己放電の大きな電気二重層キャパシタセル
の電圧の下がり過ぎを防止し寿命を延長することが可能
となる。As described above in detail with reference to the embodiments, in the polarity reversal device for an electric double layer capacitor according to claim 1 of the present invention, the shared voltage of the electric double layer capacitor is divided into a voltage sensor and a relay. In addition, the minimum voltage value is monitored among the shared voltage, and when the minimum voltage value becomes a predetermined value or less, the polarity inversion instruction circuit performs polarity inversion of the electric double layer capacitor. It is possible to prevent the voltage of the electric double layer capacitor cell, which is greatly discharged, from dropping too much, and to extend the life.
【００３１】また、本発明の請求項２に係る電気二重層
キャパシタ用極性反転装置では、電気二重層キャパシタ
の放電時間を管理するタイマーを設けると共に前記電気
二重層キャパシタの分担電圧の電圧最小値となる時間が
予め実験的又は経験的に求めて該タイマーに設定され、
該タイマーに設定された時間に従い前記電気二重層キャ
パシタの極性反転を行う極性反転指示回路を用いるた
め、極性反転したときに自己放電の大きな電気二重層キ
ャパシタセルの電圧の下がり過ぎを防止し寿命を延長す
ることが可能となる。Further, in the polarity reversing device for an electric double layer capacitor according to claim 2 of the present invention, a timer for managing the discharge time of the electric double layer capacitor is provided and the minimum voltage value of the shared voltage of the electric double layer capacitor is set. Is set in the timer by experimentally or empirically in advance,
Since the polarity reversal instruction circuit for reversing the polarity of the electric double layer capacitor according to the time set in the timer is used, the voltage of the electric double layer capacitor cell, which causes a large self-discharge when the polarity is reversed, is prevented from being excessively lowered and the life is improved. It can be extended.
【００３２】また、本発明の請求項３に係る電気二重層
キャパシタ用極性反転装置では、請求項１におけるボル
テージセンサー及びリレーに代えて、コンピュータ及び
リレーボードを用いるため、請求項１と同様な効果を奏
する他、遠隔地や別室での分担電圧の監視、制御を可能
となる。Further, in the polarity reversing device for an electric double layer capacitor according to claim 3 of the present invention, a computer and a relay board are used instead of the voltage sensor and the relay according to claim 1, and therefore the same effect as that of claim 1 is obtained. In addition to the above, it becomes possible to monitor and control the shared voltage in a remote place or a separate room.
【図１】本発明の第１の実施例に係るボルテージセンサ
ー及び絶対値出力アイソレータを用いた極性反転回路図
である。FIG. 1 is a polarity reversing circuit diagram using a voltage sensor and an absolute value output isolator according to a first exemplary embodiment of the present invention.
【図２】本発明の第２の実施例に係るリレーＡ接点とＢ
接点を用いた極性反転回路図である。FIG. 2 is a relay A contact and B according to a second embodiment of the present invention.
It is a polarity reversal circuit diagram using a contact.
【図３】本発明の第３の実施例に係るシーケンサによる
極性反転指示回路図である。FIG. 3 is a polarity inversion instruction circuit diagram by a sequencer according to a third embodiment of the present invention.
【図４】本発明の第４の実施例に係るシーケンサ内部タ
イマー回路を用いた極性反転指示回路図である。FIG. 4 is a polarity inversion instruction circuit diagram using a sequencer internal timer circuit according to a fourth embodiment of the present invention.
【図５】本発明の第５の実施例に係るデータロガーとコ
ンピュータを用いた極性反転指示回路図である。FIG. 5 is a polarity inversion instruction circuit diagram using a data logger and a computer according to a fifth embodiment of the present invention.
【図６】課電時間に対する電気二重層キャパシタの容量
変化を示すグラフである。FIG. 6 is a graph showing a change in capacitance of the electric double layer capacitor with respect to a charging time.
【図７】充電、放電及び極性反転時における各セルの分
担電圧の時間的変化を示すグラフである。FIG. 7 is a graph showing a temporal change in a shared voltage of each cell at the time of charging, discharging, and polarity reversal.
１０ 絶対値出力アイソレータ ２０ 遅延回路 ＶＳ１〜ＶＳ６ ボルテージセンサー ＳＷ１〜ＳＷ８ スイッチ ＣＲ１〜ＣＲ３ リレー ＸＲ１，ＸＲ２ インターロック用リレー Ｌ１，Ｌ２ 制御電線 Ｐ，Ｎ 主電源線 Ｒ 抵抗 10 Absolute value output isolator 20 delay circuit VS1 to VS6 voltage sensor SW1 to SW8 switches CR1 to CR3 relay XR1, XR2 Interlock relay L1, L2 control wire P, N Main power line R resistance
Claims (3)
テージセンサー及びリレーにより測定すると共に分担電
圧の中でも電圧最小値を監視し、該電圧最小値が所定値
以下となるときに前記電気二重層キャパシタの極性反転
を行う極性反転指示回路を用いることを特徴とする積層
型電気二重層キャパシタ用極性反転装置。1. A shared voltage of an electric double layer capacitor is measured by a voltage sensor and a relay, a minimum voltage value is monitored among the shared voltage, and when the minimum voltage value is equal to or less than a predetermined value, the electric double layer capacitor A polarity reversal device for a laminated electric double layer capacitor, characterized by using a polarity reversal instruction circuit for reversing the polarity.
するタイマーを設けると共に前記電気二重層キャパシタ
の分担電圧の電圧最小値となる時間が予め実験的又は経
験的に求めて該タイマーに設定され、該タイマーにより
前記電気二重層キャパシタの極性反転を行う極性反転指
示回路を用いることを特徴とする積層型電気二重層キャ
パシタ用極性反転装置。2. A timer for managing the discharge time of the electric double layer capacitor is provided, and the time at which the voltage minimum value of the shared voltage of the electric double layer capacitor becomes the minimum value is experimentally or empirically obtained in advance and set in the timer. A polarity reversing device for a laminated electric double layer capacitor, which uses a polarity reversal instruction circuit for reversing the polarity of the electric double layer capacitor by the timer.
びリレーに代えて、コンピュータ及びリレーボードを用
いることで、遠隔地や別室での分担電圧の監視、制御を
可能としたことを特徴とする電気二重層キャパシタ用極
性反転装置。3. An electric double layer, wherein a computer and a relay board are used in place of the voltage sensor and the relay according to claim 1, so that the shared voltage can be monitored and controlled in a remote place or a separate room. Polarity inversion device for capacitors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001193962A JP2003009412A (en) | 2001-06-27 | 2001-06-27 | Polarity inversion equipment for layered electric double layer capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001193962A JP2003009412A (en) | 2001-06-27 | 2001-06-27 | Polarity inversion equipment for layered electric double layer capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003009412A true JP2003009412A (en) | 2003-01-10 |
Family
ID=19032158
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001193962A Withdrawn JP2003009412A (en) | 2001-06-27 | 2001-06-27 | Polarity inversion equipment for layered electric double layer capacitor |
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| Country | Link |
|---|---|
| JP (1) | JP2003009412A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8336040B2 (en) | 2004-04-15 | 2012-12-18 | Raytheon Company | System and method for topology-aware job scheduling and backfilling in an HPC environment |
| WO2014144845A2 (en) * | 2013-03-15 | 2014-09-18 | Esionic Es, Inc. | Methods of enhancing electrochemical double layer capacitor (edlc) performance and edlc devices formed therefrom |
| WO2015139049A1 (en) * | 2014-03-14 | 2015-09-17 | Esionic Corp. | Methods of enhancing edlc performance |
| WO2019058738A1 (en) * | 2017-09-21 | 2019-03-28 | 国立研究開発法人産業技術総合研究所 | Circuit containing relay-switch and control method therefor |
-
2001
- 2001-06-27 JP JP2001193962A patent/JP2003009412A/en not_active Withdrawn
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8336040B2 (en) | 2004-04-15 | 2012-12-18 | Raytheon Company | System and method for topology-aware job scheduling and backfilling in an HPC environment |
| US9594600B2 (en) | 2004-04-15 | 2017-03-14 | Raytheon Company | System and method for topology-aware job scheduling and backfilling in an HPC environment |
| US9928114B2 (en) | 2004-04-15 | 2018-03-27 | Raytheon Company | System and method for topology-aware job scheduling and backfilling in an HPC environment |
| US10621009B2 (en) | 2004-04-15 | 2020-04-14 | Raytheon Company | System and method for topology-aware job scheduling and backfilling in an HPC environment |
| US11093298B2 (en) | 2004-04-15 | 2021-08-17 | Raytheon Company | System and method for topology-aware job scheduling and backfilling in an HPC environment |
| WO2014144845A2 (en) * | 2013-03-15 | 2014-09-18 | Esionic Es, Inc. | Methods of enhancing electrochemical double layer capacitor (edlc) performance and edlc devices formed therefrom |
| WO2014144845A3 (en) * | 2013-03-15 | 2014-10-30 | Esionic Es, Inc. | Methods of enhancing electrochemical double layer capacitor (edlc) performance and edlc devices formed therefrom |
| CN105378871A (en) * | 2013-03-15 | 2016-03-02 | 伊赛欧尼克公司 | Methods of enhancing electrochemical double layer capacitor (EDLC) performance and EDLC devices formed therefrom |
| WO2015139049A1 (en) * | 2014-03-14 | 2015-09-17 | Esionic Corp. | Methods of enhancing edlc performance |
| WO2019058738A1 (en) * | 2017-09-21 | 2019-03-28 | 国立研究開発法人産業技術総合研究所 | Circuit containing relay-switch and control method therefor |
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