JP2002374059A - Leadfree solder resistant wiring board - Google Patents
Leadfree solder resistant wiring boardInfo
- Publication number
- JP2002374059A JP2002374059A JP2001180058A JP2001180058A JP2002374059A JP 2002374059 A JP2002374059 A JP 2002374059A JP 2001180058 A JP2001180058 A JP 2001180058A JP 2001180058 A JP2001180058 A JP 2001180058A JP 2002374059 A JP2002374059 A JP 2002374059A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- solder
- pattern
- electrode pattern
- free solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Details Of Resistors (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、耐鉛フリーはんだ
配線板に関する。The present invention relates to a lead-free solder wiring board.
【０００２】[0002]
【従来の技術】従来、電子部品、例えばネットワーク抵
抗器は、図３の断面図に示すように、セラミック等の絶
縁基板１上に銀を主成分とする厚膜導体で形成された複
数の個別電極パターン２、同じく形成された共通電極パ
ターン３、各個別電極パターン２と共通電極パターン３
間に電気的に接続された抵抗膜４、その端子６ａが鉛を
一成分とするはんだ５で前記個別電極パターン２にはん
だ付けされたリードフレーム６、ガラス等による保護膜
７、外装膜８にで構成されている。前記個別電極パター
ン２、前記共通電極パターン３及び抵抗膜４を厚膜技術
で形成した場合、通常これらの膜厚は１０μｍ程度であ
る。2. Description of the Related Art Conventionally, as shown in a cross-sectional view of FIG. 3, an electronic component, for example, a network resistor, has a plurality of individual components formed of a thick film conductor mainly composed of silver on an insulating substrate 1 made of ceramic or the like. Electrode pattern 2, common electrode pattern 3 similarly formed, each individual electrode pattern 2 and common electrode pattern 3
The resistive film 4 electrically connected between the terminals, the terminal 6a of the lead frame 6 soldered to the individual electrode pattern 2 with the solder 5 containing lead as one component, the protective film 7 of glass or the like, and the exterior film 8 It is composed of When the individual electrode pattern 2, the common electrode pattern 3, and the resistive film 4 are formed by a thick film technique, their thickness is usually about 10 μm.
【０００３】[0003]
【発明が解決しようとする課題】従来、ネットワーク抵
抗器などの電子部品においては、絶縁基板上の接続用ラ
ンドとリードフレームを接続するためのはんだ材、リー
ドフレームの表面メッキ材には鉛が含まれている材料を
用いているのが一般的である。一方、電子部品のはんだ
付けが鉛フリーはんだに使用が移る傾向にある。これは
鉛による環境汚染を回避しようとする一つの対策に基づ
くものである。したがって、鉛フリー化のためには、こ
れらの材料を鉛フリーはんだ材に変更する必要がある。Conventionally, in an electronic component such as a network resistor, a solder material for connecting a connection land on an insulating substrate to a lead frame, and a lead plating on the surface of the lead frame contain lead. It is common to use the materials that are used. On the other hand, soldering of electronic components tends to shift to lead-free soldering. This is based on one measure to avoid environmental pollution from lead. Therefore, it is necessary to change these materials to a lead-free solder material in order to be lead-free.
【０００４】現在、鉛を含むはんだ、例えばＳｎ−Ｐｂ
はんだの代替え材として鉛フリーはんだ、例えばＳｎ−
Ａｇ−Ｃｕはんだ、Ｓｎ−Ａｇ−Ｂｉはんだが製品化さ
れているが、これらの鉛フリーはんだを銀を主成分とす
る厚膜導体にて形成された電子部品、例えばネットワー
ク抵抗器などのはんだ付けに利用すると、鉛を含むはん
だと比べ、接続用ランドを喰いやすくなることを知見し
た。At present, lead-containing solder, for example, Sn-Pb
Lead-free solder, such as Sn-
Ag-Cu solder and Sn-Ag-Bi solder have been commercialized, and these lead-free solders are soldered to electronic components formed of a thick film conductor containing silver as a main component, such as network resistors. It has been found that the use of lead makes it easier to eat the connection lands as compared with lead-containing solder.
【０００５】電子部品用の厚膜導体は、銀を主成分とす
るものが大半であるが、これに鉛を含むはんだを接続し
た場合、鉛により銀がはんだ側に移動するのを抑制する
効果があった。一方、鉛フリーはんだ材を利用すると、
はんだ付け時に接続用ランド中から鉛フリーはんだ側へ
の金属原子（主に銀）の移動速度が速くなり、膜厚によ
っては速く喰われて接続用ランドが無くなってしまう。[0005] Thick film conductors for electronic components are mainly composed of silver as a main component. When a solder containing lead is connected to this, the effect of suppressing the movement of silver to the solder side by the lead is obtained. was there. On the other hand, if you use lead-free solder,
At the time of soldering, the moving speed of metal atoms (mainly silver) from the connection lands to the lead-free solder side increases, and depending on the film thickness, the metal lands are quickly eroded and the connection lands disappear.
【０００６】この現象ははんだ付けの接続不良の原因と
なり、製品の信頼性の低下に繋がることになる。実験に
よれば、鉛フリーはんだ材の組成にもよるが、鉛を含む
はんだと同一はんだ付け条件なら、接続用ランドが概ね
２倍の速さで鉛フリーはんだに喰われてしまうことが判
明した。[0006] This phenomenon causes a connection failure in soldering, leading to a reduction in product reliability. According to the experiment, depending on the composition of the lead-free solder material, it was found that under the same soldering conditions as the solder containing lead, the connection lands were eroded by the lead-free solder approximately twice as fast. .
【０００７】本発明は、前記問題点に鑑み、鉛フリーは
んだによる前記喰われによっても、はんだ付けの信頼性
を確保できる接続ランドを備えた配線板及び電子部品を
提案するものである。The present invention has been made in view of the above problems, and proposes a wiring board and an electronic component having connection lands that can ensure the reliability of soldering even by the above-mentioned bite by lead-free solder.
【０００８】[0008]
【課題を解決するための手段】絶縁基板上に形成された
銀を主成分とする厚膜導体による導体パターンの内、少
なくとも鉛フリーはんだに曝される導体パターン部分を
他の導体パターン部分よりも膜厚を厚く形成する。SUMMARY OF THE INVENTION Among conductor patterns formed of a thick film conductor containing silver as a main component and formed on an insulating substrate, at least a portion of a conductor pattern exposed to a lead-free solder is made smaller than other conductor pattern portions. The film is formed thick.
【０００９】[0009]
【発明の実施の形態】以下、図１に示すネットワーク抵
抗器及び図２に示すネットワーク抵抗器を作製する工程
図を参照しながら、導体パターンが鉛フリーはんだに耐
える本発明の配線板（耐鉛フリーはんだ配線板とい
う。）及びネットワーク抵抗器などの電子部品を説明す
る。ここで、図２の各工程は絶縁基板上に順次積層する
部材のみを示し、従来と同じ構成要素には同一符号を付
している。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a wiring board (lead-resistant) according to the present invention in which a conductor pattern withstands lead-free solder will be described with reference to the process charts for manufacturing the network resistor shown in FIG. 1 and the network resistor shown in FIG. Electronic components such as free solder wiring boards) and network resistors will be described. Here, each step in FIG. 2 shows only members that are sequentially laminated on the insulating substrate, and the same reference numerals are given to the same components as in the related art.
【００１０】（工程１）セラミック等を母材とする絶縁
基板１上に銀系の厚膜導体ペーストを用いて個別電極パ
ターン２及び共通電極パターン３となる１層目の導体を
印刷・焼成して形成する。(Step 1) A first-layer conductor serving as an individual electrode pattern 2 and a common electrode pattern 3 is printed and fired on an insulating substrate 1 made of ceramic or the like by using a silver-based thick film conductor paste. Formed.
【００１１】（工程２）前記共通電極パターン３と前記
個別電極パターン２間を電気的に接続するように、Ｒｕ
Ｏ系の厚膜抵抗ペーストを印刷・焼成して抵抗膜４をそ
れぞれ形成する。(Step 2) Ru is applied so that the common electrode pattern 3 and the individual electrode pattern 2 are electrically connected.
The resistance film 4 is formed by printing and baking an O-based thick film resistance paste.
【００１２】（工程３）前記１層目の導体である個別電
極パターン２及び共通電極の端部３ａ上に２層目の導体
パターン２ａ及び３ｂを積層し、合計膜厚が２０μｍ以
上となるような条件で接続用ランドを形成する。ここで
２層目の導体パターン２ａ及び３ｂは、１層目の導体以
外の部分にも形成できるパターンでも良い。このように
接続用ランドを形成すると鉛フリーはんだによる食われ
を低減するのに好適であった。(Step 3) Second-layer conductor patterns 2a and 3b are laminated on the individual electrode pattern 2 as the first-layer conductor and the end 3a of the common electrode, so that the total film thickness becomes 20 μm or more. The connection land is formed under appropriate conditions. Here, the second-layer conductor patterns 2a and 3b may be patterns that can be formed on portions other than the first-layer conductor. Forming the connection lands in this way was suitable for reducing erosion due to lead-free solder.
【００１３】（工程４）前記抵抗膜４にレーザトリミン
グを行い、電気抵抗値を調整する。 （工程５）前記工程４までは絶縁基板１は他数個取りの
状態であるが、ここで絶縁基板１を１製品単位に分割す
る。(Step 4) Laser trimming is performed on the resistive film 4 to adjust an electric resistance value. (Step 5) Until the step 4, the insulating substrate 1 is in a state of taking several other pieces. Here, the insulating substrate 1 is divided into one product unit.
【００１４】（工程６）リードフレーム６のクリップ部
分６ａに、分割した絶縁基板を前記接続用ランドが形成
されている側から導入し、鉛フリーはんだの噴流に曝し
てフローはんだ付けを行う。該フローはんだ付けは絶縁
基板全体とリードフレーム６のクリップ部分６ａが溶け
たはんだの噴流の中を通過させて行うが、前記接続用ラ
ンドを２０μｍ以上に形成しているため、接続ランドを
含む導体パターンがはんだ噴流中を通過中にはんだによ
る喰われが生じても、電気的に不良の発生しない導体パ
ターンを確保することが可能となる。(Step 6) The divided insulating substrate is introduced into the clip portion 6a of the lead frame 6 from the side where the connection lands are formed, and is exposed to a jet of lead-free solder to perform flow soldering. The flow soldering is performed by passing the entire insulating substrate and the solder portion in which the clip portion 6a of the lead frame 6 has been melted. However, since the connection lands are formed to be 20 μm or more, the conductor including the connection lands is formed. Even if the pattern is eroded by the solder while passing through the solder jet, it is possible to secure a conductor pattern free from electrical failure.
【００１５】前記はんだ付け後、絶縁基板１をエポキシ
樹脂等を用いた外装膜８で覆い、この外装膜８の表面に
標印を施し、リードフレームを所定長に切断して図１に
示すネットワーク抵抗器が完成する。After the soldering, the insulating substrate 1 is covered with an exterior film 8 using an epoxy resin or the like, a mark is formed on the surface of the exterior film 8, and the lead frame is cut into a predetermined length to form a network shown in FIG. The resistor is completed.
【００１６】前記実施の形態では、ネットワーク抵抗器
を例に挙げて説明したが、該電子部品の他、本発明は、
配線板のはんだ付けランド等、鉛フリーはんだに曝され
る導体パターン部分に適用することができることは明ら
かである。また、はんだ付けはフローはんだ付けの他、
リフローはんだ付けにおいても同様の効果が得られる。In the above-described embodiment, the network resistor has been described as an example.
Obviously, the present invention can be applied to a conductor pattern portion exposed to lead-free solder, such as a soldering land of a wiring board. In addition to soldering, besides flow soldering,
Similar effects can be obtained in reflow soldering.
【００１７】[0017]
【発明の効果】本発明は、鉛フリーはんだに曝される導
体パターン部分の厚さを他の導体部分の厚さよりも厚く
形成したから、はんだ付け時に導体パターンが鉛フリー
はんだに曝されて導体パターンが鉛フリーはんだに食わ
れても、導体パターンに電気的に不良が発生しない。ま
た、はんだ付けランドでの電気的接続に不良が発生しな
い電子部品を実現することができる。According to the present invention, since the thickness of the conductor pattern portion exposed to the lead-free solder is formed to be thicker than the thickness of the other conductor portions, the conductor pattern is exposed to the lead-free solder during soldering. Even if the pattern is eroded by the lead-free solder, no electrical failure occurs in the conductor pattern. Further, it is possible to realize an electronic component in which a failure does not occur in the electrical connection at the soldering land.
【図１】本発明ネットワーク抵抗器の断面図である。FIG. 1 is a sectional view of a network resistor according to the present invention.
【図２】ネットワーク抵抗器の作製工程図である。FIG. 2 is a manufacturing process diagram of a network resistor.
【図３】従来のネットワーク抵抗器の断面図である。FIG. 3 is a cross-sectional view of a conventional network resistor.
２、２ａ・・個別電極パターン ３、３ａ・・共通電極
パターン ４・・抵抗膜５ａ・・鉛フリーはんだ ６・
・リードフレーム2, 2a ··· individual electrode pattern 3, 3a ··· common electrode pattern 4 ··· resistive film 5a ··· lead-free solder 6 ·
·Lead frame
Claims (4)
厚膜導体による導体パターンの内、少なくとも鉛フリー
はんだに曝される導体パターン部分を他の導体パターン
部分よりも膜厚を厚く形成したことを特徴とする耐鉛フ
リーはんだ配線板。1. A conductive pattern formed of a thick-film conductor containing silver as a main component and formed on an insulating substrate, wherein at least a part of the conductive pattern exposed to a lead-free solder is thicker than other conductive pattern parts. A lead-free solder wiring board characterized by being formed.
の厚さを２０μｍ以上の厚さに形成したことを特徴とす
る請求項１の耐鉛フリーはんだ配線板。2. The lead-free solder wiring board according to claim 1, wherein a thickness of the conductor pattern portion exposed to the lead solder is formed to a thickness of 20 μm or more.
ン部分は、はんだ付け用ランドであることを特徴とする
請求項１又は２の耐鉛フリーはんだ配線板。3. The lead-free solder wiring board according to claim 1, wherein the conductor pattern portion exposed to the lead-free solder is a land for soldering.
厚膜導体による個別電極パターン及び共通電極パターン
と、前記個別電極パターンと前記共通電極パターン間に
それぞれ電気的に接続された抵抗膜とを備えたネットワ
ーク抵抗器において、 前記個別電極パターン及び前記共通電極パターンの鉛フ
リーはんだ付け用ランドの厚さを２０μｍ以上としたこ
とを特徴とするネットワーク抵抗器。4. An individual electrode pattern and a common electrode pattern formed of a thick film conductor containing silver as a main component and formed on an insulating substrate, and a resistor electrically connected between the individual electrode pattern and the common electrode pattern. A network resistor comprising: a film; and a lead-free soldering land of the individual electrode pattern and the common electrode pattern having a thickness of 20 μm or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001180058A JP2002374059A (en) | 2001-06-14 | 2001-06-14 | Leadfree solder resistant wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001180058A JP2002374059A (en) | 2001-06-14 | 2001-06-14 | Leadfree solder resistant wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002374059A true JP2002374059A (en) | 2002-12-26 |
Family
ID=19020534
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001180058A Pending JP2002374059A (en) | 2001-06-14 | 2001-06-14 | Leadfree solder resistant wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002374059A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006066760A (en) * | 2004-08-30 | 2006-03-09 | Nippon Seiki Co Ltd | Circuit board |
| JP2007123475A (en) * | 2005-10-27 | 2007-05-17 | Nippon Seiki Co Ltd | Circuit board |
| CN110911066A (en) * | 2018-09-17 | 2020-03-24 | 三星电机株式会社 | Electronic assembly and method of manufacturing the same |
-
2001
- 2001-06-14 JP JP2001180058A patent/JP2002374059A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006066760A (en) * | 2004-08-30 | 2006-03-09 | Nippon Seiki Co Ltd | Circuit board |
| JP2007123475A (en) * | 2005-10-27 | 2007-05-17 | Nippon Seiki Co Ltd | Circuit board |
| CN110911066A (en) * | 2018-09-17 | 2020-03-24 | 三星电机株式会社 | Electronic assembly and method of manufacturing the same |
| CN110911066B (en) * | 2018-09-17 | 2022-07-15 | 三星电机株式会社 | Electronic assembly and method of manufacturing the same |
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