JP2002373970A - Mounting structure for semiconductor device - Google Patents

Mounting structure for semiconductor device

Info

Publication number
JP2002373970A
JP2002373970A JP2001181481A JP2001181481A JP2002373970A JP 2002373970 A JP2002373970 A JP 2002373970A JP 2001181481 A JP2001181481 A JP 2001181481A JP 2001181481 A JP2001181481 A JP 2001181481A JP 2002373970 A JP2002373970 A JP 2002373970A
Authority
JP
Japan
Prior art keywords
metal electrode
electrode plate
semiconductor chip
resin base
joined
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001181481A
Other languages
Japanese (ja)
Other versions
JP3741002B2 (en
Inventor
Yasuhiro Okada
安弘 岡田
Mikio Naruse
幹夫 成瀬
Sukeyuki Furukawa
資之 古川
Akihiro Shibuya
彰弘 渋谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nissan Motor Co Ltd
Original Assignee
Nissan Motor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nissan Motor Co Ltd filed Critical Nissan Motor Co Ltd
Priority to JP2001181481A priority Critical patent/JP3741002B2/en
Publication of JP2002373970A publication Critical patent/JP2002373970A/en
Application granted granted Critical
Publication of JP3741002B2 publication Critical patent/JP3741002B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent a bottom from becoming convex upward in a semiconductor module formed by stacking metallic electrode plates where semiconductor chips are joined. SOLUTION: Metallic electrode plates 10A, 20A, and 30A are molded on a resin base 50A, an IGBT 40p and an FWD 42p are joined to a main part 11A of the metallic electrode plate 10A, and an IGBT 40n and an FWD 42n are joined to a lower stage 22A of the metallic electrode plate 20A. With respect to the bottom of the module where the main part 11A and the lower stage 22A are exposed, a connecting portion 12A of the metallic electrode plate 10A and a connecting portion 32A of the metallic electrode plate 30A rise vertically on the end of the resin base, are opposed to each other, and protrude from the resin base in a perpendicular direction to a paper face to serve as an external connecting portion. Since rising portions of the connecting portions are not formed at the center, shrinkage is not prevented on a side wall of a case resin base during cooling after molding, and the bottom of the module becomes convex downward and comes into contact with a heatsink 58A.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体チップを金
属電極板に装着する半導体装置の実装構造に関する。The present invention relates to a semiconductor device mounting structure for mounting a semiconductor chip on a metal electrode plate.

【０００２】[0002]

【従来の技術】従来の半導体装置の実装構造として、例
えば図１０に示すようなものがある。図１０の（ａ）は
上面図、（ｂ）は（ａ）におけるＫ−Ｋ部断面図であ
る。これは、ＭＯＳＦＥＴの半導体チップ２個を用いて
形成されるインバータ回路の１相分を、１つの半導体モ
ジュールとしたものである。半導体モジュールは、上方
が開口したケース状の樹脂ベース７０に、金属電極板１
ａ、１ｂおよび１ｃをモールドして形成されている。金
属電極板１ａと１ｂは高さ位置が同層で横に並べて配置
され、、金属電極板１ｃは金属電極板１ａの上側に一部
重ねられて、各金属電極板は互いに離間して絶縁されて
いる。2. Description of the Related Art As a conventional mounting structure of a semiconductor device, for example, there is one as shown in FIG. FIG. 10A is a top view, and FIG. 10B is a sectional view taken along the line KK in FIG. In this configuration, one phase of an inverter circuit formed by using two MOSFET semiconductor chips is used as one semiconductor module. The semiconductor module is provided with a metal electrode plate 1 on a case-shaped resin base 70 having an open top.
a, 1b and 1c are molded. The metal electrode plates 1a and 1b have the same height and are arranged side by side in the same layer. The metal electrode plate 1c is partially overlapped on the upper side of the metal electrode plate 1a. ing.

【０００３】半導体チップ３ａと３ｂが、それぞれ半田
によって金属電極板１ａと１ｂの上面に接合されてい
る。半導体チップ３ａ、３ｂはそれぞれ金属電極板に接
合される裏面がドレイン電極とされ、上面がソース電極
とゲート電極となっている。半導体チップ３ａの上面ソ
ース電極と金属電極板１ｂが複数本の金属ワイヤ７２ａ
によって接続されており、また、半導体チップ３ａの上
面ゲート電極はゲート端子６ａと金属ワイヤ７３ａによ
って接続されている。[0005] Semiconductor chips 3a and 3b are joined to the upper surfaces of metal electrode plates 1a and 1b by soldering, respectively. Each of the semiconductor chips 3a and 3b has a back surface joined to the metal electrode plate serving as a drain electrode, and an upper surface serving as a source electrode and a gate electrode. The upper surface source electrode of the semiconductor chip 3a and the metal electrode plate 1b are composed of a plurality of metal wires 72a.
The upper gate electrode of the semiconductor chip 3a is connected to the gate terminal 6a by a metal wire 73a.

【０００４】半導体チップ３ｂのソース電極と金属電極
板１ｃが複数本の金属ワイヤ７２ｂによって接続されて
おり、また、半導体チップ３ｂのゲート電極はゲート端
子６ｂと金属ワイヤ７３ｂによって接続されている。こ
れにより、図１１に示されるように、半導体チップ３ａ
と３ｂが直列に接続された回路が形成される。金属電極
板１ａが回路の高電源側に接続されるＰ端子になり、金
属電極板１ｃが低電源側に接続されるＮ端子、金属電極
板１ｂが出力のＩＮＶ端子となる。The source electrode of the semiconductor chip 3b is connected to the metal electrode plate 1c by a plurality of metal wires 72b, and the gate electrode of the semiconductor chip 3b is connected to the gate terminal 6b by a metal wire 73b. Thereby, as shown in FIG. 11, the semiconductor chip 3a
And 3b are connected in series to form a circuit. The metal electrode plate 1a serves as a P terminal connected to the high power supply side of the circuit, the metal electrode plate 1c serves as an N terminal connected to the low power supply side, and the metal electrode plate 1b serves as an output INV terminal.

【０００５】半導体モジュールの金属電極板１ａ、１ｂ
が露出した底面には、電気的な絶縁性を有する放熱シー
ト７を介してヒートシンク８が取り付けられている。こ
れにより、半導体チップ３ａ、３ｂが動作する際に発生
する熱はヒートシンク８に伝達され、放熱される。[0005] Metal electrode plates 1a, 1b of a semiconductor module
A heat sink 8 is attached to the exposed bottom surface via a heat radiating sheet 7 having electrical insulation. As a result, heat generated when the semiconductor chips 3a and 3b operate is transmitted to the heat sink 8 and radiated.

【０００６】このような半導体装置の実装構造を備える
インバータ回路では、小電流タイプでも２０〜３０アン
ペア、大電流タイプでは１００アンペア以上の主電流を
半導体チップに流すので、２つの金属電極板１ａ、１ｃ
の自己インダクタンスによるスイッチング動作時の影響
が無視できなくなる。そこで、半導体モジュールの２つ
の金属電極板１ａ、１ｃを所定の間隔を保って互いに平
行になるように配設することにより、自己インダクタン
スを低減しようとしている。In an inverter circuit having such a semiconductor device mounting structure, a main current of 20 to 30 amperes flows through a semiconductor chip even in a small current type, and a main current of 100 amperes or more in a large current type, so that two metal electrode plates 1a, 1c
The influence of the self-inductance during the switching operation cannot be ignored. Therefore, the self-inductance is reduced by arranging the two metal electrode plates 1a and 1c of the semiconductor module so as to be parallel to each other with a predetermined interval.

【０００７】[0007]

【発明が解決しようとする課題】しかしながら、この実
装構造になる半導体装置では、その半導体モジュールに
おける２つの金属電極板１ａ、１ｃが平行になっている
箇所が一部のみであるため、自己インダクタンスの低減
効果が充分ではなく、半導体チップのスイッチング特性
が低下したり、極端な場合にはスイッチングによるター
ンオフ時のスパイク電圧により半導体チップが破壊され
る可能性もある。この対策として、本出願人は図１２に
示すように、金属電極板１ａ’と１ｂ’、１ｂ’と１
ｃ’を互いに平行に重ねて配設したうえ、金属電極板１
ａ’と１ｃ’の端部に形成される外部接続部２ａ、２ｃ
をそれぞれ各板の全幅にわたって垂直に立ち上げて、互
いに対向させることにより、２つの金属電極板１ａ’と
１ｃ’が重なる領域を多くして自己インダクタンスを一
層低減した半導体装置の実装構造を提案した。However, in the semiconductor device having this mounting structure, only two metal electrode plates 1a and 1c are parallel to each other in a part of the semiconductor module. The reduction effect is not sufficient, and the switching characteristics of the semiconductor chip may be reduced. In an extreme case, the semiconductor chip may be damaged by a spike voltage at the time of turn-off due to switching. As a countermeasure against this, the present applicant, as shown in FIG.
c ′ are arranged in parallel with each other and the metal electrode plate 1
External connection parts 2a, 2c formed at the ends of a 'and 1c'
Are vertically raised over the entire width of each plate and are opposed to each other, thereby increasing the area where the two metal electrode plates 1a 'and 1c' overlap each other, and further reducing the self-inductance. .

【０００８】しかしこの場合、樹脂ベース７０’の材質
によって、モールド成形後の冷却時に、収縮力が加わっ
てケースの開口に連なる側壁が内側に収縮しようとする
際に、半導体モジュール底面に対して垂直に立ち上げて
対向させた２つの金属電極板の外部接続部がその収縮を
阻害して、図１３の（ａ）から（ｂ）のように半導体モ
ジュール底面が下に凸となるべきところが、（ｃ）のよ
うに上に凸となってしまう場合があることを見出した。However, in this case, depending on the material of the resin base 70 ', when a side wall connected to the opening of the case tries to contract inward due to a contracting force applied during cooling after molding, the bottom surface is perpendicular to the bottom of the semiconductor module. 13 (a) to 13 (b), the external connection portion of the two metal electrode plates which are raised and opposed to each other inhibits the contraction, and as shown in FIGS. It has been found that there is a case where it becomes convex upward as in c).

【０００９】この場合、半導体モジュールをヒートシン
クに取り付けるに当たって、通常周辺部が固定される半
導体モジュールとヒートシンク間に隙間ができる結果、
熱抵抗が大きくなって半導体装置全体としての信頼性が
低下するという問題が生じる。したがって本発明は、上
記の問題点に鑑み、２つの金属電極板の自己インダクタ
ンスの低減効果を損なわずに、半導体モジュール底面が
上に凸となることを防止できる半導体装置の実装構造を
提供することを目的とする。In this case, when attaching the semiconductor module to the heat sink, a gap is formed between the semiconductor module to which the peripheral portion is normally fixed and the heat sink.
There is a problem that the thermal resistance is increased and the reliability of the entire semiconductor device is reduced. Accordingly, the present invention has been made in view of the above problems, and provides a mounting structure of a semiconductor device capable of preventing a bottom surface of a semiconductor module from projecting upward without impairing a self-inductance reduction effect of two metal electrode plates. With the goal.

【００１０】[0010]

【課題を解決するための手段】このため、請求項１の本
発明は、樹脂ベースにモールドされて互いに絶縁された
第１、第２および第３の金属電極板を備え、第１の金属
電極板上に第１の半導体チップの裏面の電極を導電性接
合材で接合し、第２の金属電極板上に第２の半導体チッ
プの裏面の電極を導電性接合材で接合し、第１の半導体
チップの上面の電極を第２の金属電極板に、第２の半導
体チップの上面の電極を第３の金属電極板にそれぞれ金
属ワイヤで接続した半導体装置の実装構造において、第
２の金属電極板の第２の半導体チップを接合した領域と
第１の金属電極板とが略同層とされて下面が樹脂ベース
の底面に露出し、第３の金属電極板は、第２の金属電極
板の第２の半導体チップを接合した領域の両側辺にそっ
て延びる延設部と該延設部をつないで第１の金属電極板
と重なる連通部を有して第１の金属電極板より高い位置
に配置され、第１の金属電極板は第３の金属電極板の連
通部に重なる重なり領域と第１の半導体チップが接合さ
れる主部とを有し、第２の金属電極板は、第２の半導体
チップを接合した領域から上方へオフセットして連通部
を乗り越え第３の金属電極板と略同層で第１の金属電極
板上に延びる高段部を備えて、第１および第３の金属電
極板はそれぞれ連通部および重なり領域を主部の側辺よ
り突出させて外部接続部とするものとした。According to a first aspect of the present invention, there is provided first, second and third metal electrode plates which are molded on a resin base and are insulated from each other. An electrode on the back surface of the first semiconductor chip is bonded on the plate with a conductive bonding material, and an electrode on the back surface of the second semiconductor chip is bonded on the second metal electrode plate with a conductive bonding material. In a semiconductor device mounting structure in which the electrode on the upper surface of the semiconductor chip is connected to the second metal electrode plate and the electrode on the upper surface of the second semiconductor chip is connected to the third metal electrode plate by metal wires, the second metal electrode The region of the plate where the second semiconductor chip is joined and the first metal electrode plate are substantially in the same layer, and the lower surface is exposed on the bottom surface of the resin base. The third metal electrode plate is formed of the second metal electrode plate. An extending portion extending along both sides of a region where the second semiconductor chip is joined; The first metal electrode plate is provided at a position higher than the first metal electrode plate with a communication portion overlapping the first metal electrode plate by connecting the extending portion, and the first metal electrode plate is connected to the communication portion of the third metal electrode plate. An overlapping region and a main portion to which the first semiconductor chip is joined, wherein the second metal electrode plate is offset upward from the region to which the second semiconductor chip is joined and rides over the communicating portion; The first and third metal electrode plates are provided with a high step portion extending on the first metal electrode plate in substantially the same layer as the metal electrode plate, and each of the first and third metal electrode plates has a communicating portion and an overlapping region protruding from the side of the main portion. An external connection was used.

【００１１】請求項２の発明は、樹脂ベースの周辺部に
いずれの金属電極板も露出しない第１の貫通穴が設けら
れているものとした。さらに請求項３の発明は、樹脂ベ
ースの中央部にいずれの金属電極板も露出しない第２の
貫通穴が設けられているものとした。[0011] In the invention of claim 2, the first through hole which does not expose any metal electrode plate is provided in the peripheral portion of the resin base. Further, in the invention according to claim 3, a second through hole is provided in a central portion of the resin base so that no metal electrode plate is exposed.

【００１２】請求項４の発明は、第２の貫通穴が第１、
第２および第３の金属電極板が重なる部位に設けられ、
第１、第２および第３の金属電極板は第２の貫通穴より
大径の穴を有して該第２の貫通穴に露出しないように構
成されているものとした。According to a fourth aspect of the present invention, the second through-hole is the first,
A second metal electrode plate is provided at a portion where the second metal electrode plate overlaps;
The first, second, and third metal electrode plates have holes larger in diameter than the second through holes and are configured not to be exposed to the second through holes.

【００１３】請求項５の発明は、樹脂ベースにモールド
されて互いに絶縁された第１、第２および第３の金属電
極板を備え、第１の金属電極板上に第１の半導体チップ
の裏面の電極を導電性接合材で接合し、第２の金属電極
板上に第２の半導体チップの裏面の電極を導電性接合材
で接合し、第１の半導体チップの上面の電極を第２の金
属電極板に、第２の半導体チップの上面の電極を第３の
金属電極板にそれぞれ金属ワイヤで接続した半導体装置
の実装構造において、第１の金属電極板の第１の半導体
チップが接合される主部と第２の金属電極板の第２の半
導体チップを接合した領域とが略同層とされて下面が樹
脂ベースの底面に露出し、第３の金属電極板は、第２の
金属電極板の第２の半導体チップを接合した領域の両側
辺にそって延び第１の金属電極板の主部より高い位置に
配置された延設部と、該延設部を樹脂ベースの外端側で
つないで上方へ立ち上げた連通部とを有し、第２の金属
電極板は、第２の半導体チップを接合した領域から上方
へオフセットして第３の金属電極板の延設部と略同層で
第１の金属電極板の主部上に延びる高段部を備え、第１
の金属電極板は主部に対して上方へ立ち上げて第３の金
属電極板の連通部に対向して重なる重なり領域を備え、
第１および第３の金属電極板はそれぞれ連通部および重
なり領域を主部の側辺より突出させて外部接続部とする
ものとした。According to a fifth aspect of the present invention, there are provided first, second and third metal electrode plates molded on a resin base and insulated from each other, and the back surface of the first semiconductor chip is provided on the first metal electrode plate. Are bonded with a conductive bonding material, the electrodes on the back surface of the second semiconductor chip are bonded on the second metal electrode plate with the conductive bonding material, and the electrodes on the upper surface of the first semiconductor chip are bonded on the second metal electrode plate. The first semiconductor chip of the first metal electrode plate is joined to the metal electrode plate in a mounting structure of a semiconductor device in which electrodes on the upper surface of the second semiconductor chip are connected to the third metal electrode plate by metal wires. The main portion of the second metal electrode plate and the region where the second semiconductor chip of the second metal electrode plate is joined are substantially in the same layer, the lower surface is exposed to the bottom surface of the resin base, and the third metal electrode plate is formed of the second metal electrode plate. The electrode plate extends along both sides of the region where the second semiconductor chip is bonded to the electrode plate. A second metal electrode having an extended portion disposed at a position higher than the main portion of the metal electrode plate, and a communicating portion which is connected to the extended portion on the outer end side of the resin base and rises upward. The plate includes a high step portion extending upward from a region where the second semiconductor chip is bonded and extending over the main portion of the first metal electrode plate in substantially the same layer as the extending portion of the third metal electrode plate. , First
The metal electrode plate has an overlapping region that is raised upward with respect to the main portion and faces and overlaps the communication portion of the third metal electrode plate.
Each of the first and third metal electrode plates has a communicating portion and an overlapping region protruding from the side of the main portion to serve as an external connecting portion.

【００１４】請求項６の発明は、とくに第１の金属電極
板が主部と連通部の間に開口を有し、該開口内に第２の
金属電極板の第２の半導体チップを接合した領域が配置
されているものとした。また、請求項７の発明は、第２
の金属電極板の第２の半導体チップを接合した領域が、
第１の金属電極板の主部を挟んで連通部と反対側に配置
され、第３の金属電極板の延設部は、第１の金属電極板
の主部上を、第２の金属電極板の第２の半導体チップを
接合した領域の両側辺まで延びているものとした。According to a sixth aspect of the present invention, the first metal electrode plate has an opening between the main portion and the communicating portion, and the second semiconductor chip of the second metal electrode plate is joined in the opening. It is assumed that the area is arranged. The invention according to claim 7 is the second invention.
The region where the second semiconductor chip of the metal electrode plate is joined is
The extended portion of the third metal electrode plate is disposed on the opposite side of the communication portion with respect to the main portion of the first metal electrode plate, and the second metal electrode extends over the main portion of the first metal electrode plate. It extends to both sides of the region where the second semiconductor chip of the plate is joined.

【００１５】請求項８の発明は、樹脂ベースの周辺部に
いずれの金属電極板も露出しない第１の貫通穴が設けら
れているものとした。また、請求項９の発明は、樹脂ベ
ースの中央部にいずれの金属電極板も露出しない第２の
貫通穴が設けられているものとした。The invention according to claim 8 is characterized in that a first through-hole which does not expose any metal electrode plate is provided in a peripheral portion of the resin base. Further, in the invention of claim 9, a second through hole is provided in a central portion of the resin base so that none of the metal electrode plates is exposed.

【００１６】請求項１０の発明は、上記各発明におい
て、とくに第２の半導体チップを接合した第２の金属電
極板が複数並列に設けられ、第３の金属電極板は各第２
の金属電極板に対応して延設部を備えるとともに、連通
部がすべての延設部をつなぎ、第１の金属電極板は第２
の半導体チップを接合した主部を各第２の金属電極板に
対応して備えるとともに、連通部に重なる重なり領域が
すべての主部をつないでいるものとした。According to a tenth aspect of the present invention, in each of the above inventions, a plurality of second metal electrode plates, in particular, a second semiconductor chip is joined in parallel, and the third metal electrode plate is
The first metal electrode plate is provided with an extended portion corresponding to the first metal electrode plate, and the communication portion connects all the extended portions.
The main part in which the semiconductor chips are joined is provided corresponding to each of the second metal electrode plates, and the overlapping region overlapping the communication part connects all the main parts.

【００１７】[0017]

【発明の効果】請求項１の発明は、第２の金属電極板の
第２の半導体チップを接合した領域と第１の金属電極板
とが略同層とされ、第３の金属電極板は第１の金属電極
板と重なる連通部と延設部を有し、第１の金属電極板は
第３の金属電極板の連通部に重なる重なり領域と主部と
を有し、連通部と重なり領域を主部の側辺より突出させ
て第１、第３の金属電極板の外部接続部とするものとし
たので、樹脂ベースの中央部では第１の金属電極板が第
３の金属電極板の連通部と上下に重なっているが、この
重なり部分は垂直に立ち上がっていないので、ヒートシ
ンクへの取り付け面となる樹脂ベースの底面がモールド
成形後の冷却時に下に凸となる方向の収縮が阻害されな
い。このため、樹脂ベースの底面は少なくも平面とな
り、第１の金属電極板および第２の金属電極板の底面に
露出する部分とヒートシンクとの間に隙間が生じること
がなく、熱抵抗が有効に低減されるので、半導体装置の
信頼性が確保されるという効果を有する。According to the first aspect of the present invention, the region of the second metal electrode plate where the second semiconductor chip is joined and the first metal electrode plate are substantially the same layer, and the third metal electrode plate is The first metal electrode plate has a communication portion and an extension portion that overlap with the first metal electrode plate. The first metal electrode plate has an overlap region and a main portion that overlap with the communication portion of the third metal electrode plate, and the communication portion overlaps with the communication portion. Since the region protrudes from the side of the main portion and serves as an external connection portion of the first and third metal electrode plates, the first metal electrode plate is located at the center of the resin base. Of the resin base, which is the surface to be attached to the heat sink, prevents shrinkage in the direction in which the bottom surface of the resin base that becomes the mounting surface to the heat sink becomes convex downward during cooling after molding. Not done. For this reason, the bottom surface of the resin base is at least flat, and there is no gap between the portions exposed on the bottom surfaces of the first metal electrode plate and the second metal electrode plate and the heat sink. Since it is reduced, there is an effect that the reliability of the semiconductor device is ensured.

【００１８】請求項２の発明は、樹脂ベースの周辺部に
第１の貫通穴が設けられているので、この貫通穴を通し
てネジで樹脂ベースをヒートシンクに固定でき、下に凸
または少なくとも平面の樹脂ベース中央部分も確実にヒ
ートシンクに当接する。According to the second aspect of the present invention, since the first through hole is provided in the peripheral portion of the resin base, the resin base can be fixed to the heat sink with a screw through the through hole, and the resin base can be convex downward or at least flat. The central portion of the base also reliably contacts the heat sink.

【００１９】請求項３の発明は、樹脂ベースの中央部に
第２の貫通穴が設けられているので、この貫通穴を通し
てネジで中央部をヒートシンクに締め付けることによ
り、温度変化などにより万一底面が上に凸になろうとし
た場合にも、ヒートシンクとの間に隙間が発生せず、安
定した冷却性能が確保される。この場合、中央部では第
１の金属電極板が第３の金属電極板の連通部と上下に重
なり、また第２の金属電極板も部分的に重なっている
が、請求項４のように、少なくも第１、第３の金属電極
板の重なり部に大径の穴を有することにより、第１、第
３の金属電極板が露出しない第２の貫通穴を設けること
ができる。さらには第２の金属電極板にも大径の穴を形
成すれば、第１、第２および第３の金属電極板が重なる
部位でも第２の貫通穴を配置することができる。According to the third aspect of the present invention, since the second through-hole is provided in the center of the resin base, the center is fastened to the heat sink with a screw through the through-hole, so that the bottom surface may be changed due to a temperature change or the like. Even if it is going to be convex upward, no gap is generated between it and the heat sink, and stable cooling performance is secured. In this case, in the central portion, the first metal electrode plate vertically overlaps with the communication portion of the third metal electrode plate, and the second metal electrode plate also partially overlaps. By having a large-diameter hole at least in the overlapping portion of the first and third metal electrode plates, it is possible to provide a second through hole in which the first and third metal electrode plates are not exposed. Furthermore, if a large-diameter hole is also formed in the second metal electrode plate, the second through hole can be arranged even in a portion where the first, second, and third metal electrode plates overlap.

【００２０】請求項５の発明は、第１の金属電極板の第
１の半導体チップが接合される主部と第２の金属電極板
の第２の半導体チップを接合した領域とを略同層とし、
第３の金属電極板は、延設部を樹脂ベースの外端側で立
ち上げた連通部を有し、第１の金属電極板は主部に対し
て上方へ立ち上げて第３の金属電極板の連通部に対向し
て重なる重なり領域を備えるので、樹脂ベース底面に対
して立ち上がった対向部分が外端に位置し、このため、
当該部分が樹脂ベースのモールド成形後の冷却時におけ
る収縮を阻害しない。したがって、樹脂ベース底面が上
に凸になることがなく、請求項１の発明と同じく、第１
の金属電極板および第２の金属電極板の底面に露出する
部分とヒートシンクとの間に隙間が生じることがなく、
熱抵抗が有効に低減されるので、半導体装置の信頼性が
確保されるという効果を有する。According to a fifth aspect of the present invention, the main portion of the first metal electrode plate to which the first semiconductor chip is bonded and the region of the second metal electrode plate to which the second semiconductor chip is bonded are substantially in the same layer. age,
The third metal electrode plate has a communicating portion whose extended portion rises up on the outer end side of the resin base, and the first metal electrode plate rises upward with respect to the main portion to form the third metal electrode. Since there is provided an overlapping area that is opposed to the communicating portion of the plate, the facing portion that rises with respect to the bottom surface of the resin base is located at the outer end.
This portion does not hinder shrinkage during cooling after molding of the resin base. Therefore, the bottom surface of the resin base does not protrude upward, and the first base is the same as the first embodiment.
No gap is generated between the heat sink and the portion exposed on the bottom surface of the metal electrode plate and the second metal electrode plate,
Since the thermal resistance is effectively reduced, there is an effect that the reliability of the semiconductor device is ensured.

【００２１】また、請求項６の発明は、第１の金属電極
板の開口内に第２の金属電極板の第２の半導体チップを
接合した領域が配置されているものとしたので、これに
より、金属電極板の重ね構成を２層にでき、半導体装置
全体の高さを低くすることができる。According to the sixth aspect of the present invention, the region where the second semiconductor chip of the second metal electrode plate is bonded is arranged in the opening of the first metal electrode plate. In addition, the metal electrode plates can be stacked in two layers, and the overall height of the semiconductor device can be reduced.

【００２２】また、請求項７の発明は、第２の金属電極
板の第２の半導体チップを接合した領域を第１の金属電
極板の主部を挟んで連通部と反対側に配置し、第３の金
属電極板の延設部第２の金属電極板の第２の半導体チッ
プを接合した領域の両側辺まで延ばしたので、これによ
っても、金属電極板を２層にでき、半導体装置全体の高
さを低くすることができる。また、第１の金属電極板が
開口を有しないので簡素な構成となる。According to a seventh aspect of the present invention, a region where the second semiconductor chip of the second metal electrode plate is joined is disposed on the opposite side of the communication portion with respect to the main portion of the first metal electrode plate. Extending portion of third metal electrode plate Since the second metal electrode plate extends to both sides of the region where the second semiconductor chip is joined, the metal electrode plate can be formed in two layers, and the entire semiconductor device can be formed. Height can be reduced. In addition, since the first metal electrode plate has no opening, the configuration is simple.

【００２３】請求項８および請求項９の発明は、請求項
２、３の発明と同様に、貫通穴を通してネジで周辺部や
中央部をヒートシンクに締め付けることにより、樹脂ベ
ースを確実にヒートシンクに当接させ、また温度変化な
どにより万一底面が上に凸になろうとした場合にも、ヒ
ートシンクとの間に隙間が発生せず、安定した冷却性能
が確保される。According to the eighth and ninth aspects of the present invention, similarly to the second and third aspects of the present invention, the resin base is securely brought into contact with the heat sink by fastening the peripheral part and the central part to the heat sink with screws through the through holes. In the event that the bottom surface is made to project upward due to temperature change or the like, no gap is formed between the heat sink and the heat sink, and stable cooling performance is secured.

【００２４】請求項１０の発明は、第２の半導体チップ
を接合した第２の金属電極板を複数並列に設け、第１の
金属電極板の主部および第３の金属電極板の延設部をこ
れに対応させたので、例えばインバータ回路の複相分を
少ない部品点数の１ユニットに実現でき、回路全体を小
型に構成できる。According to a tenth aspect of the present invention, a plurality of second metal electrode plates to which a second semiconductor chip is joined are provided in parallel, and a main portion of the first metal electrode plate and an extended portion of the third metal electrode plate. Therefore, for example, the multi-phase component of the inverter circuit can be realized as one unit having a small number of components, and the entire circuit can be configured in a small size.

【００２５】[0025]

【発明の実施の形態】以下、本発明の実施の形態をイン
バータ回路の実装ユニットに適用した実施例により説明
する。実施例では、従来例において用いられたＭＯＳＦ
ＥＴからなる半導体チップ３ａ、３ｂのかわりに、それ
ぞれＩＧＢＴ（絶縁ゲートバイポーラトランジスタ）４
０（４０ｐ、４０ｎ）とＦＷＤ（フリーホイールダイオ
ード）４２（４２ｐ、４２ｎ）の組合せに置き換え、こ
れを１相について並列に２組用いるとともに、３相分を
モジュール化して図１に示す回路とする。DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to embodiments in which the present invention is applied to a mounting unit of an inverter circuit. In the embodiment, the MOSF used in the conventional example is used.
IGBTs (Insulated Gate Bipolar Transistors) 4 instead of the semiconductor chips 3a and 3b made of ET
0 (40p, 40n) and a combination of FWD (freewheel diode) 42 (42p, 42n), two sets of which are used in parallel for one phase, and three phases are modularized into a circuit shown in FIG. .

【００２６】図２は第１の実施例を示す上面図、図３は
その断面図で、（ａ）、（ｂ）、（ｃ）、（ｄ）はそれ
ぞれ図２におけるＡ−Ａ、Ｂ−Ｂ、Ｃ−Ｃ、およびＤ−
Ｄ各部の断面を示す。また、図４は本実装ユニットの半
導体モジュールにおける金属電極板の位置関係を示す斜
視図であり、樹脂ベースを省略している。図５は、金属
電極板を互いに分離して示す斜視図である。実装ユニッ
ト１００は、全体が上方に開口したケース状を呈する樹
脂ベース５０に、Ｃｕ（銅）、Ａｌ（アルミニウム）若
しくはこれらを含む合金からなり互いに絶縁された金属
電極板１０、２０（２０ｕ、２０ｖ、２０ｗ）および３
０をモールドして形成された半導体モジュール１０１
と、放熱シート５７およびヒートシンク５８（図３の
（ａ）参照）からなっている。なお、図３の（ａ）以外
では放熱シート５７およびヒートシンク５８は図示省略
している。FIG. 2 is a top view showing the first embodiment, and FIG. 3 is a cross-sectional view thereof, wherein (a), (b), (c) and (d) are AA and B- in FIG. B, CC and D-
D shows a cross section of each part. FIG. 4 is a perspective view showing the positional relationship of the metal electrode plates in the semiconductor module of this mounting unit, and omits the resin base. FIG. 5 is a perspective view showing the metal electrode plates separated from each other. The mounting unit 100 includes a metal base plate 10, 20 (20u, 20v) made of Cu (copper), Al (aluminum), or an alloy containing them, and insulated from each other on a resin base 50 having a case shape which is entirely open upward. , 20w) and 3
Semiconductor Module 101 Formed by Molding
And a heat radiating sheet 57 and a heat sink 58 (see FIG. 3A). In addition, the heat radiation sheet 57 and the heat sink 58 are not shown in FIG.

【００２７】すなわち、半導体モジュール１０１の金属
電極板１０と２０はそれぞれ樹脂ベース５０の底面を略
２分して露出しており、金属電極板１０、２０が露出し
た半導体モジュール１０１の底面には、電気的な絶縁性
を有する放熱シート５７を介してヒートシンク５８が取
り付けられて、ネジ６０で固定されている。これによ
り、金属電極板１０、２０に接合されるＩＧＢＴ４０
（４０ｐ、４０ｎ）とＦＷＤ４２（４２ｐ、４２ｎ）が
動作する際に発生する熱は、ヒートシンク５８に伝達さ
れ、放熱される。That is, the metal electrode plates 10 and 20 of the semiconductor module 101 are respectively exposed by dividing the bottom surface of the resin base 50 into approximately two parts, and the bottom surfaces of the semiconductor module 101 where the metal electrode plates 10 and 20 are exposed are: A heat sink 58 is attached via a heat-dissipating sheet 57 having electrical insulation, and is fixed with screws 60. Thereby, the IGBT 40 joined to the metal electrode plates 10 and 20
The heat generated when the (40p, 40n) and the FWD 42 (42p, 42n) operate is transmitted to the heat sink 58 and radiated.

【００２８】半導体モジュール１０１において、金属電
極板２０ｕ、２０ｖ、２０ｗはそれぞれの低段部２２が
互いの間に隙間を設けて横方向に並べられ、この並んだ
金属電極板２０の各低段部２２の端縁と対向して金属電
極板１０が配置されている。金属電極板３０は、金属電
極板２０ｕ、２０ｖ、２０ｗの並び方向に延びる連通部
３２と該連通部３２から所定間隔で設けられた延設部３
４（３４ａ、３４ｂ、３４ｃ、３４ｄ）を有し、連通部
３２が金属電極板１０の上記金属電極板２０の各低段部
２２と対向する端縁にそって、金属電極板１０の上に所
定の間隙をおいて重なっている。そして、各延設部３４
は金属電極板２０ｕ、２０ｖ、２０ｗの各側辺に重なっ
ており、したがってとくに延設部３４ｂは金属電極板２
０ｕと２０ｖ間の隙間にそって両者に跨る幅で延び、ま
た延設部３４ｃは金属電極板２０ｖと２０ｗ間の隙間に
そって両者に跨る幅で延びている。In the semiconductor module 101, the metal electrode plates 20u, 20v, and 20w are arranged in the horizontal direction with the low step portions 22 provided with a gap between each other. The metal electrode plate 10 is arranged to face the edge of the metal electrode 22. The metal electrode plate 30 includes a communicating portion 32 extending in the direction in which the metal electrode plates 20u, 20v, and 20w are arranged, and an extending portion 3 provided at a predetermined interval from the communicating portion 32.
4 (34a, 34b, 34c, 34d), and the communicating portion 32 is placed on the metal electrode plate 10 along the edge of the metal electrode plate 10 facing the low step portion 22 of the metal electrode plate 20. They overlap with a predetermined gap. Then, each extension portion 34
Overlaps each side of the metal electrode plates 20u, 20v, and 20w.
The extending portion 34c extends along the gap between the metal electrode plates 20v and 20w along the gap between the metal electrode plates 20v and 20w.

【００２９】金属電極板２０はそれぞれその低段部２２
の金属電極板１０と対向する端縁の幅方向中央部から延
びる細幅の高段部２４を備え、この高段部２４は一旦上
方へオフセットして金属電極板３０の連通部３２を乗り
越え、それから金属電極板１０の上を所定の間隙をもっ
て金属電極板３０と同じ高さ（同層）で延び、ぞの先端
が外部接続部２６として樹脂ベース５０から側方へ突出
して露出している。Each of the metal electrode plates 20 has a low step portion 22.
A high step portion 24 having a narrow width extending from the center in the width direction of the edge facing the metal electrode plate 10. The high step portion 24 is once offset upward and climbs over the communication portion 32 of the metal electrode plate 30, Then, it extends over the metal electrode plate 10 at the same height (the same layer) as the metal electrode plate 30 with a predetermined gap, and the tip of each of the metal electrode plates 30 projects outward from the resin base 50 as the external connection portion 26 and is exposed.

【００３０】金属電極板１０は、金属電極板３０の連通
部３２が重なっている領域を同じく連通部１２とし、金
属電極板２０の高段部２４が重なっている主部１１にス
リット１３を有している。スリット幅は細く、金属電極
板２０の高段部２４はスリット１３を跨る幅で延びてい
る。金属電極板１０の連通部１２と金属電極板３０の連
通部３２とは、それぞれ一端側（ここでは延設部３４ｄ
側）で互いの間隙を保持したまま上方へ垂直に折り曲げ
られて樹脂ベース５０から上へ延び、その後、外部接続
部１６、３６として互いに逆方向、かつ連通部１２、３
２と平行に折り曲げられている。The metal electrode plate 10 has a region where the communication portion 32 of the metal electrode plate 30 overlaps the communication portion 12, and has a slit 13 in the main portion 11 where the high step portion 24 of the metal electrode plate 20 overlaps. are doing. The slit width is small, and the high step portion 24 of the metal electrode plate 20 extends with a width across the slit 13. Each of the communicating portion 12 of the metal electrode plate 10 and the communicating portion 32 of the metal electrode plate 30 has one end (here, the extending portion 34 d
Side) and vertically bent upward from the resin base 50 while maintaining the gap therebetween, and thereafter, as the external connection portions 16 and 36, in the opposite directions to each other and the communication portions 12, 3
It is bent parallel to 2.

【００３１】インバータ回路における１相分について説
明すると、樹脂ベース５０の底面にある金属電極板１０
の主部１１上には、図２の上面図上、金属電極板２０
（２０ｕ）の高段部２４を挟み、該高段部２４にそった
両側にＩＧＢＴ４０ｐとＦＷＤ４２ｐの組が１組ずつ、
合計２組が導電性接合材である半田により接合されてい
る。同じく樹脂ベース５０の底面にある金属電極板２０
の低段部２２上にも、金属電極板３０の連通部３２と延
設部３４（３４ａ、３４ｂ）でコ字形に囲まれた領域に
おいて、各延設部にそってＩＧＢＴ４０ｎとＦＷＤ４２
ｎの組が１組ずつ半田により接合されている。上記金属
電極板１０上の２組のＩＧＢＴ４０ｐとＦＷＤ４２ｐが
発明における第１の半導体チップを構成し、金属電極板
２０上の２組のＩＧＢＴ４０ｐとＦＷＤ４２ｐが発明に
おける第２の半導体チップを構成している。To explain one phase in the inverter circuit, the metal electrode plate 10 on the bottom of the resin base 50 will be described.
On the main part 11 of FIG.
A pair of the IGBT 40p and the FWD 42p is provided on both sides along the high step portion 24 with the (20u) high step portion 24 interposed therebetween.
A total of two sets are joined by a solder which is a conductive joining material. Metal electrode plate 20 also on the bottom of resin base 50
The IGBT 40n and the FWD 42 are formed along the extending portions in the region surrounded by the communication portion 32 of the metal electrode plate 30 and the extending portions 34 (34a, 34b) in a U-shape also on the low step portion 22 of FIG.
The n sets are joined one by one by soldering. The two sets of IGBTs 40p and FWD42p on the metal electrode plate 10 constitute a first semiconductor chip in the invention, and the two sets of IGBTs 40p and FWD42p on the metal electrode plate 20 constitute a second semiconductor chip in the invention. .

【００３２】さらに、金属電極板２０ｕ近傍における上
記コ字形に囲まれた領域の開口側には、ＩＧＢＴ４０ｎ
とＦＷＤ４２ｎの組に対応させて、ゲート端子４９ｎが
樹脂ベース５０にモールドされ、金属電極板１０近傍に
おける連通部１２と反対側には、ＩＧＢＴ４０ｐとＦＷ
Ｄ４２ｐの組に対応させて、ゲート端子４９ｐが樹脂ベ
ース５０にモールドされている。Further, an IGBT 40n is formed on the opening side of the region surrounded by the U-shape in the vicinity of the metal electrode plate 20u.
The gate terminal 49n is molded on the resin base 50 in correspondence with the set of the FWD 42n and the IGBT 40p and the FW
The gate terminal 49p is molded on the resin base 50 corresponding to the set of D42p.

【００３３】ＩＧＢＴ４０は半田接合面をコレクタと
し、金属電極板１０上のＩＧＢＴ４０ｐは上面のエミッ
タ電極が金属電極板２０ｕの高段部２４に複数本の金属
ワイヤＷ１によって接続されている。また、ＩＧＢＴ４
０ｐの上面のゲート電極はゲート端子４９ｐと金属ワイ
ヤＷ３によって接続されている。ＦＷＤ４２は半田接合
面をカソードとし、上面のアノード電極が高段部２４に
複数本の金属ワイヤＷ２によって接続されている。The IGBT 40 has a solder bonding surface as a collector, and the IGBT 40p on the metal electrode plate 10 has an emitter electrode on the upper surface connected to the high step portion 24 of the metal electrode plate 20u by a plurality of metal wires W1. In addition, IGBT4
The gate electrode on the upper surface of 0p is connected to the gate terminal 49p by a metal wire W3. The FWD 42 has a solder joint surface as a cathode, and an anode electrode on the upper surface is connected to the high step portion 24 by a plurality of metal wires W2.

【００３４】金属電極板２０ｕ上のＩＧＢＴ４０ｎは、
上面のエミッタ電極が金属電極板３０の延設部３４（３
４ａ、３４ｂ）に複数本の金属ワイヤＷ１によって接続
され、ゲート電極はゲート端子４９ｎと金属ワイヤＷ３
によって接続されている。また、ＦＷＤ４２ｎは上面の
アノード電極が延設部３４に複数本の金属ワイヤＷ２に
よって接続されている。The IGBT 40n on the metal electrode plate 20u is
The emitter electrode on the upper surface is connected to the extension portion 34 (3
4a, 34b) are connected by a plurality of metal wires W1, and the gate electrode is connected to the gate terminal 49n and the metal wire W3.
Connected by In the FWD 42n, an anode electrode on the upper surface is connected to the extending portion 34 by a plurality of metal wires W2.

【００３５】他の相についても同様であり、これによ
り、図１に示される回路が形成される。金属電極板１０
の外部接続部１６が回路入力のＰ端子になり、金属電極
板３０の外部接続部３６がＮ端子、金属電極板２０（２
０ｕ、２０ｖ、２０ｗ）の各外部接続部２６が出力端子
Ｕ、Ｖ、Ｗとなる。これらの入出力端子はさらにインバ
ータ装置における図示しないバスバーあるいは強電ケー
ブルに接続される。また、ゲート端子４９ｐ、４９ｎは
例えば半導体モジュールの樹脂ベース５０の上に取り付
けられる不図示の駆動信号制御基板の駆動信号出力端子
に接続される。The same applies to other phases, whereby the circuit shown in FIG. 1 is formed. Metal electrode plate 10
Of the metal electrode plate 30 is the N terminal, and the external connection portion 36 of the metal electrode plate 30 is the N terminal.
0u, 20v, 20w) become output terminals U, V, W. These input / output terminals are further connected to a bus bar or a high-power cable (not shown) in the inverter device. The gate terminals 49p and 49n are connected to, for example, drive signal output terminals of a drive signal control board (not shown) mounted on the resin base 50 of the semiconductor module.

【００３６】半導体モジュール１０１の周辺部には、樹
脂ベース５０の角部、高段部２４間の中間位置、および
延設部３４の先端近傍にネジ貫通穴５２が設けられ、半
導体モジュール１０１をヒートシンク５８に固定するた
めのネジ６０が貫通可能となっている。金属電極板１０
および金属電極板２０の低段部２２にはネジ貫通穴５２
との間に所定の間隙をもつように切り欠き１８、２８が
形成され、ネジ貫通穴５２の内壁をモールド樹脂とし
て、ネジ６０と絶縁するようになっている。At the periphery of the semiconductor module 101, screw through holes 52 are provided at the corners of the resin base 50, at an intermediate position between the high step portions 24, and near the tip of the extension portion 34. A screw 60 for fixing to 58 can penetrate. Metal electrode plate 10
And a screw through hole 52 in the low step portion 22 of the metal electrode plate 20.
Notches 18 and 28 are formed so as to have a predetermined gap therebetween, and the inner wall of the screw through hole 52 is used as a mold resin to insulate the screw 60.

【００３７】また、半導体モジュール１０１の中央部に
おいては、金属電極板２０の高段部２４、金属電極板３
０、１０の連通部３２、１２の重なり部分にネジ貫通穴
５３が設けられ、周辺部と同じくネジ６０が貫通可能と
なっている。このネジ貫通穴５３まわりにおいても、高
段部２４および連通部１２、３２にはそれぞれネジ貫通
穴５３より大径の穴が形成されて、ネジ貫通穴５３の内
壁をモールド樹脂として、ネジ６０と絶縁するようにな
っている。半導体モジュール１０１のネジ貫通穴５２、
５３に対応して、放熱シート５７には貫通穴が設けら
れ、ヒートシンク５８には雌ねじが形成されている。In the center of the semiconductor module 101, the high step portion 24 of the metal electrode plate 20 and the metal electrode plate 3
A screw through hole 53 is provided in an overlapping portion of the communication portions 32 and 12 of 0 and 10, and a screw 60 can be penetrated similarly to the peripheral portion. Also around the screw through hole 53, holes having a larger diameter than the screw through hole 53 are formed in the high step portion 24 and the communication portions 12 and 32, respectively. It is designed to be insulated. Screw through hole 52 of semiconductor module 101,
Corresponding to 53, a through hole is provided in the heat radiation sheet 57, and a female screw is formed in the heat sink 58.

【００３８】本実施例は以上のように構成され、半導体
モジュール１０１の金属電極板１０、２０、３０を上下
に重ねて配置したので、平面投影面積が小さく、コンパ
クトな実装ユニットが得られる。同じく、金属電極板２
０と１０、あるいは金属電極板３０と２０が対向して重
なり合っているので、ＩＧＢＴ４０の動作時に各金属電
極板に発生するインダクタンスが、対向している間の相
互誘導作用により打ち消されるという利点を有してい
る。In this embodiment, the metal electrode plates 10, 20, and 30 of the semiconductor module 101 are arranged one above the other, so that a compact projection unit having a small planar projection area can be obtained. Similarly, metal electrode plate 2
Since the 0 and 10 or the metal electrode plates 30 and 20 are opposed to each other and overlapped, there is an advantage that the inductance generated in each metal electrode plate during the operation of the IGBT 40 is canceled out by the mutual induction action during the opposed operation. are doing.

【００３９】そして実施例ではとくに、金属電極板１０
と金属電極板３０がそれぞれの連通部１２、３２が半導
体モジュール１０１の中央部で上下に重なっているだけ
で、各外部接続部１６、３６はそれぞれ連通部の端部に
おいて、実質樹脂ベース５０の外部に出てから立ち上げ
られている。すなわち、金属電極板１０と金属電極板３
０の外部接続部１６、３６は、樹脂ベース５０の中央部
において底面に対して垂直に立ち上がってはおらず、そ
の間にモールド樹脂を挟む構成ともなっていないから、
樹脂ベース５０のモールド成形後の冷却時に、ケースの
側壁が内側に収縮しようとするのを阻害するものがな
く、半導体モジュール１０１の底面は下に凸となる。し
たがって、半導体モジュール１０１をヒートシンク５８
に固定したとき、半導体モジュール１０１の底面とヒー
トシンク５８間に隙間が生じることがなく、熱抵抗が有
効に低減されて半導体装置の信頼性が確保される。In the embodiment, in particular, the metal electrode plate 10
The external connection portions 16 and 36 are respectively formed at the ends of the communication portions at the end portions of the communication portions 12 and 32 only at the center of the semiconductor module 101. It has been launched after going outside. That is, the metal electrode plate 10 and the metal electrode plate 3
Since the external connection portions 16 and 36 of 0 do not rise perpendicularly to the bottom surface at the center of the resin base 50 and are not configured to sandwich the mold resin therebetween,
When the resin base 50 is cooled after molding, there is nothing to prevent the side wall of the case from shrinking inward, and the bottom surface of the semiconductor module 101 is convex downward. Therefore, the semiconductor module 101 is connected to the heat sink 58.
When fixed to the semiconductor module 101, there is no gap between the bottom surface of the semiconductor module 101 and the heat sink 58, the thermal resistance is effectively reduced, and the reliability of the semiconductor device is ensured.

【００４０】また、半導体モジュール１０１の周辺部だ
けでなく中央部にもネジ貫通穴５３を設けてあるので、
このネジ貫通穴５３を通してネジ６０により中央部もヒ
ートシンク５８に締め付けることにより、温度変化など
により万一半導体モジュール１０１の底面が上に凸にな
ろうとした場合にも、ヒートシンク５８との間の隙間発
生を抑制し、安定した冷却性能が確保される。Further, since the screw through hole 53 is provided not only in the peripheral part but also in the central part of the semiconductor module 101,
By tightening the center portion of the semiconductor module 101 to the heat sink 58 by the screw 60 through the screw through hole 53, even if the bottom surface of the semiconductor module 101 is going to be convex due to a temperature change or the like, a gap between the semiconductor module 101 and the heat sink 58 is generated. And stable cooling performance is ensured.

【００４１】つぎに、第２の実施例について説明する。
図６は第２の実施例を示す上面図、図７はその断面図
で、（ａ）、（ｂ）、（ｃ）、（ｄ）はそれぞれ図６に
おけるＥ−Ｅ、Ｆ−Ｆ、Ｇ−Ｇ、およびＨ−Ｈ各部の断
面を示す。また、図８は本実装ユニットの半導体モジュ
ール１０１Ａにおける金属電極板の位置関係を示す斜視
図であり、樹脂ベースを省略している。本実装ユニット
１００Ａも半導体モジュール１０１Ａの樹脂ベース５０
Ａに３種の金属電極板を備える。Next, a second embodiment will be described.
FIG. 6 is a top view showing the second embodiment, and FIG. 7 is a cross-sectional view thereof. (A), (b), (c) and (d) show EE, FF and G in FIG. 6, respectively. -G and the cross section of each part of HH are shown. FIG. 8 is a perspective view showing the positional relationship of the metal electrode plates in the semiconductor module 101A of this mounting unit, and omits the resin base. The mounting unit 100A is also the resin base 50 of the semiconductor module 101A.
A includes three types of metal electrode plates.

【００４２】金属電極板１０Ａの主部１１Ａと２０Ａ
（２０Ａｕ、２０Ａｖ、２０Ａｗ）の低段部２２Ａはそ
れぞれ樹脂ベース５０Ａの底面において、放熱シート５
７Ａおよびヒートシンク５８Ａ側へ露出している。な
お、図７の（ａ）以外では放熱シート５７Ａおよびヒー
トシンク５８Ａは図示省略している。金属電極板１０
Ａ、２０Ａが露出した半導体モジュール１０１Ａの底面
には、電気的な絶縁性を有する放熱シート５７Ａを介し
てヒートシンク５８Ａが取り付けられて、ネジ６０で固
定されている。The main parts 11A and 20A of the metal electrode plate 10A
(20Au, 20Av, 20Aw) low step portions 22A are provided on the bottom surface of the resin base 50A, respectively.
7A and the heat sink 58A are exposed. Note that, except for FIG. 7A, the heat radiation sheet 57A and the heat sink 58A are not shown. Metal electrode plate 10
A heat sink 58A is attached to the bottom surface of the semiconductor module 101A where A and 20A are exposed via a heat-dissipating sheet 57A having electrical insulation, and is fixed with screws 60.

【００４３】半導体モジュール１０１Ａにおいて、金属
電極板１０Ａは、樹脂ベース５０Ａの底面の略半部に広
がってＩＧＢＴ４０とＦＷＤ４２が接合される主部１１
Ａから等間隔に４本の枝部１４が延び、さらに各枝部１
４の先端をつなげる連通部１２Ａを有している。これに
より、枝部１４間に３つの矩形の開口１５が形成され
る。また連通部１２Ａは主部１１Ａおよび枝部１４に対
して垂直に上方へ折り曲げられている。In the semiconductor module 101A, the metal electrode plate 10A has a main portion 11 which extends over substantially half of the bottom surface of the resin base 50A to join the IGBT 40 and the FWD 42.
A, four branches 14 extend at equal intervals from each other.
4 has a communicating portion 12A for connecting the front ends of the four. As a result, three rectangular openings 15 are formed between the branches 14. The communication portion 12A is bent vertically upward with respect to the main portion 11A and the branch portion 14.

【００４４】金属電極板１０Ａの開口１５内に、所定の
隙間をもって金属電極板２０Ａの各低段部２２Ａが配置
され、低段部２２Ａの金属電極板１０Ａの主部１１Ａに
対向する端縁から所定幅の高段部２４Ａが上方へオフセ
ットして、主部１１Ａの上を所定の間隙をもって延び、
その先端が外部接続部２６Ａとして樹脂ベース５０Ａか
ら側方へ突出して露出している。The low step portions 22A of the metal electrode plate 20A are arranged in the opening 15 of the metal electrode plate 10A with a predetermined gap, and the low step portions 22A are arranged from the edge facing the main portion 11A of the metal electrode plate 10A. The high step portion 24A having a predetermined width is offset upward, extends over the main portion 11A with a predetermined gap,
The tip is exposed as a lateral connection 26A from the resin base 50A.

【００４５】金属電極板３０Ａは、連通部３２Ａと、連
通部３２Ａから金属電極板１０Ａの枝部１４の上に所定
の間隙をもって金属電極板２０Ａの高段部２４Ａと同じ
高さ（同層）で延びる延設部３４Ａとを備え、延設部３
４Ａは、枝部１４とその枝部１４にそう隙間を挟んで隣
接の金属電極板２０Ａの低段部２２Ａに跨る幅を有して
いる。金属電極板３０Ａの連通部３２Ａは、金属電極板
１０Ａの連通部１２Ａと同じく垂直に上方へ折り曲げら
れて、所定の間隔をもって連通部１２Ａと対向してい
る。連通部１２Ａ、３２Ａはそれぞれの一端が長手方向
に延びて、樹脂ベース５０Ａの金属電極板２０Ａの外部
接続部２６Ａが突出する面とは直角の側面から突出して
露出し、外部接続部１６Ａ、３６Ａとなっている。The metal electrode plate 30A has the same height (the same layer) as the high step portion 24A of the metal electrode plate 20A with a predetermined gap between the communication portion 32A and the branch portion 14 of the metal electrode plate 10A from the communication portion 32A. Extending portion 34A extending at
4A has a width that spans the branch portion 14 and the low step portion 22A of the adjacent metal electrode plate 20A with a gap therebetween. The communication part 32A of the metal electrode plate 30A is bent vertically upward like the communication part 12A of the metal electrode plate 10A, and faces the communication part 12A at a predetermined interval. One end of each of the communication portions 12A and 32A extends in the longitudinal direction, and the communication portions 12A and 32A project from a side surface of the metal base plate 20A of the resin base 50A perpendicular to the surface where the external connection portion 26A protrudes, and are exposed. It has become.

【００４６】インバータ回路における１相分について説
明すると、金属電極板１０Ａの主部１１Ａ上には、図６
の上面図上、金属電極板２０Ａｕの高段部２４Ａの両側
に該高段部２４ＡにそったＩＧＢＴ４０ｐとＦＷＤ４２
ｐの組が１組ずつ半田により接合されている。金属電極
板２０Ａｕの低段部２２Ａ上にも、その両側辺にそって
並んだ金属電極板３０Ａの延設部３４ＡにそってＩＧＢ
Ｔ４０ｎとＦＷＤ４２ｎの組が１組ずつ半田により接合
されている。さらに、金属電極板１０Ａ上のＩＧＢＴ４
０ｐとＦＷＤ４２ｐの各組に対応させて金属電極板１０
Ａの開口１５とは反対側、および金属電極板２０Ａ上の
ＩＧＢＴ４０ｎとＦＷＤ４２ｎの各組に対応させて高段
部２４Ａとは反対側には、それぞれゲート端子４９ｐ、
４９ｎが樹脂ベース５０Ａにモールドされている。Explaining one phase in the inverter circuit, FIG.
IGBTs 40p and FWDs 42 on both sides of the high step portion 24A of the metal electrode plate 20Au on the top view of FIG.
The sets of p are joined one by one by soldering. The IGB is also formed on the low step portion 22A of the metal electrode plate 20Au along the extending portion 34A of the metal electrode plate 30A arranged along both sides.
One set of T40n and one set of FWD42n are joined by solder. Further, the IGBT4 on the metal electrode plate 10A
0p and the metal electrode plate 10 corresponding to each set of FWD42p.
The gate terminal 49p is provided on the side opposite to the opening 15 of A and on the side opposite to the high step portion 24A corresponding to each set of the IGBT 40n and the FWD 42n on the metal electrode plate 20A.
49n are molded in the resin base 50A.

【００４７】金属電極板１０Ａ上のＩＧＢＴ４０ｐは上
面のエミッタ電極が金属電極板２０Ａの高段部２４Ａに
複数本の金属ワイヤＷ１によって接続されている。ま
た、ＩＧＢＴ４０ｐ上面のゲート電極はゲート端子４９
ｐと金属ワイヤＷ３によって接続されている。ＦＷＤ４
２ｐは上面のアノード電極が高段部２４Ａに複数本の金
属ワイヤＷ２によって接続されている。The IGBT 40p on the metal electrode plate 10A has an emitter electrode on the upper surface connected to the high step portion 24A of the metal electrode plate 20A by a plurality of metal wires W1. The gate electrode on the upper surface of the IGBT 40p is a gate terminal 49.
p and a metal wire W3. FWD4
2p, the anode electrode on the upper surface is connected to the high step portion 24A by a plurality of metal wires W2.

【００４８】金属電極板２０Ａ上のＩＧＢＴ４０ｎは、
上面のエミッタ電極が金属電極板３０Ａの延設部３４Ａ
に複数本の金属ワイヤＷ１によって接続され、ゲート電
極はゲート端子４９ｎと金属ワイヤＷ３によって接続さ
れている。また、ＦＷＤ４２ｎは上面のアノード電極が
延設部３４Ａに複数本の金属ワイヤＷ２によって接続さ
れている。他の相についても同様であり、これにより、
図１に示される回路が形成される。金属電極板１０Ａの
外部接続部１６Ａが回路のＰ端子になり、金属電極板３
０Ａの外部接続部３６ＡがＮ端子、金属電極板２０Ａの
外部接続部２６Ａが出力端子となる。The IGBT 40n on the metal electrode plate 20A is
The emitter electrode on the upper surface is the extension portion 34A of the metal electrode plate 30A.
Are connected by a plurality of metal wires W1, and the gate electrode is connected to the gate terminal 49n by the metal wire W3. In the FWD 42n, an anode electrode on the upper surface is connected to the extension 34A by a plurality of metal wires W2. The same is true for the other phases, whereby
The circuit shown in FIG. 1 is formed. The external connection portion 16A of the metal electrode plate 10A becomes the P terminal of the circuit, and the metal electrode plate 3
The external connection portion 36A of 0A is an N terminal, and the external connection portion 26A of the metal electrode plate 20A is an output terminal.

【００４９】半導体モジュール１０１Ａの周辺部には、
樹脂ベース５０Ａの角部、高段部２４Ａ間の中間位置、
および開口１５における低段部２２Ａと連通部１２Ａ間
のスペースにネジ貫通穴５２が設けられ、半導体モジュ
ール１０１Ａをヒートシンク５８Ａに固定するためのネ
ジ６０が貫通可能となっている。金属電極板１０Ａには
ネジ貫通穴５２との間に所定の間隙をもつように切り欠
き１８Ａが形成され、ネジ貫通穴５２の内壁をモールド
樹脂として、ネジ６０と絶縁するようになっている。In the peripheral portion of the semiconductor module 101A,
A corner portion of the resin base 50A, an intermediate position between the high step portions 24A,
A screw through hole 52 is provided in a space between the low step portion 22A and the communication portion 12A in the opening 15, and a screw 60 for fixing the semiconductor module 101A to the heat sink 58A can pass therethrough. A notch 18A is formed in the metal electrode plate 10A so as to have a predetermined gap between the metal electrode plate 10A and the screw through-hole 52, and the inner wall of the screw through-hole 52 is used as a mold resin to insulate the screw 60.

【００５０】また、半導体モジュール１０１Ａの中央部
においても、開口１５における低段部２２Ａと主部１１
Ａ間のスペースに高段部２４Ａを挟んでネジ貫通穴５３
が設けられ、周辺部と同じくネジ６０が貫通可能となっ
ている。各ネジ貫通穴５２、５３の内壁はモールド樹脂
とされ、ネジ６０と絶縁するようになっている。その他
の構成は、第１の実施例と同様である。また、放熱シー
ト５７Ａおよびヒートシンク５８Ａは、樹脂ベース５０
Ａのサイズに対応するとともにネジ貫通穴５２、５３の
配置に応じてネジの通過穴および雌ネジの位置が相違し
得るほかは、放熱シート５７およびヒートシンク５８と
同じである。Also, in the central portion of the semiconductor module 101A, the low step portion 22A and the main portion 11 in the opening 15 are formed.
A through-hole 53 with high step portion 24A interposed between spaces A
Are provided, and the screw 60 can be penetrated similarly to the peripheral part. The inner wall of each of the screw through holes 52 and 53 is made of a mold resin, and is insulated from the screw 60. Other configurations are the same as those of the first embodiment. Further, the heat radiation sheet 57A and the heat sink 58A are
The heat radiation sheet 57 and the heat sink 58 are the same as the heat radiation sheet 57 and the heat sink 58, except that the position of the screw passage hole and the internal thread may be different depending on the size of A and the arrangement of the screw through holes 52 and 53.

【００５１】本実施例は以上のように構成され、金属電
極板を重ねた配置により第１の実施例と同じくインダク
タンスが打ち消されるほか、金属電極板１０Ａと金属電
極板３０Ａの外部接続部１６Ａ、３６Ａに連なる連通部
１２Ａ、３２Ａの立上がりが樹脂ベース５０Ａの中央部
でなく樹脂ベースにおける側壁部分となっていることに
加えて、さらに、金属電極板の重なりが２枚までで、中
央部で３枚重なることもないから、第１の実施例に比較
して一層樹脂ベース５０Ａにおける収縮阻害が解消さ
れ、半導体モジュール１０１Ａの底面が上に凸となるこ
とがない。The present embodiment is constructed as described above. By arranging the metal electrode plates in an overlapping manner, the inductance is canceled as in the first embodiment, and the external connection portions 16A of the metal electrode plate 10A and the metal electrode plate 30A, In addition to the rising portions of the communication portions 12A and 32A connected to 36A being not the center portion of the resin base 50A but the side wall portions of the resin base, the overlap of the metal electrode plates is limited to two sheets, and Since there is no overlap, shrinkage inhibition in the resin base 50A is further eliminated as compared with the first embodiment, and the bottom surface of the semiconductor module 101A does not project upward.

【００５２】また、全体として金属電極板の重なりが２
層であるから、底面に対して連通部１２Ａ、３２Ａを垂
直に立ち上げた側部を除き、半導体モジュール１０１Ａ
の主要部の高さを必要に応じて低くできるという利点を
有する。また、第１の実施例と同様に、半導体モジュー
ル１０１Ａの周辺部ならびに中央部にネジ貫通穴５３を
設けて、このネジ貫通穴を通してネジ６０によりヒート
シンク５８Ａに締め付けるようになっているので、常に
確実にヒートシンク５８Ａとの間の隙間発生が防止さ
れ、半導体装置の信頼性が確保される。とくに金属電極
板１０Ａがその枝部１４を含めて樹脂ベース５０Ａの底
面全面に張り渡されているので、半導体モジュール底面
の反りが一様となり、ネジ締めされる各部位の圧接力の
ばらつきも減少する。Further, as a whole, the overlap of the metal electrode plates is 2
The semiconductor module 101A except for the side where the communicating portions 12A and 32A rise vertically to the bottom surface.
Has the advantage that the height of the main part can be reduced as required. Further, as in the first embodiment, screw through holes 53 are provided in the peripheral portion and the central portion of the semiconductor module 101A, and the semiconductor module 101A is tightened to the heat sink 58A by the screws 60 through the screw through holes. In addition, the generation of a gap with the heat sink 58A is prevented, and the reliability of the semiconductor device is ensured. In particular, since the metal electrode plate 10A is stretched over the entire bottom surface of the resin base 50A including the branch portions 14, the warpage of the semiconductor module bottom surface becomes uniform, and the variation in the press-contact force of each portion to be screwed is reduced. I do.

【００５３】図９は、第２の実施例に対する変形例を示
す、図８相当の半導体モジュールの斜視図である。この
変形例は、金属電極板１０Ａの主部と金属電極板２０Ａ
の低段部の配置を入れ替えたもので、各部材に新たな参
照番号を付して説明する。半導体モジュール１０１Ｂで
は、金属電極板１０Ｂの主部１１Ｂと金属電極板２０Ｂ
（２０Ｂｕ、２０Ｂｖ、２０Ｂｗ）の低段部２２Ｂがそ
れぞれ不図示の樹脂ベースの底面に露出している。金属
電極板１０Ｂは、上記主部１１Ｂと、主部１１Ｂに対し
て垂直に上方へ折り曲げられた連通部１２Ｂとからな
り、連通部１２Ｂは第２の実施例における連通部１２Ａ
と同じく、樹脂ベースの側壁内を延びて、長手方向の一
端が外部接続部１６Ｂとして樹脂ベースから側方へ突出
して露出する。FIG. 9 is a perspective view of a semiconductor module corresponding to FIG. 8, showing a modification of the second embodiment. In this modification, the main part of the metal electrode plate 10A and the metal electrode plate 20A
The arrangement of the low step portion is replaced, and each member is described with a new reference number. In the semiconductor module 101B, the main part 11B of the metal electrode plate 10B and the metal electrode plate 20B
The lower steps 22B of (20Bu, 20Bv, 20Bw) are respectively exposed on the bottom surface of the resin base (not shown). The metal electrode plate 10B includes the main portion 11B and a communication portion 12B that is bent vertically upward with respect to the main portion 11B. The communication portion 12B is a communication portion 12A in the second embodiment.
Similarly to the above, one end in the longitudinal direction extends in the side wall of the resin base, and is exposed to the side from the resin base as an external connection portion 16B.

【００５４】金属電極板１０Ｂの主部１１Ｂの連通部１
２Ｂと反対側の端縁に対向して、所定の隙間をもって金
属電極板２０Ｂの低段部２２Ｂが配置されている。金属
電極板２０Ｂｕ、２０Ｂｖ、２０Ｂｗは互いの間にも隙
間を設けて横方向に並べられ、それぞれ低段部２２Ｂの
端縁の中央から所定幅の高段部２４Ｂが上方へオフセッ
トして、主部１１Ｂの上を所定の間隙をもって連通部１
２Ｂ方向へ延びている。また、金属電極板２０Ｂの低段
部２２Ｂからは、高段部２４Ｂと反対方向に高段部２４
Ｂと同じ高さにオフセットして所定幅の外部接続部２６
Ｂが延び、樹脂ベースから側方へ突出して露出する。Communication part 1 of main part 11B of metal electrode plate 10B
The low step portion 22B of the metal electrode plate 20B is arranged with a predetermined gap facing the edge opposite to 2B. The metal electrode plates 20Bu, 20Bv, and 20Bw are arranged side by side with a gap between them, and the high step portion 24B having a predetermined width is offset upward from the center of the edge of the low step portion 22B. Communication part 1 with a predetermined gap on the part 11B
It extends in the 2B direction. Further, from the low step portion 22B of the metal electrode plate 20B, the high step portion 24 is formed in a direction opposite to the high step portion 24B.
The external connection portion 26 having a predetermined width offset to the same height as
B extends and projects laterally from the resin base and is exposed.

【００５５】金属電極板３０Ｂは、連通部３２Ｂと、連
通部３２Ｂから金属電極板１０Ｂの主部１１Ｂ上に所定
の間隙をもって金属電極板２０Ｂの高段部２４Ｂと同じ
高さ（同層）で延びる４本の延設部３４Ｂとを備えてい
る。各延設部３４Ｂは相互間に等幅の間隔を形成して、
各金属電極板２０Ｂ間の隙間上に延びている。中間２つ
の延設部３４Ｂは隙間を挟んで隣接する金属電極板２０
Ｂの低段部２２Ｂに跨る幅を有している。The metal electrode plate 30B has the same height (the same layer) as the high step portion 24B of the metal electrode plate 20B with a predetermined gap from the communication portion 32B to the main portion 11B of the metal electrode plate 10B from the communication portion 32B. And four extending portions 34B that extend. Each extending portion 34B forms an equal width interval between each other,
It extends over the gap between each metal electrode plate 20B. The two intermediate extending portions 34B are adjacent to each other with a gap therebetween.
B has a width spanning the low step portion 22B.

【００５６】金属電極板３０Ｂの連通部３２Ｂは、金属
電極板１０Ｂの連通部１２Ｂと同じく垂直に上方へ折り
曲げられて、所定の間隔をもって連通部１２Ｂと対向し
ている。連通部３２Ｂは一端が樹脂ベースの側面から突
出して露出し、金属電極板１０Ｂの外部接続部１６Ｂと
対向する外部接続部３６Ｂとなっている。The communication part 32B of the metal electrode plate 30B is bent vertically upward similarly to the communication part 12B of the metal electrode plate 10B, and faces the communication part 12B at a predetermined interval. One end of the communication portion 32B is projected and exposed from the side surface of the resin base, and serves as an external connection portion 36B facing the external connection portion 16B of the metal electrode plate 10B.

【００５７】インバータ回路における１相分について説
明すると、金属電極板１０Ｂの主部１１Ｂ上には、金属
電極板３０Ｂの延設部３４Ｂ間のスペースにおいて金属
電極板２０Ｂｕの高段部２４Ｂの両側に該高段部にそっ
たＩＧＢＴ４０ｐとＦＷＤ４２ｐの組が１組ずつ半田に
より接合されている。さらに、金属電極板１０Ｂ上のＩ
ＧＢＴ４０ｐとＦＷＤ４２ｐの各組に対応させて、連通
部１２Ｂ側には、それぞれゲート端子４９ｐが樹脂ベー
スにモールドされている。To explain one phase in the inverter circuit, the main portion 11B of the metal electrode plate 10B is provided on both sides of the high step portion 24B of the metal electrode plate 20Bu in the space between the extending portions 34B of the metal electrode plate 30B. One set of the IGBT 40p and the FWD 42p along the high step portion is joined by solder. Further, I on the metal electrode plate 10B
A gate terminal 49p is molded on the resin base on the communication portion 12B side in correspondence with each set of the GBT 40p and the FWD 42p.

【００５８】金属電極板１０Ｂ上のＩＧＢＴ４０ｐは上
面のエミッタ電極が金属電極板２０Ｂの高段部２４Ｂに
複数本の金属ワイヤＷ１によって接続されている。ま
た、ＩＧＢＴ４０ｐ上面のゲート電極はゲート端子４９
ｐと金属ワイヤＷ３によって接続されている。ＦＷＤ４
２ｐは上面のアノード電極が高段部２４Ｂに複数本の金
属ワイヤＷ２によって接続されている。The IGBT 40p on the metal electrode plate 10B has an emitter electrode on the upper surface connected to the high step portion 24B of the metal electrode plate 20B by a plurality of metal wires W1. The gate electrode on the upper surface of the IGBT 40p is a gate terminal 49.
p and a metal wire W3. FWD4
2p, the anode electrode on the upper surface is connected to the high step portion 24B by a plurality of metal wires W2.

【００５９】金属電極板２０Ｂｕの低段部２２Ｂ上に
も、その両側に並んだ金属電極板３０Ｂの延設部３４Ｂ
にそってＩＧＢＴ４０ｎとＦＷＤ４２ｎの組が１組ずつ
半田により接合されている。そして、金属電極板２０Ｂ
上のＩＧＢＴ４０ｎとＦＷＤ４２ｎの各組に対応させ
て、上記スペースの開口側には、それぞれゲート端子４
９ｐが樹脂ベースにモールドされている。The extended portion 34B of the metal electrode plate 30B arranged on both sides is also provided on the low step portion 22B of the metal electrode plate 20Bu.
A set of the IGBT 40n and the FWD 42n is joined by soldering one by one. Then, the metal electrode plate 20B
In correspondence with each set of the above IGBT 40n and FWD 42n, a gate terminal 4 is provided on the opening side of the space.
9p is molded on the resin base.

【００６０】金属電極板２０Ｂｕ上のＩＧＢＴ４０ｎ
は、上面のエミッタ電極が金属電極板３０Ｂの延設部３
４Ｂに複数本の金属ワイヤＷ１によって接続され、ゲー
ト電極はゲート端子４９ｎと金属ワイヤＷ３によって接
続されている。また、ＦＷＤ４２ｎは上面のアノード電
極が延設部３４Ｂに複数本の金属ワイヤＷ２によって接
続されている。他の相についても同様であり、これによ
り、図１に示される回路が形成される。金属電極板１０
Ｂの外部接続部１６Ｂが回路のＰ端子になり、金属電極
板３０Ｂの外部接続部３６ＢがＮ端子、金属電極板２０
Ｂの外部接続部２６Ｂが出力端子となる。IGBT 40n on metal electrode plate 20Bu
Indicates that the emitter electrode on the upper surface is the extended portion 3 of the metal electrode plate 30B.
4B is connected by a plurality of metal wires W1, and the gate electrode is connected to the gate terminal 49n by the metal wire W3. In the FWD 42n, the anode electrode on the upper surface is connected to the extension 34B by a plurality of metal wires W2. The same is true for the other phases, whereby the circuit shown in FIG. 1 is formed. Metal electrode plate 10
The external connection portion 16B of B serves as the P terminal of the circuit, the external connection portion 36B of the metal electrode plate 30B serves as the N terminal, and the metal electrode plate 20B.
The external connection portion 26B of B serves as an output terminal.

【００６１】半導体モジュール１０１Ｂの周辺部には、
金属電極板２０Ｂの低段部２２Ｂの角部、および高段部
２４Ｂの先端近傍に、前述各実施例におけるネジ貫通穴
５２と同じネジ貫通穴が設けられ、半導体モジュール１
０１Ｂを不図示のヒートシンクに固定するためのネジ６
０が貫通可能となっている。低段部２２Ｂの角部にはネ
ジ貫通穴との間に所定の間隙をもつように切り欠き２８
Ｂが形成され、金属電極板１０Ｂには高段部２４Ｂの先
端近傍にネジ貫通穴より大径の穴５４が形成されて、そ
れぞれネジ貫通穴の内壁をモールド樹脂として、ネジ６
０と絶縁するようになっている。At the periphery of the semiconductor module 101B,
The same screw through hole 52 as the screw through hole 52 in each of the above-described embodiments is provided near the corner of the low step portion 22B and near the tip of the high step portion 24B of the metal electrode plate 20B.
Screw 6 for fixing 01B to a heat sink (not shown)
0 is penetrable. Notches 28 are formed at the corners of the low step portion 22B so as to have a predetermined gap with the screw through hole.
B is formed in the metal electrode plate 10B, and a hole 54 having a diameter larger than the screw through hole is formed near the tip of the high step portion 24B.
0 is insulated.

【００６２】また、半導体モジュール１０１Ｂの中央部
においても、金属電極板１０Ｂと金属電極板２０Ｂ間の
隙間において、延設部３４Ｂと高段部２４Ｂ間ごとにネ
ジ貫通穴が設けられ、周辺部と同じくネジ６０が貫通可
能となっている。ここでもネジ貫通穴の内壁をモールド
樹脂として、ネジ６０と絶縁するようになっている。そ
の他の構成は、第２の実施例と同じである。In the central portion of the semiconductor module 101B, a screw through hole is provided between the extending portion 34B and the high step portion 24B in the gap between the metal electrode plate 10B and the metal electrode plate 20B. Similarly, the screw 60 can be penetrated. Also in this case, the inner wall of the screw through hole is used as a mold resin so as to be insulated from the screw 60. Other configurations are the same as those of the second embodiment.

【００６３】この変形例によっても、底面に対して垂直
に立ち上がって対向する連通部１２Ｂ、３２Ｂは樹脂ベ
ースの側部に位置するとともに、全体として金属電極板
の重なりが２層であるから、第２の実施例と同じく、樹
脂ベースの収縮阻害が有効に解消され、半導体モジュー
ル１０１Ｂの底面が上に凸となることがなく、また半導
体モジュール１０１Ｂの主要部の高さを必要に応じて低
くできるという利点を有する。According to this modification as well, the communicating portions 12B and 32B which stand perpendicularly to the bottom surface and are opposed to each other are located on the side portions of the resin base, and the metal electrode plates overlap in two layers as a whole. As in the second embodiment, the resin-based shrinkage inhibition is effectively eliminated, the bottom surface of the semiconductor module 101B does not project upward, and the height of the main part of the semiconductor module 101B can be reduced as necessary. It has the advantage that.

【００６４】また、半導体モジュール１０１Ｂの周辺部
ならびに中央部にネジ貫通穴を設けて、このネジ貫通穴
を通してネジ６０によりヒートシンクに締め付けるよう
になっているので、常に確実にヒートシンクとの間の隙
間発生が防止され、半導体装置の信頼性が確保される。
さらに、第２の実施例では金属電極板１０Ａが樹脂ベー
ス５０Ａの底面全体に張り渡される一方で、主部１１Ａ
と連通部１２Ａの間に開口１５を有するため材料の歩留
まりが若干低いのに対して、この変形例では金属電極板
１０Ｂの形状が簡素化され、歩留まりが向上するという
利点を有する。Further, screw through holes are provided in the peripheral portion and the central portion of the semiconductor module 101B, and the semiconductor module 101B is fastened to the heat sink by the screws 60 through the screw through holes. Is prevented, and the reliability of the semiconductor device is ensured.
Further, in the second embodiment, while the metal electrode plate 10A is stretched over the entire bottom surface of the resin base 50A, the main portion 11A is formed.
Although the yield of the material is slightly lower due to the presence of the opening 15 between the and the communicating portion 12A, this modification has an advantage that the shape of the metal electrode plate 10B is simplified and the yield is improved.

【００６５】なお、各実施例および変形例では、３相の
インバータ回路に適用した例について、各相ごとにＰ側
とＮ側に半導体チップとしてＩＧＢＴ４０とＦＷＤ４２
の組を２組ずつ並列に設けたものを示したが、これに限
定されず、１組ずつとすることができ、また、３相では
なく１相ずつの半導体モジュールとすることもできる。
また、半導体チップとしてＩＧＢＴとＦＷＤの組を用い
た例を示したが、これに限定されず、これらの組の代わ
りにＭＯＳＦＥＴに置き換えることもできる。In each of the embodiments and the modifications, in the case where the present invention is applied to a three-phase inverter circuit, the IGBT 40 and the FWD 42 as semiconductor chips are provided on the P side and the N side for each phase.
Are shown in parallel, two sets are provided in parallel. However, the present invention is not limited to this, and one set may be provided, and a semiconductor module may be provided not for three phases but for one phase.
Further, although an example in which a set of an IGBT and an FWD is used as a semiconductor chip has been described, the present invention is not limited to this, and a MOSFET can be used instead of the set.

【００６６】さらに、各実施例および変形例では、半導
体モジュールの周辺部および中央部に樹脂ベースを貫通
する貫通ネジ穴５２、５３を設けて、ネジ６０により半
導体モジュールをヒートシンクに固定するものとした
が、固定法はこれに限られず、例えば樹脂ベースの周辺
側壁を別部材でヒートシンクに押し付けるようにしても
よい。しかし、実施例のように貫通ネジ穴を通してネジ
で直接固定するのが最も簡単確実で好ましい。なお、固
定に用いるネジの本数、したがって樹脂ベースの貫通ネ
ジ穴の数は適宜に選択することができ、また状況によっ
て中央部のみ、あるいは周辺部のみで固定してもよい。Further, in each of the embodiments and the modified examples, through screw holes 52 and 53 penetrating the resin base are provided in the peripheral portion and the central portion of the semiconductor module, and the semiconductor module is fixed to the heat sink by screws 60. However, the fixing method is not limited to this. For example, the peripheral side wall of the resin base may be pressed against the heat sink by another member. However, it is the simplest, safest, and most preferable to directly fix with a screw through a through screw hole as in the embodiment. The number of screws used for fixing, that is, the number of through screw holes in the resin base can be appropriately selected. Depending on the situation, fixing may be performed only at the central portion or only at the peripheral portion.

【図面の簡単な説明】[Brief description of the drawings]

【図１】実施の形態において形成されるインバータ回路
を示す図である。FIG. 1 is a diagram showing an inverter circuit formed in an embodiment.

【図２】第１の実施例を示す上面図である。FIG. 2 is a top view showing the first embodiment.

【図３】第１の実施例の断面図である。FIG. 3 is a sectional view of the first embodiment.

【図４】第１の実施例における金属電極板の位置関係を
示す斜視図である。FIG. 4 is a perspective view showing a positional relationship of a metal electrode plate in the first embodiment.

【図５】金属電極板を分離して示す斜視図である。FIG. 5 is a perspective view showing a metal electrode plate separately.

【図６】第２の実施例を示す上面図である。FIG. 6 is a top view showing a second embodiment.

【図７】第２の実施例の断面図である。FIG. 7 is a sectional view of a second embodiment.

【図８】第２の実施例における金属電極板の位置関係を
示す斜視図である。FIG. 8 is a perspective view showing a positional relationship of a metal electrode plate in the second embodiment.

【図９】変形例を示す斜視図である。FIG. 9 is a perspective view showing a modification.

【図１０】従来例を示す図である。FIG. 10 is a diagram showing a conventional example.

【図１１】従来例によるインバータ１相分の回路図であ
る。FIG. 11 is a circuit diagram of one phase of an inverter according to a conventional example.

【図１２】他の実装構造案を示す図である。FIG. 12 is a diagram illustrating another proposed mounting structure.

【図１３】他の実装構造案における問題点を示す説明図
である。FIG. 13 is an explanatory diagram showing a problem in another mounting structure plan.

【符号の説明】[Explanation of symbols]

１０、１０Ａ、１０Ｂ 金属電極板（第１の金属電極
板） １１、１１Ａ、１１Ｂ 主部 １２、１２Ａ、１２Ｂ 連通部（第３の金属電極板の
連通部に重なる領域） １３ スリット １４ 枝部 １５ 開口 １６、１６Ａ、１６Ｂ 外部接続部 １８、１８Ａ、２８、２８Ｂ 切り欠き ２０ｕ、２０ｖ、２０ｗ 金属電極板（第２の金属電
極板） ２０Ａｕ、２０Ａｖ、２０Ａｗ 金属電極板（第２の
金属電極板） ２０Ｂｕ、２０Ｂｖ、２０Ｂｗ 金属電極板（第２の
金属電極板） ２２、２２Ａ、２２Ｂ 低段部（第２の半導体チップ
を接合した領域） ２４、２４Ａ、２４Ｂ 高段部 ２６、２６Ａ、２６Ｂ 外部接続部 ３０、３０Ａ、３０Ｂ 金属電極板（第３の金属電極
板） ３２、３２Ａ、３２Ｂ 連通部 ３４ａ、３４ｂ、３４ｃ、３４ｄ、３４Ａ、３４Ｂ
延設部 ３６、３６Ａ、３６Ｂ 外部接続部 ４０ｐ、４０ｎ ＩＧＢＴ ４２ｐ、４２ｎ ＦＷＤ ４９ｐ、４９ｎ ゲート端子 ５０、５０Ａ 樹脂ベース ５２ ネジ貫通穴（第１の貫通穴） ５３ ネジ貫通穴（第２の貫通穴） ５４ 穴 ５７、５７Ａ 放熱シート ５８、５８Ａ ヒートシンク ６０ ネジ Ｗ１ 金属ワイヤ Ｗ２ 金属ワイヤ Ｗ３ 金属ワイヤ １００、１００Ａ 実装ユニット １０１、１０１Ａ、１０１Ｂ 半導体モジュール10, 10A, 10B Metal electrode plate (first metal electrode plate) 11, 11A, 11B Main portion 12, 12A, 12B Communication portion (region overlapping with communication portion of third metal electrode plate) 13 Slit 14 Branch portion 15 Opening 16, 16A, 16B External connection part 18, 18A, 28, 28B Notch 20u, 20v, 20w Metal electrode plate (second metal electrode plate) 20Au, 20Av, 20Aw Metal electrode plate (second metal electrode plate) 20Bu, 20Bv, 20Bw Metal electrode plate (second metal electrode plate) 22, 22A, 22B Low step (region where second semiconductor chip is bonded) 24, 24A, 24B High step 26, 26A, 26B External connection Portion 30, 30A, 30B Metal electrode plate (third metal electrode plate) 32, 32A, 32B Communication portion 34a, 34b, 34c, 34d, 34A, 34B
Extension portion 36, 36A, 36B External connection portion 40p, 40n IGBT 42p, 42n FWD 49p, 49n Gate terminal 50, 50A Resin base 52 Screw through hole (first through hole) 53 Screw through hole (second through hole) ) 54 holes 57, 57A heat dissipation sheet 58, 58A heat sink 60 screw W1 metal wire W2 metal wire W3 metal wire 100, 100A mounting unit 101, 101A, 101B semiconductor module

───────────────────────────────────────────────────── フロントページの続き (72)発明者 古川 資之 神奈川県横浜市神奈川区宝町２番地 日産 自動車株式会社内 (72)発明者 渋谷 彰弘 神奈川県横浜市神奈川区宝町２番地 日産 自動車株式会社内 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor: Yoshiyuki Furukawa, Nissan Motor Co., Ltd., 2 Takaracho, Kanagawa-ku, Yokohama, Kanagawa Prefecture (72) Inventor Akihiro Shibuya, 2 Takaracho, Kanagawa-ku, Yokohama, Kanagawa Prefecture

Claims (10)

【特許請求の範囲】[Claims] 【請求項１】 樹脂ベースにモールドされて互いに絶縁
された第１、第２および第３の金属電極板を備え、第１
の金属電極板上に第１の半導体チップの裏面の電極を導
電性接合材で接合し、第２の金属電極板上に第２の半導
体チップの裏面の電極を導電性接合材で接合し、第１の
半導体チップの上面の電極を第２の金属電極板に、第２
の半導体チップの上面の電極を第３の金属電極板にそれ
ぞれ金属ワイヤで接続した半導体装置の実装構造におい
て、前記第２の金属電極板の第２の半導体チップを接合
した領域と第１の金属電極板とが略同層とされて下面が
樹脂ベースの底面に露出し、前記第３の金属電極板は、
第２の金属電極板の第２の半導体チップを接合した領域
の両側辺にそって延びる延設部と該延設部をつないで第
１の金属電極板と重なる連通部を有して第１の金属電極
板より高い位置に配置され、前記第１の金属電極板は第
３の金属電極板の前記連通部に重なる重なり領域と前記
第１の半導体チップが接合される主部とを有し、前記第
２の金属電極板は、前記第２の半導体チップを接合した
領域から上方へオフセットして前記連通部を乗り越え前
記第３の金属電極板と略同層で第１の金属電極板上に延
びる高段部を備えて、前記第１および第３の金属電極板
はそれぞれ連通部および重なり領域を前記主部の側辺よ
り突出させて外部接続部とすることを特徴とする半導体
装置の実装構造。A first metal electrode plate molded on a resin base and insulated from each other;
The electrode on the back surface of the first semiconductor chip is joined with a conductive bonding material on the metal electrode plate, and the electrode on the back surface of the second semiconductor chip is joined with the conductive bonding material on the second metal electrode plate. The electrode on the upper surface of the first semiconductor chip is connected to the second metal electrode plate,
In the mounting structure of the semiconductor device in which the electrodes on the upper surface of the semiconductor chip are connected to the third metal electrode plate by metal wires, respectively, the region of the second metal electrode plate where the second semiconductor chip is bonded and the first metal The third metal electrode plate is substantially the same layer as the electrode plate, and the lower surface is exposed on the bottom surface of the resin base.
A first extending portion extending along both sides of a region of the second metal electrode plate to which the second semiconductor chip is joined, and a communicating portion connecting the extending portions and overlapping the first metal electrode plate; The first metal electrode plate has an overlapping region overlapping the communication portion of the third metal electrode plate, and a main portion to which the first semiconductor chip is joined. The second metal electrode plate is offset upward from a region where the second semiconductor chip is bonded, and climbs over the communication portion, and is substantially the same layer as the third metal electrode plate on the first metal electrode plate. Wherein the first and third metal electrode plates each have a communication portion and an overlapping region protruding from a side of the main portion to form an external connection portion. Mounting structure. 【請求項２】 前記樹脂ベースの周辺部には、いずれの
金属電極板も露出しない第１の貫通穴が設けられている
ことを特徴とする請求項１記載の半導体装置の実装構
造。2. The mounting structure of a semiconductor device according to claim 1, wherein a first through hole not exposing any metal electrode plate is provided in a peripheral portion of said resin base. 【請求項３】 前記樹脂ベースの中央部には、いずれの
金属電極板も露出しない第２の貫通穴が設けられている
ことを特徴とする請求項１または２記載の半導体装置の
実装構造。3. The mounting structure for a semiconductor device according to claim 1, wherein a second through hole exposing no metal electrode plate is provided in a central portion of the resin base. 【請求項４】 前記第２の貫通穴は、前記第１、第２お
よび第３の金属電極板が重なる部位に設けられ、第１、
第２および第３の金属電極板は第２の貫通穴より大径の
穴を有して該第２の貫通穴に露出しないことを特徴とす
る請求項３記載の半導体装置の実装構造。4. The first through hole is provided in a portion where the first, second, and third metal electrode plates overlap, and
4. The semiconductor device mounting structure according to claim 3, wherein the second and third metal electrode plates have holes larger in diameter than the second through holes and are not exposed to the second through holes. 【請求項５】 樹脂ベースにモールドされて互いに絶縁
された第１、第２および第３の金属電極板を備え、第１
の金属電極板上に第１の半導体チップの裏面の電極を導
電性接合材で接合し、第２の金属電極板上に第２の半導
体チップの裏面の電極を導電性接合材で接合し、第１の
半導体チップの上面の電極を第２の金属電極板に、第２
の半導体チップの上面の電極を第３の金属電極板にそれ
ぞれ金属ワイヤで接続した半導体装置の実装構造におい
て、前記第１の金属電極板の第１の半導体チップが接合
される主部と第２の金属電極板の第２の半導体チップを
接合した領域とが略同層とされて下面が樹脂ベースの底
面に露出し、前記第３の金属電極板は、第２の金属電極
板の第２の半導体チップを接合した領域の両側辺にそっ
て延び第１の金属電極板の主部より高い位置に配置され
た延設部と、該延設部を前記樹脂ベースの外端側でつな
いで上方へ立ち上げた連通部とを有し、前記第２の金属
電極板は、前記第２の半導体チップを接合した領域から
上方へオフセットして前記第３の金属電極板の延設部と
略同層で第１の金属電極板の主部上に延びる高段部を備
え、前記第１の金属電極板は主部に対して上方へ立ち上
げて第３の金属電極板の連通部に対向して重なる重なり
領域を備え、前記第１および第３の金属電極板はそれぞ
れ連通部および重なり領域を前記主部の側辺より突出さ
せて外部接続部とすることを特徴とする半導体装置の実
装構造。5. A semiconductor device comprising: a first, a second, and a third metal electrode plate molded on a resin base and insulated from each other;
The electrode on the back surface of the first semiconductor chip is joined with a conductive bonding material on the metal electrode plate, and the electrode on the back surface of the second semiconductor chip is joined with the conductive bonding material on the second metal electrode plate. The electrode on the upper surface of the first semiconductor chip is connected to the second metal electrode plate,
In the mounting structure of the semiconductor device in which the electrodes on the upper surface of the semiconductor chip are connected to the third metal electrode plate by metal wires, respectively, the main part of the first metal electrode plate to which the first semiconductor chip is bonded and the second part are connected to each other. The region where the second semiconductor chip of the metal electrode plate is bonded is substantially the same layer, and the lower surface is exposed to the bottom surface of the resin base. The third metal electrode plate is formed of the second metal electrode plate. An extended portion extending along both sides of the region where the semiconductor chip is joined and disposed at a position higher than the main portion of the first metal electrode plate, and the extended portion is connected to the outer end side of the resin base. A communication portion rising upward, wherein the second metal electrode plate is offset upward from a region where the second semiconductor chip is joined, and is substantially equal to an extension of the third metal electrode plate. A high step portion extending in the same layer above the main portion of the first metal electrode plate; The electrode plate is provided with an overlapping region that rises upward with respect to the main portion and faces and overlaps the communicating portion of the third metal electrode plate, and the first and third metal electrode plates define a communicating portion and an overlapping region, respectively. A mounting structure for a semiconductor device, wherein the mounting portion protrudes from a side of the main portion to form an external connection portion. 【請求項６】 前記第１の金属電極板は主部と連通部の
間に開口を有し、該開口内に前記第２の金属電極板の第
２の半導体チップを接合した領域が配置されていること
を特徴とする請求項５記載の半導体装置の実装構造。6. The first metal electrode plate has an opening between a main part and a communication part, and a region where the second semiconductor chip of the second metal electrode plate is joined is arranged in the opening. The mounting structure of a semiconductor device according to claim 5, wherein: 【請求項７】 前記第２の金属電極板の第２の半導体チ
ップを接合した領域が、前記第１の金属電極板の主部を
挟んで連通部と反対側に配置され、前記第３の金属電極
板の延設部は、第１の金属電極板の主部上を、第２の金
属電極板の第２の半導体チップを接合した領域の両側辺
まで延びていることを特徴とする請求項５記載の半導体
装置の実装構造。7. A region of the second metal electrode plate to which a second semiconductor chip is bonded is disposed on a side opposite to a communication portion with respect to a main portion of the first metal electrode plate, and The extended portion of the metal electrode plate extends on a main portion of the first metal electrode plate to both sides of a region where the second semiconductor chip of the second metal electrode plate is joined. Item 6. A mounting structure of the semiconductor device according to Item 5. 【請求項８】 前記樹脂ベースの周辺部には、いずれの
金属電極板も露出しない第１の貫通穴が設けられている
ことを特徴とする請求項５、６または７記載の半導体装
置の実装構造。8. The mounting of the semiconductor device according to claim 5, wherein a first through hole exposing no metal electrode plate is provided in a peripheral portion of the resin base. Construction. 【請求項９】 前記樹脂ベースの中央部には、いずれの
金属電極板も露出しない第２の貫通穴が設けられている
ことを特徴とする請求項５、６、７または８記載の半導
体装置の実装構造。9. The semiconductor device according to claim 5, wherein a second through hole exposing no metal electrode plate is provided in a central portion of the resin base. Mounting structure. 【請求項１０】 前記第２の半導体チップを接合した第
２の金属電極板が複数並列に設けられ、前記第３の金属
電極板は各第２の金属電極板に対応して前記延設部を備
えるとともに、前記連通部がすべての延設部をつなぎ、
前記第１の金属電極板は前記第２の半導体チップを接合
した主部を各第２の金属電極板に対応して備えるととも
に、前記連通部に重なる重なり領域がすべての主部をつ
ないでいることを特徴とする請求項１から９のいずれか
に記載の半導体装置の実装構造。10. A plurality of second metal electrode plates to which said second semiconductor chip is joined are provided in parallel, and said third metal electrode plate corresponds to each of said second metal electrode plates. And the communication portion connects all the extending portions,
The first metal electrode plate has a main portion joined to the second semiconductor chip corresponding to each of the second metal electrode plates, and an overlapping region overlapping the communication portion connects all the main portions. The mounting structure of the semiconductor device according to claim 1, wherein:
JP2001181481A 2001-06-15 2001-06-15 Mounting structure of semiconductor device Expired - Fee Related JP3741002B2 (en)

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