JP2002368353A - Printed wiring board - Google Patents
Printed wiring boardInfo
- Publication number
- JP2002368353A JP2002368353A JP2001168593A JP2001168593A JP2002368353A JP 2002368353 A JP2002368353 A JP 2002368353A JP 2001168593 A JP2001168593 A JP 2001168593A JP 2001168593 A JP2001168593 A JP 2001168593A JP 2002368353 A JP2002368353 A JP 2002368353A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- power supply
- ground
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
Description
【０００１】[0001]
【技術分野】本発明は，プリント配線板に関し，特に信
号回路の電気特性を改善するための構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board, and more particularly to a structure for improving electric characteristics of a signal circuit.
【０００２】[0002]
【従来技術】プリント配線板としては，電子部品を搭載
するための搭載部を設け，その周囲に信号回路，電源回
路及び接地回路を配置したものがある。上記プリント配
線板では，信号回路間のクロストークノイズや，インピ
ーダンスの変化によって反射ノイズが生じることがあっ
た。特に，信号回路が高密度に配置されている部分で，
これらのノイズが大きくなる傾向にある。2. Description of the Related Art As a printed wiring board, there is a printed wiring board in which a mounting portion for mounting an electronic component is provided, and a signal circuit, a power supply circuit, and a ground circuit are arranged around the mounting portion. In the printed wiring board, crosstalk noise between signal circuits and change in impedance sometimes cause reflection noise. In particular, where signal circuits are densely arranged,
These noises tend to increase.
【０００３】近年，プリント配線板は，高密度高速化の
傾向にあるため，回路間での影響が生じ易く，クロスト
ークノイズや反射ノイズが生じやすくなってきている。
また，高密度配線化に伴い，精密な回路形成が要求され
ている。しかし，回路の粗密があると，粗い部分のエッ
チング量が，密な部分よりも多くなり，回路の仕上がり
が不均一になる傾向にある。[0003] In recent years, printed wiring boards tend to be high-density and high-speed, so that influences between circuits are likely to occur, and crosstalk noise and reflection noise are likely to occur.
In addition, with the increase in wiring density, precise circuit formation is required. However, if the circuit is coarse and dense, the amount of etching in the rough part is larger than that in the dense part, and the finish of the circuit tends to be uneven.
【０００４】[0004]
【解決しようとする課題】本発明はかかる従来の問題点
に鑑み，クロストークノイズ及び反射ノイズの低減を図
ることができ，かつ仕上がりの均一な回路を有するプリ
ント配線板を提供しようとするものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a printed wiring board capable of reducing crosstalk noise and reflection noise and having a circuit with a uniform finish. is there.
【０００５】[0005]
【課題の解決手段】本発明は，同一面内の導体層におい
て，信号回路が，電源回路または／及び接地回路によ
り，挟まれるかまたは囲まれてなるプリント配線板であ
って，上記接地回路または上記電源回路は，隣接する信
号回路に沿った形状からなる並行部を有するとともに，
該並行部と上記信号回路との間には絶縁領域が所定幅を
維持して介在していることを特徴とするプリント配線板
である（請求項１）。According to the present invention, there is provided a printed wiring board in which a signal circuit is sandwiched or surrounded by a power supply circuit and / or a ground circuit in a conductor layer in the same plane. The power supply circuit has a parallel portion having a shape along an adjacent signal circuit,
The printed wiring board is characterized in that an insulating region is interposed between the parallel portion and the signal circuit while maintaining a predetermined width.
【０００６】本発明においては，同一面内の導体層にお
いて，信号回路が，電源回路または／及び接地回路によ
り挟まれているか，もしくは同一面内の導体層におい
て，信号回路が，電源回路または接地回路により囲まれ
ている。このため，信号回路間の電気的結合が，隣接す
る電源回路または接地回路の影響により弱くなり，クロ
ストークノイズが減少する。According to the present invention, the signal circuit is sandwiched between the power supply circuit and / or the ground circuit in the conductor layer in the same plane, or the power supply circuit or the ground circuit is sandwiched in the conductor layer in the same plane. Surrounded by circuits. Therefore, the electric coupling between the signal circuits is weakened by the influence of the adjacent power supply circuit or ground circuit, and the crosstalk noise is reduced.
【０００７】また，接地回路または電源回路は，隣接す
る信号回路に沿った形状の並行部を有する。接地回路ま
たは電源回路の並行部における信号回路側の側縁部と，
信号回路における接地回路または電源回路の側の側縁部
とが，相対している。このため，接地回路または電源回
路は，この並行部において，信号回路との間に，所定間
隔に保たれた絶縁領域が介在することになる。従って，
信号回路のインピーダンスの変化が抑制され，反射ノイ
ズを抑制することができる。また，信号回路と，接地回
路または電源回路の並行部との間は，所定間隔に保たれ
ることになるため，回路の粗密が少なくなり，エッチン
グ，めっき及び現像による回路の仕上がりが均一にな
る。Further, the ground circuit or the power supply circuit has a parallel portion shaped along the adjacent signal circuit. A side edge on the signal circuit side in a parallel portion of the ground circuit or the power supply circuit;
A side edge of the signal circuit on the side of the ground circuit or the power supply circuit is opposed. For this reason, the grounding circuit or the power supply circuit has an insulating region maintained at a predetermined interval between the parallel circuit and the signal circuit. Therefore,
The change in the impedance of the signal circuit is suppressed, and the reflection noise can be suppressed. In addition, since a predetermined interval is maintained between the signal circuit and the parallel portion of the ground circuit or the power supply circuit, the density of the circuit is reduced, and the finish of the circuit by etching, plating and development becomes uniform. .
【０００８】以上のように，本発明によれば，クロスト
ークノイズ及び反射ノイズの低減を図ることができ，か
つ仕上がりの均一な回路を有するプリント配線板を提供
することができる。As described above, according to the present invention, it is possible to provide a printed wiring board which can reduce crosstalk noise and reflection noise and has a circuit with a uniform finish.
【０００９】[0009]
【発明の実施の形態】本発明において，接地回路または
電源回路は，信号回路に沿った形状の並行部を有する。
接地回路又は電源回路は，少なくとも一部が並行部であ
る。接地回路又は電源回路のうち並行部が多いほどクロ
ストークノイズや反射ノイズが少なくなる傾向にある。DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, a ground circuit or a power supply circuit has a parallel portion shaped along a signal circuit.
At least a part of the ground circuit or the power supply circuit is a parallel part. There is a tendency that as the number of parallel portions in the ground circuit or the power supply circuit increases, crosstalk noise and reflection noise decrease.
【００１０】上記並行部と信号回路との間には，所定幅
の絶縁領域が介在している。上記絶縁領域の幅は，３０
〜２００μｍであることが好ましい（請求項２）。３０
μｍ未満の場合には，回路形成が困難になるおそれがあ
り，２００μｍを超える場合にはクロストークノイズ減
少効果が急激に低下するおそれがある。更に好ましく
は，上記信号回路と，上記電源回路または接地回路の上
記並行部との間には，４０〜１５０μｍの間隙が設けら
れていることである。これにより，クロストークノイズ
を一層低下させることができる。An insulating region having a predetermined width is interposed between the parallel portion and the signal circuit. The width of the insulating region is 30
It is preferably from 200 to 200 μm (claim 2). 30
If it is less than μm, circuit formation may be difficult, and if it exceeds 200 μm, the effect of reducing crosstalk noise may be sharply reduced. More preferably, a gap of 40 to 150 μm is provided between the signal circuit and the parallel portion of the power supply circuit or the ground circuit. Thereby, crosstalk noise can be further reduced.
【００１１】上記接地回路または上記電源回路における
上記信号回路に沿った形状の上記並行部の幅は，信号回
路の配線部の幅よりも広いことが好ましい（請求項
３）。接地回路または電源回路の並行部の幅を，信号回
路の配線部よりも広くすると，信号回路のクロストーク
ノイズをより一層低減させることができる。また，信号
回路が９０°以下の鋭角を持つクサビ状の部分を有する
場合に，エッチング，めっき等の際に他の基板の歩留ま
りの低下を抑制することができる。The width of the parallel portion of the ground circuit or the power supply circuit along the signal circuit is preferably wider than the width of the wiring portion of the signal circuit. If the width of the parallel part of the ground circuit or the power supply circuit is made wider than the wiring part of the signal circuit, the crosstalk noise of the signal circuit can be further reduced. Further, when the signal circuit has a wedge-shaped portion having an acute angle of 90 ° or less, it is possible to suppress a decrease in the yield of another substrate during etching, plating, or the like.
【００１２】すなわち，信号回路の上記クサビ形状に沿
って細幅の接地回路または電源回路を配置すると，その
接地回路または電源回路が鋭角な部分を持つことにな
る。すると，回路の鋭角な部分を作るレジストがメッキ
液やエッチング液等の中で剥れ飛び散ったりして，他の
製品の歩留まりを低下させるおそれもある。本発明のよ
うに，接地回路または電源回路における並行部の幅を，
信号回路の配線部よりも太くすることにより，レジスト
が剥れにくく飛び散りにくくなり，他の製品の歩留まり
への影響を抑制することができる。That is, if a narrow ground circuit or power supply circuit is arranged along the wedge shape of the signal circuit, the ground circuit or power supply circuit has an acute angle portion. Then, there is a possibility that the resist forming the sharp portion of the circuit may be peeled off and scattered in the plating solution, the etching solution, or the like, thereby lowering the yield of other products. As in the present invention, the width of the parallel portion in the ground circuit or the power supply circuit is
By making the wiring portion thicker than the wiring portion of the signal circuit, the resist is less likely to be peeled off and scattered, and the effect on the yield of other products can be suppressed.
【００１３】信号回路が上記クサビ状の屈曲部を有する
場合にも，これに隣接する接地回路や電源回路はそのク
サビ状の信号回路に沿って形成される。この場合，接地
回路及び電源回路における少なくとも並行部は，信号回
路の配線部よりも幅が広い幅広部であることが好まし
い。これにより，レジストが剥れにくく飛び散りにくく
なり，他の製品の歩留まりへの影響を抑制することがで
きる。Even when the signal circuit has the wedge-shaped bent portion, the ground circuit and the power supply circuit adjacent to the bent portion are formed along the wedge-shaped signal circuit. In this case, it is preferable that at least the parallel portion in the ground circuit and the power supply circuit is a wide portion wider than the wiring portion of the signal circuit. As a result, the resist is hardly peeled off and scattered, so that the influence on the yield of other products can be suppressed.
【００１４】信号回路間のクロストークノイズの減少お
よび信号回路の高密度化の観点から，同一面内の導体層
において，２本の信号回路が，電源回路または／及び接
地回路により，挟まれるか又は囲まれてなることが好ま
しい（請求項４）。[0014] From the viewpoint of reducing crosstalk noise between signal circuits and increasing the density of signal circuits, two signal circuits may be sandwiched by a power supply circuit and / or a ground circuit in a conductor layer in the same plane. Or it is preferable to be surrounded (claim 4).
【００１５】上記電源回路，接地回路及び信号回路の内
部には，０．０４９ｍｍ２以下の回路未形成部分，即
ち，孤立絶縁領域が存在しないことが好ましい（請求項
５）。コンピュータによる一般の回路設計では，回路の
内部に微小な回路未形成部分が残る場合がある。０．０
４９ｍｍ２以下の小さい回路未形成部分に設けられたレ
ジスト膜は，剥離しやすい。このため，メッキ，エッチ
ングなどの処理の際に，処理液中を浮遊して，他の基板
に付着したりして，めっき不良や現像不良を起こすおそ
れがある。そこで，上記のように０．０４９ｍｍ２以下
の小さい回路未形成部分を残さないように回路設計をす
ると，そこに形成されるレジスト膜の剥離が生じにくく
なり，処理液中において他の基板の不良を起こしにくく
なる。It is preferable that no circuit-less portion of 0.049 mm 2 or less, that is, an isolated insulating region does not exist inside the power supply circuit, the ground circuit, and the signal circuit. In general circuit design using a computer, a minute circuit-unformed portion may remain inside the circuit. 0.0
A resist film provided in a small circuit-less portion of 49 mm 2 or less is easily peeled. For this reason, at the time of processing such as plating and etching, there is a possibility that floating in the processing solution and adhesion to other substrates may cause defective plating and defective development. Therefore, if the circuit is designed so as not to leave a small circuit-unformed portion of 0.049 mm 2 or less as described above, the resist film formed there is less likely to be peeled off, and the failure of the other substrate in the processing solution will occur. Is less likely to occur.
【００１６】[0016]
【実施例】本発明の実施形態について実施例を用いて更
に詳細に説明する。 （実施例１）本例においては，図１に示すごとく，プリ
ント配線板の表面の導体層において，２本の信号回路Ｓ
の両側が，接地回路Ｇにより挟まれている。接地回路Ｇ
は，隣接する信号回路Ｓに沿った形状からなる並行部Ｇ
０８を有する。並行部Ｇ０８では，信号回路Ｓ側の側縁
部Ｇ１００と，信号回路Ｓにおける接地回路Ｇの側の側
縁部Ｓ１００とが，相対している。並行部Ｇ０８と信号
回路Ｓとの間には絶縁領域１が所定幅を維持して介在し
ている。The embodiments of the present invention will be described in more detail with reference to examples. (Embodiment 1) In this embodiment, as shown in FIG. 1, two signal circuits S are provided on a conductor layer on the surface of a printed wiring board.
Are sandwiched between ground circuits G. Grounding circuit G
Is a parallel portion G having a shape along the adjacent signal circuit S.
08. In the parallel portion G08, the side edge portion G100 on the signal circuit S side and the side edge portion S100 on the ground circuit G side in the signal circuit S are opposed to each other. An insulating region 1 is interposed between the parallel portion G08 and the signal circuit S while maintaining a predetermined width.
【００１７】並行部Ｇ０８の幅ＢＧは，１００μｍであ
り，信号回路Ｓの配線部Ｓ０５の幅ＢＳは７０μｍであ
って，前者は後者よりも広い。信号回路Ｓと並行部Ｇ０
８との間に介在する絶縁領域１の幅Ｂ１は，７０μｍで
ある。２本の信号回路Ｓの間には，７０μｍの幅Ｂ１０
の絶縁領域１０が介在している。The width B G parallel portion G08 is 100 [mu] m, the width B S of the wiring portion S05 of the signal circuit S A 70 [mu] m, the former is wider than the latter. Signal circuit S and parallel section G0
Width B 1 of the insulating region 1 interposed between the 8 is 70 [mu] m. A width B 10 of 70 μm is provided between the two signal circuits S.
The insulating region 10 is interposed.
【００１８】本例の接地回路Ｇは，隣接する信号回路Ｓ
に沿った形状の並行部Ｇ０８を有する。このため，並行
部Ｇ０８と信号回路Ｓとの間に，所定間隔に保たれた絶
縁領域１が介在することになる。従って，信号回路のイ
ンピーダンスの変化が抑制され，反射ノイズを抑制する
ことができる。信号回路Ｓと並行部Ｇ０８との間は，所
定間隔に保たれることになるため，回路の粗密が少なく
なり，エッチングによる回路の仕上がりが均一になる。
並行部Ｇ０８の幅は，信号回路Ｓの配線部Ｓ０５よりも
広いため，クロストークノイズの減少効果が大きい。The ground circuit G of the present embodiment is composed of an adjacent signal circuit S
And a parallel portion G08 having a shape along the line. Therefore, the insulating region 1 kept at a predetermined interval is interposed between the parallel portion G08 and the signal circuit S. Therefore, the change in the impedance of the signal circuit is suppressed, and the reflection noise can be suppressed. Since a predetermined interval is maintained between the signal circuit S and the parallel portion G08, the density of the circuit is reduced, and the finish of the circuit by etching becomes uniform.
Since the width of the parallel portion G08 is wider than the wiring portion S05 of the signal circuit S, the effect of reducing the crosstalk noise is large.
【００１９】（実施例２）本例は，図２に示すごとく，
２本の信号回路Ｓの両側を，電源回路Ｐにより挟んだ例
である。その他は実施例１と同様である。本例において
も実施例１と同様に，信号回路Ｓ間のクロストークノイ
ズ及び反射ノイズが減少し，回路の仕上がりもよくな
る。(Embodiment 2) In this embodiment, as shown in FIG.
In this example, both sides of two signal circuits S are sandwiched between power supply circuits P. Others are the same as the first embodiment. In this embodiment, as in the first embodiment, the crosstalk noise and the reflection noise between the signal circuits S are reduced, and the circuit finish is improved.
【００２０】（実施例３）本例は，図３に示すごとく，
２本の信号回路Ｓの両側を電源回路Ｐと接地回路Ｇによ
り挟んだ例である。その他は実施例１と同様である。本
例においても実施例１と同様に，信号回路Ｓ間のクロス
トークノイズ及び反射ノイズが減少し，回路の仕上がり
もよくなる。(Embodiment 3) In this embodiment, as shown in FIG.
In this example, both sides of two signal circuits S are sandwiched between a power supply circuit P and a ground circuit G. Others are the same as the first embodiment. In this embodiment, as in the first embodiment, the crosstalk noise and the reflection noise between the signal circuits S are reduced, and the circuit finish is improved.
【００２１】（実施例４）本例は，図４に示すごとく，
２本の信号回路Ｓを接地回路Ｇにより囲んだ例である。
接地回路Ｇの幅ＢＧは１００μｍである。その他は実施
例１と同様である。本例においても実施例１と同様に，
信号回路Ｓ間のクロストークノイズ及び反射ノイズが減
少し，回路の仕上がりもよくなる。(Embodiment 4) In this embodiment, as shown in FIG.
This is an example in which two signal circuits S are surrounded by a ground circuit G.
Width B G of the ground circuit G is 100 [mu] m. Others are the same as the first embodiment. In this example, similarly to the first embodiment,
Crosstalk noise and reflection noise between the signal circuits S are reduced, and the circuit finish is improved.
【００２２】（実施例５）本例は，図５に示すごとく，
１本の信号回路Ｓの両側を，接地回路Ｇにより挟んだ例
である。その他は，実施例１と同様である。本例は，２
本の信号回路の場合に比べてクロストークノイズ減少効
果が大きい。一方，信号回路に対する接地回路の面積比
率が大きくなるため，信号回路の高密度配線化について
は，実施例１の場合ほどは貢献しない。(Embodiment 5) In this embodiment, as shown in FIG.
In this example, both sides of one signal circuit S are sandwiched between ground circuits G. Others are the same as the first embodiment. In this example, 2
The crosstalk noise reduction effect is greater than in the case of this signal circuit. On the other hand, since the area ratio of the ground circuit to the signal circuit increases, the high-density wiring of the signal circuit does not contribute as much as in the first embodiment.
【００２３】（実施例６）本例は，図６に示すごとく，
３本の信号回路Ｓの両側を，接地回路Ｇにより挟んだ例
である。その他は，実施例１と同様である。本例は，２
本の信号回路の場合に比べて，クロストークノイズ減少
効果が小さいが，接地回路に対する信号回路の面積比率
が大きいため，信号回路の高密度配線化に有利である。(Embodiment 6) As shown in FIG.
In this example, both sides of three signal circuits S are sandwiched between ground circuits G. Others are the same as the first embodiment. In this example, 2
Although the effect of reducing crosstalk noise is smaller than that of the signal circuit of the present invention, the area ratio of the signal circuit to the ground circuit is large, which is advantageous in increasing the density of the signal circuit.
【００２４】（実施例７）図７に，本例のプリント配線
板の表面の回路配置を示す。図７には信号回路Ｓの一例
としてＳ１〜Ｓ８，電源回路Ｐの一例としてＰ１〜Ｐ
３，接地回路Ｇの一例としてＧ１〜Ｇ４を示している。
このプリント配線板の表面において，信号回路Ｓ１〜Ｓ
８は，電源回路Ｐ１〜Ｐ３及び接地回路Ｇ１〜Ｇ２によ
り挟まれている。電源回路Ｐ１〜Ｐ３及び接地回路Ｇ１
〜Ｇ２は，隣接する信号回路Ｓ１〜Ｓ１０に沿った形状
を有する。(Embodiment 7) FIG. 7 shows a circuit arrangement on the surface of a printed wiring board of this embodiment. FIG. 7 shows S1 to S8 as an example of the signal circuit S, and P1 to P as an example of the power supply circuit P.
3, G1 to G4 are shown as examples of the ground circuit G.
On the surface of the printed wiring board, signal circuits S1 to S
8 is sandwiched between power supply circuits P1 to P3 and ground circuits G1 to G2. Power supply circuits P1 to P3 and ground circuit G1
G2 have a shape along the adjacent signal circuits S1 to S10.
【００２５】具体的に説明すると，信号回路Ｓ１〜Ｓ８
は，ボンディングパッド部Ｓ０６と，配線部Ｓ０５と，
マザーボードなどの相手部材に半田接合するためのパッ
ド部Ｓ０７とを有する。電源回路Ｐ１〜Ｐ３は，信号回
路Ｓ１〜Ｓ８の配線部Ｓ０５よりも幅が広い幅広部Ｐ０
１と，配線部Ｓ０５とほぼ同じ幅の配線部Ｐ０５と，搭
載部８の周囲を囲む帯状端子部Ｐ０６とを有する。幅広
部Ｐ０１及び配線部Ｐ０５のいずれも，隣接する信号回
路Ｓ１〜Ｓ４，Ｓ８の形状に沿って配置された並行部Ｐ
０８を有する。More specifically, the signal circuits S1 to S8
Are the bonding pad part S06, the wiring part S05,
And a pad portion S07 for soldering to a mating member such as a motherboard. The power supply circuits P1 to P3 have wide portions P0 wider than the wiring portions S05 of the signal circuits S1 to S8.
1, a wiring portion P05 having substantially the same width as the wiring portion S05, and a strip-shaped terminal portion P06 surrounding the periphery of the mounting portion 8. Both the wide portion P01 and the wiring portion P05 are parallel portions P arranged along the shapes of the adjacent signal circuits S1 to S4 and S8.
08.
【００２６】接地回路Ｇ１〜Ｇ２は，信号回路Ｓ１〜Ｓ
８の配線部Ｓ０５よりも幅が広い幅広部Ｇ０１と，配線
部Ｓ０５とほぼ同じ幅の配線部Ｇ０５と，搭載部８の周
囲を囲む帯状端子部Ｇ０６とを有する。配線部Ｇ０５と
帯状端子部Ｇ０６との間は，図示しない内部回路及びビ
アホールにより電気的に接続されている。幅広部Ｇ０１
及び配線部Ｇ０５のいずれも，隣接する信号回路Ｓ５〜
Ｓ８の形状に沿って並行に配置された並行部Ｇ０８を有
する。The ground circuits G1 and G2 are connected to the signal circuits S1 and S2, respectively.
8 has a wide portion G01 wider than the wiring portion S05, a wiring portion G05 having substantially the same width as the wiring portion S05, and a strip-shaped terminal portion G06 surrounding the periphery of the mounting portion 8. The wiring section G05 and the strip-shaped terminal section G06 are electrically connected by an internal circuit (not shown) and via holes. Wide part G01
And the wiring section G05, the adjacent signal circuits S5 to S5
There is a parallel portion G08 arranged in parallel along the shape of S8.
【００２７】電源回路及び接地回路の並行部Ｐ０８，Ｇ
０８は，信号回路の直線部及び屈曲部のいずれに対して
も，その形状に沿って形成されている。電源回路及び接
地回路は，その一部に信号回路Ｓ１〜Ｓ８に沿った形状
の並行部Ｐ０８，Ｇ０８を有する。並行部Ｐ０８，Ｇ０
８と信号回路との間には，３０〜２００μｍの範囲の中
の所定幅の絶縁領域１が介在している。Parallel parts P08, G of power supply circuit and ground circuit
08 is formed along the shape of both the straight portion and the bent portion of the signal circuit. The power supply circuit and the ground circuit have parallel portions P08 and G08 in a part thereof along the signal circuits S1 to S8. Parallel part P08, G0
An insulating region 1 having a predetermined width in a range of 30 to 200 μm is interposed between the signal circuit 8 and the signal circuit.
【００２８】電源回路Ｐ１〜Ｐ３及び接地回路Ｇ１〜Ｇ
２の幅広部Ｐ０１，Ｇ０１は，信号回路Ｓ１〜Ｓ１０の
隙間を埋めるように形成されており，その一部は相手部
材を半田接合するためのパッドを兼用している。上記の
電源回路，接地回路及び信号回路は，その内部に０．０
４９ｍｍ２以下の小さい回路未形成部分を残さないよう
に配置してある。Power supply circuits P1 to P3 and ground circuits G1 to G
The two wide portions P01 and G01 are formed so as to fill gaps between the signal circuits S1 to S10, and a part of the wide portions P01 and G01 also serves as a pad for soldering a mating member. The above power supply circuit, ground circuit, and signal circuit
It is arranged so as not to leave a small circuit-unformed portion of 49 mm 2 or less.
【００２９】搭載部８には，電子部品が搭載される。電
子部品は，ボンディングワイヤーにより，ボンディング
パッド部Ｓ０６または帯状端子部Ｇ０６，Ｐ０６との間
が電気的に接続される。信号回路，接地回路および電源
回路のいずれも，絶縁基板２に貼着した銅箔のエッチン
グ，めっき，レジストの露光及び現像等の手段を用いる
アディティブ法やサブトラクティブ法などにより形成す
る。Electronic parts are mounted on the mounting part 8. The electronic components are electrically connected to the bonding pad portions S06 or the strip-shaped terminal portions G06 and P06 by bonding wires. All of the signal circuit, the ground circuit, and the power supply circuit are formed by an additive method, a subtractive method, or the like using means such as etching, plating, exposure and development of a resist on a copper foil adhered to the insulating substrate 2.
【００３０】本例においては，同一面内の導体層におい
て，信号回路Ｓ２，Ｓ３が電源回路Ｐ１，Ｐ２により，
信号回路Ｓ４，Ｓ５が電源回路Ｐ２及び接地回路Ｇ１に
より，信号回路Ｓ６，Ｓ７が接地回路Ｇ１，Ｇ２により
挟まれている。このため，互いに隣接する信号回路Ｓ
２，Ｓ３の間，Ｓ４，Ｓ５の間，Ｓ６，Ｓ７の間の電気
的結合が，隣接する電源回路または接地回路の影響によ
り弱くなり，クロストークノイズが減少する。電源回路
Ｐ１〜Ｐ３及び接地回路Ｇ１〜Ｇ２は，隣接する信号回
路Ｓ１〜Ｓ１０に沿って並行に配置された並行部Ｇ０８
を有する。このため，信号回路のインピーダンスの変化
が抑制され，反射ノイズを抑制することができる。In this embodiment, in the conductor layers in the same plane, the signal circuits S2 and S3 are controlled by the power circuits P1 and P2.
The signal circuits S4 and S5 are sandwiched between the power supply circuit P2 and the ground circuit G1, and the signal circuits S6 and S7 are sandwiched between the ground circuits G1 and G2. Therefore, the adjacent signal circuits S
The electrical coupling between S2, S3, S4, S5, S6, and S7 is weakened by the influence of the adjacent power supply circuit or ground circuit, and crosstalk noise is reduced. The power supply circuits P1 to P3 and the ground circuits G1 to G2 are connected to a parallel section G08 arranged in parallel along the adjacent signal circuits S1 to S10.
Having. Therefore, a change in the impedance of the signal circuit is suppressed, and the reflection noise can be suppressed.
【００３１】図７に示すごとく，接地回路Ｇ１〜Ｇ２及
び電源回路Ｐ１〜Ｐ３は信号回路Ｓ１〜Ｓ８の間を埋め
るように形成されており，また信号回路Ｓ１〜Ｓ８と，
接地回路Ｇ１〜Ｇ２または電源回路Ｐ１〜Ｐ３の並行部
Ｇ０８，Ｐ０８との間は，所定間隔に保たれている。こ
のため，回路の粗密が少なくなり，エッチングによる回
路の仕上がりが均一になる。As shown in FIG. 7, the ground circuits G1 to G2 and the power supply circuits P1 to P3 are formed so as to fill the space between the signal circuits S1 to S8.
A predetermined interval is maintained between the ground circuits G1 and G2 and the parallel portions G08 and P08 of the power supply circuits P1 and P3. For this reason, the density of the circuit is reduced, and the finish of the circuit by etching becomes uniform.
【００３２】電源回路，接地回路及び信号回路の内部に
は，０．０４９ｍｍ２以下の小さい回路未形成部分を残
さないように回路設計してある。０．０４９ｍｍ２を超
える大きさの回路未形成部分に形成されるレジスト膜
は，メッキ処理または現像処理の際に処理液中を浮遊す
ることは少なく，他の基板のめっき不良や現像不良を防
止できる。The circuit is designed so that a small circuit-less portion of 0.049 mm 2 or less is not left inside the power supply circuit, the ground circuit, and the signal circuit. Resist film formed on the circuit unformed portions of a size greater than 0.049 mm 2, it is less to float in the treatment liquid during the plating process or the development process, prevent defective plating or other substrate development failure it can.
【００３３】一方，図８に示すごとく，接地回路Ｇの内
部に０．０４９ｍｍ２以下の回路未形成部分１１が残っ
ている場合には，その回路未形成部分１１に形成される
レジスト膜は剥離しやすい。このため，レジスト膜が，
めっき液または現像液中を浮遊し，他の基板に付着して
めっき不良や現像不良を起こす原因となる。On the other hand, as shown in FIG. 8, when the circuit unformed portion 11 of 0.049 mm 2 or less remains in the ground circuit G, the resist film formed on the circuit unformed portion 11 is peeled off. It's easy to do. Therefore, the resist film
It floats in a plating solution or a developing solution and adheres to another substrate to cause plating failure and development failure.
【図１】実施例１のプリント配線板の平面図。FIG. 1 is a plan view of a printed wiring board according to a first embodiment.
【図２】実施例２のプリント配線板の平面図。FIG. 2 is a plan view of a printed wiring board according to a second embodiment.
【図３】実施例３のプリント配線板の平面図。FIG. 3 is a plan view of a printed wiring board according to a third embodiment.
【図４】実施例４のプリント配線板の平面図。FIG. 4 is a plan view of a printed wiring board according to a fourth embodiment.
【図５】実施例５のプリント配線板の平面図。FIG. 5 is a plan view of a printed wiring board according to a fifth embodiment.
【図６】実施例６のプリント配線板の平面図。FIG. 6 is a plan view of a printed wiring board according to a sixth embodiment.
【図７】実施例７のプリント配線板の平面図。FIG. 7 is a plan view of a printed wiring board according to a seventh embodiment.
【図８】実施例７における，小さい回路未形成部分のあ
る場合の説明図。FIG. 8 is an explanatory diagram in the case where there is a small circuit non-formed portion in the seventh embodiment.
１，１０．．．絶縁領域， １１．．．回路未形成部分， ２．．．絶縁基板， Ｓ，Ｓ１〜Ｓ８．．．信号回路， Ｇ，Ｇ１〜Ｇ２．．．接地回路， Ｐ，Ｐ１〜Ｐ３．．．電源回路， Ｓ０１，Ｇ０１，Ｐ０１．．．幅広部， Ｓ０５，Ｇ０５，Ｐ０５．．．配線部， Ｓ０６．．．ボンディングパッド部， Ｇ０６，Ｐ０６．．．帯状端子部， Ｇ０９．．．屈曲部， ８．．．搭載部， 1,10. . . 10. insulating region; . . 1. Circuit unformed part; . . Insulating substrate, S, S1 to S8. . . Signal circuit, G, G1 to G2. . . Grounding circuit, P, P1 to P3. . . Power supply circuit, S01, G01, P01. . . Wide part, S05, G05, P05. . . Wiring section, S06. . . Bonding pad section, G06, P06. . . Strip terminal section, G09. . . Bend, 8. . . Mounting part,
Claims (5)
が，電源回路または／及び接地回路により，挟まれるか
または囲まれてなるプリント配線板であって，上記接地
回路または上記電源回路は，隣接する信号回路に沿った
形状からなる並行部を有するとともに，該並行部と上記
信号回路との間には絶縁領域が所定幅を維持して介在し
ていることを特徴とするプリント配線板。1. A printed circuit board in which a signal circuit is sandwiched or surrounded by a power supply circuit and / or a ground circuit in a conductor layer in the same plane, wherein the ground circuit or the power supply circuit is A printed wiring board, comprising: a parallel portion having a shape along an adjacent signal circuit, and an insulating region interposed between the parallel portion and the signal circuit while maintaining a predetermined width.
並行部との間に介在する上記絶縁領域の幅は，３０〜２
００μｍであることを特徴とするプリント配線板。2. The device according to claim 1, wherein the width of the insulating region interposed between the signal circuit and the parallel portion is 30 to 2 mm.
A printed wiring board having a thickness of 00 μm.
路または上記電源回路における上記信号回路に沿った形
状の上記並行部の幅は，信号回路の配線部の幅よりも広
いことを特徴とするプリント配線板。3. The signal processing circuit according to claim 1, wherein a width of the parallel portion of the ground circuit or the power supply circuit along the signal circuit is wider than a width of a wiring portion of the signal circuit. Printed wiring board.
同一面内の導体層において，２本の信号回路が，電源回
路または／及び接地回路により，挟まれるか又は囲まれ
てなることを特徴とするプリント配線板。4. The method according to claim 1, wherein:
A printed wiring board characterized in that two signal circuits are sandwiched or surrounded by a power supply circuit and / or a ground circuit in a conductor layer in the same plane.
上記電源回路，接地回路及び信号回路の内部には，０．
０４９ｍｍ２以下の回路未形成部分が存在しないことを
特徴とするプリント配線板。5. The method according to claim 1, wherein:
The inside of the power supply circuit, the ground circuit, and the signal circuit includes:
A printed wiring board characterized by having no circuit-unformed portion of 049 mm 2 or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001168593A JP2002368353A (en) | 2001-06-04 | 2001-06-04 | Printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001168593A JP2002368353A (en) | 2001-06-04 | 2001-06-04 | Printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002368353A true JP2002368353A (en) | 2002-12-20 |
Family
ID=19010803
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001168593A Pending JP2002368353A (en) | 2001-06-04 | 2001-06-04 | Printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002368353A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006156820A (en) * | 2004-11-30 | 2006-06-15 | Toshiba Corp | Circuit board |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH098465A (en) * | 1995-06-16 | 1997-01-10 | Ibiden Co Ltd | Multilayer printed-wiring board |
| JPH1041637A (en) * | 1996-07-23 | 1998-02-13 | Nec Corp | High-density multilayer wiring board |
| JPH1168322A (en) * | 1997-08-09 | 1999-03-09 | Ibiden Co Ltd | Multi-layer printed wiring board |
| JP2000277928A (en) * | 1999-03-25 | 2000-10-06 | Kyocera Corp | Multilayer wiring board |
| JP2001111182A (en) * | 1999-10-07 | 2001-04-20 | Sumitomo Metal Electronics Devices Inc | Wiring board |
-
2001
- 2001-06-04 JP JP2001168593A patent/JP2002368353A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH098465A (en) * | 1995-06-16 | 1997-01-10 | Ibiden Co Ltd | Multilayer printed-wiring board |
| JPH1041637A (en) * | 1996-07-23 | 1998-02-13 | Nec Corp | High-density multilayer wiring board |
| JPH1168322A (en) * | 1997-08-09 | 1999-03-09 | Ibiden Co Ltd | Multi-layer printed wiring board |
| JP2000277928A (en) * | 1999-03-25 | 2000-10-06 | Kyocera Corp | Multilayer wiring board |
| JP2001111182A (en) * | 1999-10-07 | 2001-04-20 | Sumitomo Metal Electronics Devices Inc | Wiring board |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006156820A (en) * | 2004-11-30 | 2006-06-15 | Toshiba Corp | Circuit board |
| JP4664657B2 (en) * | 2004-11-30 | 2011-04-06 | 株式会社東芝 | Circuit board |
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