JP2002368192A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2002368192A
JP2002368192A JP2001174731A JP2001174731A JP2002368192A JP 2002368192 A JP2002368192 A JP 2002368192A JP 2001174731 A JP2001174731 A JP 2001174731A JP 2001174731 A JP2001174731 A JP 2001174731A JP 2002368192 A JP2002368192 A JP 2002368192A
Authority
JP
Japan
Prior art keywords
chips
chip
semiconductor device
parallel
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001174731A
Other languages
Japanese (ja)
Other versions
JP4715040B2 (en
Inventor
Takatoshi Kobayashi
孝敏 小林
Sohiko Betsuda
惣彦 別田
Shinichi Yoshito
新一 吉渡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP2001174731A priority Critical patent/JP4715040B2/en
Publication of JP2002368192A publication Critical patent/JP2002368192A/en
Application granted granted Critical
Publication of JP4715040B2 publication Critical patent/JP4715040B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Inverter Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To suppress rise in Tj(junction temperature) by efficiently dissipating heat generated, in the case of connecting a plurality of transistor chips in parallel and turning them on/off simultaneously in a package. SOLUTION: In a semiconductor device having a large capacity which is used for an inverter, three IGBT chips are arranged on an insulation substrate 2. In this case, the chips 1a are arranged in zigzag manner, to connect them in parallel. Diode chips 1b are arranged in a region unoccupied by the chips 1a.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、スイッチング電源
装置などのコンバータ、インバータなどに適用するパワ
ー半導体モジュールに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor module applied to a converter, an inverter and the like of a switching power supply.

【０００２】[0002]

【従来の技術】近年，産業用インバータなどの電力変換
装置において，40kW〜1MWクラスの大容量品の需要が高
まってきており，これに使用されるパワーデバイスには
さらなる小型化，高信頼性，使いやすさが求められてい
る。このようなパワーデバイスでは制御する電流は数百
A以上となり，半導体素子での発生損失（熱）は数百Ｗ
以上となる。そのため、パワーモジュールには放熱，ジ
ュール熱を考慮した熱設計が求められる。2. Description of the Related Art In recent years, demand for large-capacity products of 40 kW to 1 MW class has been increasing in power converters such as industrial inverters. Ease of use is required. In such a power device, the current to be controlled is several hundred.
A, and the loss (heat) generated by the semiconductor device is several hundred W
That is all. Therefore, a thermal design is required for the power module in consideration of heat radiation and Joule heat.

【０００３】一般的なIGBTモジュールの断面構造を図８
に示す。ここで，半導体素子（チップ１）で発生した熱
は，絶縁基板２→ヒートシンク（Ｃuベース３）→冷却
体（放熱フイン図示せず）と移動し，外界に放熱され
る。パワーモジュールは省スペース化と大容量化が図ら
れている。そのため，パッケージとしての熱抵抗は大き
くなり，実使用時のチップ接合温度(Tj)の上昇が心配さ
れる。Tjを保証温度125℃以下に保つためには，チップ
の低損失化と，パッケージの適切な熱設計が必要とな
る。しかしながら、大容量化のためには、同特性のチッ
プを複数並列に接続して使用されるのが通例であり、か
かるチップを並列接続する場合に同じタイミングでオン
・オフさせるために一直線上に配置していた。FIG. 8 shows a cross-sectional structure of a general IGBT module.
Shown in Here, the heat generated in the semiconductor element (chip 1) moves from the insulating substrate 2 → the heat sink (Cu base 3) → the cooling body (not shown) and is radiated to the outside. Power modules have been reduced in space and increased in capacity. Therefore, the thermal resistance of the package increases, and there is a concern that the chip bonding temperature (Tj) in actual use will increase. In order to keep Tj below the guaranteed temperature of 125 ° C, it is necessary to reduce the loss of the chip and to design the package appropriately. However, in order to increase the capacity, it is customary to use a plurality of chips having the same characteristics connected in parallel, and when such chips are connected in parallel, they are turned on and off at the same timing, so that they are arranged in a straight line. Had been placed.

【０００４】[0004]

【発明が解決しようとする課題】パワーモジュールの大
容量化をはかるために複数のチップを並列接続した場合
に、これら複数のチップが同時にオン・オフのスイッチ
ングを行いその配置個所の温度上昇が避けられないばか
りか、チップ相互の熱干渉の問題が生じ、熱的な不具合
による特性の低下が考えられる。本発明は、チップで発
生した熱をパッケージ内で効率良く拡散させ， Tjの上
昇(ΔTj)を抑える構造を提供することを目的とする。When a plurality of chips are connected in parallel in order to increase the capacity of a power module, the plurality of chips switch on and off at the same time to avoid a rise in temperature at the location where the chips are arranged. In addition to this, the problem of thermal interference between the chips may occur, and the characteristics may be degraded due to thermal defects. SUMMARY OF THE INVENTION It is an object of the present invention to provide a structure in which heat generated in a chip is efficiently diffused in a package and a rise in Tj (ΔTj) is suppressed.

【０００５】[0005]

【課題を解決するための手段】上記目的を達成するため
に、本発明によれば、複数のトランジスタチップが並列
に接続され１つのスイッチング素子をなすものにおい
て、トランジスタチップが千鳥状に絶縁基板上に配置さ
れていることとする。前記複数のトランジスタチップが
並列に接続され１つのスイッチング素子をなすものが複
数形成されインバータ回路の各アームのスイッチング素
子となるのがよい。また、前記トランジスタチップにダ
イオードチップが並列に接続されたものとする。そし
て、絶縁基板上のトランジスタチップのエミッタの接続
個所に抵抗低減のための接続体を介在させるのがよい。
その際にトランジスタチップのエミッタと接続体との接
合がボンデイングワイヤであることとする。半導体装置
が３００A／１２００Vまたは４５０A／１２００Vの定格
であることとする。According to the present invention, a plurality of transistor chips are connected in parallel to form one switching element, and the transistor chips are staggered on an insulating substrate. It is assumed that it is arranged in. A plurality of transistor chips connected in parallel to form one switching element are preferably formed and serve as switching elements for each arm of the inverter circuit. It is also assumed that a diode chip is connected in parallel to the transistor chip. Then, it is preferable that a connection body for reducing resistance is interposed at the connection point of the emitter of the transistor chip on the insulating substrate.
At this time, it is assumed that the junction between the emitter of the transistor chip and the connection body is a bonding wire. The semiconductor device has a rating of 300 A / 1200 V or 450 A / 1200 V.

【０００６】[0006]

【発明の実施の形態】図２に示す簡易モデルでチップ配
置を有限要素法解析で検討を行った。1はチップ、２は
銅パターンが両面に形成された絶縁基板、３はＣuベー
ス、４は冷却体である。図３に示す解析結果から，二つ
のチップ１にオフセット量を与えパッケージ上に対角配
置することで，チップ間隔を大きく取った場合と同様に
熱干渉を軽減でき，ΔTjを抑えられることが分かる。な
お，Tjはチップセンターの温度である。また，この対角
配置により，Al2O3(λ＝20W/m.K)で構成された絶縁基板
であっても，従来大定格モジュールに採用されていた高
熱伝導率を有するAlN(λ＝170W/m.K)を用いた場合と同
等のΔTjを実現できることが分かる。図２、図３の解析
結果から，Tjはチップ配置に影響を受けることが分か
る。そこで，Tjの上昇を抑えるためIGBTチップの配置を
図４のように対角（千鳥）配置とし、絶縁基板２にはAl
2O3を採用した。大きいチップ１ａがＩＧＢＴチップで
あり、小さいチップ１ｂがダイオードチップである。こ
の場合は、３つのＩＧＢＴチップ１ａが並列に接続され
て１つのスイッチング素子をなし、このスイッチング素
子が６組配置されインバータの各アームを形成すること
となる。ダイオードチップ１ｂは、フリーホイリング用
であり、この場合はＩＧＢＴチップ１つに対して１つ設
けているが、並列接続したＩＧＢＴチップ１ａの３つに
対して１つあるいは２つとしてもよい。９はＣｕベース
３に空けた貫通孔であり、Ｃｕベース３の応力が絶縁基
板２に加わるのを軽減するためのものである。ここで重
要なのは、ＩＧＢＴチップ１ａを千鳥状に配置すること
である。チップ配置の効果を確認するため，熱伝導解析
と温度測定実験を実施した。解析対象は300A/1,200V定
格パッケージとし，発熱量は約70W/chip，冷却条件は周
囲温度Ta=25℃，強制空冷(v=3.5m/s)とした。図５は熱
解析による温度分布図，図６はサーモグラフィーによる
実験での温度分布図である。図５のシミュレーション結
果，図６の実測結果ともに複数あるＩＧＢＴチップの特
定のチップのみが高温になることはなく，チップで発生
した熱が効率良くパッケージ内で拡散されていることが
確認できる。これはＩＧＢＴのチップを千鳥配置とした
ことにより，熱干渉を抑え，パッケージ全体を冷却体へ
の熱伝導に有効利用できた結果である。図７は450A/1,2
00V定格パッケージをfc=1kHz，100%負荷で動作させた場
合を想定したシミュレーション結果である。実動作時は
IGBT，ダイオード(Free WheelingDiode)チップともに発
熱するが，この場合も，各相内で特定のチップのみが熱
干渉によって高温となる現象は生じていないことが温度
分布図から確認できる。DESCRIPTION OF THE PREFERRED EMBODIMENTS The chip arrangement was examined by a finite element analysis using the simple model shown in FIG. 1 is a chip, 2 is an insulating substrate having copper patterns formed on both sides, 3 is a Cu base, and 4 is a cooling body. From the analysis results shown in FIG. 3, it can be seen that by giving an offset amount to the two chips 1 and diagonally arranging them on the package, thermal interference can be reduced and ΔTj can be reduced, as in the case where the chip spacing is increased. . Here, Tj is the temperature of the chip center. Also, due to this diagonal arrangement, even if the insulating substrate is made of Al 2 O 3 (λ = 20 W / mK), AlN (λ = 170 W / It can be seen that ΔTj equivalent to the case using (mK) can be realized. From the analysis results of FIGS. 2 and 3, it can be seen that Tj is affected by the chip arrangement. In order to suppress the rise of Tj, the IGBT chips are arranged diagonally (staggered) as shown in FIG.
2 O 3 was employed. The large chip 1a is an IGBT chip, and the small chip 1b is a diode chip. In this case, three IGBT chips 1a are connected in parallel to form one switching element, and six sets of these switching elements are arranged to form each arm of the inverter. The diode chip 1b is for freewheeling. In this case, one diode chip 1b is provided for one IGBT chip, but one or two diode chips 1b may be provided for three IGBT chips 1a connected in parallel. Reference numeral 9 denotes a through-hole formed in the Cu base 3 for reducing the stress of the Cu base 3 from being applied to the insulating substrate 2. What is important here is that the IGBT chips 1a are arranged in a staggered manner. Thermal conduction analysis and temperature measurement experiments were performed to confirm the effect of chip placement. The analysis target was a 300A / 1,200V rated package, the heat value was about 70W / chip, the cooling conditions were ambient temperature Ta = 25 ° C, and forced air cooling (v = 3.5m / s). FIG. 5 is a temperature distribution diagram by thermal analysis, and FIG. 6 is a temperature distribution diagram in an experiment by thermography. Both the simulation result of FIG. 5 and the measurement result of FIG. 6 indicate that only a specific one of the plurality of IGBT chips does not become high in temperature, and that the heat generated in the chip is efficiently diffused in the package. This is a result of the fact that the IGBT chips are arranged in a staggered manner, thereby suppressing thermal interference and effectively utilizing the entire package for heat conduction to the cooling body. Figure 7 shows 450A / 1,2
This is a simulation result assuming a case where a 00V rated package is operated at fc = 1 kHz and 100% load. During actual operation
Both the IGBT and diode (Free Wheeling Diode) chips generate heat. In this case, too, it can be confirmed from the temperature distribution diagram that the phenomenon that only a specific chip becomes high in temperature due to thermal interference does not occur.

【０００７】図１に内部配線モデルの一部を示し、
（ａ）は蓋を外した状態での平面図であり、（ｂ）は側
面の一部断面図である。本実施例の特徴である薄型パッ
ケージでは，従来の銅バーによる空中配線が困難であ
り，端子と絶縁基板間および絶縁基板と絶縁基板間の接
続配線高さを低く抑える必要がある。課題は細いアルミ
ワイヤーに最大450A(1,200V系)の大電流を流すことによ
るワイヤー発熱温度を，封止用シリコーンゲルの耐熱温
度以下になるよう設計することである。FIG. 1 shows a part of an internal wiring model.
(A) is a plan view with the lid removed, and (b) is a partial cross-sectional view of a side surface. In the thin package, which is a feature of the present embodiment, it is difficult to perform aerial wiring using a conventional copper bar, and it is necessary to keep the connection wiring height between the terminal and the insulating substrate and between the insulating substrate and the insulating substrate low. The challenge is to design the heat generation temperature of a thin aluminum wire by applying a large current of 450A (1,200V) to the heat resistance temperature of the silicone gel for sealing.

【０００８】IN部（電極）よりDC450Aを流し，アルミワ
イヤー及び銅配線を通りOUT部（銅配線端部）から流れ
出る設定とし、通電条件をインバータ運転条件の450A(t
=60sec)で解析を行った。解析の都合上，ワイヤー形状
は角柱としたが，実ワイヤーの断面積と等しくなるよう
に構造モデルを作成した。解析ソフトはSOLIDIS3D(スイ
スISE社製)を用い，過渡解析モードで60秒後の電流密度
分布及び温度分布の計算を行った。解析及び実測（サー
モグラフィー）による450A(t=60sec)通電時のワイヤー
温度及びワイヤー位置とワイヤー温度の関係をみると、
解析結果が実測値とほぼ一致することが確認できた。発
熱状態は，電流経路が最短となるワイヤーに電流が集中
的に流れ（温度148℃），封止ゲルの耐熱温度以上とな
ることが明確となった。電流集中の改善策として，絶
縁基板上の銅配線のコーナー部にＲを付ける，Ｒ付け
＋アルミワイヤーの太線化について検証した。改善策
及び改善策について解析した結果、電流経路の銅配線
コーナー部にＲを付けることにより，電流のアンバラン
スが改善され，ワイヤー位置による温度分布がなだらか
になった。さらにアルミワイヤーを太線化することで抵
抗を下げ，ワイヤー全体の温度を94℃まで下げられるこ
とが分かった。改善策で解析したワイヤー位置と電流
密度の結果をみると、Ｒ付けすることにより，改善前に
比べワイヤー間での電流密度差が少なくなり，太線化に
より電流密度自体の値を下げている。以上より，銅配線
コーナー部へのＲ付け及びワイヤーの太線化が電流アン
バランスの改善，ワイヤー温度上昇の低減に有効である
ことが示され，目標温度以内におさめることができた。[0008] DC450A is supplied from the IN section (electrode), flows out of the OUT section (copper wiring end) through aluminum wire and copper wiring, and the energizing condition is 450A (t) of the inverter operating condition.
= 60sec). Although the wire shape was a prism for the sake of analysis, a structural model was created so that it would be equal to the cross-sectional area of the actual wire. The analysis software used SOLIDIS3D (made by ISE, Switzerland) to calculate the current density distribution and the temperature distribution after 60 seconds in the transient analysis mode. Looking at the relationship between wire temperature and wire position and wire temperature when conducting 450A (t = 60sec) by analysis and actual measurement (thermography),
It was confirmed that the analysis result almost coincided with the actually measured value. In the heat generation state, it became clear that current concentrated on the wire with the shortest current path (temperature: 148 ° C) and exceeded the heat resistance temperature of the sealing gel. As a measure to improve the current concentration, we verified that R was added to the corners of the copper wiring on the insulating substrate and that R was added and the aluminum wire was made thicker. As a result of analyzing the improvement measures and the improvement measures, the current imbalance was improved and the temperature distribution depending on the wire position became gentle by adding R to the copper wiring corner of the current path. Furthermore, it was found that the resistance was reduced by making the aluminum wire thicker, and the temperature of the entire wire could be reduced to 94 ° C. Looking at the results of the wire position and the current density analyzed by the improvement measures, the current density difference between the wires was reduced by adding R, compared to before the improvement, and the value of the current density itself was reduced by thickening. From the above, it was shown that the addition of the radius to the copper wiring corner and the thickening of the wire were effective in improving the current imbalance and reducing the rise in the wire temperature, and could be kept within the target temperature.

【０００９】図１に示す製品例は、スイッチング素子が
６枚の絶縁基板２に分けてＣｕベース３の上に並置して
搭載されており、Ｃｕベース３はその板厚が４ｍｍ、外
形サイズが縦１２２ｍｍ、横１６２ｍｍである。一方、
各絶縁基板２は、板厚０．３２ｍｍのアルミナ板に銅パ
ターンを両面に接合したセラミックであり、その外形サ
イズは縦３８ｍｍ、横４１．９ｍｍである。そして、Ｃ
ｕベース３と各絶縁基板２とがＳｎ−Ｐｂ半田で半田接
合されており、その半田接合層の厚さは０．１５ｍｍで
ある。各絶縁基板２上には３つのＩＧＢＴチップ１ａが
千鳥状に配置されて電気的には並列接続にされている。
そして、ＩＧＢＴチップ１ａに対応するようにダイオー
ドチップ１ｂが、ＩＧＢＴチップ１ａの搭載されずにあ
いている位置にダイオードとＩＧＢＴそれぞれが隣接す
るように３つ配置されている。このようにＩＧＢＴチッ
プ１ａに隣接してダイオードチップ１ｂを設けるとトラ
ンジスタのエミッタとダイオードのアノードを接続する
ステッチボンデイングがしやすくなるので、製造が容易
となる利点もある。５は主電流が流れる主端子であり、
６は制御信号を与えるための制御端子である。この例で
は左側の主端子が下より上アームのコレクタ、下アーム
のエミッタの順になっており、右側の主端子がＵ，Ｖ，
Ｗの各中間出力端子となっている。そして更に、上アー
ム側のＩＧＢＴチップのエミッタがワイヤで接続される
銅パターン上に幅４ｍｍ、板厚１．５ｍｍの銅板の接続
体７が介在している。この接続体７はチップのダイボン
デイング時に同時に接続すればよい。この接続体７によ
り、主端子での抵抗が、２ｍΩから１ｍΩに低減するこ
とができ、パッケージ全体の発熱低下と電圧ドロップの
低減が図られている。また、主電流が流れる部分でのワ
イヤボンデイングされる銅パターンには電流集中が起き
やすくそれによる発熱がしやすいので、主電流が通流す
る個所でのワイヤボンデイングする銅パターンは直線で
あることが好ましいが、配置レイアウトの関係で必ずし
も直線とはできずにＬ字状に形成する場合がある。この
ようなＬ字状とする時は、ワイヤボンデイングする部分
の銅パターンの幅を他の部分の幅よりも広くして電流集
中を防ぐようにしておけばよい。In the product example shown in FIG. 1, switching elements are divided into six insulating substrates 2 and mounted side by side on a Cu base 3. The Cu base 3 has a plate thickness of 4 mm and an outer size. The length is 122 mm and the width is 162 mm. on the other hand,
Each insulating substrate 2 is a ceramic in which a copper pattern is bonded to both sides of an alumina plate having a plate thickness of 0.32 mm, and its outer dimensions are 38 mm long and 41.9 mm wide. And C
The u base 3 and each of the insulating substrates 2 are soldered with Sn-Pb solder, and the thickness of the solder bonding layer is 0.15 mm. On each insulating substrate 2, three IGBT chips 1a are arranged in a staggered manner and are electrically connected in parallel.
Three diode chips 1b are arranged so as to correspond to the IGBT chips 1a so that the diodes and the IGBTs are adjacent to each other at positions where the IGBT chips 1a are not mounted. When the diode chip 1b is provided adjacent to the IGBT chip 1a in this manner, stitch bonding for connecting the emitter of the transistor and the anode of the diode is facilitated, so that there is an advantage that the manufacture is facilitated. 5 is a main terminal through which a main current flows,
Reference numeral 6 denotes a control terminal for providing a control signal. In this example, the left main terminal is the collector of the upper arm and the emitter of the lower arm in this order from below, and the right main terminal is U, V,
W are intermediate output terminals. Further, a copper plate connecting body 7 having a width of 4 mm and a thickness of 1.5 mm is interposed on a copper pattern to which the emitter of the IGBT chip on the upper arm side is connected by a wire. The connection body 7 may be connected at the same time as die bonding of the chip. With this connector 7, the resistance at the main terminal can be reduced from 2 mΩ to 1 mΩ, so that the heat generation of the entire package and the voltage drop are reduced. In addition, current-concentration tends to occur in the copper pattern that is wire-bonded in the area where the main current flows, and heat is easily generated by the current concentration.Therefore, the copper pattern that is wire-bonded where the main current flows is straight. Although it is preferable, it may not always be straight and may be formed in an L-shape due to the arrangement layout. When forming such an L-shape, the width of the copper pattern in the portion to be wire-bonded may be made wider than the width of the other portions to prevent current concentration.

【００１０】以上の実施例において、インバータのため
のスイッチング素子の配置について説明したが、本発明
は少なくとも２つのトランジスタチップ(バイポーラ、M
OS、ＩＧＢＴなど)を並列に接続して大容量化を図り、
同時にオン・オフさせるものであれば、複数の並列のト
ランジスタチップからなるスイッチング素子が１つだけ
設けられるもの、例えば自動車の内燃機関点火回路のス
イッチング素子にも適用ができる。In the above embodiments, the arrangement of the switching elements for the inverter has been described. However, the present invention provides at least two transistor chips (bipolar, M-type).
OS, IGBT, etc.) in parallel to increase capacity.
As long as they are turned on and off at the same time, the present invention can also be applied to a device provided with only one switching element including a plurality of parallel transistor chips, for example, a switching device of an ignition circuit of an internal combustion engine of an automobile.

【００１１】[0011]

【発明の効果】以上のように、主スイッチング素子のチ
ップを並列に接続する場合に千鳥状に配置することで、
大容量化と小型化が進むパワーデバイスの信頼性向上に
重要な熱分担の均等化あるいは低減を図ることができ
る。As described above, by arranging the chips of the main switching elements in a staggered manner when they are connected in parallel,
Equalization or reduction of heat sharing, which is important for improving the reliability of a power device whose capacity and size have been progressing, can be achieved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明による絶縁基板６枚形のパワー半導体モ
ジュール製品の構成図であり、（ａ）は平面図、（ｂ）
は側面部分断面図FIG. 1 is a configuration diagram of a power semiconductor module product having six insulating substrates according to the present invention, wherein (a) is a plan view and (b).
Is a side sectional view

【図２】本発明の簡易モデルの斜視図FIG. 2 is a perspective view of a simplified model of the present invention.

【図３】図２の簡易モデルの解析結果状態図3 is an analysis result state diagram of the simplified model of FIG. 2;

【図４】本発明の解析用平面図FIG. 4 is a plan view for analysis of the present invention.

【図５】図４の構成の熱解析による温度分布図FIG. 5 is a temperature distribution diagram by thermal analysis of the configuration of FIG. 4;

【図６】図４の構成のサーモグラフィーによる実験での
温度分布図FIG. 6 is a temperature distribution diagram in an experiment by thermography with the configuration of FIG. 4;

【図７】450A/1,200V定格パッケージをfc=1kHz，100%負
荷で動作させた場合を想定したシミュレーション結果の
温度分布図FIG. 7 is a temperature distribution diagram of a simulation result assuming that a 450A / 1,200V rated package is operated at fc = 1kHz and 100% load.

【図８】従来のＩＧＢＴモジュールの断面図FIG. 8 is a sectional view of a conventional IGBT module.

【符号の説明】[Explanation of symbols]

１ チップ １ａ ＩＧＢＴチップ １ｂ ダイオードチップ ２ 絶縁基板 ２ａ 銅パターン ３ Ｃｕベース ４ 冷却体 ５ 主端子 ６ 制御端子 ７ 接続体 DESCRIPTION OF SYMBOLS 1 Chip 1a IGBT chip 1b Diode chip 2 Insulating substrate 2a Copper pattern 3 Cu base 4 Cooling body 5 Main terminal 6 Control terminal 7 Connection body

───────────────────────────────────────────────────── フロントページの続き (72)発明者 吉渡 新一 神奈川県川崎市川崎区田辺新田１番１号 富士電機株式会社内 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Shinichi Yoshiwatto 1-1, Tanabe-Nitta, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fuji Electric Co., Ltd.

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】複数のトランジスタチップが並列に接続さ
れ１つのスイッチング素子をなすものにおいて、トラン
ジスタチップが千鳥状に絶縁基板上に配置されているこ
とを特徴とする半導体装置。1. A semiconductor device in which a plurality of transistor chips are connected in parallel to form one switching element, wherein the transistor chips are arranged in a staggered manner on an insulating substrate. 【請求項２】前記複数のトランジスタチップが並列に接
続され１つのスイッチング素子をなすものが複数形成さ
れインバータ回路の各アームのスイッチング素子となる
ことを特徴とする請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein a plurality of said plurality of transistor chips connected in parallel to form one switching element are formed as switching elements of each arm of the inverter circuit. 【請求項３】前記トランジスタチップにダイオードチッ
プが並列に接続されたことを特徴とする請求項２記載の
半導体装置。3. The semiconductor device according to claim 2, wherein a diode chip is connected to said transistor chip in parallel. 【請求項４】絶縁基板上のトランジスタチップのエミッ
タの接続個所に抵抗低減のための接続体を介在させたこ
とを特徴とする請求項２記載の半導体装置。4. The semiconductor device according to claim 2, wherein a connection body for reducing resistance is interposed at a connection point of the emitter of the transistor chip on the insulating substrate. 【請求項５】トランジスタチップのエミッタと接続体と
の接合がボンデイングワイヤであることを特徴とする請
求項４記載の半導体装置。5. The semiconductor device according to claim 4, wherein the junction between the emitter of the transistor chip and the connection body is a bonding wire. 【請求項６】半導体装置が３００A／１２００Vまたは４
５０A／１２００Vの定格であることを特徴とする請求項
２記載の半導体装置。6. A semiconductor device having a capacity of 300 A / 1200 V or 4
3. The semiconductor device according to claim 2, wherein the rating is 50 A / 1200 V.
JP2001174731A 2001-06-08 2001-06-08 Semiconductor device Expired - Lifetime JP4715040B2 (en)

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CN108447847A (en) * 2018-06-06 2018-08-24 臻驱科技（上海）有限公司 A kind of power semiconductor modular substrate and power semiconductor modular
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