JP2002368080A5 - - Google Patents

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JP2002368080A5
JP2002368080A5 JP2001169631A JP2001169631A JP2002368080A5 JP 2002368080 A5 JP2002368080 A5 JP 2002368080A5 JP 2001169631 A JP2001169631 A JP 2001169631A JP 2001169631 A JP2001169631 A JP 2001169631A JP 2002368080 A5 JP2002368080 A5 JP 2002368080A5
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misfet
element isolation
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length direction
circuit device
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Priority to TW91108115A priority patent/TWI223434B/en
Priority to PCT/JP2002/003944 priority patent/WO2002099872A1/en
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ＭＩＳＦＥＴが形成された活性領域を囲む素子分離部の少なくともゲート長方向の一方の分離幅を相対的に狭くして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に大きくし、By relatively narrowing at least one isolation width in the gate length direction of the element isolation portion surrounding the active region where the MISFET is formed, the electrical characteristic change of the MISFET is relatively increased,
前記素子分離部の分離幅を相対的に広くして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に小さくし、  The isolation width of the element isolation part is relatively wide, the change in electrical characteristics of the MISFET is relatively small,
前記分離幅と前記電気的特性変化との関係に基づいて、前記分離幅を調整することにより、前記ＭＩＳＦＥＴの所望する特性を得ることを特徴とする半導体集積回路装置。  A semiconductor integrated circuit device characterized in that a desired characteristic of the MISFET is obtained by adjusting the separation width based on a relationship between the separation width and the change in electrical characteristics. ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの少なくとも一方の距離を相対的に大きくして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に小さくし、By relatively increasing the distance between at least one of the gate electrode of the MISFET and the element isolation portion in the gate length direction, the electrical characteristic change of the MISFET is relatively decreased
前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの距離を相対的に小さくして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に大きくし、  A relatively small distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction, and a relatively large change in electrical characteristics of the MISFET;
前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの距離と前記電気的特性変化との関係に基づいて、前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの少なくとも一方の距離を調整することにより、前記ＭＩＳＦＥＴの所望する特性を得ることを特徴とする半導体集積回路装置。  Based on the relationship between the distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction and the change in the electrical characteristics, at least one distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction is adjusted Thus, a desired characteristic of the MISFET is obtained. ＭＩＳＦＥＴが形成された活性領域を囲む素子分離部の少なくともゲート長方向の一方の分離幅を相対的に狭くして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に大きくし、By relatively narrowing at least one isolation width in the gate length direction of the element isolation portion surrounding the active region where the MISFET is formed, the electrical characteristic change of the MISFET is relatively increased,
前記素子分離部の分離幅を相対的に広くして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に小さくし、  The isolation width of the element isolation part is relatively wide, the change in electrical characteristics of the MISFET is relatively small,
前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの少なくとも一方の距離を相対的に大きくして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に小さくし、  A relatively large distance between at least one of the gate electrode of the MISFET and the element isolation portion in the gate length direction, and a relatively small change in electrical characteristics of the MISFET;
前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの距離を相対的に小さくして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に大きくし、  A relatively small distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction, and a relatively large change in electrical characteristics of the MISFET;
前記分離幅と前記電気的特性変化との関係に基づいて、前記分離幅を調整すると共に、前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの距離と前記電気的特性変化との関係に基づいて、前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの少なくとも一方の距離を調整することにより、前記ＭＩＳＦＥＴの所望する特性を得ることを特徴とする半導体集積回路装置。  The isolation width is adjusted based on the relationship between the isolation width and the change in the electrical characteristics, and the relationship between the distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction and the change in the electrical characteristics. A semiconductor integrated circuit device characterized in that a desired characteristic of the MISFET is obtained by adjusting at least one distance from the gate electrode of the MISFET to an element isolation portion in the gate length direction. ＭＩＳＦＥＴが形成された活性領域と、前記活性領域とゲート長方向に隣接するダミー活性領域との間の素子分離部の分離幅を相対的に狭くして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に大きくし、The isolation width of the element isolation portion between the active region in which the MISFET is formed and the dummy active region adjacent to the active region in the gate length direction is relatively narrowed, and the electrical characteristic change of the MISFET is relatively reduced. To make it bigger
前記素子分離部の分離幅を相対的に広くして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に小さくし、  The isolation width of the element isolation part is relatively wide, the change in electrical characteristics of the MISFET is relatively small,
前記分離幅と前記電気的特性変化との関係に基づいて前記分離幅を調整することにより、前記ＭＩＳＦＥＴの所望する特性を得ることを特徴とする半導体集積回路装置。  A semiconductor integrated circuit device characterized in that a desired characteristic of the MISFET is obtained by adjusting the isolation width based on a relationship between the isolation width and the change in electrical characteristics. ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの少なくとも一方の距離を相対的に大きくして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に小さくし、By relatively increasing the distance between at least one of the gate electrode of the MISFET and the element isolation portion in the gate length direction, the electrical characteristic change of the MISFET is relatively decreased
前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの距離を相対的に小さくして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に大きくし、  A relatively small distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction, and a relatively large change in electrical characteristics of the MISFET;
前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの距離と前記電気的特性変化との関係に基づいて、前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの少なくとも一方の距離を調整することにより、前記ＭＩＳＦＥＴの所望する特性を得る半導体集積回路装置において、  At least one distance from the gate electrode of the MISFET to the element isolation part in the gate length direction is adjusted based on the relationship between the distance from the gate electrode of the MISFET to the element isolation part in the gate length direction and the change in the electrical characteristics. In the semiconductor integrated circuit device that obtains the desired characteristics of the MISFET,
前記ＭＩＳＦＥＴが形成された活性領域上にダミーゲート電極が形成されていることを特徴とする半導体集積回路装置。  A semiconductor integrated circuit device, wherein a dummy gate electrode is formed on an active region where the MISFET is formed. ＭＩＳＦＥＴが形成された活性領域を囲む素子分離部の少なくともゲAt least the gate of the element isolation portion surrounding the active region where the MISFET is formed. ート長方向の一方の分離幅を相対的に狭くして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に大きくし、One of the isolation lengths in the direction of the gate length is relatively narrowed, and the change in electrical characteristics of the MISFET is relatively large,
前記素子分離部の分離幅を相対的に広くして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に小さくし、  The isolation width of the element isolation part is relatively wide, the change in electrical characteristics of the MISFET is relatively small,
前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの少なくとも一方の距離を相対的に大きくして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に小さくし、  A relatively large distance between at least one of the gate electrode of the MISFET and the element isolation portion in the gate length direction, and a relatively small change in electrical characteristics of the MISFET;
前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの距離を相対的に小さくして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に大きくし、  A relatively small distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction, and a relatively large change in electrical characteristics of the MISFET;
前記分離幅と前記電気的特性変化との関係に基づいて、前記分離幅を調整すると共に、前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの距離と前記電気的特性変化との関係に基づいて、前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの少なくとも一方の距離を調整することにより、前記ＭＩＳＦＥＴの所望する特性を得る半導体集積回路装置において、  The isolation width is adjusted based on the relationship between the isolation width and the change in the electrical characteristics, and the relationship between the distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction and the change in the electrical characteristics. On the basis of the semiconductor integrated circuit device that obtains the desired characteristics of the MISFET by adjusting at least one distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction,
前記ＭＩＳＦＥＴが形成された活性領域上にダミーゲート電極が形成されていることを特徴とする半導体集積回路装置。  A semiconductor integrated circuit device, wherein a dummy gate electrode is formed on an active region where the MISFET is formed. 請求項１〜６のいずれか１項に記載の半導体集積回路装置であって、
前記ＭＩＳＦＥＴが形成された活性領域を囲む素子分離部のゲート幅方向の分離幅は、０.３５μｍ以上であることを特徴とする半導体集積回路装置。A semiconductor integrated circuit device according to any one of claims 1 to 6,
2. A semiconductor integrated circuit device according to claim 1, wherein the isolation width in the gate width direction of the element isolation portion surrounding the active region where the MISFET is formed is 0.35 μm or more. 請求項１〜６のいずれか１項に記載の半導体集積回路装置であって、
前記素子分離部は溝アイソレーションまたはＬＯＣＯＳアイソレーションで構成されることを特徴とする半導体集積回路装置。A semiconductor integrated circuit device according to any one of claims 1 to 6,
2. The semiconductor integrated circuit device according to claim 1, wherein the element isolation portion is constituted by trench isolation or LOCOS isolation. 請求項１〜６のいずれか１項に記載の半導体集積回路装置であって、
前記ＭＩＳＦＥＴの特性は、しきい値電圧または駆動電流であることを特徴とする半導体集積回路装置。A semiconductor integrated circuit device according to any one of claims 1 to 6,
The semiconductor integrated circuit device characterized in that the characteristic of the MISFET is a threshold voltage or a drive current. 基板の主面上にしきい値電圧が互いに異なる第１のＭＩＳＦＥＴと第２のＭＩＳＦＥＴとを有する半導体集積回路装置において、
分離幅が相対的に広い素子分離部で囲まれた第１活性領域に前記第１のＭＩＳＦＥＴが形成され、少なくともゲート長方向の一方を分離幅が相対的に狭い素子分離部で囲まれた第２活性領域に前記第２のＭＩＳＦＥＴが形成されることを特徴とする半導体集積回路装置。In a semiconductor integrated circuit device having a first MISFET and a second MISFET having different threshold voltages on a main surface of a substrate,
The first MISFET is formed in a first active region surrounded by an element isolation portion having a relatively wide isolation width, and at least one of the gate length directions is surrounded by an element isolation portion having a relatively small isolation width. 2. The semiconductor integrated circuit device, wherein the second MISFET is formed in two active regions. 基板の主面上にしきい値電圧が互いに異なる第１のＭＩＳＦＥＴと第２のＭＩＳＦＥＴとを有する半導体集積回路装置において、
前記第１のＭＩＳＦＥＴが形成される第１活性領域のゲート電極からゲート長方向の素子分離部までの距離が相対的に大きく、前記第２のＭＩＳＦＥＴが形成される第２活性領域のゲート電極からゲート長方向の素子分離部までの少なくとも一方の距離が相対的に小さいことを特徴とする半導体集積回路装置。In a semiconductor integrated circuit device having a first MISFET and a second MISFET having different threshold voltages on a main surface of a substrate,
The distance from the gate electrode of the first active region where the first MISFET is formed to the element isolation portion in the gate length direction is relatively large, and from the gate electrode of the second active region where the second MISFET is formed A semiconductor integrated circuit device characterized in that at least one distance to the element isolation portion in the gate length direction is relatively small. 基板の主面上にしきい値電圧が互いに異なる第１のＭＩＳＦＥＴと第２のＭＩＳＦＥＴとを有する半導体集積回路装置において、
分離幅が相対的に広い素子分離部で囲まれた第１活性領域に前記第１のＭＩＳＦＥＴが形成され、少なくともゲート長方向の一方を分離幅が相対的に狭い素子分離部で囲まれた第２活性領域に前記第２のＭＩＳＦＥＴが形成され、前記第１活性領域のゲート電極からゲート長方向の素子分離部までの距離が相対的に大きく、前記第２活性領域のゲート電極からゲート長方向の素子分離部までの少なくとも一方の距離が相対的に小さいことを特徴とする半導体集積回路装置。In a semiconductor integrated circuit device having a first MISFET and a second MISFET having different threshold voltages on a main surface of a substrate,
The first MISFET is formed in a first active region surrounded by an element isolation portion having a relatively wide isolation width, and at least one of the gate length directions is surrounded by an element isolation portion having a relatively small isolation width. The second MISFET is formed in two active regions, the distance from the gate electrode of the first active region to the element isolation portion in the gate length direction is relatively large, and the gate length direction from the gate electrode of the second active region A semiconductor integrated circuit device characterized in that at least one distance to the element isolation portion is relatively small. 請求項１０記載の半導体集積回路装置であって、
前記第１活性領域のゲート電極からゲート長方向の素子分離部までの一方の距離と、前記第２活性領域のゲート電極からゲート長方向の素子分離部までの一方の距離とがほぼ同じであることを特徴とする半導体集積回路装置。The semiconductor integrated circuit device according to claim 10,
One distance from the gate electrode of the first active region to the element isolation portion in the gate length direction is substantially the same as one distance from the gate electrode of the second active region to the element isolation portion in the gate length direction. A semiconductor integrated circuit device. 請求項１１記載の半導体集積回路装置であって、
前記第１活性領域を囲む素子分離部のゲート長方向の一方の分離幅と、前記第２活性領域を囲む素子分離部のゲート長方向の一方の分離幅とがほぼ同じであり、前記第１活性領域を囲む素子分離部のゲート長方向の他方の分離幅と、前記第２活性領域を囲む素子分離部のゲート長方向の他方の分離幅とがほぼ同じであることを特徴とする半導体集積回路装置。A semiconductor integrated circuit device according to claim 11,
One isolation width in the gate length direction of the element isolation portion surrounding the first active region is substantially the same as one isolation width in the gate length direction of the element isolation portion surrounding the second active region, and A semiconductor integration characterized in that the other isolation width in the gate length direction of the element isolation portion surrounding the active region is substantially the same as the other isolation width in the gate length direction of the element isolation portion surrounding the second active region. Circuit device. 請求項１０または１２記載の半導体集積回路装置であって、
相対的に狭い素子分離部の分離幅は、０.３５μｍ以下であることを特徴とする半導体集積回路装置。The semiconductor integrated circuit device according to claim 10 or 12,
A semiconductor integrated circuit device characterized in that a relatively narrow isolation width of an element isolation portion is 0.35 μm or less. 請求項１１または１２記載の半導体集積回路装置であって、
前記第２のＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの間にダミーゲート電極が形成されていることを特徴とする半導体集積回路装置。A semiconductor integrated circuit device according to claim 11 or 12,
A semiconductor integrated circuit device, wherein a dummy gate electrode is formed between the gate electrode of the second MISFET and the element isolation portion in the gate length direction. 請求項１、３、４、１０または１２記載の半導体集積回路装置であって、
素子分離部の分離幅を相対的に狭くすることによりＭＩＳＦＥＴのチャネル領域へ及ぼす応力の影響を大きくして、しきい値電圧の変化を相対的に大きくし、素子分離部の分離幅を相対的に広くすることによりＭＩＳＦＥＴのチャネル領域へ及ぼす応力の影響を小さくして、しきい値電圧の変化を相対的に小さくすることを特徴とする半導体集積回路装置。A semiconductor integrated circuit device according to claim 1, 3, 4, 10 or 12,
By relatively narrowing the isolation width of the element isolation portion, the influence of stress on the channel region of the MISFET is increased, the change in threshold voltage is relatively increased, and the isolation width of the element isolation portion is relatively increased. A semiconductor integrated circuit device characterized in that the influence of the stress on the channel region of the MISFET is reduced by making the width of the MISFET smaller, and the change in threshold voltage is made relatively small. 請求項２、３、５、６、１１または１６記載の半導体集積回路装置であって、
ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの距離を相対的に大きくすることによりＭＩＳＦＥＴのチャネル領域へ及ぼす応力の影響を小さくして、しきい値電圧の変化を相対的に小さくし、ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの距離を相対的に小さくすることによりＭＩＳＦＥＴのチャネル領域へ及ぼす応力の影響を大きくして、しきい値電圧の変化を相対的に大きくすることを特徴とする半導体集積回路装置。A semiconductor integrated circuit device according to claim 2, 3, 5, 6, 11 or 16,
By relatively increasing the distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction, the influence of the stress on the channel region of the MISFET is reduced, and the change in the threshold voltage is relatively reduced. By relatively reducing the distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction, the influence of the stress on the channel region of the MISFET is increased, and the change in the threshold voltage is relatively increased. A semiconductor integrated circuit device. ＭＩＳＦＥＴが形成された活性領域を囲む素子分離部の少なくともゲート長方向の一方の分離幅を相対的に狭くして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に大きくする工程と、A step of relatively narrowing at least one isolation width in the gate length direction of the element isolation portion surrounding the active region where the MISFET is formed to relatively increase the electrical characteristic change of the MISFET;
前記素子分離部の分離幅を相対的に広くして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に小さくする工程と、  A step of relatively widening an isolation width of the element isolation portion to relatively reduce a change in electrical characteristics of the MISFET;
前記分離幅と前記電気的特性変化との関係に基づいて前記分離幅を調整する工程とにより、所望する特性のＭＩＳＦＥＴを形成することを特徴とする半導体集積回路装置の製造方法。  A method of manufacturing a semiconductor integrated circuit device, wherein a MISFET having a desired characteristic is formed by adjusting the separation width based on a relationship between the separation width and the change in electrical characteristics. ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの少なくとも一方の距離を相対的に大きくして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に小さくする工程と、A step of relatively increasing a distance between at least one of the gate electrode of the MISFET and the element isolation portion in the gate length direction to relatively reduce a change in electrical characteristics of the MISFET;
前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの距離を相対的に小さくして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に大きくする工程と、  Relatively decreasing the distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction to relatively increase the electrical characteristic change of the MISFET;
前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの距離と前記電気的特性変化との関係に基づいて、前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの少なくとも一方の距離を調整する工程とにより、所望する特性のＭＩＳＦＥＴを形成することを特徴とする半導体集積回路装置の製造方法。  Based on the relationship between the distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction and the change in the electrical characteristics, at least one distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction is adjusted And a step of forming a MISFET having a desired characteristic. ＭＩＳＦＥＴが形成された活性領域を囲む素子分離部の少なくともゲート長方向の一方の分離幅を相対的に狭くして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に大きくする工程と、A step of relatively narrowing at least one isolation width in the gate length direction of the element isolation portion surrounding the active region where the MISFET is formed to relatively increase the electrical characteristic change of the MISFET;
前記素子分離部の分離幅を相対的に広くして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に小さくする工程と、  A step of relatively widening an isolation width of the element isolation portion to relatively reduce a change in electrical characteristics of the MISFET;
前記分離幅と前記電気的特性変化との関係に基づいて前記分離幅を調整することにより、前記ＭＩＳＦＥＴの所望する特性を得る工程と、  Obtaining the desired characteristics of the MISFET by adjusting the isolation width based on the relationship between the isolation width and the change in electrical characteristics;
前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの少なくとも一方の  At least one of the gate electrode of the MISFET and the element isolation portion in the gate length direction 距離を相対的に大きくして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に小さくする工程と、A step of relatively increasing a distance to relatively reduce a change in electrical characteristics of the MISFET;
前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの距離を相対的に小さくして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に大きくする工程と、  Relatively decreasing the distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction to relatively increase the electrical characteristic change of the MISFET;
前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの距離と前記電気的特性変化との関係に基づいて、前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの少なくとも一方の距離を調整する工程とにより、所望する特性のＭＩＳＦＥＴを形成することを特徴とする半導体集積回路装置の製造方法。  Based on the relationship between the distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction and the change in the electrical characteristics, at least one distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction is adjusted A method of manufacturing a semiconductor integrated circuit device, wherein a MISFET having a desired characteristic is formed. ＭＩＳＦＥＴが形成された活性領域と、前記活性領域とゲート長方向に隣接するダミー活性領域との間の素子分離部の分離幅を相対的に狭くして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に大きくする工程と、The isolation width of the element isolation portion between the active region in which the MISFET is formed and the dummy active region adjacent to the active region in the gate length direction is relatively narrowed, and the electrical characteristic change of the MISFET is relatively reduced. The process of making
前記素子分離部の分離幅を相対的に広くして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に小さくし、前記分離幅と前記電気的特性変化との関係に基づいて前記分離幅を調整する工程とにより、所望する特性のＭＩＳＦＥＴを形成することを特徴とする半導体集積回路装置の製造方法。  The isolation width of the element isolation portion is relatively widened, the change in electrical characteristics of the MISFET is relatively reduced, and the isolation width is adjusted based on the relationship between the isolation width and the change in electrical characteristics. A method of manufacturing a semiconductor integrated circuit device, wherein a MISFET having desired characteristics is formed by a process. ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの少なくとも一方の距離を相対的に大きくして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に小さくする工程と、A step of relatively increasing a distance between at least one of the gate electrode of the MISFET and the element isolation portion in the gate length direction to relatively reduce a change in electrical characteristics of the MISFET;
前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの距離を相対的に小さくして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に大きくする工程と、  Relatively decreasing the distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction to relatively increase the electrical characteristic change of the MISFET;
前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの距離と前記電気的特性変化との関係に基づいて、前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの少なくとも一方の距離を調整する工程とにより、所望する特性のＭＩＳＦＥＴを形成する半導体集積回路装置の製造方法において、  At least one distance from the gate electrode of the MISFET to the element isolation part in the gate length direction is adjusted based on the relationship between the distance from the gate electrode of the MISFET to the element isolation part in the gate length direction and the change in the electrical characteristics. In the method of manufacturing a semiconductor integrated circuit device for forming a MISFET having desired characteristics by the step of:
前記ＭＩＳＦＥＴが形成された活性領域上にダミーゲート電極を形成することを特徴とする半導体集積回路装置の製造方法。  A method of manufacturing a semiconductor integrated circuit device, comprising: forming a dummy gate electrode on an active region in which the MISFET is formed. ＭＩＳＦＥＴが形成された活性領域を囲む素子分離部の少なくともゲート長方向の一方の分離幅を相対的に狭くして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に大きくする工程と、A step of relatively narrowing at least one isolation width in the gate length direction of the element isolation portion surrounding the active region where the MISFET is formed to relatively increase the electrical characteristic change of the MISFET;
前記素子分離部の分離幅を相対的に広くして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に小さくする工程と、  A step of relatively widening an isolation width of the element isolation portion to relatively reduce a change in electrical characteristics of the MISFET;
前記分離幅と前記電気的特性変化との関係に基づいて前記分離幅を調整することにより、前記ＭＩＳＦＥＴの所望する特性を得る工程と、  Obtaining the desired characteristics of the MISFET by adjusting the isolation width based on the relationship between the isolation width and the change in electrical characteristics;
前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの少なくとも一方の距離を相対的に大きくして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に小さくする工程と、  A step of relatively increasing at least one distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction to relatively reduce a change in electrical characteristics of the MISFET;
前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの距離を相対的に小さくして、前記ＭＩＳＦＥＴの電気的特性変化を相対的に大きくする工程と、  Relatively decreasing the distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction to relatively increase the electrical characteristic change of the MISFET;
前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの距離と前記電気的特性変化との関係に基づいて、前記ＭＩＳＦＥＴのゲート電極からゲート長方向の素子分離部までの少なくとも一方の距離を調整する工程とにより、所望する特性のＭＩＳＦＥＴを形成する半導体集積回路装置の製造方法において、  Based on the relationship between the distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction and the change in the electrical characteristics, at least one distance from the gate electrode of the MISFET to the element isolation portion in the gate length direction is adjusted In the method of manufacturing a semiconductor integrated circuit device for forming a MISFET having desired characteristics by the step of:
前記ＭＩＳＦＥＴが形成された活性領域上にダミーゲート電極を形成することを特徴とする半導体集積回路装置の製造方法。  A method of manufacturing a semiconductor integrated circuit device, comprising: forming a dummy gate electrode on an active region in which the MISFET is formed. 基板の主面上に特性が互いに異なる第１のＭＩＳＦＥＴと第２のＭＩＳＦＥＴとを形成する半導体集積回路装置の製造方法において、
分離幅が相対的に広い素子分離部で囲まれた第１活性領域に前記第１のＭＩＳＦＥＴを形成し、少なくともゲート長方向の一方を分離幅が相対的に狭い素子分離部で囲まれた第２活性領域に前記第２のＭＩＳＦＥＴを形成し、前記第１のＭ
ＩＳＦＥＴのゲート絶縁膜と前記第２のＭＩＳＦＥＴのゲート絶縁膜とを同一工程で形成し、前記第１活性領域へのイオン打ち込みと前記第２活性領域へのイオン打ち込みとを同一工程で行うことを特徴とする半導体集積回路装置の製造方法。In a method for manufacturing a semiconductor integrated circuit device, wherein a first MISFET and a second MISFET having different characteristics are formed on a main surface of a substrate.
The first MISFET is formed in a first active region surrounded by a relatively wide isolation region, and at least one of the gate length directions is surrounded by a relatively narrow isolation region. The second MISFET is formed in two active regions, and the first M
The gate insulating film of the ISFET and the gate insulating film of the second MISFET are formed in the same step, and the ion implantation into the first active region and the ion implantation into the second active region are performed in the same step. A method of manufacturing a semiconductor integrated circuit device. 基板の主面上に特性が互いに異なる第１のＭＩＳＦＥＴと第２のＭＩＳＦＥＴとを形成する半導体集積回路装置の製造方法において、
前記第１のＭＩＳＦＥＴが形成される第１活性領域のゲート電極からゲート長方向の素子分離部までの距離を相対的に大きく形成し、前記第２のＭＩＳＦＥＴが形成される第２活性領域のゲート電極からゲート長方向の素子分離部までの少なくとも一方の距離を相対的に小さく形成し、前記第１のＭＩＳＦＥＴのゲート絶縁膜と前記第２のＭＩＳＦＥＴのゲート絶縁膜とを同一工程で形成し、前記第１活性領域へのイオン打ち込みと前記第２活性領域へのイオン打ち込みとを同一工程で行うことを特徴とする半導体集積回路装置の製造方法。In a method for manufacturing a semiconductor integrated circuit device, wherein a first MISFET and a second MISFET having different characteristics are formed on a main surface of a substrate.
The distance from the gate electrode of the first active region where the first MISFET is formed to the element isolation portion in the gate length direction is relatively large, and the gate of the second active region where the second MISFET is formed Forming at least one distance from the electrode to the element isolation portion in the gate length direction relatively small, and forming the gate insulating film of the first MISFET and the gate insulating film of the second MISFET in the same step; A method of manufacturing a semiconductor integrated circuit device, wherein ion implantation into the first active region and ion implantation into the second active region are performed in the same step. 基板の主面上に特性が互いに異なる第１のＭＩＳＦＥＴと第２のＭＩＳＦＥＴとを形成する半導体集積回路装置の製造方法において、
分離幅が相対的に広い素子分離部で囲まれた第１活性領域に前記第１のＭＩＳＦＥＴを形成し、少なくともゲート長方向の一方を分離幅が相対的に狭い素子分離部で囲まれた第２活性領域に前記第２のＭＩＳＦＥＴを形成し、前記第１活性領域のゲート電極からゲート長方向の素子分離部までの距離を相対的に大きく形成し、前記第２活性領域のゲート電極からゲート長方向の素子分離部までの少なくとも一方の距離を相対的に小さく形成し、前記第１のＭＩＳＦＥＴのゲート絶縁膜と前記第２のＭＩＳＦＥＴのゲート絶縁膜とを同一工程で形成し、前記第１活性領域へのイオン打ち込みと前記第２活性領域へのイオン打ち込みとを同一工程で行うことを特徴とする半導体集積回路装置の製造方法。In a method for manufacturing a semiconductor integrated circuit device, wherein a first MISFET and a second MISFET having different characteristics are formed on a main surface of a substrate.
The first MISFET is formed in a first active region surrounded by a relatively wide isolation region, and at least one of the gate length directions is surrounded by a relatively narrow isolation region. The second MISFET is formed in two active regions, the distance from the gate electrode of the first active region to the element isolation portion in the gate length direction is relatively large, and the gate electrode of the second active region is gated At least one distance to the element isolation portion in the long direction is formed to be relatively small, the gate insulating film of the first MISFET and the gate insulating film of the second MISFET are formed in the same process, and the first A method of manufacturing a semiconductor integrated circuit device, wherein ion implantation into an active region and ion implantation into the second active region are performed in the same process. 請求項２５記載の半導体集積回路装置の製造方法であって、
前記第１活性領域のゲート電極からゲート長方向の素子分離部までの一方の距離と、前記第２活性領域のゲート電極からゲート長方向の素子分離部までの一方の距離とがほぼ同じであることを特徴とする半導体集積回路装置の製造方法。A method of manufacturing a semiconductor integrated circuit device according to claim 25,
One distance from the gate electrode of the first active region to the element isolation portion in the gate length direction is substantially the same as one distance from the gate electrode of the second active region to the element isolation portion in the gate length direction. A method of manufacturing a semiconductor integrated circuit device. 請求項２６記載の半導体集積回路装置の製造方法であって、
前記第１活性領域を囲む素子分離部のゲート長方向の一方の分離幅と、前記第２活性領域を囲む素子分離部のゲート長方向の一方の分離幅とがほぼ同じであり、前記第１活性領域を囲む素子分離部のゲート長方向の他方の分離幅と、前記第２活性領域を囲む素子分離部のゲート長方向の他方の分離幅とがほぼ同じであることを特徴とする半導体集積回路装置の製造方法。A method of manufacturing a semiconductor integrated circuit device according to claim 26, wherein
One isolation width in the gate length direction of the element isolation portion surrounding the first active region is substantially the same as one isolation width in the gate length direction of the element isolation portion surrounding the second active region, and A semiconductor integration characterized in that the other isolation width in the gate length direction of the element isolation portion surrounding the active region is substantially the same as the other isolation width in the gate length direction of the element isolation portion surrounding the second active region. A method of manufacturing a circuit device. 請求項２５または２７記載の半導体集積回路装置の製造方法であって、
相対的に狭い素子分離部の分離幅は、０.３５μｍ以下であることを特徴とする半導体集積回路装置の製造方法。28. A method of manufacturing a semiconductor integrated circuit device according to claim 25 or 27, comprising:
A method of manufacturing a semiconductor integrated circuit device, wherein the isolation width of a relatively narrow element isolation portion is 0.35 μm or less. 請求項１９〜３０のいずれか１項に記載の半導体集積回路装置の製造方法であって、
前記ＭＩＳＦＥＴの特性は、しきい値電圧または駆動電流であることを特徴とする半導体集積回路装置の製造方法。A method for manufacturing a semiconductor integrated circuit device according to any one of claims 19 to 30, comprising:
The method of manufacturing a semiconductor integrated circuit device, wherein the characteristic of the MISFET is a threshold voltage or a drive current. 請求項１０〜１６のいずれか１項に記載の半導体集積回路装置であって、前記第１のＭＩＳＦＥＴと前記第２のＭＩＳＦＥＴとは、同一電源電圧で動作することを特徴とする半導体集積回路装置。17. The semiconductor integrated circuit device according to claim 10, wherein the first MISFET and the second MISFET operate with the same power supply voltage. .
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