JP2002359392A - Semiconductor relay - Google Patents
Semiconductor relayInfo
- Publication number
- JP2002359392A JP2002359392A JP2001164062A JP2001164062A JP2002359392A JP 2002359392 A JP2002359392 A JP 2002359392A JP 2001164062 A JP2001164062 A JP 2001164062A JP 2001164062 A JP2001164062 A JP 2001164062A JP 2002359392 A JP2002359392 A JP 2002359392A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor relay
- substrate
- present
- mosfets
- relay according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)
- Electronic Switches (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、光結合によるアイ
ソレーションを用いた半導体リレーに関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor relay using isolation by optical coupling.
【０００２】[0002]
【従来の技術】従来より、電気的アイソレーションに優
れた光結合型の半導体リレーが、種々提案され、また種
々の用途に採用されている。2. Description of the Related Art Hitherto, various optically coupled semiconductor relays having excellent electrical isolation have been proposed and employed for various applications.
【０００３】図９は、従来例に係る半導体リレーの回路
図である。図１０は、従来例に係る半導体リレーの全体
構成を示す概略断面図である。受光素子である光起電力
素子３とスイッチ素子であるＭＯＳＦＥＴ４とが銀ペー
スト等でリードフレーム２５ａ上にダイボンディングさ
れ、更にワイヤボンディングされている。ここで、光起
電力素子３とは、図９における、フォトダイオードアレ
イ２２、駆動用のＭＯＳＦＥＴ２３及び抵抗Ｒが１チッ
プ化された素子のことである。FIG. 9 is a circuit diagram of a conventional semiconductor relay. FIG. 10 is a schematic sectional view showing the entire configuration of a semiconductor relay according to a conventional example. A photovoltaic element 3 as a light receiving element and a MOSFET 4 as a switching element are die-bonded on a lead frame 25a with silver paste or the like, and further wire-bonded. Here, the photovoltaic element 3 is an element in which the photodiode array 22, the driving MOSFET 23, and the resistor R are integrated into one chip in FIG.
【０００４】一方、発光素子である発光ダイオード（Ｌ
ＥＤ:Light Emitting Diode）２が銀ペースト等でリー
ドフレーム２５ｂ上に、ダイボンディングされ、更にワ
イヤボンディングされており、リードフレーム２５ａ，
２５ｂをＬＥＤ２と光起電力素子３とが対向するように
配置されている。On the other hand, a light emitting diode (L
An ED (Light Emitting Diode) 2 is die-bonded to the lead frame 25b with a silver paste or the like, and is further wire-bonded to the lead frame 25a.
25b is arranged so that the LED 2 and the photovoltaic element 3 face each other.
【０００５】そして、ＬＥＤ２と光起電力素子３との間
には、光を透過するカップリング樹脂９が充填され、全
体を封止樹脂１０から成るパッケージによりモールドさ
れている。この時、パッケージからは、リードフレーム
２５ａ，２５ｂの一端が突出する構成となっている。[0005] The space between the LED 2 and the photovoltaic element 3 is filled with a coupling resin 9 that transmits light, and the whole is molded by a package made of a sealing resin 10. At this time, one ends of the lead frames 25a and 25b protrude from the package.
【０００６】また、ＭＯＳＦＥＴを１チップのみ実装す
ると、ＭＯＳＦＥＴのダイオード特性により直流用のみ
にしか使用できないが、図１０に示すように２個のＭＯ
ＳＦＥＴ４a、４bを実装すると、直流・交流の両方に使
用可能となる。Further, if only one MOSFET is mounted, it can be used only for direct current due to the diode characteristics of the MOSFET. However, as shown in FIG.
When the SFETs 4a and 4b are mounted, they can be used for both DC and AC.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、図１０
に示すような構造では、ＭＯＳＦＥＴの裏面電極はリー
ドフレームに搭載され、そのリードフレームがパッケー
ジ外部に出て、折り曲げられて基板に搭載されることに
なる。また、ＭＯＳＦＥＴ間はリードフレームにそれぞ
れワイヤボンディングする。その為、一方のＭＯＳＦＥ
Ｔからもう一方のＭＯＳＦＥＴへ高周波の電流が流れる
時に、リードフレームの長さや、折曲げ部の影響でイン
ピーダンス不整合が起こり、立ち上がり特性が劣化す
る。また、金属ワイヤのＬ成分によりインピーダンスが
高くなり電流が流れにくくなるという問題を生じてい
た。However, FIG.
In the structure as shown in (1), the back electrode of the MOSFET is mounted on a lead frame, and the lead frame comes out of the package, is bent, and is mounted on the substrate. Wire bonding is performed between the MOSFETs on the lead frame. Therefore, one MOSFE
When a high-frequency current flows from T to the other MOSFET, impedance mismatch occurs due to the length of the lead frame and the bent portion, and the rising characteristics deteriorate. In addition, there has been a problem that the impedance is increased due to the L component of the metal wire, making it difficult for a current to flow.
【０００８】本発明は、かかる事由に鑑み、なされたも
ので、本発明の目的は、上記したような高周波特性の改
善と同時に、一層の小型化及び製造工程の合理化が可能
な半導体リレーを提供することにある。The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor relay capable of improving the high-frequency characteristics as described above, and further reducing the size and streamlining the manufacturing process. Is to do.
【０００９】[0009]
【課題を解決するための手段】上記課題を解決するため
に、請求項１記載の半導体リレーの発明にあっては、少
なくとも、ＬＥＤと、光起電力素子と、複数のＭＯＳＦ
ＥＴとを備えたＢＧＡ基板を有する半導体リレーであっ
て、前記ＢＧＡ基板の前記ＭＯＳＦＥＴ搭載部の裏面に
ハンダボールを形成した電極を設け、該電極と導通した
埋込スルーホールを介して前記ＭＯＳＦＥＴと前記ハン
ダボールとを電気的に接続したことを特徴とするもので
ある。According to a first aspect of the present invention, at least an LED, a photovoltaic element, and a plurality of MOSFs are provided.
A semiconductor relay having a BGA substrate provided with an ET, provided with an electrode on which a solder ball is formed on the back surface of the MOSFET mounting portion of the BGA substrate, and connected to the MOSFET through a buried through hole electrically connected to the electrode. The solder balls are electrically connected to each other.
【００１０】請求項２記載の半導体リレーの発明にあっ
ては、請求項１記載の半導体リレーにおいて、前記ＭＯ
ＳＦＥＴの電極上に、金属突起を形成し、前記複数のＭ
ＯＳＦＥＴ相互間の接続、導通を該金属突起を介して、
これらに接続したフリップチップ基板により達成される
ことを特徴とするものである。According to a second aspect of the present invention, there is provided a semiconductor relay according to the first aspect, wherein the MO
A metal projection is formed on the electrode of the SFET, and the plurality of M
The connection and conduction between the OSFETs are performed through the metal protrusions.
This is achieved by a flip chip substrate connected thereto.
【００１１】請求項３記載の半導体リレーの発明にあっ
ては、請求項２記載の半導体リレーにおいて、少なくと
も、前記ＬＥＤと、前記光起電力素子とを前記フリップ
チップ基板に電気的に接続したことを特徴とするもので
ある。According to a third aspect of the present invention, in the semiconductor relay according to the second aspect, at least the LED and the photovoltaic element are electrically connected to the flip-chip substrate. It is characterized by the following.
【００１２】請求項４記載の半導体リレーの発明にあっ
ては、請求項２記載の半導体リレーにおいて、前記ＬＥ
Ｄを前記ＢＧＡ基板に形成された凹部に埋没するように
実装すると共に、前記光起電力素子を、該ＬＥＤに正対
せしめ、且つ、前記フリップチップ基板に電気的に接続
したことを特徴とするものである。According to a fourth aspect of the present invention, there is provided the semiconductor relay according to the second aspect, wherein the LE
D is mounted so as to be buried in a recess formed in the BGA substrate, and the photovoltaic element is directly opposed to the LED and is electrically connected to the flip chip substrate. Things.
【００１３】請求項５記載の半導体リレーの発明にあっ
ては、請求項２乃至請求項４のいずれかに記載の半導体
リレーにおいて、前記フリップチップ基板内にＧＮＤ層
を形成することを特徴とするものである。According to a fifth aspect of the present invention, in the semiconductor relay according to any one of the second to fourth aspects, a GND layer is formed in the flip chip substrate. Things.
【００１４】請求項６記載の半導体リレーの発明にあっ
ては、請求項１記載の半導体リレーにおいて、前記複数
のＭＯＳＦＥＴ相互間の接続、導通が鍍金配線により達
成されることを特徴とするものである。According to a sixth aspect of the present invention, in the semiconductor relay according to the first aspect, connection and conduction between the plurality of MOSFETs are achieved by plating wiring. is there.
【００１５】請求項７記載の半導体リレーの発明にあっ
ては、請求項１乃至請求項６のいずれかに記載の半導体
リレーにおいて、前記ＢＧＡ基板内にＧＮＤ層を形成す
ることを特徴とするものである。According to a seventh aspect of the present invention, in the semiconductor relay according to any one of the first to sixth aspects, a GND layer is formed in the BGA substrate. It is.
【００１６】[0016]
【発明の実施の形態】以下、本発明の実施形態を図面に
基づき説明する。なお、本発明の半導体リレーは、下記
の実施形態にのみ限定されるものではなく、本発明の要
旨を逸脱しない範囲内において種々変更を加え得ること
は勿論である。Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the semiconductor relay of the present invention is not limited to only the following embodiment, and it is needless to say that various changes can be made without departing from the gist of the present invention.
【００１７】[第１の実施形態]図１は本発明の半導体リ
レーの実施形態の要部の基本構成を示すもので、(a)は
上面からの模式図、(b)は(a)におけるＡ1-Ｂ1線に沿っ
て切断した場合の概略を示す断面模式図である。ＢＧＡ
(Ball Grid Array)基板１上にＬＥＤ２と光起電力素子
（受光素子）３と２個のＭＯＳＦＥＴ４が搭載されてお
り、これらの各素子の表面電極（図示せず）とＢＧＡ基
板１とが金属ワイヤ５にて接続されており、更に、ＭＯ
ＳＦＥＴ４のゲート電極（図示せず）と光起電力素子３
とが直接、金属ワイヤ５aにて接続され、ＭＯＳＦＥＴ
４の搭載部のＢＧＡ基板１の真下に埋込スルーホール６
が形成されており、さらに基板裏面部に電極７を介しハ
ンダボール８が形成されている。また、ＬＥＤ２と光起
電力素子３とはカップリング樹脂９により平面カップリ
ングされ、ＢＧＡ基板１上を封止樹脂１０により封止さ
れている。即ち、本実施形態においては、リードフレー
ムを使用せず、ＢＧＡ実装により、母基板(図示せず)に
接続されるため、ＭＯＳＦＥＴ４から外部への電気的接
続を、全体として、短く構成することが可能で、配線の
曲折も低減され、リードフレームを使用しないため、イ
ンピーダンス不整合を大幅に低減することが可能とな
る。[First Embodiment] FIGS. 1A and 1B show a basic configuration of a main part of an embodiment of a semiconductor relay according to the present invention, wherein FIG. 1A is a schematic view from the top, and FIG. FIG. 3 is a schematic cross-sectional view schematically showing a case where the semiconductor device is cut along a line A 1 -B 1 . BGA
(Ball Grid Array) An LED 2, a photovoltaic element (light receiving element) 3 and two MOSFETs 4 are mounted on a substrate 1, and a surface electrode (not shown) of each of these elements and the BGA substrate 1 are made of metal. Connected by wire 5, and
Gate electrode (not shown) of SFET 4 and photovoltaic element 3
Are directly connected by the metal wire 5a, and the MOSFET
Embedded through hole 6 directly below the BGA substrate 1 in the mounting portion 4
Are formed, and solder balls 8 are formed on the back surface of the substrate with electrodes 7 interposed therebetween. The LED 2 and the photovoltaic element 3 are planarly coupled by a coupling resin 9, and the BGA substrate 1 is sealed by a sealing resin 10. That is, in this embodiment, since the lead frame is not used and the mother board (not shown) is connected by BGA mounting, the electrical connection from the MOSFET 4 to the outside can be shortened as a whole. It is possible, the bending of the wiring is reduced, and the impedance mismatch can be greatly reduced because the lead frame is not used.
【００１８】[第２の実施形態]図２は本発明の半導体リ
レーの上記と異なる実施形態の要部の構成を示すもの
で、(a)は上面からの模式図(但し、フリップチップ基板
１２は破線で外郭のみ示し、該フリップチップ基板１２
表面上の回路パターン１４については図示せず。)、(b)
は(a)におけるＡ2-Ｂ2線に沿って切断した場合の概略を
示す断面模式図である。本実施形態においては、２個の
ＭＯＳＦＥＴ４の電極（図示せず）上に金属突起１１を
形成し、フリップチップ基板１２にその金属突起１１を
接続し、２個のＭＯＳＦＥＴ４の間をこのフリップチッ
プ基板１２を通じて接続するというものである。このた
め、例えば、前述の第１の実施形態と比較すると、２個
のＭＯＳＦＥＴ相互間の金属ワイヤ接続を無く、その配
線が太く短くなるため、配線経路中のＬ成分の影響が小
さくすることが可能で、信号の劣化を低減できるという
ものである。[Second Embodiment] FIGS. 2A and 2B show the configuration of a main part of a semiconductor relay according to a second embodiment of the present invention which is different from the above. FIG. 2A is a schematic view from the top (the flip-chip substrate 12). Indicates only the outline by a broken line, and the flip chip substrate 12
The circuit pattern 14 on the surface is not shown. ), (B)
Is a schematic cross-sectional view showing a schematic of a case taken along the A 2 -B 2-wire in (a). In this embodiment, a metal projection 11 is formed on electrodes (not shown) of two MOSFETs 4, the metal projection 11 is connected to a flip-chip substrate 12, and the flip-chip substrate is 12 is connected. For this reason, for example, compared to the first embodiment described above, there is no metal wire connection between the two MOSFETs, and the wiring is thick and short, so that the influence of the L component in the wiring path can be reduced. It is possible, and the deterioration of the signal can be reduced.
【００１９】[第３の実施形態]図３は本発明の半導体リ
レーの更に上記と異なる実施形態の要部の構成を示すも
ので、(a)は上面からの模式図(但し、フリップチップ基
板１２は破線で外郭のみ示し、該フリップチップ基板１
２表面上の回路パターン１４については図示せず。)、
(b)は(a)におけるＡ3-Ｂ3線に沿って切断した場合の概
略を示す断面模式図である。即ち、本実施形態において
は、金属突起１１を介して２個のＭＯＳＦＥＴ４の間の
電気的接続にフリップチップ基板１２を使用するという
第２の実施形態に留まらず、少なくとも、ＬＥＤ２、光
起電力素子３と２個のＭＯＳＦＥＴ４を含んで、ＢＧＡ
基板１上に搭載された全ての素子をフリップチップ基板
１２上にフリップチップ実装するというものである。こ
の結果、本発明に係る半導体リレーの各素子が、ＢＧＡ
基板１及びフリップチップ基板１２上に、金属突起１
１、導電性樹脂１３、回路パターン１４等を介し、原則
として、金属ワイヤ５によることなく、電気的に接続さ
れることとなる。このため、ワイヤボンド工程が原則と
して、不要となり、工程短縮と製造コスト低減に寄与し
得るというものである。[Third Embodiment] FIGS. 3A and 3B show the configuration of a main part of a semiconductor relay according to a third embodiment of the present invention which is different from the above. FIG. Numeral 12 indicates only the outline by a broken line, and the flip chip substrate 1
The circuit pattern 14 on the second surface is not shown. ),
(b) is a schematic cross-sectional view showing an outline when cut along the line A 3 -B 3 in (a). That is, in the present embodiment, not only the second embodiment in which the flip-chip substrate 12 is used for the electrical connection between the two MOSFETs 4 via the metal protrusions 11, but also at least the LED 2 and the photovoltaic element BGA including 3 and 2 MOSFETs 4
All the elements mounted on the substrate 1 are flip-chip mounted on the flip-chip substrate 12. As a result, each element of the semiconductor relay according to the present invention is
The metal projection 1 is provided on the substrate 1 and the flip chip substrate 12.
1, through the conductive resin 13, the circuit pattern 14, and the like, they are electrically connected in principle without using the metal wires 5. For this reason, a wire bonding step is not required in principle, which can contribute to shortening of the step and reduction of manufacturing cost.
【００２０】[第４の実施形態]図４は本発明の半導体リ
レーの第４の実施形態の要部の構成を示すもので、(a)
は上面からの模式図(但し、フリップチップ基板１２は
破線で外郭のみ示し、該フリップチップ基板１２表面上
の回路パターン１４については図示せず。)、(b)は(a)
におけるＡ4-Ｂ4線に沿って切断した場合の概略を示す
断面模式図である。本実施形態においては、ＭＩＤ(Mol
ded Interconnection Device) の製造技術を応用して、
ＢＧＡ基板１[即ち、本実施形態においては、底面にハ
ンダボール８を有するＭＩＤ基板１５]にＬＥＤ２を埋
没するように実装する凹部１６aを形成し、ＬＥＤ２を
光起電力素子３と正対するように前記凹部１６aの底面
に搭載すると共に、さらに光起電力素子３をフリップチ
ップ基板１２上にフリップチップ実装することにより構
成するものである。即ち、本実施形態においては、ＬＥ
Ｄ２と光起電力素子３が正対する構成を有するので、両
者間の光伝達効率が良好となるため、消費電力の低減
や、ＬＥＤ２と光起電力素子３のサイズの小型化が可能
となり、延いては、半導体リレーの小型化に寄与し得る
というものである。[Fourth Embodiment] FIG. 4 shows a configuration of a main part of a fourth embodiment of a semiconductor relay according to the present invention.
Is a schematic view from the top (however, the flip chip substrate 12 is indicated only by the dashed outline and the circuit pattern 14 on the surface of the flip chip substrate 12 is not shown), and (b) is (a)
FIG. 4 is a schematic cross-sectional view schematically showing a case of cutting along the line A 4 -B 4 in FIG. In the present embodiment, the MID (Mol
ded Interconnection Device) manufacturing technology,
In the BGA substrate 1 [that is, in the present embodiment, the MID substrate 15 having the solder balls 8 on the bottom surface], a concave portion 16a for mounting the LED 2 so as to be buried is formed, and the LED 2 is directly opposed to the photovoltaic element 3. The photovoltaic element 3 is mounted on the bottom surface of the concave portion 16a, and is further mounted on the flip chip substrate 12 by flip chip mounting. That is, in the present embodiment, LE
Since D2 and the photovoltaic element 3 have a configuration facing each other, the light transmission efficiency between them becomes good, so that the power consumption can be reduced and the size of the LED 2 and the photovoltaic element 3 can be reduced. In other words, it can contribute to downsizing of the semiconductor relay.
【００２１】[第５の実施形態]図５は本発明の半導体リ
レーの第５の実施形態の要部の構成を示すもので、(a)
は上面からの模式図(但し、フリップチップ基板１２は
破線で外郭のみ示し、該フリップチップ基板１２表面上
の回路パターン１４については図示せず。)、(b)は(a)
におけるＡ5-Ｂ5線に沿って切断した場合の概略を示す
断面模式図である。本実施形態においては、ＢＧＡ基板
１を基板を積層することにより作成し、該積層基板１７
の上部の一部を刳り貫き、ＢＧＡ基板１にＬＥＤ２を埋
没するように実装する凹部１６bを形成し、ＬＥＤ２を
光起電力素子３と正対するように前記凹部１６bの底面
に搭載すると共に、さらに光起電力素子３をフリップチ
ップ基板１２上にフリップチップ実装することにより構
成するものである。即ち、本実施形態においては、第４
の実施形態と同様に、ＬＥＤ２と光起電力素子３が正対
する構成を有するので、両者間の光伝達効率が良好とな
るため、消費電力の低減や、ＬＥＤ２と光起電力素子３
の小型化が可能となり、延いては、半導体リレーの小型
化に寄与し得るというものである。これに加えて、本実
施形態では、例えば、上記第４の実施形態と比較して、
ＭＯＳＦＥＴ４の裏面からの配線長を一層短く構成する
ことが可能であり、配線の曲折も低減され、インピーダ
ンス不整合を更に、低減することができるというもので
ある。[Fifth Embodiment] FIG. 5 shows a configuration of a main part of a fifth embodiment of the semiconductor relay according to the present invention.
Is a schematic view from the top (however, the flip chip substrate 12 is indicated only by the dashed outline and the circuit pattern 14 on the surface of the flip chip substrate 12 is not shown), and (b) is (a)
FIG. 3 is a schematic cross-sectional view schematically showing a case of cutting along line A 5 -B 5 in FIG. In the present embodiment, the BGA substrate 1 is formed by laminating the substrates,
A part of the upper part is hollowed out, a recess 16b is formed in the BGA substrate 1 for mounting the LED 2 so as to be buried, and the LED 2 is mounted on the bottom of the recess 16b so as to face the photovoltaic element 3, and The photovoltaic element 3 is formed by flip-chip mounting on a flip-chip substrate 12. That is, in the present embodiment, the fourth
Similarly to the embodiment, the LED 2 and the photovoltaic element 3 have a configuration facing each other, so that the light transmission efficiency between the two is improved.
It is possible to reduce the size of the semiconductor relay, which can contribute to the miniaturization of the semiconductor relay. In addition to this, in the present embodiment, for example, compared to the fourth embodiment,
The wiring length from the back surface of the MOSFET 4 can be further reduced, the bending of the wiring can be reduced, and the impedance mismatch can be further reduced.
【００２２】[第６の実施形態]図６は本発明の半導体リ
レーの第６の実施形態の要部の実施形態の要部の構成を
示すもので、(a)は上面からの模式図(但し、フリップチ
ップ基板１２は破線で外郭のみ示し、該フリップチップ
基板１２表面上の回路パターン１４については図示せ
ず。)、(b)は(a)におけるＡ6-Ｂ6線に沿って切断した場
合の概略を示す断面模式図である。本実施形態における
半導体リレーは、上記第３の実施形態におけるフリップ
チップ基板１２内にＧＮＤ層１８を有する構成を特徴と
するものである。このことにより、本実施形態における
半導体リレーは、第３の実施形態で述べた効果に加え
て、ＭＯＳＦＥＴ４間の配線に対し、パッケージ下部か
らシールドが可能となるため、半導体リレーを母基板に
実装後、母基板の回路上の信号からの影響を低減できる
というものである。いうまでもなく、フリップチップ基
板内にＧＮＤ層を有する構成は上記第３の実施形態にの
み留まるものではなく、フリップチップ基板を有する本
発明の半導体リレーに適用可能であり、上記課題解決に
寄与する限りにおいて、何ら制約はない。[Sixth Embodiment] FIGS. 6A and 6B show a configuration of a main part of a semiconductor relay according to a sixth embodiment of the present invention. FIG. However, the flip chip substrate 12 is indicated only by the outline by a broken line, and the circuit pattern 14 on the surface of the flip chip substrate 12 is not shown.), (B) is cut along the line A 6 -B 6 in (a). It is a cross section which shows the outline in the case of having done. The semiconductor relay according to the present embodiment is characterized in that the GND layer 18 is provided in the flip chip substrate 12 according to the third embodiment. Thus, in addition to the effects described in the third embodiment, the semiconductor relay according to the present embodiment can shield the wiring between the MOSFETs 4 from the lower part of the package. That is, the influence from signals on the circuit of the motherboard can be reduced. Needless to say, the configuration having the GND layer in the flip-chip substrate is not limited to the above-described third embodiment, but can be applied to the semiconductor relay of the present invention having the flip-chip substrate, contributing to solving the above-mentioned problems. There are no restrictions as long as you do.
【００２３】[第７の実施形態]図７は、本発明の半導体
リレー半導体リレーの第７の実施形態の要部の上記と異
なる実施形態の要部の構成を示すもので、(a)は上面か
らの模式図、(b)は(a)におけるＡ7-Ｂ7線に沿って切断
した場合の概略を示す断面模式図である。本実施形態に
おいては、２つのＭＯＳＦＥＴ４をＢＧＡ基板１に搭載
した後、ＭＯＳＦＥＴ４上の電極（図示せず）以外をマ
スクしてこの２個のＭＯＳＦＥＴ４の電極相互間を鍍金
配線し、この鍍金配線部１９により、この２個のＭＯＳ
ＦＥＴ４間の接続、導通を達成するというものである。
このため、例えば、前述の第１の実施形態と比較する
と、上述の第２の実施形態と同様に、２個のＭＯＳＦＥ
Ｔ相互間の金属ワイヤ接続が無く、その部分の配線を相
対的に太く短く構成することが可能で、配線経路中のＬ
成分の影響が小さくすることができ、信号の劣化を低減
できるというものである。更に、本実施形態において
は、これに加えて、例えば、上述の第２の実施形態と比
較すると、フリップチップ用基板が不要であり、突起電
極の形成、フリップチップ実装工程等も不要となり、工
程の短縮と製造コストの低減に寄与し得るというもので
ある。[Seventh Embodiment] FIG. 7 shows a configuration of a main part of a semiconductor relay according to a seventh embodiment of the present invention which is different from the main part of the seventh embodiment of the present invention. FIG. 3B is a schematic view from the top, and FIG. 4B is a schematic cross-sectional view schematically illustrating a section taken along line A 7 -B 7 in FIG. In this embodiment, after the two MOSFETs 4 are mounted on the BGA substrate 1, the electrodes other than the electrodes (not shown) on the MOSFETs 4 are masked, and the electrodes of the two MOSFETs 4 are plated and wired. 19, the two MOSs
The connection and conduction between the FETs 4 are achieved.
For this reason, for example, as compared with the first embodiment, two MOSFEs are provided similarly to the second embodiment.
Since there is no metal wire connection between T, the wiring at that portion can be made relatively thick and short, and the L
The effect of the component can be reduced, and the deterioration of the signal can be reduced. Furthermore, in this embodiment, in addition to this, for example, as compared with the above-described second embodiment, the flip-chip substrate is not required, and the formation of the protruding electrodes, the flip-chip mounting step, and the like are also unnecessary. This can contribute to shortening of manufacturing cost and manufacturing cost.
【００２４】[第８の実施形態]図８は本発明の半導体リ
レーの第８の実施形態の要部の実施形態の要部の構成を
示すもので、(a)は上面からの模式図、(b)は(a)におけ
るＡ8-Ｂ8線に沿って切断した場合の概略を示す断面模
式図である。本実施形態における半導体リレーは、上記
第１の実施形態におけるＢＧＡ基板１内にＧＮＤ層２０
を有する構成を特徴とするものである。このことによ
り、本実施形態における半導体リレーは、第３の実施形
態で述べた効果に加えて、ＭＯＳＦＥＴ間の配線に対
し、パッケージ下部からシールドが可能となるため、半
導体リレーを母基板に実装後、母基板の回路上の信号か
らの影響を低減できるというものである。いうまでもな
く、ＢＧＡ基板内にＧＮＤ層を有する構成は上記第３の
実施形態にのみ留まるものではなく、ＢＧＡ基板を有す
る本発明の半導体リレーに適用可能であり、上記課題解
決に寄与する限りにおいて、何ら制約はない。[Eighth Embodiment] FIGS. 8A and 8B show a configuration of a main part of an embodiment of a semiconductor relay according to an eighth embodiment of the present invention. FIG. (b) is a schematic sectional view showing an outline of the case taken along the a 8 -B 8 line in (a). The semiconductor relay according to the present embodiment includes the GND layer 20 in the BGA substrate 1 according to the first embodiment.
Is characterized by having the following configuration. Thus, in addition to the effects described in the third embodiment, the semiconductor relay according to the present embodiment can shield the wiring between MOSFETs from the lower part of the package. That is, the influence from signals on the circuit of the motherboard can be reduced. Needless to say, the configuration having the GND layer in the BGA substrate is not limited to the above-described third embodiment, and can be applied to the semiconductor relay of the present invention having the BGA substrate, as long as it contributes to solving the above problem. In, there is no restriction.
【００２５】[0025]
【発明の効果】以上のように、請求項１記載の半導体リ
レーの発明にあっては、少なくとも、ＬＥＤと、光起電
力素子と、複数のＭＯＳＦＥＴとを備えたＢＧＡ基板を
有する半導体リレーであって、前記ＢＧＡ基板の前記Ｍ
ＯＳＦＥＴ搭載部の裏面にハンダボールを形成した電極
を設け、該電極と導通した埋込スルーホールを介して前
記ＭＯＳＦＥＴと前記ハンダボールとを電気的に接続し
たことを特徴とし、リードフレームを使用せず、ＢＧＡ
実装により、母基板(図示せず)に接続されるため、ＭＯ
ＳＦＥＴ４から外部への電気的接続を、全体として、短
く構成することが可能で、配線の曲折も低減され、リー
ドフレームを使用しないため、インピーダンス不整合を
大幅に低減できるという優れた効果を奏し得る。As described above, the semiconductor relay according to the first aspect of the present invention is a semiconductor relay having a BGA substrate including at least an LED, a photovoltaic element, and a plurality of MOSFETs. And the M of the BGA substrate
An electrode on which a solder ball is formed is provided on the back surface of the OSFET mounting portion, and the MOSFET and the solder ball are electrically connected through a buried through hole that is electrically connected to the electrode. , BGA
Since it is connected to the mother board (not shown) by mounting,
The overall electrical connection from the SFET 4 to the outside can be shortened as a whole, wiring bends are reduced, and a lead frame is not used, so that an excellent effect of greatly reducing impedance mismatch can be achieved. .
【００２６】請求項２記載の半導体リレーの発明にあっ
ては、請求項１記載の半導体リレーにおいて、前記ＭＯ
ＳＦＥＴの電極上に、金属突起を形成し、前記複数のＭ
ＯＳＦＥＴ相互間の接続、導通を該金属突起を介して、
これらに接続したフリップチップ基板により達成される
ことを特徴とするので、請求項１記載の半導体リレーの
発明の効果に加えて、複数のＭＯＳＦＥＴ相互間の金属
ワイヤ接続が不要となり、また、その複数のＭＯＳＦＥ
Ｔ相互間の配線を太く短くすることができるため、配線
経路中のＬ成分の影響が小さくすることが可能で、信号
の劣化を低減できるという優れた効果を奏し得る。According to a second aspect of the present invention, there is provided a semiconductor relay according to the first aspect, wherein the MO
A metal projection is formed on the electrode of the SFET, and the plurality of M
The connection and conduction between the OSFETs are performed through the metal protrusions.
Since the present invention is achieved by a flip-chip substrate connected to these, in addition to the effect of the invention of the semiconductor relay according to claim 1, metal wire connection between a plurality of MOSFETs is not required. MOSFE
Since the wiring between T can be made thicker and shorter, the effect of the L component in the wiring path can be reduced, and an excellent effect of reducing signal degradation can be obtained.
【００２７】請求項３記載の半導体リレーの発明にあっ
ては、請求項２記載の半導体リレーにおいて、少なくと
も、前記ＬＥＤと、前記光起電力素子とを前記フリップ
チップ基板に電気的に接続したことを特徴とするので、
請求項２記載の半導体リレーの発明の効果に加えて、ワ
イヤボンド工程が不要となり、工程短縮と製造コスト低
減に寄与し得るという優れた効果を奏し得る。According to a third aspect of the present invention, in the semiconductor relay according to the second aspect, at least the LED and the photovoltaic element are electrically connected to the flip chip substrate. Because it is characterized by
In addition to the effect of the invention of the semiconductor relay according to the second aspect, an excellent effect that a wire bonding step is not required can be achieved, which can contribute to shortening of the step and reduction of manufacturing cost.
【００２８】請求項４記載の半導体リレーの発明にあっ
ては、請求項２記載の半導体リレーにおいて、前記ＬＥ
Ｄを前記ＢＧＡ基板に形成された凹部に埋没するように
実装すると共に、前記光起電力素子を、該ＬＥＤに正対
せしめ、且つ、前記フリップチップ基板に電気的に接続
したことを特徴とするので、請求項２記載の半導体リレ
ーの発明の効果に加えて、ＬＥＤと光起電力素子の間の
光伝達効率が良好となり、消費電力の低減や、ＬＥＤと
光起電力素子のサイズの小型化が可能となるため、半導
体リレーの小型化にも寄与し得るという優れた効果を奏
する。According to a fourth aspect of the present invention, there is provided the semiconductor relay according to the second aspect, wherein the LE
D is mounted so as to be buried in a recess formed in the BGA substrate, and the photovoltaic element is directly opposed to the LED and is electrically connected to the flip chip substrate. Therefore, in addition to the effect of the invention of the semiconductor relay according to the second aspect, the light transmission efficiency between the LED and the photovoltaic element is improved, the power consumption is reduced, and the size of the LED and the photovoltaic element is reduced. Therefore, an excellent effect of being able to contribute to miniaturization of the semiconductor relay is achieved.
【００２９】請求項５記載の半導体リレーの発明にあっ
ては、請求項２乃至請求項４のいずれかに記載の半導体
リレーにおいて、前記フリップチップ基板内にＧＮＤ層
を形成することを特徴とするので、請求項２乃至請求項
４のいずれかに記載の半導体リレーの発明の効果に加え
て、ＭＯＳＦＥＴ間の配線に対し、パッケージ下部から
シールドが可能となるため、半導体リレーを母基板に実
装後、母基板の回路上の信号からの影響を低減できると
いう優れた効果を奏し得る。According to a fifth aspect of the present invention, in the semiconductor relay according to any one of the second to fourth aspects, a GND layer is formed in the flip chip substrate. Therefore, in addition to the effect of the invention of the semiconductor relay according to any one of claims 2 to 4, the wiring between the MOSFETs can be shielded from the lower part of the package. Thus, an excellent effect that the influence from the signal on the circuit of the motherboard can be reduced can be obtained.
【００３０】請求項６記載の半導体リレーの発明にあっ
ては、請求項１記載の半導体リレーにおいて、前記複数
のＭＯＳＦＥＴ相互間の接続、導通が鍍金配線により達
成されることを特徴とするので、請求項１記載の半導体
リレーの発明の効果に加えて、複数のＭＯＳＦＥＴ相互
間の金属ワイヤ接続が不要となり、また、その複数のＭ
ＯＳＦＥＴ相互間の配線を太く短くすることができるた
め、配線経路中のＬ成分の影響が小さくすることが可能
で、信号の劣化を低減でき、更に、これに加えて、工程
の短縮と製造コストの低減に寄与し得るという優れた効
果を奏し得る。According to a sixth aspect of the present invention, in the semiconductor relay according to the first aspect, connection and conduction between the plurality of MOSFETs are achieved by plating wiring. In addition to the effect of the invention of the semiconductor relay according to claim 1, metal wire connection between a plurality of MOSFETs becomes unnecessary, and the plurality of M
Since the wiring between the OSFETs can be made thicker and shorter, the influence of the L component in the wiring path can be reduced, signal deterioration can be reduced, and further, the process can be shortened and the manufacturing cost can be reduced. An excellent effect of contributing to the reduction of the size can be obtained.
【００３１】請求項７記載の半導体リレーの発明にあっ
ては、請求項１乃至請求項６のいずれかに記載の半導体
リレーにおいて、前記ＢＧＡ基板内にＧＮＤ層を形成す
ることを特徴とするので、請求項２乃至請求項４のいず
れかに記載の半導体リレーの発明の効果に加えて、ＭＯ
ＳＦＥＴ間の配線に対し、パッケージ下部からシールド
が可能となるため、半導体リレーを母基板に実装後、母
基板の回路上の信号からの影響を低減できるという優れ
た効果を奏し得る。According to a seventh aspect of the present invention, in the semiconductor relay according to any one of the first to sixth aspects, a GND layer is formed in the BGA substrate. In addition to the effects of the invention of the semiconductor relay according to any one of claims 2 to 4,
Since the wiring between the SFETs can be shielded from the lower part of the package, an excellent effect of reducing the influence of signals on the circuit of the mother board after mounting the semiconductor relay on the mother board can be obtained.
【図１】本発明の半導体リレーの実施形態の要部の基本
構成を示すもので、(a)は上面からの模式図、(b)は(a)
におけるＡ1-Ｂ1線に沿って切断した場合の概略を示す
断面模式図である。FIG. 1 shows a basic configuration of a main part of an embodiment of a semiconductor relay of the present invention, wherein (a) is a schematic view from the top, and (b) is (a).
FIG. 2 is a schematic cross-sectional view schematically showing a case of cutting along the line A 1 -B 1 in FIG.
【図２】本発明の半導体リレーの上記と異なる実施形態
の要部の基本構成を示すもので、(a)は上面からの模式
図、(b)は(a)におけるＡ2-Ｂ2線に沿って切断した場合
の概略を示す断面模式図である。FIGS. 2A and 2B show a basic configuration of a main part of an embodiment different from the above of the semiconductor relay of the present invention, wherein FIG. 2A is a schematic view from the top, and FIG. 2B is a line A 2 -B 2 in FIG. FIG. 3 is a schematic cross-sectional view schematically illustrating a case where the semiconductor device is cut along the line A.
【図３】本発明の半導体リレーの更に上記と異なる実施
形態の要部の基本構成を示すもので、(a)は上面からの
模式図、(b)は(a)におけるＡ3-Ｂ3線に沿って切断した
場合の概略を示す断面模式図である。3A and 3B show a basic configuration of a main part of a semiconductor relay according to another embodiment of the present invention, in which FIG. 3A is a schematic view from the top, and FIG. 3B is a schematic view of A 3 -B 3 in FIG. FIG. 3 is a schematic cross-sectional view schematically illustrating a case where the semiconductor device is cut along a line.
【図４】本発明の半導体リレーの第４の実施形態の要部
の基本構成を示すもので、(a)は上面からの模式図、(b)
は(a)におけるＡ4-Ｂ4線に沿って切断した場合の概略を
示す断面模式図である。4A and 4B show a basic configuration of a main part of a semiconductor relay according to a fourth embodiment of the present invention, wherein FIG. 4A is a schematic view from the top, and FIG.
FIG. 3 is a schematic cross-sectional view schematically showing a case of cutting along the line A 4 -B 4 in FIG.
【図５】本発明の半導体リレーの第５の実施形態の要部
の基本構成を示すもので、(a)は上面からの模式図、(b)
は(a)におけるＡ5-Ｂ5線に沿って切断した場合の概略を
示す断面模式図である。5A and 5B show a basic configuration of a main part of a semiconductor relay according to a fifth embodiment of the present invention, wherein FIG. 5A is a schematic view from the top, and FIG.
FIG. 2 is a schematic cross-sectional view schematically showing a case where the semiconductor device is cut along line A 5 -B 5 in FIG.
【図６】本発明の半導体リレーの第６の実施形態の要部
の基本構成を示すもので、(a)は上面からの模式図、(b)
は(a)におけるＡ6-Ｂ6線に沿って切断した場合の概略を
示す断面模式図である。6A and 6B show a basic configuration of a main part of a semiconductor relay according to a sixth embodiment of the present invention, wherein FIG. 6A is a schematic view from the top, and FIG.
Is a schematic cross-sectional view showing a schematic of a case taken along the A 6 -B 6 lines in (a).
【図７】本発明の半導体リレーの第７の実施形態の要部
の基本構成を示すもので、(a)は上面からの模式図、(b)
は(a)におけるＡ7-Ｂ7線に沿って切断した場合の概略を
示す断面模式図である。7A and 7B show a basic configuration of a main part of a semiconductor relay according to a seventh embodiment of the present invention, wherein FIG. 7A is a schematic view from the top, and FIG.
FIG. 2 is a schematic cross-sectional view schematically showing a case of cutting along line A 7 -B 7 in FIG.
【図８】本発明の半導体リレーの第８の実施形態の要部
の基本構成を示すもので、(a)は上面からの模式図、(b)
は(a)におけるＡ8-Ｂ8線に沿って切断した場合の概略を
示す断面模式図である。8A and 8B show a basic configuration of a main part of an eighth embodiment of the semiconductor relay of the present invention, wherein FIG. 8A is a schematic view from above, and FIG.
FIG. 4 is a schematic cross-sectional view schematically showing a case of cutting along line A 8 -B 8 in FIG.
【図９】従来例に係る半導体リレーの回路図である。FIG. 9 is a circuit diagram of a semiconductor relay according to a conventional example.
【図１０】従来例に係る半導体リレーの全体構成を示す
概略断面図である。FIG. 10 is a schematic sectional view showing the entire configuration of a semiconductor relay according to a conventional example.
１ ＢＧＡ基板 ２ ＬＥＤ ３ 光起電力素子（受光素子） ４ ＭＯＳＦＥＴ ５ 金属ワイヤ ６ 埋込スルーホール ７ 電極 ８ ハンダボール ９ カップリング樹脂 １０ 封止樹脂 １１ 金属突起 １２ フリップチップ基板 １３ 導電性樹脂 １４ 回路パターン １５ ＭＩＤ基板 １６ 凹部 １７ 積層基板 １８ ＧＮＤ層 １９ 鍍金配線部 ２０ ＧＮＤ層 ２１ リレー入力端子 ２２ フォトダイオードアレイ ２３ 駆動用ＭＯＳＦＥＴ ２４ リレー出力端子 ２５ リードフレーム DESCRIPTION OF SYMBOLS 1 BGA board 2 LED 3 Photovoltaic element (light receiving element) 4 MOSFET 5 Metal wire 6 Embedded through hole 7 Electrode 8 Solder ball 9 Coupling resin 10 Sealing resin 11 Metal projection 12 Flip chip substrate 13 Conductive resin 14 Circuit Pattern 15 MID substrate 16 Depression 17 Laminated substrate 18 GND layer 19 Plating wiring section 20 GND layer 21 Relay input terminal 22 Photodiode array 23 Driving MOSFET 24 Relay output terminal 25 Lead frame
───────────────────────────────────────────────────── フロントページの続き (72)発明者 角 貞幸 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 高見 茂成 大阪府門真市大字門真1048番地松下電工株 式会社内 Ｆターム(参考） 5F089 AA06 AB01 AB03 AC02 AC09 AC15 CA20 EA04 EA10 5J050 AA37 AA47 AA49 BB21 DD01 DD03 DD08 EE17 FF02 FF10 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Sadayuki Kado, Matsushita Electric Works Co., Ltd., 1048, Kazumasa, Kadoma, Osaka Prefecture (72) Inventor Shigenari Takami 1048, Kazuma, Kazumasa, Kadoma, Osaka, Japan Matsushita Electric Works, Ltd. F term (reference) 5F089 AA06 AB01 AB03 AC02 AC09 AC15 CA20 EA04 EA10 5J050 AA37 AA47 AA49 BB21 DD01 DD03 DD08 EE17 FF02 FF10
Claims (7)
と、複数のＭＯＳＦＥＴとを備えたＢＧＡ基板を有する
半導体リレーであって、前記ＢＧＡ基板の前記ＭＯＳＦ
ＥＴ搭載部の裏面にハンダボールを形成した電極を設
け、該電極と導通した埋込スルーホールを介して前記Ｍ
ＯＳＦＥＴと前記ハンダボールとを電気的に接続したこ
とを特徴とする半導体リレー。1. A semiconductor relay having a BGA substrate having at least an LED, a photovoltaic element, and a plurality of MOSFETs, wherein the MOSF of the BGA substrate is provided.
An electrode on which a solder ball is formed is provided on the back surface of the ET mounting portion, and the M
A semiconductor relay, wherein an OSFET and the solder ball are electrically connected.
を形成し、前記複数のＭＯＳＦＥＴ相互間の接続、導通
を該金属突起を介して、これらに接続したフリップチッ
プ基板により達成されることを特徴とする請求項１記載
の半導体リレー。2. The method according to claim 1, wherein a metal projection is formed on an electrode of the MOSFET, and connection and conduction between the plurality of MOSFETs are achieved by a flip chip substrate connected to the MOSFET via the metal projection. The semiconductor relay according to claim 1.
力素子とを前記フリップチップ基板に電気的に接続した
ことを特徴とする請求項２記載の半導体リレー。3. The semiconductor relay according to claim 2, wherein at least the LED and the photovoltaic element are electrically connected to the flip-chip substrate.
た凹部に埋没するように実装すると共に、前記光起電力
素子を、該ＬＥＤに正対せしめ、且つ、前記フリップチ
ップ基板に電気的に接続したことを特徴とする請求項２
記載の半導体リレー。4. The LED is mounted so as to be buried in a recess formed in the BGA substrate, and the photovoltaic element is directly opposed to the LED and is electrically connected to the flip chip substrate. 3. The method according to claim 2, wherein
Semiconductor relay as described.
形成することを特徴とする請求項２乃至請求項４のいず
れかに記載の半導体リレー。5. The semiconductor relay according to claim 2, wherein a GND layer is formed in the flip chip substrate.
導通が鍍金配線により達成されることを特徴とする請求
項１記載の半導体リレー。6. A connection between the plurality of MOSFETs.
The semiconductor relay according to claim 1, wherein the conduction is achieved by plating wiring.
ことを特徴とする請求項１乃至請求項６のいずれかに記
載の半導体リレー。7. The semiconductor relay according to claim 1, wherein a GND layer is formed in the BGA substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001164062A JP2002359392A (en) | 2001-05-31 | 2001-05-31 | Semiconductor relay |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001164062A JP2002359392A (en) | 2001-05-31 | 2001-05-31 | Semiconductor relay |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002359392A true JP2002359392A (en) | 2002-12-13 |
Family
ID=19006929
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001164062A Pending JP2002359392A (en) | 2001-05-31 | 2001-05-31 | Semiconductor relay |
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| Country | Link |
|---|---|
| JP (1) | JP2002359392A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2016195276A (en) * | 2016-07-22 | 2016-11-17 | 株式会社東芝 | Semiconductor device |
| JP2016219823A (en) * | 2016-07-22 | 2016-12-22 | 株式会社東芝 | Semiconductor device |
| JP2017033961A (en) * | 2015-07-28 | 2017-02-09 | 株式会社東芝 | Optical coupling device |
| WO2020218175A1 (en) * | 2019-04-26 | 2020-10-29 | ローム株式会社 | Semiconductor light emitting device |
| US11367715B2 (en) | 2019-12-04 | 2022-06-21 | Kabushiki Kaisha Toshiba | Photorelay |
-
2001
- 2001-05-31 JP JP2001164062A patent/JP2002359392A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017033961A (en) * | 2015-07-28 | 2017-02-09 | 株式会社東芝 | Optical coupling device |
| JP2016195276A (en) * | 2016-07-22 | 2016-11-17 | 株式会社東芝 | Semiconductor device |
| JP2016219823A (en) * | 2016-07-22 | 2016-12-22 | 株式会社東芝 | Semiconductor device |
| WO2020218175A1 (en) * | 2019-04-26 | 2020-10-29 | ローム株式会社 | Semiconductor light emitting device |
| JP7407177B2 (en) | 2019-04-26 | 2023-12-28 | ローム株式会社 | semiconductor light emitting device |
| US11367715B2 (en) | 2019-12-04 | 2022-06-21 | Kabushiki Kaisha Toshiba | Photorelay |
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