JP2002353401A - Die collet for sucking chip, and method for manufacturing semiconductor - Google Patents

Die collet for sucking chip, and method for manufacturing semiconductor

Info

Publication number
JP2002353401A
JP2002353401A JP2001158588A JP2001158588A JP2002353401A JP 2002353401 A JP2002353401 A JP 2002353401A JP 2001158588 A JP2001158588 A JP 2001158588A JP 2001158588 A JP2001158588 A JP 2001158588A JP 2002353401 A JP2002353401 A JP 2002353401A
Authority
JP
Japan
Prior art keywords
suction
chip
semiconductor
semiconductor chips
die collet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001158588A
Other languages
Japanese (ja)
Inventor
Akihiko Murata
昭彦 村田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Priority to JP2001158588A priority Critical patent/JP2002353401A/en
Publication of JP2002353401A publication Critical patent/JP2002353401A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301—Bonding head
    • H01L2224/75302—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a die collet for sucking a chip which can accurately and efficiently mount a plurality of stages of semiconductor chips in one package, and to provide a method for manufacturing a semiconductor. SOLUTION: The die collet 11 sucks and holds the first semiconductor chip C1, in a state in which the chip C1 is sucked to and held on a first adsorbing surface 13a and the second semiconductor chip C2 to and in a second adsorbing surface 13b, so as to bring the chip C2 into close contact with an adhesive material 17 interposed between the chips C1 and C2. Then, the collet 11 mounts the chips C1 and C2, in a state in which the chips C1 and C2 are sucked and held, on a circuit board coated with the adhesive material.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、チップ吸着用ダイ
コレット及び半導体製造方法に係り、詳しくは一つのパ
ッケージ内に半導体チップを複数段積み重ねて搭載する
際に使用して好適なチップ吸着用ダイコレット及び半導
体製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip collecting die collet and a semiconductor manufacturing method, and more particularly, to a chip collecting die suitable for use when stacking a plurality of semiconductor chips in one package. The present invention relates to a collet and a semiconductor manufacturing method.

【０００２】近年、半導体集積回路は小型化及び高機能
化が要求され、一つのパッケージ内に複数の半導体チッ
プを積み重ねて搭載するスタック型マルチチップパッケ
ージ（スタックＭＣＰ）技術が開発されている。2. Description of the Related Art In recent years, there has been a demand for miniaturization and high performance of semiconductor integrated circuits, and a stack type multi-chip package (stack MCP) technology for stacking and mounting a plurality of semiconductor chips in one package has been developed.

【０００３】[0003]

【従来の技術】スタックＭＣＰの製造においては、先ず
ダイシングした半導体チップをチップ吸着用のダイコレ
ットを使用して真空吸着によりピックアップし、接着材
を塗布したＦＰＣ（Flexible Print Circuit）等の配線
基板上に搭載する。次いで、搭載した半導体チップの表
面に接着材を塗布し、該チップの上段にさらに半導体チ
ップを搭載する。各半導体チップは、ダイコレットを装
着したボンディング装置により配線基板上の所定位置あ
るいは下段の半導体チップ上に精密に位置決めされて搭
載される。そして、複数段にて搭載された各半導体チッ
プはワイヤーボンディングされた後に封止される。2. Description of the Related Art In the manufacture of a stacked MCP, first, a diced semiconductor chip is picked up by vacuum suction using a die collet for chip suction, and is mounted on a wiring board such as an FPC (Flexible Print Circuit) coated with an adhesive. To be mounted on. Next, an adhesive is applied to the surface of the mounted semiconductor chip, and the semiconductor chip is further mounted on the upper stage of the chip. Each semiconductor chip is precisely positioned and mounted on a predetermined position on a wiring board or on a lower semiconductor chip by a bonding apparatus equipped with a die collet. Each semiconductor chip mounted in a plurality of stages is sealed after being wire-bonded.

【０００４】図１１は、第一従来例のダイコレット３１
を示す概略斜視図である。ダイコレット３１はボンディ
ング装置（図示略）に装着され、このボンディング装置
により吸着孔３２を介して吸着面３３に半導体チップＣ
３（図１２参照）を真空吸着する。ダイコレット３１は
例えば金属又は樹脂又はゴムにて形成され、図１２に示
すように吸着面３３は略四角錐形状の凹部をなす。つま
り、ダイコレット３１は半導体チップＣ３を該チップＣ
３の辺が吸着面３３に接した状態で吸着する。また、図
１３に示すように、吸着面３３の四隅には吸着抜け孔３
２ａが切り欠き形成され、これら吸着抜け孔３２ａは半
導体チップＣ３を真空吸引した際に該チップＣ３の撓み
と四隅の破損を防止する。FIG. 11 shows a die collet 31 of the first conventional example.
FIG. The die collet 31 is mounted on a bonding device (not shown), and the semiconductor chip C is attached to the suction surface 33 through the suction hole 32 by the bonding device.
3 (see FIG. 12) is vacuum-adsorbed. The die collet 31 is formed of, for example, metal, resin, or rubber, and the suction surface 33 forms a substantially quadrangular pyramid-shaped recess as shown in FIG. That is, the die collet 31 replaces the semiconductor chip C3 with the chip C3.
The suction is performed in a state where the side 3 is in contact with the suction surface 33. Also, as shown in FIG.
The suction holes 32a prevent the semiconductor chip C3 from bending and being damaged at four corners when the semiconductor chip C3 is suctioned by vacuum.

【０００５】図１４は、第二従来例のダイコレット４１
を示す概略側面図である。上記同様にダイコレット４１
は、ボンディング装置により吸着孔４２を介して半導体
チップＣ３を真空吸着する。ダイコレット４１は例えば
金属又は樹脂又はゴムにて形成され、その下面には接着
テープ４３等を介してスポンジ又はゴム等の吸着部材４
４が取着されている。つまり、ダイコレット４１は半導
体チップＣ３を該チップＣ３の表面に接した状態で吸着
する。FIG. 14 shows a die collet 41 of a second conventional example.
FIG. Die collet 41 as above
The semiconductor chip C3 is vacuum-sucked through the suction holes 42 by a bonding device. The die collet 41 is formed of, for example, metal, resin, or rubber, and the lower surface thereof is provided with an adsorbing member 4 such as sponge or rubber via an adhesive tape 43 or the like.
4 are attached. That is, the die collet 41 attracts the semiconductor chip C3 in contact with the surface of the chip C3.

【０００６】[0006]

【発明が解決しようとする課題】ところで、従来のダイ
コレットは、一度に１個の半導体チップを真空吸着によ
りピックアップして配線基板上又は先に搭載した下段の
半導体チップ上に搭載する。そして、全ての半導体チッ
プが搭載された後にキュアが実施され、接着材が硬化さ
れる。これにより配線基板と半導体チップ、及び各半導
体チップ間は完全に接着される。In the conventional die collet, one semiconductor chip at a time is picked up by vacuum suction and mounted on a wiring board or a lower semiconductor chip mounted earlier. After all the semiconductor chips are mounted, curing is performed, and the adhesive is cured. As a result, the wiring board and the semiconductor chip, and between the semiconductor chips are completely bonded.

【０００７】しかしながら、このような製造過程におい
て上段の半導体チップを搭載する際、その搭載時に実施
されるスクラブあるいはダイコレットを装着したボンデ
ィング装置の振動により、先に搭載した下段の半導体チ
ップに位置ずれが生じる。この位置ずれは、先に搭載し
た下段の半導体チップと配線基板との間（又は各半導体
チップ間）の接着材が完全に硬化されていない状態で、
上段の半導体チップが搭載されるために生じる。特に、
一つのパッケージ内に搭載される半導体チップの段数が
多くなるほど、より下段側に搭載される半導体チップの
位置ずれは大きくなる。However, when the upper semiconductor chip is mounted in such a manufacturing process, the position of the lower semiconductor chip mounted earlier is displaced by the vibration of the bonding device mounted with the scrub or the die collet. Occurs. This misalignment occurs when the adhesive between the lower semiconductor chip and the wiring board previously mounted (or between the semiconductor chips) is not completely cured.
This occurs because the upper semiconductor chip is mounted. In particular,
As the number of semiconductor chips mounted in one package increases, the positional shift of the semiconductor chips mounted on the lower side increases.

【０００８】そこで、このような位置ずれを防止するた
め、各段の半導体チップを搭載毎にその都度キュアを実
施する方法が考えられる。しかし、この方法では、キュ
アを複数回実施するため非効率となる。In order to prevent such misalignment, a method is conceivable in which curing is performed each time a semiconductor chip in each stage is mounted. However, this method is inefficient because the curing is performed a plurality of times.

【０００９】本発明は、上記問題点を解消するためにな
されたものであって、その目的は複数段の半導体チップ
を一つのパッケージ内に精度良く且つ効率的に搭載する
ことができるチップ吸着用ダイコレット及び半導体製造
方法を提供することにある。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a chip suction device capable of accurately and efficiently mounting a plurality of stages of semiconductor chips in one package. An object of the present invention is to provide a die collet and a semiconductor manufacturing method.

【００１０】[0010]

【課題を解決するための手段】上記目的を達成するた
め、請求項１に記載の発明によれば、チップ吸着用ダイ
コレットは、複数の半導体チップを積層状態に真空吸着
保持し、各段のチップ間に介在させた接着部材を該接着
部材の上下のチップに密着させるように形成した凹部を
有する。ダイコレットは、凹部に形成された吸着面に各
半導体チップの辺が当接する状態で各段のチップをそれ
ぞれ吸着保持する。In order to achieve the above object, according to the first aspect of the present invention, a die collet for chip attraction holds a plurality of semiconductor chips in a stacked state by vacuum suction and holds each semiconductor chip. It has a recess formed so that the adhesive member interposed between the chips is brought into close contact with the chips above and below the adhesive member. The die collet sucks and holds the chips of each stage in a state where the sides of the respective semiconductor chips are in contact with the suction surfaces formed in the concave portions.

【００１１】請求項２に記載の発明によれば、請求項１
に記載の発明の作用に加えて、ダイコレットの凹部は略
四角錐形状に形成されるとともに、その吸着面は各半導
体チップのチップサイズに対応して各チップの吸着保持
位置にて同一又は異なる勾配を有してなる。According to the invention described in claim 2, according to claim 1,
In addition to the operation of the invention described in the above, the concave portion of the die collet is formed in a substantially quadrangular pyramid shape, and its suction surface is the same or different at the suction holding position of each chip corresponding to the chip size of each semiconductor chip It has a gradient.

【００１２】請求項３に記載の発明によれば、請求項１
に記載の発明の作用に加えて、ダイコレットの吸着面に
は、各半導体チップ及び接着材料毎の厚みに対応して当
該各段のチップの搭載位置を位置決めする所定の開口幅
を有した略階段状の段差が形成されている。[0012] According to the third aspect of the present invention, the first aspect is provided.
In addition to the operation of the invention described in the above, the suction surface of the die collet has a predetermined opening width for positioning the mounting position of the chip of each stage corresponding to the thickness of each semiconductor chip and each adhesive material. A step-like step is formed.

【００１３】請求項４に記載の発明によれば、請求項１
乃至３のいずれかに記載の発明の作用に加えて、ダイコ
レットの吸着面には、各半導体チップの吸着保持位置に
対応する吸着孔がそれぞれ設けられている。[0013] According to the invention described in claim 4, according to claim 1 of the present invention.
In addition to the effects of the invention described in any one of (3) to (3), the suction surface of the die collet is provided with suction holes corresponding to the suction holding positions of the respective semiconductor chips.

【００１４】請求項５に記載の発明によれば、ダイコレ
ットは、先ず最上段に搭載する半導体チップを吸着し、
次いで二段目以降の半導体チップを接着材料を介して順
次吸着する。そして、ダイコレットは、複数の半導体チ
ップ間を吸着力により密着させた状態で該複数の半導体
チップを同時に配線基板上に搭載する。その後、キュア
により接着材料が硬化される。According to the fifth aspect of the invention, the die collet first sucks the semiconductor chip mounted on the uppermost stage,
Next, the second and subsequent semiconductor chips are sequentially adsorbed via an adhesive material. Then, the die collet simultaneously mounts the plurality of semiconductor chips on the wiring board in a state where the plurality of semiconductor chips are brought into close contact with each other by an attraction force. Thereafter, the adhesive material is cured by curing.

【００１５】[0015]

【発明の実施の形態】以下、本発明を具体化した一実施
形態を図１〜図１０に従って説明する。図１は、ダイコ
レットの断面図を示す。ダイコレット１１は、例えばダ
イボンダー等のボンディング装置に装着され、吸着孔１
２より半導体チップを真空吸着する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a sectional view of the die collet. The die collet 11 is mounted on a bonding device such as a die bonder, for example.
The semiconductor chip is vacuum-adsorbed from 2.

【００１６】ダイコレット１１は略四角錐形状の凹部を
有し、該凹部には第１及び第２の吸着面１３ａ，１３ｂ
が形成されている。これら第１及び第２の吸着面１３
ａ，１３ｂには互いにチップサイズの異なる第１及び第
２の半導体チップＣ１，Ｃ２が吸着保持される。第１及
び第２の吸着面１３ａ，１３ｂは、各半導体チップＣ
１，Ｃ２のチップサイズに対応した開口幅（ポケットサ
イズ）にて略階段状の段差を有し、当該各吸着面１３
ａ，１３ｂは同一の勾配をなしている。The die collet 11 has a substantially quadrangular pyramid-shaped recess, and the recess has first and second suction surfaces 13a, 13b.
Are formed. These first and second suction surfaces 13
The first and second semiconductor chips C1 and C2 having different chip sizes from each other are held by suction at a and 13b. The first and second suction surfaces 13a and 13b are each
Each of the suction surfaces 13 has a substantially step-like step with an opening width (pocket size) corresponding to the chip size of C1 and C2.
a and 13b have the same gradient.

【００１７】このように構成されたダイコレット１１
は、第１及び第２の吸着面１３ａ，１３ｂに第１及び第
２の半導体チップＣ１，Ｃ２を当該チップＣ１，Ｃ２の
辺が各吸着面１３ａ，１３ｂに接した状態でそれぞれ吸
着保持する。因みに、第１及び第２の吸着面１３ａ，１
３ｂにおいて、第１及び第２の半導体チップＣ１，Ｃ２
を吸着する吸着保持位置には該チップＣ１，Ｃ２の撓み
と四隅の破損を防止する吸着抜け孔１４が形成されてい
る。The die collet 11 thus configured
The first and second semiconductor chips C1 and C2 are suction-held on the first and second suction surfaces 13a and 13b, respectively, with the sides of the chips C1 and C2 contacting the suction surfaces 13a and 13b, respectively. Incidentally, the first and second suction surfaces 13a, 1
3b, the first and second semiconductor chips C1, C2
At the suction holding position for sucking, suction suction holes 14 for preventing bending of the chips C1 and C2 and breakage of the four corners are formed.

【００１８】そして、第１及び第２の吸着面１３ａ，１
３ｂは、第１及び第２の半導体チップＣ１，Ｃ２の厚み
に対応して各チップＣ１，Ｃ２をそれぞれ垂直方向に並
べて吸着できるよう互いに異なる高さに設けられてい
る。言い換えれば、ダイコレット１１は、第１の吸着面
１３ａにて第１の半導体チップＣ１を吸着保持した状態
で、第２の吸着面１３ｂにて第１の半導体チップＣ１の
直下に第２の半導体チップＣ２を吸着保持する。The first and second suction surfaces 13a, 13a
3b is provided at different heights so that the chips C1 and C2 can be vertically aligned and sucked, respectively, in accordance with the thicknesses of the first and second semiconductor chips C1 and C2. In other words, the die collet 11 holds the first semiconductor chip C1 on the first suction surface 13a and holds the second semiconductor chip directly below the first semiconductor chip C1 on the second suction surface 13b. The chip C2 is held by suction.

【００１９】尚、上記のように構成されるダイコレット
１１においては、図１に破線で示すように吸着孔１２か
らバイパスさせて吸着孔１５を形成することにより、第
２の半導体チップＣ２を真空吸着する際の吸着力を増加
させることもできる。この際、図２に破線で示すように
吸着孔１２と別経路の吸着孔１６を形成してもよい。In the die collet 11 configured as described above, the second semiconductor chip C2 is evacuated by forming the suction hole 15 by bypassing the suction hole 12 as shown by a broken line in FIG. It is also possible to increase the attraction force at the time of adsorption. At this time, as shown by a broken line in FIG. 2, the suction hole 12 may be formed in a different path from the suction hole 12.

【００２０】次に、上記のように構成されるダイコレッ
ト１１を使用して一つのパッケージ内に複数段の半導体
チップを搭載する場合（スタック型マルチチップパッケ
ージ（スタックＭＣＰ））の製造方法を図３〜図８に従
って説明する。尚、説明の簡略化のため、本実施形態で
は第１及び第２の半導体チップＣ１，Ｃ２の二段を積み
重ねて搭載する場合について説明する。Next, a method for manufacturing a case where a plurality of stages of semiconductor chips are mounted in one package using the die collet 11 configured as described above (stack type multi-chip package (stack MCP)) will be described. This will be described with reference to FIGS. For the sake of simplicity, the present embodiment will describe a case where two stages of the first and second semiconductor chips C1 and C2 are stacked and mounted.

【００２１】図３は、ボンディング装置の概略平面図を
示す。ボンディング装置２１は、複数種類の半導体チッ
プを供給するチップ供給部２２と、それら各半導体チッ
プを実装する例えばＦＰＣ（Flexible Print Circuit；
ポリイミド樹脂を用いたプリント基板）等の配線基板Ｓ
１を搬送する基板搬送部２３とを備える。また、ボンデ
ィング装置２１には、第１及び第２の半導体チップＣ
１，Ｃ２を吸着する上記ダイコレット１１が装着されて
いる。FIG. 3 is a schematic plan view of the bonding apparatus. The bonding apparatus 21 includes a chip supply unit 22 that supplies a plurality of types of semiconductor chips, and a FPC (Flexible Print Circuit;
Wiring board S such as printed board using polyimide resin)
And a substrate transport section 23 for transporting the substrate 1. The bonding device 21 includes the first and second semiconductor chips C
The die collet 11 for adsorbing C1 and C2 is mounted.

【００２２】今、チップ供給部２２には、第１の半導体
チップＣ１を形成した第１の半導体ウェハＷ１及び第２
の半導体チップＣ２を形成した第２の半導体ウェハＷ２
が準備されている。尚、本実施形態では、第１の半導体
チップＣ１のチップサイズは、第２の半導体チップＣ２
のそれより大きい。即ち、配線基板Ｓ１のダイパッド上
に第２の半導体チップＣ２が搭載され、その第２の半導
体チップＣ２上に第１の半導体チップＣ１が搭載され
る。Now, the first semiconductor wafer W1 on which the first semiconductor chip C1 is formed and the second
Semiconductor wafer W2 on which semiconductor chip C2 is formed
Is prepared. In the present embodiment, the chip size of the first semiconductor chip C1 is the same as that of the second semiconductor chip C2.
Greater than that of. That is, the second semiconductor chip C2 is mounted on the die pad of the wiring substrate S1, and the first semiconductor chip C1 is mounted on the second semiconductor chip C2.

【００２３】先ず、図４に示すように、ダイコレット１
１は第１の半導体チップＣ１を真空吸着によりピックア
ップする。第１の半導体チップＣ１は、第１の吸着面１
３ａに吸着保持される。First, as shown in FIG.
1 picks up the first semiconductor chip C1 by vacuum suction. The first semiconductor chip C1 has the first suction surface 1
3a holds by suction.

【００２４】次に、ボンディング装置２１に配設される
ディスペンサ（図示略）により、図５に示すように第２
の半導体チップＣ２上に接着材料１７を塗布した状態
で、ダイコレット１１は、第２の半導体チップＣ２を真
空吸着によりピックアップする（図６参照）。第２の半
導体チップＣ２は、第２の吸着面１３ｂに吸着保持され
る。即ち、ダイコレット１１は、第１の半導体チップＣ
１を第１の吸着面１３ａに吸着した状態で、接着材料１
７を塗布した第２の半導体チップＣ２を第２の吸着面１
３ｂに吸着保持する。これにより、互いのチップＣ１，
Ｃ２を接着する接着材料１７が吸着力により引き伸ばさ
れ、その接着材料１７を介して第１及び第２の半導体チ
ップＣ１，Ｃ２が密着される。Next, as shown in FIG. 5, a second dispenser (not shown) provided in the bonding apparatus 21
The die collet 11 picks up the second semiconductor chip C2 by vacuum suction with the adhesive material 17 applied on the semiconductor chip C2 (see FIG. 6). The second semiconductor chip C2 is suction-held on the second suction surface 13b. That is, the die collet 11 is provided with the first semiconductor chip C.
1 is adsorbed to the first adsorption surface 13a, and the adhesive material 1
7 is applied to the second suction surface 1 of the second semiconductor chip C2.
3b. Thereby, each chip C1,
The adhesive material 17 for adhering C2 is stretched by the attraction force, and the first and second semiconductor chips C1 and C2 are adhered through the adhesive material 17.

【００２５】次に、上記ディスペンサにより、図７に示
すように配線基板Ｓ１上に接着材料１８を塗布した状態
で、ダイコレット１１は、第１及び第２の半導体チップ
Ｃ１，Ｃ２を配線基板Ｓ１上に搭載する（図８参照）。
この際、ダイコレット１１の荷重又はスクラブ動作によ
り接着材料１８が引き伸ばされ、その接着材料１８を介
して配線基板Ｓ１と第２の半導体チップＣ２とが密着さ
れる。更に、このとき配線基板Ｓ１上に各半導体チップ
Ｃ１，Ｃ２を搭載する場合においては、当該各チップＣ
１，Ｃ２が各吸着面１３ａ，１３ｂの開口幅（ポケット
サイズ）に規制され、それらの搭載位置が位置決めされ
る。Next, as shown in FIG. 7, the die collet 11 attaches the first and second semiconductor chips C1 and C2 to the wiring board S1 while the adhesive material 18 is applied on the wiring board S1 by the dispenser. Mounted on top (see FIG. 8).
At this time, the adhesive material 18 is stretched by the load of the die collet 11 or the scrubbing operation, and the wiring substrate S1 and the second semiconductor chip C2 are adhered through the adhesive material 18. Further, at this time, when each of the semiconductor chips C1 and C2 is mounted on the wiring
1 and C2 are regulated by the opening width (pocket size) of each suction surface 13a, 13b, and their mounting positions are determined.

【００２６】次に、ダイコレット１１の真空吸着をオフ
し、図９に示すように、配線基板Ｓ１上に第１及び第２
の半導体チップＣ１，Ｃ２が搭載された状態でキュアを
実施して各接着材料１７，１８を硬化させる。これによ
り、配線基板Ｓ１と第２の半導体チップＣ２とが完全に
接着されるとともに、第２の半導体チップＣ２と第１の
半導体チップＣ１とが完全に接着される。Next, the vacuum suction of the die collet 11 is turned off, and as shown in FIG.
In the state where the semiconductor chips C1 and C2 are mounted, curing is performed to cure the adhesive materials 17 and 18. Thus, the wiring substrate S1 and the second semiconductor chip C2 are completely bonded, and the second semiconductor chip C2 and the first semiconductor chip C1 are completely bonded.

【００２７】その後、図１０に示すように、ボンディン
グ装置２１により各半導体チップＣ１，Ｃ２と配線基板
Ｓ１とのワイヤーボンディングを行った後に封止する
（図中、破線で示す）。Thereafter, as shown in FIG. 10, the semiconductor chips C1 and C2 and the wiring substrate S1 are wire-bonded by the bonding device 21 and then sealed (indicated by broken lines in the drawing).

【００２８】以上記述したように、本実施の形態によれ
ば、以下の効果を奏する。 （１）ダイコレット１１は、第１の半導体チップＣ１を
第１の吸着面１３ａに吸着保持した状態で、第２の半導
体チップＣ２を当該各チップＣ１，Ｃ２間に介在する接
着材料１７に密着させるように第２の吸着面１３ｂに吸
着保持する。次いで、ダイコレット１１は、各半導体チ
ップＣ１，Ｃ２を吸着保持した状態で、それら各半導体
チップＣ１，Ｃ２を、接着材料１８を塗布した配線基板
Ｓ１上に搭載する。このように、接着材料１７を介して
各半導体チップＣ１，Ｃ２間を密着させた状態で、複数
段のチップＣ１，Ｃ２を配線基板Ｓ１上に同時に搭載す
ることで、該基板Ｓ１上に搭載される下段側のチップの
位置ずれを防止することができる。即ち、複数段の半導
体チップを配線基板Ｓ１上に精度良く搭載可能となる。As described above, the present embodiment has the following advantages. (1) The die collet 11 adheres the second semiconductor chip C2 to the adhesive material 17 interposed between the respective chips C1 and C2 in a state where the first semiconductor chip C1 is adsorbed and held on the first adsorption surface 13a. The second suction surface 13b is suction-held so as to perform the suction. Next, the die collet 11 mounts the respective semiconductor chips C1 and C2 on the wiring board S1 to which the adhesive material 18 has been applied, while holding the respective semiconductor chips C1 and C2 by suction. As described above, by mounting the chips C1 and C2 in a plurality of stages simultaneously on the wiring board S1 in a state where the semiconductor chips C1 and C2 are in close contact with each other via the adhesive material 17, the semiconductor chip C1 and C2 are mounted on the board S1. Position of the lower chip can be prevented. That is, a plurality of semiconductor chips can be accurately mounted on the wiring board S1.

【００２９】（２）各半導体チップＣ１，Ｃ２を配線基
板Ｓ１上に搭載する際、各半導体チップＣ１，Ｃ２は該
チップＣ１，Ｃ２の辺が各吸着面１３ａ，１３ｂに接す
る状態で搭載される。従って、各チップＣ１，Ｃ２の搭
載時には、該チップＣ１，Ｃ２は、各吸着面１３ａ，１
３ｂにおける開口幅（ポケットサイズ）により規制され
て配線基板Ｓ１上に位置決めされる。この結果、搭載時
に実施されるスクラブ動作により、下段側のチップ（第
２の半導体チップＣ２）に水平方向の位置ずれが生じた
場合にその位置ずれを開口幅の範囲内に抑えることがで
きる。(2) When mounting the semiconductor chips C1 and C2 on the wiring board S1, the semiconductor chips C1 and C2 are mounted with the sides of the chips C1 and C2 in contact with the suction surfaces 13a and 13b. . Therefore, when the chips C1 and C2 are mounted, the chips C1 and C2 are attached to the suction surfaces 13a and 13a.
Positioning on the wiring board S1 is regulated by the opening width (pocket size) in 3b. As a result, when a horizontal displacement occurs in the lower chip (second semiconductor chip C2) due to the scrub operation performed during mounting, the displacement can be suppressed within the range of the opening width.

【００３０】（３）配線基板Ｓ１上に第１及び第２の半
導体チップＣ１，Ｃ２を搭載した後にキュアが１回のみ
実施される。従って、キュアの回数が増加することを抑
止して効率的に製造することができる。(3) After mounting the first and second semiconductor chips C1 and C2 on the wiring board S1, curing is performed only once. Therefore, it is possible to suppress the increase in the number of times of curing and to efficiently manufacture.

【００３１】（４）吸着孔１２からバイパスして吸着孔
１５を形成することで、又は吸着孔１２と別経路の吸着
孔１６を形成することで、第２の半導体チップＣ２の吸
着力を増加させることができる。即ち、このように構成
することで、複数段の半導体チップを吸着するダイコレ
ット１１において、下段側のチップの吸着力を高めるこ
とができる。(4) The suction force of the second semiconductor chip C2 is increased by forming the suction hole 15 bypassing the suction hole 12 or by forming the suction hole 16 on a different path from the suction hole 12. Can be done. That is, with this configuration, in the die collet 11 that suctions the semiconductor chips in a plurality of stages, the suction force of the lower chip can be increased.

【００３２】（５）複数段の半導体チップを精度良く搭
載することができるため、歩留まりを向上させ、生産コ
ストの低下に貢献することができる。尚、上記実施形態
は、以下のように変更してもよい。(5) Since a plurality of stages of semiconductor chips can be mounted with high accuracy, the yield can be improved and the production cost can be reduced. The above embodiment may be modified as follows.

【００３３】・本実施形態では、第１及び第２の吸着面
１３ａ，１３ｂは同一の勾配にて形成したが、これらは
吸着する半導体チップのチップサイズに対応して異なる
勾配にて形成してもよい。In the present embodiment, the first and second suction surfaces 13a and 13b are formed with the same gradient, but they are formed with different gradients according to the chip size of the semiconductor chip to be suctioned. Is also good.

【００３４】・本実施形態では、第１及び第２の吸着面
１３ａ，１３ｂは、所定の開口幅（ポケットサイズ）を
持つ略階段状の段差を有してなるが、これら各吸着面１
３ａ，１３ｂは連続して形成されるようにしてもよい。In the present embodiment, the first and second suction surfaces 13a and 13b have substantially stepped steps having a predetermined opening width (pocket size).
3a and 13b may be formed continuously.

【００３５】・また、第１及び第２の吸着面１３ａ，１
３ｂを連続して形成する場合には、それら吸着面１３
ａ，１３ｂは、吸着する半導体チップのチップサイズに
対応して異なる勾配にて形成してもよい。The first and second suction surfaces 13a, 13a;
3b are formed in a continuous manner,
a and 13b may be formed with different gradients according to the chip size of the semiconductor chip to be adsorbed.

【００３６】・本実施形態では、第１の半導体チップＣ
１の直下に第２の半導体チップＣ２をそれらチップＣ
１，Ｃ２の中心が一致するようにして搭載したが、各チ
ップＣ１，Ｃ２の中心をずらして搭載可能とするような
勾配にて各吸着面１３ａ，１３を形成してもよい。In the present embodiment, the first semiconductor chip C
1 and the second semiconductor chips C2
Although the mounting is performed so that the centers of the chips C1 and C2 coincide with each other, the suction surfaces 13a and 13 may be formed with a gradient such that the centers of the chips C1 and C2 can be shifted and mounted.

【００３７】・本実施形態で第１及び第２の半導体チッ
プＣ１，Ｃ２を搭載する配線基板Ｓ１は、ＦＰＣ以外の
リードフレームとしてもよい。 ・本実施形態では、第１及び第２の半導体チップＣ１，
Ｃ２の二段を配線基板Ｓ１上に搭載したが、三段以上の
複数段としてもよい。即ち、ダイコレット１１が三段以
上の半導体チップを吸着できるように構成してもよい。In this embodiment, the wiring board S1 on which the first and second semiconductor chips C1 and C2 are mounted may be a lead frame other than the FPC. In the present embodiment, the first and second semiconductor chips C1,
The two stages of C2 are mounted on the wiring board S1, but may be three or more stages. That is, the die collet 11 may be configured to be able to adsorb three or more stages of semiconductor chips.

【００３８】・配線基板Ｓ１上に塗布する接着材料１８
は、該配線基板Ｓ１の材質により、第１及び第２の半導
体チップＣ１，Ｃ２間を接着する接着材料１７と同一の
接着材料としてもよい。即ち、接着材料１７，１８は、
接着する材質に合わせて同一材料又は異なる材料に適宜
変更させる。The adhesive material 18 applied on the wiring board S1
May be the same adhesive material as the adhesive material 17 that bonds the first and second semiconductor chips C1 and C2 depending on the material of the wiring board S1. That is, the adhesive materials 17 and 18
The same material or a different material is appropriately changed according to the material to be bonded.

【００３９】・本実施形態では、第１及び第２の半導体
チップＣ１，Ｃ２を接着する接着材料１７を第２の半導
体チップＣ２の上面に塗布したが、接着材料１７を第１
の半導体チップＣ１の下面に塗布するようにしてもよ
い。同様に、第２の半導体チップＣ２と配線基板Ｓ１と
を接着する接着材料１８を第２の半導体チップＣ２の下
面に塗布するようにしてもよい。In the present embodiment, the adhesive material 17 for bonding the first and second semiconductor chips C1 and C2 is applied to the upper surface of the second semiconductor chip C2.
May be applied to the lower surface of the semiconductor chip C1. Similarly, an adhesive material 18 for bonding the second semiconductor chip C2 and the wiring board S1 may be applied to the lower surface of the second semiconductor chip C2.

【００４０】・また、接着材料１７，１８はペースト状
のものに限らず、フィルム状の接着シートを使用しても
よい。上記実施形態をまとめると、以下のようになる。 （付記１） 複数の半導体チップを真空吸着するチップ
吸着用ダイコレットであって、前記各半導体チップの辺
が当接する吸着面からなり、前記複数の半導体チップを
積層状態に吸着保持するとともに、各段の半導体チップ
間に介在させた接着部材を該接着部材の上下の半導体チ
ップに密着させるように形成された凹部を有することを
特徴とするチップ吸着用ダイコレット。 （付記２） 前記凹部は略四角錐形状に形成され、前記
吸着面は前記各半導体チップのチップサイズに対応して
当該各半導体チップの吸着保持位置にて同一又は異なる
勾配を有してなることを特徴とする付記１に記載のチッ
プ吸着用ダイコレット。 （付記３） 前記吸着面には、前記各半導体チップ及び
前記接着材料毎の厚みに対応して当該各半導体チップの
搭載位置を位置決めする所定の開口幅を有した略階段状
の段差が形成されていることを特徴とする付記１に記載
のチップ吸着用ダイコレット。 （付記４） 前記吸着面には、前記各半導体チップの吸
着保持位置に対応する吸着孔がそれぞれ設けられている
ことを特徴とする付記１乃至３のいずれかに記載のチッ
プ吸着用ダイコレット。 （付記５） 最上段に搭載する半導体チップを真空吸着
する吸着孔を形成するとともに、該吸着孔からバイパス
させて二段目以降の半導体チップを真空吸着する複数の
吸着孔を形成したことを特徴とする付記４に記載のチッ
プ吸着用ダイコレット。 （付記６） 前記各半導体チップを真空吸着する吸着孔
を個別の経路にて形成したことを特徴とする付記４に記
載のチップ吸着用ダイコレット。 （付記７） 同一の配線基板上に複数の半導体チップを
積み重ねて搭載する半導体製造装置において、前記複数
の半導体チップを各半導体チップ間に接着材料を介して
順次吸着保持し、前記各半導体チップ間を吸着力により
密着させた状態で該各半導体チップを前記配線基板上に
同時に搭載するダイコレットを備えたことを特徴とする
半導体製造装置。 （付記８） ダイコレットにより真空吸着してピックア
ップした複数の半導体チップを同一の配線基板上に積み
重ねて搭載する半導体製造方法であって、最上段に搭載
する半導体チップを吸着保持した状態で二段目以降の半
導体チップを接着材料を介して順次吸着保持し、前記複
数の半導体チップ間を密着させた状態で当該複数の半導
体チップを前記配線基板上に同時に搭載した後、前記接
着材料をキュアにより硬化させることを特徴とする半導
体製造方法。 （付記９） 前記ダイコレットは、前記半導体チップの
水平方向の移動を規制し、前記配線基板に対してスクラ
ブする工程を含むことを特徴とする付記８に記載の半導
体製造方法。The adhesive materials 17 and 18 are not limited to paste-like materials, but may be film-like adhesive sheets. The above embodiments are summarized as follows. (Supplementary Note 1) A chip collecting die collet for vacuum-sucking a plurality of semiconductor chips, comprising a suction surface with which the sides of the respective semiconductor chips are in contact with each other. A die collet for chip suction, comprising a concave portion formed so that an adhesive member interposed between semiconductor chips in a step is brought into close contact with semiconductor chips above and below the adhesive member. (Supplementary Note 2) The concave portion is formed in a substantially quadrangular pyramid shape, and the suction surface has the same or different gradient at the suction holding position of each semiconductor chip corresponding to the chip size of each semiconductor chip. The die collet for chip adsorption according to claim 1, characterized in that: (Supplementary Note 3) A substantially step-shaped step having a predetermined opening width for positioning a mounting position of each semiconductor chip corresponding to the thickness of each of the semiconductor chips and the adhesive material is formed on the suction surface. 2. The die collet for chip adsorption according to claim 1, wherein (Supplementary Note 4) The die collet for chip suction according to any one of Supplementary notes 1 to 3, wherein suction holes corresponding to suction holding positions of the semiconductor chips are provided on the suction surface, respectively. (Supplementary Note 5) A suction hole for vacuum-sucking the semiconductor chip mounted on the uppermost stage is formed, and a plurality of suction holes for vacuum-sucking the second and subsequent semiconductor chips by bypassing the suction hole are formed. A die collet for chip adsorption according to Supplementary Note 4. (Supplementary Note 6) The die collet for chip suction according to Supplementary Note 4, wherein suction holes for vacuum-sucking the semiconductor chips are formed in individual paths. (Supplementary Note 7) In a semiconductor manufacturing apparatus in which a plurality of semiconductor chips are stacked and mounted on the same wiring board, the plurality of semiconductor chips are sequentially sucked and held between the respective semiconductor chips via an adhesive material. A die collet for simultaneously mounting the respective semiconductor chips on the wiring substrate in a state where the semiconductor chips are brought into close contact with each other by an attraction force. (Supplementary Note 8) This is a semiconductor manufacturing method in which a plurality of semiconductor chips picked up by vacuum suction using a die collet are stacked and mounted on the same wiring board, and a two-stage process is performed in a state where the semiconductor chip mounted on the uppermost stage is suction-held. The semiconductor chips subsequent to the eyes are sequentially held by suction via an adhesive material, and after the plurality of semiconductor chips are simultaneously mounted on the wiring substrate in a state where the plurality of semiconductor chips are in close contact with each other, the adhesive material is cured by curing. A semiconductor manufacturing method characterized by curing. (Supplementary Note 9) The semiconductor manufacturing method according to Supplementary Note 8, wherein the die collet includes a step of restricting horizontal movement of the semiconductor chip and scrubbing the wiring board.

【００４１】[0041]

【発明の効果】以上記述したように、この発明は、複数
段の半導体チップを一つのパッケージ内に精度良く且つ
効率的に搭載することができるチップ吸着用ダイコレッ
ト及び半導体製造方法を提供することができる。As described above, the present invention provides a chip collecting die collet and a semiconductor manufacturing method capable of accurately and efficiently mounting a plurality of stages of semiconductor chips in one package. Can be.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 一実施形態のダイコレットの断面図である。FIG. 1 is a cross-sectional view of a die collet of one embodiment.

【図２】 一実施形態のダイコレットの断面図である。FIG. 2 is a cross-sectional view of the die collet of one embodiment.

【図３】 ボンディング装置の概略平面図である。FIG. 3 is a schematic plan view of a bonding apparatus.

【図４】 製造方法を説明する説明図である。FIG. 4 is an explanatory diagram illustrating a manufacturing method.

【図５】 製造方法を説明する説明図である。FIG. 5 is an explanatory diagram illustrating a manufacturing method.

【図６】 製造方法を説明する説明図である。FIG. 6 is an explanatory diagram illustrating a manufacturing method.

【図７】 製造方法を説明する説明図である。FIG. 7 is an explanatory diagram illustrating a manufacturing method.

【図８】 製造方法を説明する説明図である。FIG. 8 is an explanatory diagram illustrating a manufacturing method.

【図９】 製造方法を説明する説明図である。FIG. 9 is an explanatory diagram illustrating a manufacturing method.

【図１０】 製造方法を説明する説明図である。FIG. 10 is an explanatory diagram illustrating a manufacturing method.

【図１１】 第一従来例のダイコレットの斜視図であ
る。FIG. 11 is a perspective view of a die collet of the first conventional example.

【図１２】 第一従来例のダイコレットの断面図であ
る。FIG. 12 is a sectional view of a die collet of the first conventional example.

【図１３】 第一従来例のダイコレットの底面図であ
る。FIG. 13 is a bottom view of the die collet of the first conventional example.

【図１４】 第二従来例のダイコレットの側面図であ
る。FIG. 14 is a side view of a die collet of a second conventional example.

【符号の説明】[Explanation of symbols]

Ｃ１ 半導体チップ（第１の半導体チップ） Ｃ２ 半導体チップ（第２の半導体チップ） １１ ダイコレット １３ａ 吸着面（第１の吸着面） １３ｂ 吸着面（第２の吸着面） １７ 接着材料 １８ 接着材料 C1 Semiconductor chip (first semiconductor chip) C2 Semiconductor chip (second semiconductor chip) 11 Dicollet 13a Suction surface (first suction surface) 13b Suction surface (second suction surface) 17 Adhesive material 18 Adhesive material

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】 複数の半導体チップを真空吸着するチッ
プ吸着用ダイコレットであって、 前記各半導体チップの辺が当接する吸着面からなり、前
記複数の半導体チップを積層状態に吸着保持するととも
に、各段の半導体チップ間に介在させた接着部材を該接
着部材の上下の半導体チップに密着させるように形成さ
れた凹部を有することを特徴とするチップ吸着用ダイコ
レット。1. A die-collapsing die collet for vacuum-suctioning a plurality of semiconductor chips, comprising a suction surface in which sides of the respective semiconductor chips are in contact with each other, the plurality of semiconductor chips being suction-held in a stacked state, A die collet for chip suction, comprising a concave portion formed so that an adhesive member interposed between semiconductor chips of each stage is brought into close contact with semiconductor chips above and below the adhesive member. 【請求項２】 前記凹部は略四角錐形状に形成され、前
記吸着面は前記各半導体チップのチップサイズに対応し
て当該各半導体チップの吸着保持位置にて同一又は異な
る勾配を有してなることを特徴とする請求項１に記載の
チップ吸着用ダイコレット。2. The concave portion is formed in a substantially quadrangular pyramid shape, and the suction surface has the same or different gradient at a suction holding position of each semiconductor chip corresponding to a chip size of each semiconductor chip. The die collet for chip attraction according to claim 1, characterized in that: 【請求項３】 前記吸着面には、前記各半導体チップ及
び前記接着材料毎の厚みに対応して当該各半導体チップ
の搭載位置を位置決めする所定の開口幅を有した略階段
状の段差が形成されていることを特徴とする請求項１に
記載のチップ吸着用ダイコレット。3. A substantially step-shaped step having a predetermined opening width for positioning a mounting position of each semiconductor chip corresponding to a thickness of each of the semiconductor chips and the adhesive material is formed on the suction surface. The die collet for chip attraction according to claim 1, wherein the die collet is provided. 【請求項４】 前記吸着面には、前記各半導体チップの
吸着保持位置に対応する吸着孔がそれぞれ設けられてい
ることを特徴とする請求項１乃至３のいずれかに記載の
チップ吸着用ダイコレット。4. The chip suction die according to claim 1, wherein suction holes corresponding to suction holding positions of the respective semiconductor chips are provided on the suction surface. Collet. 【請求項５】 ダイコレットにより真空吸着してピック
アップした複数の半導体チップを同一の配線基板上に積
み重ねて搭載する半導体製造方法であって、最上段に搭
載する半導体チップを吸着保持した状態で二段目以降の
半導体チップを接着材料を介して順次吸着保持し、前記
複数の半導体チップ間を密着させた状態で当該複数の半
導体チップを前記配線基板上に同時に搭載した後、前記
接着材料をキュアにより硬化させることを特徴とする半
導体製造方法。5. A semiconductor manufacturing method in which a plurality of semiconductor chips picked up by vacuum suction using a die collet are stacked and mounted on the same wiring board, wherein the semiconductor chip mounted on the uppermost stage is suction-held and held. After successively holding the semiconductor chips of the first and second stages via an adhesive material and holding the plurality of semiconductor chips in close contact with each other, the plurality of semiconductor chips are simultaneously mounted on the wiring board, and then the adhesive material is cured. A semiconductor manufacturing method characterized by curing by:
JP2001158588A 2001-05-28 2001-05-28 Die collet for sucking chip, and method for manufacturing semiconductor Pending JP2002353401A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001158588A JP2002353401A (en) 2001-05-28 2001-05-28 Die collet for sucking chip, and method for manufacturing semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001158588A JP2002353401A (en) 2001-05-28 2001-05-28 Die collet for sucking chip, and method for manufacturing semiconductor

Publications (1)

Publication Number Publication Date
JP2002353401A true JP2002353401A (en) 2002-12-06

Family

ID=19002280

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001158588A Pending JP2002353401A (en) 2001-05-28 2001-05-28 Die collet for sucking chip, and method for manufacturing semiconductor

Country Status (1)

Country Link
JP (1) JP2002353401A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003086758A (en) * 2001-09-10 2003-03-20 Mitsubishi Electric Corp Semiconductor device, and method and device for manufacturing same
CN113410169A (en) * 2021-05-18 2021-09-17 深圳市百柔新材料技术有限公司 Transfer device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003086758A (en) * 2001-09-10 2003-03-20 Mitsubishi Electric Corp Semiconductor device, and method and device for manufacturing same
CN113410169A (en) * 2021-05-18 2021-09-17 深圳市百柔新材料技术有限公司 Transfer device

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