JP2002353235A - Active matrix substrate, display using the same, and its manufacturing method - Google Patents
Active matrix substrate, display using the same, and its manufacturing methodInfo
- Publication number
- JP2002353235A JP2002353235A JP2001154590A JP2001154590A JP2002353235A JP 2002353235 A JP2002353235 A JP 2002353235A JP 2001154590 A JP2001154590 A JP 2001154590A JP 2001154590 A JP2001154590 A JP 2001154590A JP 2002353235 A JP2002353235 A JP 2002353235A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- thin film
- active matrix
- circuit element
- element groups
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は液晶ディスプレイや
有機エレクトロルミネッセンス（ＥＬ）ディスプレイ等
の表示装置やラインセンサーやエリアセンサーなどの撮
像装置に利用されるアクティブマトリクス基板に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix substrate used for a display device such as a liquid crystal display and an organic electroluminescence (EL) display and an imaging device such as a line sensor and an area sensor.
【０００２】[0002]
【従来の技術】従来、液晶ディスプレイや有機エレクト
ロルミネッセンス（ＥＬ）ディスプレイ等の表示装置
や、ラインセンサーやエリアセンサーなどの撮像装置に
利用されるアクティブマトリクス基板の製造方法は、半
導体作成技術や設備を改良し大型の透光性基板に対応で
きるようにしたものであった。2. Description of the Related Art Conventionally, a method of manufacturing an active matrix substrate used for a display device such as a liquid crystal display or an organic electroluminescence (EL) display and an imaging device such as a line sensor or an area sensor requires a semiconductor manufacturing technology and equipment. It was improved to be able to handle large translucent substrates.
【０００３】以下に従来のアクティブマトリクス基板の
製造方法について説明する。Hereinafter, a conventional method for manufacturing an active matrix substrate will be described.
【０００４】図８は従来のアクティブマトリクス基板の
一つの単位である薄膜トランジスタ（ＴＦＴ）の断面構
造を示すものである。図８において、ガラス基板１の表
面に、ゲート電極２が例えばスパッタリング装置にてＴ
ｉとＡｌの積層構造で形成されている。その表面にはゲ
ート絶縁膜３が形成され、その上にイントリンシックな
特性（故意に不純物を添加しない）を有する非晶質シリ
コン４が形成され、その表面にＰをドープした非晶質シ
リコン５が形成されている。ゲート絶縁膜３，非晶質シ
リコン４と表面にＰをドープした非晶質シリコン５は、
プラズマＣＶＤ装置にて連続形成されている。その表面
にソース・ドレイン電極６が形成されている。ソース・
ドレイン電極６は、一例としてはスパッタリング装置に
てＴｉとＡｌの積層構造で形成されている。各薄膜層は
フォトリソグラフィによるレジストパターンとドライま
たはウェットエッチングによってパターニングされＴＦ
Ｔの形状を作製する。FIG. 8 shows a sectional structure of a thin film transistor (TFT) which is one unit of a conventional active matrix substrate. 8, a gate electrode 2 is formed on a surface of a glass substrate 1 by, for example, a sputtering apparatus.
It is formed with a laminated structure of i and Al. A gate insulating film 3 is formed on the surface thereof, an amorphous silicon 4 having intrinsic characteristics (do not intentionally add impurities) is formed thereon, and a P-doped amorphous silicon 5 is formed on the surface thereof. Are formed. The gate insulating film 3, the amorphous silicon 4 and the amorphous silicon 5 doped with P
It is formed continuously by a plasma CVD apparatus. Source / drain electrodes 6 are formed on the surface. Source·
As an example, the drain electrode 6 is formed in a laminated structure of Ti and Al by a sputtering device. Each thin film layer is patterned by a resist pattern by photolithography and dry or wet etching and TF
Create a T shape.
【０００５】図９は従来のアクティブマトリクス基板を
液晶ディスプレイに適用した場合の一つの画素単位の平
面図であり、ＴＦＴ部分は上記の断面図と同様である
が、ＴＦＴ以外では、７は画素電極、８は画素電極７と
ゲート配線２１の重なり部分で形成する蓄積容量であ
る。図１０は図６の等価回路を示したものである。図７
の６１はソース配線、Ｖｓはソース配線に印加されてる
信号電圧、Ｖｇはゲート配線に印可される走査パルスで
ある。FIG. 9 is a plan view of one pixel unit when a conventional active matrix substrate is applied to a liquid crystal display. The TFT portion is the same as the cross-sectional view described above. Reference numerals 8 denote storage capacitors formed at overlapping portions of the pixel electrodes 7 and the gate lines 21. FIG. 10 shows an equivalent circuit of FIG. FIG.
Reference numeral 61 denotes a source wiring, Vs denotes a signal voltage applied to the source wiring, and Vg denotes a scanning pulse applied to the gate wiring.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、前記従
来例の構成では、図９からもわかる様にＴＦＴの占める
面積(2,4,5,6の部分)はごく一部であり、ＴＦＴの領域
以外は同じ成膜プロセスとパターニングプロセスで処理
されるが、全て除去される。ＴＦＴ作製のための設備、
それらを設置するクリーンルームや原動設備は非常に高
価である。さらに人件費も加わりことになり、その結果
としてアクティブマトリクス基板の原価は非常に高いと
いう問題点を有していた。また、ＴＦＴ作製のために形
成した薄膜もほとんどの部分が除去されて廃棄されるの
で、地球資源の浪費であるとともに、廃棄される部分た
めに多くのエネルギーとエッチング用のガスや薬液類を
使用していることになり、地球環境にも多大の影響を与
えていた。However, in the configuration of the conventional example, the area occupied by the TFTs (portions 2, 4, 5, and 6) is very small, as can be seen from FIG. Other than the above, the same film forming process and patterning process are performed, but all are removed. Equipment for TFT fabrication,
The clean rooms and prime movers where they are installed are very expensive. Further, labor costs are added, and as a result, the cost of the active matrix substrate is very high. In addition, most of the thin film formed for TFT fabrication is removed and discarded, which wastes global resources. In addition, a lot of energy and etching gas and chemicals are used for the discarded portion. And had a great impact on the global environment.
【０００７】本発明は、前記従来の問題を解決するた
め、付加価値の高いＴＦＴや半導体回路を第１の基板に
複数作り、第二の基板の必要部分に移載することによ
り、アクティブマトリクス基板のコストを下げ、部材や
エネルギーの無駄を低減したアクティブマトリクス基板
とそれを用いた表示装置およびその製造方法を提供する
ことを目的とする。[0007] In order to solve the above-mentioned conventional problems, the present invention is to form a plurality of high value-added TFTs and semiconductor circuits on a first substrate and transfer them to a required portion of a second substrate, thereby forming an active matrix substrate. It is an object of the present invention to provide an active matrix substrate in which the cost of the device is reduced, waste of members and energy is reduced, a display device using the same, and a method of manufacturing the same.
【０００８】[0008]
【課題を解決するための手段】この目的を達成するため
に本発明のアクティブマトリクス基板は、第一の基板上
に形成された複数の薄膜トランジスタまたは回路素子群
と、前記複数の薄膜トランジスタまたは回路素子群の一
部を積載するための第二の基板と、前記第二の基板上の
パターニングされた薄膜とを含むことを特徴とする。In order to achieve this object, an active matrix substrate according to the present invention comprises a plurality of thin film transistors or circuit element groups formed on a first substrate, and the plurality of thin film transistor or circuit element groups. And a patterned thin film on the second substrate.
【０００９】前記第二の基板上のパターニングされた薄
膜は、導電体と絶縁体とからなることが好ましい。It is preferable that the patterned thin film on the second substrate comprises a conductor and an insulator.
【００１０】前記第一の基板が、ガラス基板、石英基板
およびシリコン単結晶基板から選ばれる少なくとも一つ
であることが好ましい。It is preferable that the first substrate is at least one selected from a glass substrate, a quartz substrate, and a silicon single crystal substrate.
【００１１】また前記第二の基板がガラス基板またはプ
ラスチック基板であることが好ましい。It is preferable that the second substrate is a glass substrate or a plastic substrate.
【００１２】また前記第二の基板上には金属配線パター
ンと所定の場所に通電により発熱する抵抗パターンが設
けられていることが好ましい。It is preferable that a metal wiring pattern and a resistance pattern which generates heat when energized are provided at a predetermined location on the second substrate.
【００１３】また、前記第二の基板に転写された薄膜ト
ランジスタまたは回路素子群と、前記第二の基板と薄膜
トランジスタまたは回路素子群上の絶縁膜と、前記絶縁
膜の所定の部分に形成されたコンタクトホールと、金属
配線とからなることが好ましい。A thin film transistor or a circuit element group transferred to the second substrate; an insulating film on the second substrate and the thin film transistor or the circuit element group; and a contact formed on a predetermined portion of the insulating film. It is preferable to include a hole and a metal wiring.
【００１４】次に本発明の第１番目のアクティブマトリ
クス基板の製造方法は、複数の薄膜トランジスタまたは
回路素子群を形成した第一の基板から前記複数の薄膜ト
ランジスタまたは回路素子群の一部を第二の基板上に移
動させることを特徴とする。Next, in a first method of manufacturing an active matrix substrate according to the present invention, a part of the plurality of thin film transistors or circuit element groups is formed from a first substrate on which a plurality of thin film transistors or circuit element groups are formed by a second method. It is characterized in that it is moved onto a substrate.
【００１５】次に本発明の第２番目のアクティブマトリ
クス基板の製造方法は、複数の薄膜トランジスタまたは
回路素子群を形成した第一の基板から前記複数の薄膜ト
ランジスタまたは回路素子群の一部を第三の基板を介し
て第二の基板上に移動させることを特徴とする。Next, in a second method of manufacturing an active matrix substrate according to the present invention, a part of the plurality of thin film transistors or circuit element groups is converted from a first substrate on which a plurality of thin film transistors or circuit element groups are formed to a third method. It is characterized in that it is moved onto a second substrate via the substrate.
【００１６】次に本発明の第３番目のアクティブマトリ
クス基板の製造方法は、第一の基板上に形成した複数の
薄膜トランジスタまたは回路素子群を所定の単位毎に剥
離可能とした上で、第二の基板に移動させることを特徴
とする。Next, a third method of manufacturing an active matrix substrate according to the present invention comprises the steps of: separating a plurality of thin film transistors or circuit element groups formed on the first substrate into predetermined units; Characterized by being moved to a substrate.
【００１７】前記第１〜３番目の方法においては、第一
の基板がガラス基板または石英基板またはシリコン単結
晶基板であることが好ましい。In the first to third methods, it is preferable that the first substrate is a glass substrate, a quartz substrate, or a silicon single crystal substrate.
【００１８】また前記方法においては、第二の基板がガ
ラス基板またはプラスチック基板であることが好まし
い。In the above method, the second substrate is preferably a glass substrate or a plastic substrate.
【００１９】また前記方法においては、第三の基板上の
第一の接着樹脂により第一の基板に形成した複数の薄膜
トランジスタまたは回路素子群を転写し、第二の基板上
に形成した第二の接着樹脂により第三の基板上の複数の
薄膜トランジスタまたは回路素子群の一部を第二の基板
上に転写することが好ましい。In the above method, the plurality of thin film transistors or circuit element groups formed on the first substrate are transferred by the first adhesive resin on the third substrate, and the second group formed on the second substrate is transferred. It is preferable that a part of the plurality of thin film transistors or circuit element groups on the third substrate be transferred onto the second substrate by an adhesive resin.
【００２０】また前記方法においては、第三の基板はプ
ラスチックフィルムからなることが好ましい。In the above method, the third substrate is preferably made of a plastic film.
【００２１】また前記方法においては、第一の接着樹脂
は熱可塑性であり、第二の接着樹脂は熱硬化性であるこ
とが好ましい。In the above method, it is preferable that the first adhesive resin is thermoplastic and the second adhesive resin is thermosetting.
【００２２】また前記方法においては、第三の基板は液
体または気体を通す機能を有することが好ましい。In the above method, the third substrate preferably has a function of passing a liquid or a gas.
【００２３】また前記方法においては、第二の基板上に
は金属配線パターンと所定の場所に通電により発熱する
抵抗パターンを設けることが好ましい。In the above method, it is preferable that a metal wiring pattern and a resistance pattern which generates heat when energized are provided on a predetermined position on the second substrate.
【００２４】また前記方法においては、第二の基板に転
写された薄膜トランジスタまたは回路素子群と、前記第
二の基板と薄膜トランジスタまたは回路素子群上の絶縁
膜と、前記絶縁膜の所定の部分に形成されたコンタクト
ホールと、金属配線とからなることが好ましい。In the above method, the thin film transistor or the circuit element group transferred to the second substrate, the insulating film on the second substrate and the thin film transistor or the circuit element group, and the insulating film formed on a predetermined portion of the insulating film may be formed. It is preferable that the contact hole and the metal wiring are formed.
【００２５】次に本発明の表示装置は、第一の基板上に
形成された複数の薄膜トランジスタまたは回路素子群
と、前記複数の薄膜トランジスタまたは回路素子群の一
部を積載する第二の基板と、前記第二の基板上のパター
ニングされた薄膜とからなることを特徴とする。Next, the display device of the present invention comprises a plurality of thin film transistors or circuit element groups formed on a first substrate, and a second substrate on which a part of the plurality of thin film transistor or circuit element groups is mounted. And a patterned thin film on the second substrate.
【００２６】以上説明したとおり、第一の基板上に高密
度にＴＦＴや回路素子群を形成し、これらのＴＦＴや回
路素子群を個別に第二の基板に移載するという構成を有
している。As described above, there is a configuration in which TFTs and circuit element groups are formed on the first substrate at high density, and these TFTs and circuit element groups are individually transferred to the second substrate. I have.
【００２７】[0027]
【発明の実施の形態】（実施の形態１）以下、本発明の
実施の形態について図面を参照しながら説明する。まず
第一の基板と第二の基板の作製方法を説明する。図１は
第一の基板上に作成されたＴＦＴを示している。ＴＦＴ
そのものの構成は図８と同じであるが、基板３１上には
犠牲層３２とアンダーコート層３３を、またＴＦＴ上部
にはパッシベーション層３４を形成している。例えば、
犠牲層３２には非晶質シリコン、金属材料や予めイオン
注入などで改質した層を用い、アンダーコート層３３に
は酸化シリコンを、パッシベーション層３４には窒化シ
リコンを用いる。３５は各ＴＦＴを分離して剥離するた
めに設けた薄膜除去部分である。(Embodiment 1) Hereinafter, embodiments of the present invention will be described with reference to the drawings. First, a method for manufacturing the first substrate and the second substrate will be described. FIG. 1 shows a TFT formed on a first substrate. TFT
The structure is the same as that of FIG. 8, except that a sacrificial layer 32 and an undercoat layer 33 are formed on a substrate 31, and a passivation layer 34 is formed on the TFT. For example,
Amorphous silicon, a metal material or a layer modified in advance by ion implantation or the like is used for the sacrifice layer 32, silicon oxide is used for the undercoat layer 33, and silicon nitride is used for the passivation layer. Reference numeral 35 denotes a thin film removed portion provided for separating and separating each TFT.
【００２８】図２は図１の基板の平面図であり、第一の
基板上にはＴＦＴの一単位３６−１，２，３をプロセス
ルールの許容範囲で数多く形成する。FIG. 2 is a plan view of the substrate shown in FIG. 1. On the first substrate, a number of TFT units 36-1, 2, 3 are formed within the allowable range of the process rules.
【００２９】図３は第二の基板の平面図であり、配線パ
ターンをあらかじめ形成しておく。この実施例の場合、
ソース配線３７とゲート配線の一部３９をあらかじめ形
成している。３８は後述する熱発生部分である。FIG. 3 is a plan view of the second substrate, in which a wiring pattern is formed in advance. In this example,
The source wiring 37 and a part 39 of the gate wiring are formed in advance. Numeral 38 is a heat generating portion described later.
【００３０】次に、第一の基板から第二の基板にＴＦＴ
を移載する方法を図４〜６のプロセス工程図を用いて説
明する。Next, the TFT is transferred from the first substrate to the second substrate.
Will be described with reference to the process step diagrams of FIGS.
【００３１】図４(a)において、４１は第三の基板であ
り、この例の場合プラスチック基板を用いる。４２は熱
可塑性の接着層である。第三の基板にはエッティング用
のガスや薬液が侵入可能な穴４３が開いている。第三の
基板に図1の第二の基板上のＴＦＴを加熱圧接し、第二
の基板と第三の基板を接着した状態（図４(b)）で、犠
牲層３２を全面エッティング除去する。犠牲層３２が非
晶質シリコンの場合は水素ラジカルやＮＦ3やＳＦ6など
のラジカルまたはフッ酸と硝酸の混合液を用いる。上記
の処理によりＴＦＴは第一の基板から剥離できる（図４
（ｃ））。In FIG. 4A, reference numeral 41 denotes a third substrate. In this example, a plastic substrate is used. 42 is a thermoplastic adhesive layer. The third substrate is provided with a hole 43 through which an etching gas or a chemical solution can enter. The TFT on the second substrate of FIG. 1 is heated and pressed against the third substrate to bond the second substrate and the third substrate (FIG. 4 (b)). I do. When the sacrificial layer 32 is made of amorphous silicon, a hydrogen radical, a radical such as NF 3 or SF 6 , or a mixed solution of hydrofluoric acid and nitric acid is used. By the above processing, the TFT can be peeled off from the first substrate (FIG. 4).
(C)).
【００３２】次に、図５(a)の第二の基板４４上の所定
の領域には熱硬化性の接着剤４５を塗布しておき、第二
の基板と第三の基板を圧接加熱した後、二つの基板を分
離すると、ＴＦＴは第二の基板へ移載される（図５
(b)）。加熱は基板全面しても良いし、図３に示した抵
抗体部分３８に電流を流し発熱させても構わない。Next, a thermosetting adhesive 45 is applied to a predetermined area on the second substrate 44 in FIG. 5A, and the second substrate and the third substrate are pressed and heated. Thereafter, when the two substrates are separated, the TFT is transferred to the second substrate (FIG. 5).
(b)). Heating may be performed on the entire surface of the substrate, or heat may be generated by applying a current to the resistor portion 38 shown in FIG.
【００３３】次に、パッシベーション層５１を再度形成
しコンタクトホール５２を形成後（図６(a)）、配線間
をつなぐ金属配線５３パターンを形成する（図６
(b)）。パッシベーション層５１を形成する工程は、第
二の基板上に予めパッシベーション層を形成しておくこ
とで省略することが可能である。また、配線間をつなぐ
金属パターンを先に形成した後、パッシベーション層を
形成しても構わない。その場合、ＴＦＴのドレイン部分
のみパッシベーション層にコンタクトホールを形成し、
画素電極を形成してもよい。また、第二の基板はガラス
でもプラスチックでも、表面が平滑であれば材料を選ば
ない。Next, after the passivation layer 51 is formed again and the contact holes 52 are formed (FIG. 6A), a metal wiring 53 pattern connecting the wirings is formed (FIG. 6).
(b)). The step of forming the passivation layer 51 can be omitted by forming the passivation layer on the second substrate in advance. Further, a passivation layer may be formed after a metal pattern connecting the wirings is formed first. In that case, a contact hole is formed in the passivation layer only in the drain portion of the TFT,
A pixel electrode may be formed. Further, the material of the second substrate is not limited to glass or plastic as long as the surface is smooth.
【００３４】（実施の形態２）第２の実施例として、回
路素子群を移載する例を説明する。図７はＳｉ単結晶ウ
ェハー上に形成された回路素子群７２を示している。回
路素子群としてはドライバーＩＣ、コントローラーＩ
Ｃ、ＲＡＭやＣＰＵなどの集積回路である。これらの回
路素子群を例えば図１の方法で第二の基板４４に移載す
る。例として、表示装置であるなら、画素の部分は第一
の実施例のように形成し、周辺にこれらの回路素子群を
移載すると良い。ＴＦＴや回路素子群はガラス基板上の
低温ポリシリコンＴＦＴを構成要素とするものでも構わ
ない。上記構成のアクティブマトリクス基板と液晶セル
や有機ＥＬなどの光強度を制御する素子と組み合わせる
ことによりシステムディスプレイを簡単にかつ低コスト
で作る事が出来る。この様なシステムディスプレイの応
用としては、携帯電話やＰＤＡ(personal digital assi
stance)等の携帯情報端末向けの表示装置があり小型・
軽量・薄型化がはかれる。また、シート状のパーソナル
コンピュータ、液晶テレビ、ノートパソコン用表示装置
や液晶モニターなどにも適用できる。いずれもさらに薄
く高機能な表示装置を実現できる。さらに、反射型の液
晶ディスプレイや有機ＥＬを用いた表示装置の場合、第
二の基板の裏面にも上記方法にて回路素子群を形成可能
であるから、より高機能化をはかれる。例えば、第二の
基板の表面は画素を駆動するＴＦＴと配線だけ形成し、
裏面にドライバーＩＣ、コントローラーＩＣやＲＡＭ等
を形成すると、薄型で究極の狭額縁を具現した表示装置
も作製可能となる。(Embodiment 2) As a second embodiment, an example of transferring a circuit element group will be described. FIG. 7 shows a circuit element group 72 formed on a Si single crystal wafer. Driver IC, Controller I
C, an integrated circuit such as a RAM or a CPU. These circuit element groups are transferred to the second substrate 44 by, for example, the method of FIG. As an example, in the case of a display device, it is preferable to form a pixel portion as in the first embodiment, and transfer these circuit element groups to the periphery. The TFT and the circuit element group may be a low-temperature polysilicon TFT on a glass substrate as a constituent element. By combining the active matrix substrate having the above configuration with an element for controlling light intensity such as a liquid crystal cell or an organic EL, a system display can be easily and at low cost. Applications of such a system display include a mobile phone and a PDA (personal digital assi
stance) for portable information terminals.
Lightweight and thinner. Further, the present invention can be applied to a sheet-shaped personal computer, a liquid crystal television, a display device for a notebook computer, a liquid crystal monitor, and the like. In each case, a thinner and more sophisticated display device can be realized. Further, in the case of a display device using a reflection type liquid crystal display or an organic EL, since the circuit element group can be formed on the back surface of the second substrate by the above-described method, higher functions can be achieved. For example, on the surface of the second substrate, only TFTs for driving pixels and wiring are formed,
When a driver IC, a controller IC, a RAM, and the like are formed on the back surface, a display device that is thin and realizes an ultimate narrow frame can be manufactured.
【００３５】以上のように本発明の実施の形態によれ
ば、付加価値の高いＴＦＴや半導体回路群を第１の基板
に無数に作り、第二の基板の必要部分に移載することに
よりアクティブマトリクス基板の原価を大幅に減らすこ
とが出来るとともに、部材やエネルギーの無駄を大幅に
低減出来る。また、第一の基板や第三の基板は再利用可
能であり、この面でもコスト低減や地球環境の面で多大
な寄与をする。さらに、第一の基板のサイズと第二の基
板のサイズは異なり、例えば第一の基板を既存の生産ラ
インで作製し、工程の少ない第二の基板の生産ラインを
新しい生産ラインを用いるなどすると大画面の表示装置
の実現も少ない設備投資額や少ない人員で可能となる。As described above, according to the embodiment of the present invention, an infinite number of TFTs and semiconductor circuits having a high added value are formed on the first substrate and transferred to necessary parts of the second substrate, thereby enabling active circuits. The cost of the matrix substrate can be significantly reduced, and the waste of members and energy can be significantly reduced. In addition, the first substrate and the third substrate can be reused, which also contributes greatly to cost reduction and global environment. Furthermore, the size of the first substrate and the size of the second substrate are different, for example, when the first substrate is manufactured on an existing production line, and the production line of the second substrate with few steps is used on a new production line. The realization of a large-screen display device is also possible with a small capital investment and a small number of personnel.
【００３６】[0036]
【発明の効果】以上のように本発明は、第一の基板上に
高密度に形成したＴＦＴまたは回路素子群を第二の基板
に移載するという方法をとることにより、低コストのア
クティブマトリクス基板実現することが出来きる。さら
に限られた資源の有効活用もできる。これを用いること
により高い表示装置や撮像装置を実現できる。As described above, the present invention provides a low-cost active matrix by transferring TFTs or circuit elements formed on a first substrate at high density to a second substrate. Substrate can be realized. In addition, limited resources can be used effectively. By using this, a high display device or an imaging device can be realized.
【図１】本発明の実施の形態１における第一の基板の断
面図FIG. 1 is a cross-sectional view of a first substrate according to Embodiment 1 of the present invention.
【図２】本発明の実施の形態１における第一の基板の平
面図FIG. 2 is a plan view of a first substrate according to the first embodiment of the present invention.
【図３】本発明の実施の形態１における第二の基板の平
面図FIG. 3 is a plan view of a second substrate according to the first embodiment of the present invention.
【図４】（ａ）〜（ｃ）は本発明の実施の形態１におけ
るアクティブマトリクス基板の製造工程を示す断面図FIGS. 4A to 4C are cross-sectional views illustrating a manufacturing process of the active matrix substrate according to the first embodiment of the present invention.
【図５】（ａ）〜（ｂ）は同製造工程を示す断面図FIGS. 5A and 5B are cross-sectional views showing the same manufacturing process.
【図６】（ａ）〜（ｂ）は同製造工程を示す断面図FIGS. 6A and 6B are cross-sectional views showing the same manufacturing process.
【図７】本発明の実施の形態２のＳｉウェハー上の回路
素子群を示す平面図FIG. 7 is a plan view showing a circuit element group on a Si wafer according to a second embodiment of the present invention.
【図８】従来のアクティブマトリクス基板の断面図FIG. 8 is a cross-sectional view of a conventional active matrix substrate.
【図９】従来のアクティブマトリクス基板の平面図FIG. 9 is a plan view of a conventional active matrix substrate.
【図１０】図９のアクティブマトリクス基板の等価回路
図FIG. 10 is an equivalent circuit diagram of the active matrix substrate of FIG. 9;
３１ 第一の基板 ３２ 犠牲層 ３３ アンダーコート層 ３４ パッシベーション層 ４１ 第三の基板 ４２ 熱可塑性接着剤 ４３ エッティング用ガスまたは薬液の透過する穴 ４４ 第二の基板 ４５ 熱硬化性接着剤 ５１ パッシベーション層 ５２ コンタクトホール ５３ 金属配線 ７１ Ｓｉ単結晶基板 ７２ 回路素子群 DESCRIPTION OF SYMBOLS 31 First substrate 32 Sacrificial layer 33 Undercoat layer 34 Passivation layer 41 Third substrate 42 Thermoplastic adhesive 43 Hole through which etching gas or chemical solution passes 44 Second substrate 45 Thermosetting adhesive 51 Passivation layer 52 contact hole 53 metal wiring 71 Si single crystal substrate 72 circuit element group
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｇ０９Ｆ 9/30 ３１０ Ｇ０９Ｆ 9/30 ３３８ ３３８ ３４８Ａ ３４８ Ｈ０１Ｌ 27/12 Ｂ Ｈ０１Ｌ 27/12 29/78 ６２７Ｄ 29/786 ６２６Ｃ Ｆターム(参考） 2H090 JB02 JB03 JB04 2H092 GA29 JA24 MA12 NA29 PA01 5C094 AA43 AA44 AA45 BA03 CA19 DA15 FB01 5F110 AA30 BB01 CC07 DD01 DD02 DD12 DD13 DD17 DD25 EE03 EE04 EE14 EE44 FF30 GG02 GG13 GG15 GG35 GG45 HK03 HK04 HK09 HK16 HK22 HK25 HK33 HK35 QQ16 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) G09F 9/30 310 G09F 9/30 338 338 348A 348 H01L 27/12 B H01L 27/12 29/78 627D 29 / 786 626C F-term (Reference) 2H090 JB02 JB03 JB04 2H092 GA29 JA24 MA12 NA29 PA01 5C094 AA43 AA44 AA45 BA03 CA19 DA15 FB01 5F110 AA30 BB01 CC07 DD01 DD02 DD12 DD13 DD17 DD25 EE03 GG04 FF30 GG03 HK22 HK25 HK33 HK35 QQ16
Claims (18)
ランジスタまたは回路素子群と、前記複数の薄膜トラン
ジスタまたは回路素子群の一部を積載するための第二の
基板と、前記第二の基板上のパターニングされた薄膜と
を含むアクティブマトリクス基板。1. A plurality of thin film transistors or circuit element groups formed on a first substrate, a second substrate for mounting a part of the plurality of thin film transistors or circuit element groups, and the second substrate An active matrix substrate comprising: a patterned thin film thereon;
薄膜は、導電体と絶縁体とからなる請求項１に記載のア
クティブマトリクス基板。2. The active matrix substrate according to claim 1, wherein the patterned thin film on the second substrate comprises a conductor and an insulator.
よびシリコン単結晶基板から選ばれる少なくとも一つで
ある請求項1または２に記載のアクティブマトリクス基
板。3. The active matrix substrate according to claim 1, wherein the first substrate is at least one selected from a glass substrate, a quartz substrate, and a silicon single crystal substrate.
ック基板である請求項1または２に記載のアクティブマ
トリクス基板。4. The active matrix substrate according to claim 1, wherein the second substrate is a glass substrate or a plastic substrate.
定の場所に通電により発熱する抵抗パターンが設けられ
ている請求項１，２または４に記載のアクティブマトリ
クス基板。5. The active matrix substrate according to claim 1, wherein a metal wiring pattern and a resistance pattern that generates heat when energized are provided at predetermined locations on the second substrate.
タまたは回路素子群と、前記第二の基板と薄膜トランジ
スタまたは回路素子群上の絶縁膜と、前記絶縁膜の所定
の部分に形成されたコンタクトホールと、金属配線とか
らなる請求項１，２，４または５に記載のアクティブマ
トリクス基板。6. A thin film transistor or circuit element group transferred to a second substrate, an insulating film on the second substrate and the thin film transistor or circuit element group, and a contact hole formed in a predetermined portion of the insulating film. 6. The active matrix substrate according to claim 1, comprising a metal wiring.
群を形成した第一の基板から前記複数の薄膜トランジス
タまたは回路素子群の一部を第二の基板上に移動させる
ことを特徴とするアクティブマトリクス基板の製造方
法。7. A method of manufacturing an active matrix substrate, comprising: moving a part of the plurality of thin film transistors or circuit element groups onto a second substrate from a first substrate on which a plurality of thin film transistors or circuit element groups are formed. Method.
群を形成した第一の基板から前記複数の薄膜トランジス
タまたは回路素子群の一部を第三の基板を介して第二の
基板上に移動させることを特徴とするアクティブマトリ
クス基板の製造方法。8. A method according to claim 1, wherein a portion of the plurality of thin film transistors or circuit element groups is moved from a first substrate on which a plurality of thin film transistors or circuit element groups are formed to a second substrate via a third substrate. Of manufacturing an active matrix substrate.
ンジスタまたは回路素子群を所定の単位毎に剥離可能と
した上で、第二の基板に移動させることを特徴とするア
クティブマトリクス基板の製造方法。9. A method for manufacturing an active matrix substrate, wherein a plurality of thin film transistors or circuit element groups formed on a first substrate can be peeled off in predetermined units and then moved to a second substrate. Method.
板またはシリコン単結晶基板である請求項７〜９のいず
れかに記載のアクティブマトリクス基板の製造方法。10. The method for manufacturing an active matrix substrate according to claim 7, wherein the first substrate is a glass substrate, a quartz substrate, or a silicon single crystal substrate.
チック基板である請求項７〜９のいずれかに記載のアク
ティブマトリクス基板の製造方法。11. The method for manufacturing an active matrix substrate according to claim 7, wherein the second substrate is a glass substrate or a plastic substrate.
第一の基板に形成した複数の薄膜トランジスタまたは回
路素子群を転写し、第二の基板上に形成した第二の接着
樹脂により第三の基板上の複数の薄膜トランジスタまた
は回路素子群の一部を第二の基板上に転写する請求項８
に記載のアクティブマトリクス基板の製造方法。12. A plurality of thin film transistors or circuit element groups formed on a first substrate are transferred by a first adhesive resin on a third substrate, and are transferred by a second adhesive resin formed on a second substrate. 9. The method according to claim 8, wherein a part of the plurality of thin film transistors or circuit element groups on the third substrate is transferred onto the second substrate.
3. The method for manufacturing an active matrix substrate according to 1.
らなる請求項８または１２に記載のアクティブマトリク
ス基板の製造方法。13. The method according to claim 8, wherein the third substrate is made of a plastic film.
二の接着樹脂は熱硬化性である請求項１２に記載のアク
ティブマトリクス基板の製造方法。14. The method according to claim 12, wherein the first adhesive resin is thermoplastic and the second adhesive resin is thermosetting.
能を有する請求項８、１２または１３に記載のアクティ
ブマトリクス基板の製造方法。15. The method for manufacturing an active matrix substrate according to claim 8, wherein the third substrate has a function of passing a liquid or a gas.
所定の場所に通電により発熱する抵抗パターンを設ける
請求項７〜９のいずれかに記載のアクティブマトリクス
基板の製造方法。16. The method for manufacturing an active matrix substrate according to claim 7, wherein a metal wiring pattern and a resistance pattern which generates heat by energization are provided at predetermined locations on the second substrate.
スタまたは回路素子群と、前記第二の基板と薄膜トラン
ジスタまたは回路素子群上の絶縁膜と、前記絶縁膜の所
定の部分に形成されたコンタクトホールと、金属配線と
からなる請求項７〜９のいずれかに記載のアクティブマ
トリクス基板の製造方法。17. A thin film transistor or circuit element group transferred to a second substrate, an insulating film on the second substrate and the thin film transistor or circuit element group, and a contact hole formed in a predetermined portion of the insulating film. 10. The method of manufacturing an active matrix substrate according to claim 7, comprising: a metal wiring.
トランジスタまたは回路素子群と、前記複数の薄膜トラ
ンジスタまたは回路素子群の一部を積載する第二の基板
と、前記第二の基板上のパターニングされた薄膜とから
なるアクティブマトリクス基板を用いた表示装置。18. A plurality of thin film transistors or circuit element groups formed on a first substrate, a second substrate on which a part of the plurality of thin film transistors or circuit element groups are mounted, and A display device using an active matrix substrate composed of a patterned thin film.
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|---|---|---|---|
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|---|---|---|---|
| JP2001154590A JP2002353235A (en) | 2001-05-23 | 2001-05-23 | Active matrix substrate, display using the same, and its manufacturing method |
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