JP2002314079A - Mosfet - Google Patents

Mosfet

Info

Publication number
JP2002314079A
JP2002314079A JP2001115266A JP2001115266A JP2002314079A JP 2002314079 A JP2002314079 A JP 2002314079A JP 2001115266 A JP2001115266 A JP 2001115266A JP 2001115266 A JP2001115266 A JP 2001115266A JP 2002314079 A JP2002314079 A JP 2002314079A
Authority
JP
Japan
Prior art keywords
pad electrode
electrode
sense
gate
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001115266A
Other languages
Japanese (ja)
Inventor
Shin Oikawa
慎 及川
Hiroki Eto
弘樹 江藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2001115266A priority Critical patent/JP2002314079A/en
Publication of JP2002314079A publication Critical patent/JP2002314079A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7815—Vertical DMOS transistors, i.e. VDMOS transistors with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To solve such problems in a MOSFET with a sense terminal that an actual operating region is reduced and that wirings are complex. SOLUTION: A sense pad electrode 3 is formed near a gate pad electrode 1 in the same area as the gate pad electrode 1. This enables to use a bonding wire 10 having the same diameter as the gate pad electrode 1 and thus facilitates wiring to an IC without changing assembling work efficiency. Further, this minimizes the ineffective region of an actual operating region 5 to suppress the resistance component of polysilicon for connecting the gate pad electrode 1 to the sense pad electrode 3 to thereby prevent a shift in ON timing.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明はＭＯＳＦＥＴに係
り、特にセンス端子付きＭＯＳＦＥＴのオン抵抗の低減
と配線作業効率の向上を実現するＭＯＳＦＥＴに関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOSFET, and more particularly, to a MOSFET which realizes a reduction in on-resistance of a MOSFET with a sense terminal and an improvement in wiring work efficiency.

【０００２】[0002]

【従来の技術】情報化社会の進展に伴い、一般家庭を含
め電子機器は著しく普及し、スイッチング電源は小型で
低損失のため、ほとんどの電子機器に利用されている。
このため、最近の電子機器の多様化は電源に対する要求
をますます複雑なものにしており、特にスイッチング電
源のワンチップ化は電源の究極の課題と考えられる。ス
イッチング電源の小型化を達成するための基本的手段と
しては、スイッチング周波数の高周波化、損失の低減、
部品数の低減と機能化がある。これらの手段により実際
に製品化を行うには、低コスト化の厳しい関門を通らな
ければならず、それには量産化に適する方式であること
が条件となる。2. Description of the Related Art With the progress of the information-oriented society, electronic devices including ordinary households have become extremely popular, and switching power supplies have been used in almost all electronic devices because of their small size and low loss.
For this reason, the recent diversification of electronic devices has made the demands for power supplies more and more complicated. In particular, the one-chip switching power supply is considered to be the ultimate task of the power supply. Basic means for achieving the miniaturization of the switching power supply include higher switching frequency, lower loss,
There is a reduction in the number of parts and functionalization. In order to actually commercialize the product by these means, it is necessary to pass through a strict barrier to cost reduction, which requires a method suitable for mass production.

【０００３】また、省エネルギーの立場から、火をいれ
たままスタンバイ状態にあるときの電力、すなわちホッ
トスタンバイ電力は小さいことが必要で、できればゼロ
が望ましい。スタンバイ電力を低減するには出力に応じ
て回路の動作電力を減少させることが必要である。これ
には間欠発振の利用が一般に用いられているが、より完
全に行うには、制御電力を出力から取る、いわゆる自励
形回路の適用が有効である。自励形回路ではＲＣＣ（Ri
nging Choke Converter）がよく知られており、ＲＣ
Ｃ方式のスイッチング電源ＩＣには、多くの場合、電流
検出用のセンス端子付きＭＯＳＦＥＴが用いられてい
る。また、近年ではＲＣＣ方式のスイッチング電源ＩＣ
とセンス端子付きＭＯＳＦＥＴを2段重ねにすることに
より小型パッケージに内蔵が可能となっている。Further, from the standpoint of energy saving, it is necessary that the electric power when in the standby state with the fire on, that is, the hot standby electric power, is small, and is desirably zero if possible. To reduce the standby power, it is necessary to reduce the operating power of the circuit according to the output. The use of intermittent oscillation is generally used for this purpose, but in order to perform the operation more completely, application of a so-called self-excited circuit that takes control power from an output is effective. RCC (Ri
nging Choke Converter) is well known and RC
In many cases, a C-type switching power supply IC uses a MOSFET with a sense terminal for current detection. In recent years, RCC switching power supply ICs
By stacking two MOSFETs with a sense terminal and a MOSFET with a sense terminal, they can be built in a small package.

【０００４】図３に従来のセンス端子付きＭＯＳＦＥＴ
の上面図を示す。パワーＭＯＳＦＥＴは、ゲートパッド
電極３１と、センス部３２と、センスパッド電極３３
と、ゲート連結電極３４と、実動作領域３５と、ＭＯＳ
トランジスタのセル３６と、ソース電極３７と、シール
ド電極３８と、ソースパッド電極３９とで構成される。FIG. 3 shows a conventional MOSFET with a sense terminal.
FIG. The power MOSFET includes a gate pad electrode 31, a sense part 32, and a sense pad electrode 33.
, Gate connection electrode 34, actual operation area 35, MOS
It comprises a transistor cell 36, a source electrode 37, a shield electrode 38, and a source pad electrode 39.

【０００５】ゲートパッド電極３１は、ゲート電極と連
結し、点線の丸印で示すようにボンディングワイヤーで
電極の取り出しが行われる。[0005] The gate pad electrode 31 is connected to the gate electrode, and the electrode is taken out by a bonding wire as shown by a dotted circle.

【０００６】センス部３２は、過電流を保護するため
に、実動作領域３５上の複数のＭＯＳトランジスタを電
流検出用のセンス端子として使用し、センスパッド電極
３３にコンタクトしている。センス部３２を駆動するゲ
ート電極はＭＯＳＦＥＴ本体のゲート電極と共通である
が、チップ上でポリシリコンにより連結されている。The sense section 32 uses a plurality of MOS transistors on the actual operation area 35 as sense terminals for current detection and contacts a sense pad electrode 33 in order to protect the overcurrent. The gate electrode for driving the sense unit 32 is common to the gate electrode of the MOSFET body, but is connected by polysilicon on the chip.

【０００７】センスパッド電極３３は、電極の取り出し
にソースパッド電極のボンディングワイヤと同径のワイ
ヤを用いるため、その圧着面積に合わせてセンス部とし
て必要な面積よりも大きく形成し、点線の丸印で示すよ
うにボンディングワイヤが熱圧着される。Since the sense pad electrode 33 uses a wire having the same diameter as the bonding wire of the source pad electrode for taking out the electrode, the sense pad electrode 33 is formed to have a larger area than that required for the sense portion in accordance with the pressure bonding area, and is indicated by a dotted circle. The bonding wire is thermocompression-bonded as shown by.

【０００８】ゲート連結電極３４は、各セル３６のゲー
ト電極と接続され且つ実動作領域３５の周囲に配置され
ている。The gate connection electrode 34 is connected to the gate electrode of each cell 36 and is arranged around the actual operation area 35.

【０００９】実動作領域３５は、この中にパワーＭＯＳ
ＦＥＴを構成する多数のＭＯＳトランジスタのセル３６
が配列されている。The actual operation area 35 includes a power MOS
Many MOS transistor cells 36 constituting an FET
Are arranged.

【００１０】ソース電極３７は、実動作領域３５上に設
けられ且つ各セル３６のソース領域と接続して設けられ
る。The source electrode 37 is provided on the actual operation area 35 and connected to the source area of each cell 36.

【００１１】シールド電極３８は、その下に設けられた
アニュラーリングとコンタクトして、チップ終端への空
乏層の拡がりを抑える。The shield electrode 38 is in contact with an annular ring provided thereunder to prevent the depletion layer from spreading to the end of the chip.

【００１２】ソースパッド電極３９は、ソース電極３７
に接続され、電流容量を稼ぐため、点線の丸印で示すよ
うに直径１５０μｍのアルミ線等の径の大きいボンディ
ングワイヤが熱圧着され、電極の取り出しを行う。The source pad electrode 39 is
In order to increase the current capacity, a bonding wire having a large diameter such as an aluminum wire having a diameter of 150 μm or the like is thermocompression-bonded as shown by a dotted circle to take out an electrode.

【００１３】図４に、トレンチ型の各セル３６の断面構
造を示す。ＮチャンネルのパワーＭＯＳＦＥＴにおいて
は、Ｎ+型の半導体基板４１の上にＮ-型のエピタキシャ
ル層からなるドレイン領域４２を設け、その上にＰ型の
チャネル層４３を設ける。チャネル層４３からドレイン
領域４２まで到達するトレンチ４４を作り、トレンチ４
４の内壁をゲート酸化膜４５で被膜し、トレンチ４４に
充填されたポリシリコンよりなるゲート電極４６を設け
て各セル３６を形成する。トレンチ４４に隣接したチャ
ネル層４３表面にはＮ+型のソース領域４８が形成さ
れ、隣り合う２つのセルのソース領域４８間のチャネル
層４３表面にはＰ+型のボディコンタクト領域４９が形
成される。さらにチャネル層４３にはソース領域４８か
らトレンチ４４に沿ってチャネル領域４７が形成され
る。トレンチ４４上は層間絶縁膜５０で覆い、ソース領
域４８およびボディコンタクト領域４９にコンタクトす
るソース電極３４を設ける。チップ全面を覆って設けた
表面保護膜５１に開口部を設けて、ゲートパッド電極お
よびセンスパッド電極、ソースパッド電極（図示せず）
を形成する。かかるセル３６は図３の実動作領域５に多
数個配列される。具体的には小さい四角で表示したもの
が１個のセルである。FIG. 4 shows a sectional structure of each trench-type cell 36. In the N-channel power MOSFET, a drain region 42 made of an N − -type epitaxial layer is provided on an N + -type semiconductor substrate 41, and a P-type channel layer 43 is provided thereon. A trench 44 extending from the channel layer 43 to the drain region 42 is formed.
4 is coated with a gate oxide film 45, and a gate electrode 46 made of polysilicon filled in the trench 44 is provided to form each cell 36. An N + type source region 48 is formed on the surface of the channel layer 43 adjacent to the trench 44, and a P + type body contact region 49 is formed on the surface of the channel layer 43 between the source regions 48 of two adjacent cells. You. Further, a channel region 47 is formed in the channel layer 43 from the source region 48 along the trench 44. The trench 44 is covered with an interlayer insulating film 50, and a source electrode 34 that contacts a source region 48 and a body contact region 49 is provided. Openings are provided in the surface protection film 51 provided so as to cover the entire surface of the chip, and gate pad electrodes, sense pad electrodes, and source pad electrodes (not shown) are provided.
To form Many such cells 36 are arranged in the actual operation area 5 of FIG. Specifically, one cell is represented by a small square.

【００１４】[0014]

【発明が解決しようとする課題】かかる従来のセンス付
きパワーＭＯＳＦＥＴでは、センスパッド電極に接続す
るボンディングワイヤをソース電極に接続するボンディ
ングワイヤと同じものを使用するため、ＭＯＳＦＥＴの
組立作業効率上ソースパッド電極近くに設けられてい
る。しかし、チップオンチップ構造でＩＣと接続し、小
型パッケージに内蔵する場合に、配線が交差して複雑化
していた。In such a conventional power MOSFET with sense, the same bonding wire connected to the sense pad electrode as the bonding wire connected to the source electrode is used. It is provided near the electrode. However, when connecting to an IC in a chip-on-chip structure and incorporating it in a small package, the wiring crosses and becomes complicated.

【００１５】また、ソース側ボンディングワイヤの径
は、電流容量を稼ぐために大きくする必要があり、例え
ば１５０μｍのアルミ線などを使用していた。つまり太
いボンディングワイヤを圧着するセンスパッドは、その
圧着面積に合わせて大きくするため、センス端子として
使用する面積よりも必要以上に大きいセンスパッドとな
っていた。Further, the diameter of the source-side bonding wire must be increased in order to obtain a large current capacity. For example, a 150 μm aluminum wire has been used. In other words, the sense pad for crimping the thick bonding wire is made larger in accordance with the crimping area, so that the sense pad is unnecessarily larger than the area used as the sense terminal.

【００１６】これにより、実動作領域上での無効領域が
多くなりセル密度を稼げないため、オン抵抗が低減でき
ない要因となっていた。As a result, the number of ineffective areas on the actual operation area increases, and the cell density cannot be increased.

【００１７】[0017]

【課題を解決するための手段】本発明はかかる課題に鑑
みてなされ、多数のＭＯＳトランジスタのセルを配列し
た実動作領域と、該実動作領域上に設けられ前記ＭＯＳ
トランジスタの各セルのソース領域と接続されたソース
電極と、該ソース電極と接続したソースパッド電極と、
前記ＭＯＳトランジスタの各セルのゲート電極と接続し
たゲートパッド電極と、前記ＭＯＳトランジスタのうち
の複数のセルからなるセンス部、該センス部と接続され
前記ゲートパッド電極の近くに設けられたセンスパッド
電極と、前記ソース電極、前記ゲートパッド電極および
前記センスパッド電極にそれぞれ固着するワイヤとを具
備することを特徴とし、ゲートパッド電極近くでゲート
パッド電極に使用するボンディングワイヤと同じワイヤ
で配線するため、センスパッド電極の大きさをゲートパ
ッド電極の大きさとあわせることができる。これによ
り、組み立ての作業効率を低下させずに実動作領域の無
効領域を最小限に押さえられる。SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has been made in consideration of the above-mentioned problems, and has an actual operation area in which a large number of MOS transistor cells are arranged.
A source electrode connected to the source region of each cell of the transistor, a source pad electrode connected to the source electrode,
A gate pad electrode connected to a gate electrode of each cell of the MOS transistor; a sense unit including a plurality of cells of the MOS transistor; a sense pad electrode connected to the sense unit and provided near the gate pad electrode And a wire fixed to the source electrode, the gate pad electrode and the sense pad electrode, respectively, in order to wire with the same wire as the bonding wire used for the gate pad electrode near the gate pad electrode, The size of the sense pad electrode can be matched with the size of the gate pad electrode. Thus, the invalid area of the actual operation area can be minimized without lowering the work efficiency of the assembly.

【００１８】また、センスパッド電極とゲートパッド電
極とを近づけることにより、それらを連結しているポリ
シリコンでの抵抗成分を低減し、スイッチングのタイミ
ングのずれを低減し、高品質なセンス部を有するＭＯＳ
ＦＥＴを提供できる。Further, by bringing the sense pad electrode and the gate pad electrode close to each other, the resistance component of the polysilicon connecting them is reduced, the shift in switching timing is reduced, and a high-quality sensing portion is provided. MOS
An FET can be provided.

【００１９】[0019]

【発明の実施の形態】本発明の実施の形態を図１および
図２を参照して詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to FIGS.

【００２０】本発明のパワーＭＯＳＦＥＴの平面図を図
１に示す。FIG. 1 shows a plan view of the power MOSFET of the present invention.

【００２１】パワーＭＯＳＦＥＴは、ゲートパッド電極
１と、センス部２と、センスパッド電極３と、ゲート連
結電極４と、実動作領域５と、ＭＯＳトランジスタのセ
ル６と、ソース電極７と、シールド電極８と、ソースパ
ッド電極９と、ボンディングワイヤ１０とで構成され
る。The power MOSFET includes a gate pad electrode 1, a sense part 2, a sense pad electrode 3, a gate connection electrode 4, an actual operation area 5, a MOS transistor cell 6, a source electrode 7, and a shield electrode. 8, a source pad electrode 9, and a bonding wire 10.

【００２２】ゲートパッド電極１は、ゲート電極と連結
し、点線の丸印で示すようにボンディングワイヤ１０で
電極の取り出しが行われる。このゲートパッド電極の大
きさは、ボンディングワイヤ１０が圧着するのに必要か
つ十分な大きさとする。The gate pad electrode 1 is connected to the gate electrode, and the electrode is taken out by a bonding wire 10 as shown by a dotted circle. The size of the gate pad electrode is necessary and sufficient for the bonding wire 10 to be crimped.

【００２３】センス部２は、過電流を保護するために、
実動作領域５上の複数のＭＯＳトランジスタを電流検出
用のセンス端子として使用し、センスパッド電極３にコ
ンタクトしている。センス部２を駆動するゲート電極は
ＭＯＳＦＥＴ本体のゲート電極と共通であり、チップ上
でポリシリコンにより連結されている。The sense unit 2 is provided to protect an overcurrent
A plurality of MOS transistors on the actual operation region 5 are used as sense terminals for current detection, and are in contact with the sense pad electrode 3. The gate electrode for driving the sense unit 2 is common to the gate electrode of the MOSFET body and is connected on the chip by polysilicon.

【００２４】センスパッド電極３は、ゲートパッド電極
１の近くで、ゲートパッド電極１と同面積に表面保護膜
を開口して形成する。更に、センスパッド電極３には、
点線の丸印で示すように、ゲートパッド電極１と同じボ
ンディングワイヤ１０が熱圧着され、電極の取り出しを
行う。The sense pad electrode 3 is formed near the gate pad electrode 1 by opening a surface protective film in the same area as the gate pad electrode 1. Further, the sense pad electrode 3 has
As shown by the dotted circles, the same bonding wire 10 as the gate pad electrode 1 is thermocompression-bonded to take out the electrode.

【００２５】ゲート連結電極４は、各セル６のゲート電
極と接続され且つ実動作領域５の周囲に配置されてい
る。The gate connection electrode 4 is connected to the gate electrode of each cell 6 and is arranged around the actual operation area 5.

【００２６】実動作領域５は、この中にパワーＭＯＳＦ
ＥＴを構成する多数のＭＯＳトランジスタのセル６が配
列されている。The actual operation area 5 includes a power MOSF therein.
A large number of MOS transistor cells 6 constituting the ET are arranged.

【００２７】ソース電極７は、実動作領域５上に設けら
れ且つ各セル６のソース領域と接続して設けられる。The source electrode 7 is provided on the actual operation area 5 and connected to the source area of each cell 6.

【００２８】シールド電極８は、その下に設けられたア
ニュラーリングとコンタクトして、チップ終端への空乏
層の拡がりを抑える。The shield electrode 8 is in contact with an annular ring provided thereunder to suppress the spread of the depletion layer to the end of the chip.

【００２９】ソースパッド電極９は、ゲートパッド電極
１およびセンスパッド電極３と同じボンディングワイヤ
１０を２〜３本使用し、点線の丸印で示すように熱圧着
され、電極の取り出しを行う。The source pad electrode 9 uses two or three bonding wires 10 which are the same as the gate pad electrode 1 and the sense pad electrode 3, and is thermocompression-bonded as shown by a dotted circle to take out the electrode.

【００３０】ボンディングワイヤ１０は、直径４０μｍ
のＡｕ等の金属細線で、ゲートパッド電極１およびセン
スパッド電極３、ソースパッド電極９にそれぞれ熱圧着
される。The bonding wire 10 has a diameter of 40 μm.
Are thermocompression-bonded to the gate pad electrode 1, the sense pad electrode 3, and the source pad electrode 9, respectively.

【００３１】図２は本発明に用いるトレンチ型のセル６
の断面構造を示す。尚、図１に示すものと同一構成要素
は同一記号とする。Ｎ+型の半導体基板１１の上にＮ-型
のエピタキシャル層からなるドレイン領域１２を設け、
その上にＰ型のチャネル層１３を設ける。チャネル層１
３からドレイン領域１２まで到達するトレンチ１４を作
り、トレンチ１４の内壁をゲート酸化膜１５で被膜し、
トレンチ１４に充填されたポリシリコンよりなるゲート
電極１６を設けて各セル６を形成する。トレンチ１４に
隣接したチャネル層１３表面にはＮ+型のソース領域１
８が形成され、隣り合う２つのセルのソース領域１８間
のチャネル層１３表面にはＰ+型のボディコンタクト領
域１９が形成される。さらにチャネル層１３にはソース
領域１８からトレンチ１４に沿ってチャネル領域１７が
形成される。トレンチ１４上は層間絶縁膜２０で覆い、
ソース領域１８およびボディコンタクト領域１９にコン
タクトするソース電極７を設ける。チップ全面を覆って
設けた表面保護膜２１に開口部を設けて、ゲートパッド
電極およびセンスパッド電極、ソースパッド電極（図示
せず）を形成する。かかるセル６は図１の実動作領域５
に多数個配列される。具体的には小さい四角で表示した
ものが１個のセルである。FIG. 2 shows a trench type cell 6 used in the present invention.
1 shows a cross-sectional structure. The same components as those shown in FIG. A drain region 12 made of an N − type epitaxial layer is provided on an N + type semiconductor substrate 11,
A P-type channel layer 13 is provided thereon. Channel layer 1
3, a trench 14 reaching the drain region 12 is formed, and an inner wall of the trench 14 is coated with a gate oxide film 15,
Each cell 6 is formed by providing a gate electrode 16 made of polysilicon filling the trench 14. An N + type source region 1 is formed on the surface of the channel layer 13 adjacent to the trench 14.
8 are formed, and a P + type body contact region 19 is formed on the surface of the channel layer 13 between the source regions 18 of two adjacent cells. Further, a channel region 17 is formed in the channel layer 13 from the source region 18 along the trench 14. The trench 14 is covered with an interlayer insulating film 20,
Source electrode 7 is provided for contacting source region 18 and body contact region 19. An opening is provided in the surface protection film 21 provided to cover the entire surface of the chip, and a gate pad electrode, a sense pad electrode, and a source pad electrode (not shown) are formed. The cell 6 corresponds to the actual operation area 5 shown in FIG.
Are arranged in large numbers. Specifically, one cell is represented by a small square.

【００３２】本発明の特徴は、センスパッド電極３にあ
る。ゲートパッド電極１の近くに設けることにより、チ
ップオンチップ構造にする場合に、ＩＣとの配線が容易
になる。The feature of the present invention resides in the sense pad electrode 3. Providing near the gate pad electrode 1 facilitates wiring to an IC when a chip-on-chip structure is formed.

【００３３】また、ゲートパッド電極１とセンスパッド
電極３を同面積にすることにより、ゲートパッド電極１
に固着するボンディングワイヤ１０と同じ配線で組み立
てが可能となるので、組み立ての作業効率を低下させず
に容易にＩＣと配線できる。Further, by making the gate pad electrode 1 and the sense pad electrode 3 have the same area, the gate pad electrode 1
Since it is possible to assemble with the same wiring as the bonding wire 10 adhered to the IC, it is possible to easily wire with the IC without lowering the work efficiency of the assembling.

【００３４】更に、センス端子を駆動するゲート電極
と、ＭＯＳＦＥＴ本体のゲート電極は共通であり、それ
らをチップ上でポリシリコンにより連結して動作させる
ため、センス部２とゲートパッド電極１の距離が近くな
れば、ポリシリコンによる抵抗成分が低減されるため、
オンするタイミングの差が小さくなる。センス部２は本
体ＭＯＳＦＥＴの保護用に設けられているので、極力早
くオンする必要があり、オンするタイミングの差が縮ま
れば、センス部２としての特性も向上する。Further, the gate electrode for driving the sense terminal and the gate electrode of the MOSFET body are common, and they are connected on the chip by polysilicon to operate. Therefore, the distance between the sense section 2 and the gate pad electrode 1 is reduced. If it gets closer, the resistance component due to polysilicon will be reduced,
The difference in the ON timing is reduced. Since the sense unit 2 is provided to protect the main body MOSFET, it is necessary to turn on as soon as possible. If the difference in the timing of turning on is reduced, the characteristics of the sense unit 2 are improved.

【００３５】その上、センスパッド電極３は、径の小さ
いボンディングワイヤ１０が圧着するのに必要且つ十分
な大きさであるので、従来のセンスパッド電極を設ける
ことによる、実動作領域５の無効領域を最小限に押さえ
られるのでセル密度も向上し、オン抵抗の低減に大きく
寄与できる。In addition, since the sense pad electrode 3 is necessary and large enough for the bonding wire 10 having a small diameter to be crimped, an invalid area of the actual operation area 5 by providing the conventional sense pad electrode is provided. Is reduced to a minimum, so that the cell density is also improved, which can greatly contribute to a reduction in on-resistance.

【００３６】[0036]

【発明の効果】本発明に依れば、第１にセンスパッド電
極をゲートパッド電極の近くに設けることにより、ゲー
トパッド電極と同じ側に配線できるので、チップオンチ
ップ構造にした場合、ＩＣとの配線が容易になる。According to the present invention, first, by providing the sense pad electrode near the gate pad electrode, wiring can be performed on the same side as the gate pad electrode. Wiring becomes easy.

【００３７】第２に、ゲートパッド電極とセンスパッド
電極を同面積にすることにより、ゲートパッド電極に固
着するボンディングワイヤと同じ配線で組み立てが可能
となるので、組み立ての作業効率を低下させずに、容易
にＩＣと配線できる。Second, by making the gate pad electrode and the sense pad electrode the same area, it is possible to assemble with the same wiring as the bonding wire fixed to the gate pad electrode, without lowering the work efficiency of the assembly. , And can be easily wired to the IC.

【００３８】第３に、センス端子を駆動するゲート電極
と、ＭＯＳＦＥＴ本体のゲート電極は共通であり、それ
らをチップ上でポリシリコンにより連結して動作させる
ため、センス部とゲートパッド電極の距離が近くなれ
ば、ポリシリコンによる抵抗成分が低減されるため、オ
ンするタイミングの差が小さくなる。つまり、センス部
は本体ＭＯＳＦＥＴの保護用に設けられているので、極
力早くオンする必要があり、オンするタイミングの差が
縮まれば、センス部としての特性も向上する。Third, the gate electrode for driving the sense terminal and the gate electrode of the MOSFET body are common, and they are connected on the chip by polysilicon to operate. Therefore, the distance between the sense portion and the gate pad electrode is reduced. If the distance is closer, the resistance component due to polysilicon is reduced, and the difference in the ON timing is reduced. That is, since the sense section is provided for protecting the main body MOSFET, it is necessary to turn on as soon as possible. If the difference in the timing of turning on is reduced, the characteristics of the sense section are improved.

【００３９】第４に、センスパッド電極を設けることに
よる、実動作領域の無効領域を最小限に押さえられるの
でセル密度が向上し、オン抵抗の低減に大きく寄与でき
る。Fourth, the provision of the sense pad electrodes minimizes the ineffective area of the actual operation area, thereby improving the cell density and greatly contributing to the reduction of the on-resistance.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明のＭＯＳＦＥＴを説明する平面図であ
る。FIG. 1 is a plan view illustrating a MOSFET of the present invention.

【図２】本発明のＭＯＳＦＥＴを説明する断面図であ
る。FIG. 2 is a cross-sectional view illustrating a MOSFET according to the present invention.

【図３】従来のＭＯＳＦＥＴを説明する平面図である。FIG. 3 is a plan view illustrating a conventional MOSFET.

【図４】従来のＭＯＳＦＥＴを説明する断面図である。FIG. 4 is a cross-sectional view illustrating a conventional MOSFET.

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】多数のＭＯＳトランジスタのセルを配列し
た実動作領域と、 該実動作領域上に設けられ前記ＭＯＳトランジスタの各
セルのソース領域と接続されたソース電極と、 該ソース電極と接続したソースパッド電極と、 前記ＭＯＳトランジスタの各セルのゲート電極と接続し
たゲートパッド電極と、 前記ＭＯＳトランジスタのうちの複数のセルからなるセ
ンス部と、 該センス部と接続され前記ゲートパッド電極の近くに設
けられたセンスパッド電極と、 前記ソース電極、前記ゲートパッド電極および前記セン
スパッド電極にそれぞれ固着するワイヤとを具備するこ
とを特徴とするＭＯＳＦＥＴ。An actual operating region in which a number of MOS transistor cells are arranged; a source electrode provided on the actual operating region and connected to a source region of each cell of the MOS transistor; and a source electrode connected to the source electrode. A source pad electrode, a gate pad electrode connected to a gate electrode of each cell of the MOS transistor, a sensing unit including a plurality of cells of the MOS transistor, and a vicinity of the gate pad electrode connected to the sensing unit. A MOSFET comprising: a sense pad electrode provided; and wires fixed to the source electrode, the gate pad electrode, and the sense pad electrode, respectively. 【請求項２】前記センスパッド電極は前記ゲートパッド
電極と同面積とすることを特徴とする請求項１記載のＭ
ＯＳＦＥＴ。2. The M according to claim 1, wherein said sense pad electrode has the same area as said gate pad electrode.
OSFET. 【請求項３】前記センスパッド電極および前記ゲートパ
ッド電極はワイヤの圧着に要する面積の必要且つ十分な
大きさであることを特徴とする請求項１に記載のＭＯＳ
ＦＥＴ。3. The MOS according to claim 1, wherein the sense pad electrode and the gate pad electrode have a necessary and sufficient area for crimping a wire.
FET. 【請求項４】前記ワイヤは同径であることを特徴とする
請求項１に記載のＭＯＳＦＥＴ。4. The MOSFET according to claim 1, wherein said wires have the same diameter.
JP2001115266A 2001-04-13 2001-04-13 Mosfet Pending JP2002314079A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001115266A JP2002314079A (en) 2001-04-13 2001-04-13 Mosfet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001115266A JP2002314079A (en) 2001-04-13 2001-04-13 Mosfet

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Publication Number Publication Date
JP2002314079A true JP2002314079A (en) 2002-10-25

Family

ID=18966192

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102024812A (en) * 2009-09-16 2011-04-20 三菱电机株式会社 Semiconductor device and method of manufacturing the same
WO2011161721A1 (en) * 2010-06-24 2011-12-29 三菱電機株式会社 Power semiconductor device
US9905652B2 (en) 2016-03-15 2018-02-27 Fuji Electric Co., Ltd. Semiconductor device having varying wiring resistance
JP2020155784A (en) * 2020-06-16 2020-09-24 富士電機株式会社 Semiconductor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102024812A (en) * 2009-09-16 2011-04-20 三菱电机株式会社 Semiconductor device and method of manufacturing the same
US8278706B2 (en) 2009-09-16 2012-10-02 Mitsubishi Electric Corporation Semiconductor device and method of manufacturing the same
CN102024812B (en) * 2009-09-16 2013-01-16 三菱电机株式会社 Semiconductor device and method of manufacturing the same
WO2011161721A1 (en) * 2010-06-24 2011-12-29 三菱電機株式会社 Power semiconductor device
JP5606529B2 (en) * 2010-06-24 2014-10-15 三菱電機株式会社 Power semiconductor device
US9293572B2 (en) 2010-06-24 2016-03-22 Mitsubishi Electric Corporation Power semiconductor device
US9905652B2 (en) 2016-03-15 2018-02-27 Fuji Electric Co., Ltd. Semiconductor device having varying wiring resistance
JP2020155784A (en) * 2020-06-16 2020-09-24 富士電機株式会社 Semiconductor device
JP7052826B2 (en) 2020-06-16 2022-04-12 富士電機株式会社 Semiconductor device

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