JP2002299809A - Electronic component mounting method and equipment - Google Patents
Electronic component mounting method and equipmentInfo
- Publication number
- JP2002299809A JP2002299809A JP2001095739A JP2001095739A JP2002299809A JP 2002299809 A JP2002299809 A JP 2002299809A JP 2001095739 A JP2001095739 A JP 2001095739A JP 2001095739 A JP2001095739 A JP 2001095739A JP 2002299809 A JP2002299809 A JP 2002299809A
- Authority
- JP
- Japan
- Prior art keywords
- mounting
- circuit board
- electronic component
- adhesive
- solder paste
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
- H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体素子やチップ
部品等を回路基板に接続する電子部品の実装方法および
実装装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for mounting electronic components for connecting semiconductor elements, chip components and the like to a circuit board.
【０００２】[0002]
【従来の技術】従来、半導体素子と受動部品を１枚の回
路基板に実装して回路モジュールを作成する場合に、Ｑ
ＦＰ等に加工済みの半導体素子を使用し、はんだペース
トを回路基板に印刷転写後、半導体素子及び受動部品を
所定の位置に設置し、その後加熱炉にて一括はんだリフ
ロー工程を通し実装完了する方法が広く用いられてい
る。2. Description of the Related Art Conventionally, when a semiconductor module and a passive component are mounted on one circuit board to form a circuit module, Q
Using a semiconductor element that has been processed into FP, etc., after printing and transferring the solder paste to the circuit board, placing the semiconductor element and passive components in place, and then completing the mounting through a batch solder reflow process in a heating furnace. Is widely used.
【０００３】一方、近年電子機器には、携帯機器等に代
表される薄型化、小型化の要求が高まっており、半導体
素子のパッケージに対しても薄型化要求が強く、金属リ
ードフレームに半導体素子を固定し金線等で配線後樹脂
封止する従来のパッケージ方法に対し、半導体素子単体
を回路基板にアクティブ面を向けてフェースダウン実装
する、いわゆるフリップチップ実装方法の使用が増大し
ている。On the other hand, in recent years, there has been an increasing demand for thinner and smaller electronic devices, such as portable devices, and there is a strong demand for thinner semiconductor device packages. In contrast to the conventional packaging method in which a semiconductor element is fixed with a gold wire or the like and then sealed with a resin, the use of a so-called flip-chip mounting method in which a semiconductor element alone is face-down mounted on a circuit board with its active surface facing is increasing.
【０００４】フリップチップ実装方法の代表的なもの
は、半導体素子上の接続パッドに金属薄膜を形成後はん
だボールを形成し、はんだボール面を前記のはんだペー
スト印刷転写部に対向させて位置合わせ後設置し、その
後加熱炉にてはんだリフローを行い接続完了するもので
ある。さらに信頼性を向上させるために、回路基板と半
導体素子の隙間に樹脂を充填し硬化することも行われ
る。A typical flip-chip mounting method is to form a metal thin film on a connection pad on a semiconductor element, form a solder ball, and align the solder ball with the solder ball printed surface facing the above-mentioned solder paste print transfer portion. After installation, solder reflow is performed in a heating furnace to complete the connection. In order to further improve the reliability, the gap between the circuit board and the semiconductor element is filled with a resin and cured.
【０００５】前記はんだによるフリップチップ実装方法
は、端子ピッチの狭いものはショートが発生しやすく、
最も狭ピッチのものでも２５０μｍ程度である点と、高
信頼性を得るためには樹脂充填硬化の追加工程が必要と
いう問題がある。[0005] In the flip-chip mounting method using solder, short-circuiting is liable to occur when the terminal pitch is small.
The narrowest pitch is about 250 μm, and there is a problem that an additional step of resin filling and curing is required to obtain high reliability.
【０００６】この問題を解決するため、熱硬化型異方導
電性接着剤を用いたフリップチップ実装方法が最近導入
されている。この工程を図を用いて説明する。In order to solve this problem, a flip chip mounting method using a thermosetting anisotropic conductive adhesive has recently been introduced. This step will be described with reference to the drawings.
【０００７】図３に示すように、半導体素子４上の接続
パッドに金線ボールボンディング法やメッキ法を用い高
さ数十μｍの突起状電極５を形成し（図３（ａ））、異
方導電性接着剤９を回路基板１上に仮固定した後（図３
（ｂ））、前記半導体素子の突起状電極面を回路基板面
に対向させ、接続用ランド８と位置合わせ後圧着ツール
６にて加圧及び加熱を行い（図３（ｃ））突起状電極５
と回路基板上のランド８との電気的導通を得ると同時に
接着剤を硬化させ接続を完了する（図３（ｄ））。As shown in FIG. 3, a protruding electrode 5 having a height of several tens μm is formed on the connection pad on the semiconductor element 4 by using a gold wire ball bonding method or a plating method (FIG. 3A). After temporarily fixing the conductive adhesive 9 on the circuit board 1 (FIG. 3)
(B)) The protruding electrode surface of the semiconductor element is opposed to the circuit board surface, and after positioning with the connection land 8, pressurization and heating are performed with the crimping tool 6 (FIG. 3C) 5
At the same time, electrical connection between the substrate and the land 8 on the circuit board is obtained, and the adhesive is cured to complete the connection (FIG. 3D).
【０００８】[0008]
【発明が解決しようとする課題】前記のように、異方導
電性接着剤を用いたフリップチップ実装方法は、はんだ
接続方法に比べ接続パッドのピッチが狭いものに対応で
きるという特長があるが、１枚の回路基板上に半導体素
子と受動部品等はんだ接続が必要な部品を混載する場合
に、工程が増え工程時間が長くなるという問題がある。As described above, the flip-chip mounting method using an anisotropic conductive adhesive has a feature that it can cope with a connection pad having a smaller pitch than a solder connection method. When a semiconductor element and a component that requires solder connection, such as a passive component, are mixedly mounted on one circuit board, there is a problem that the number of processes increases and the process time increases.
【０００９】すなわち、半導体素子のフリップチップ実
装にはんだ接続法を使用する場合は、受動部品等と同様
に回路基板に設置した後、一回の加熱処理で同時にはん
だリフローを行えるため、フリップチップ実装の半導体
素子と受動部品が混在する回路基板でも、特に工程の増
加や工程時間の延長はない。In other words, when the solder connection method is used for flip-chip mounting of a semiconductor element, it is possible to perform solder reflow simultaneously with a single heat treatment after mounting on a circuit board as in the case of passive components and the like. Even in a circuit board in which a semiconductor element and a passive component coexist, there is no particular increase in the number of steps and no increase in the processing time.
【００１０】一方、異方導電性接着剤を用いる場合は、
受動部品等のはんだ接続工程と別工程で半導体素子を回
路基板に実装する工程を通らなければならない。On the other hand, when using an anisotropic conductive adhesive,
It is necessary to go through a process of mounting the semiconductor element on the circuit board in a process different from a solder connection process for passive components or the like.
【００１１】また、一般に異方導電性接着剤を用いた部
品実装には加圧加熱工程として最短でも１０秒程度必要
である。多数個の半導体素子を実装する場合は合計１０
秒×個数分の時間が必要となり工程時間として長大なも
のになってしまうという問題がある。In general, mounting a component using an anisotropic conductive adhesive requires at least about 10 seconds as a pressing and heating step. 10 when mounting multiple semiconductor elements
There is a problem that the time required for seconds × the number is required, and the process time becomes long.
【００１２】工程時間を短縮するために加圧加熱ヘッド
を複数個設け、同時に複数個の半導体素子を加圧加熱す
ることも実施されているが、加圧加熱機構の寸法及び精
度の点よりヘッド数はせいぜい２，３個が限界である。
また、近接した位置に同時に複数個の素子を実装するこ
とが困難であるなど根本的な問題解決にならない。In order to shorten the process time, a plurality of pressurizing and heating heads are provided, and a plurality of semiconductor elements are pressurized and heated at the same time. The number is at most a few.
In addition, it is difficult to mount a plurality of elements at close positions at the same time.
【００１３】[0013]
【課題を解決するための手段】この課題を解決するため
に、本発明の電子部品の実装方法は、接続パッド上に突
起状電極を形成した半導体素子等の電子部品を熱硬化性
接着剤を用いて回路基板に装着し半硬化状態まで加圧加
熱する工程と、受動部品等の電子部品をはんだペースト
を用いて前記回路基板に装着する工程と、前記はんだペ
ーストをリフローすると同時に前記接着剤を完全に硬化
させる加熱工程からなるものである。In order to solve this problem, a method for mounting an electronic component according to the present invention is to provide a method for mounting an electronic component such as a semiconductor device having a protruding electrode on a connection pad by using a thermosetting adhesive. Using a solder paste to mount the electronic component such as a passive component on the circuit board using a solder paste, and reflowing the solder paste and simultaneously applying the adhesive. It consists of a heating step for complete curing.
【００１４】また、本発明の電子部品の実装装置は、熱
硬化性接着剤およびはんだペーストを回路基板上の所定
位置に配置する手段と、前記熱硬化性接着剤が配置され
た回路基板上の所定位置の突起状電極を形成した電子部
品を装着し半硬化状態まで加圧加熱する手段と、前記は
んだペーストが配置された回路基板上の所定位置に電子
部品を装着する手段と、前記はんだペーストをリフロー
すると同時に前記熱硬化性接着剤または熱硬化型異方導
電性接着剤を完全に硬化させる加熱手段を有する装置で
あり、前記第１の発明の電子部品の実装方法を完全に実
施できるものである。[0014] The electronic component mounting apparatus of the present invention further comprises means for arranging the thermosetting adhesive and the solder paste at predetermined positions on the circuit board, and means for arranging the thermosetting adhesive and the solder paste on the circuit board on which the thermosetting adhesive is arranged. Means for mounting an electronic component on which a protruding electrode is formed at a predetermined position and pressurizing and heating it to a semi-cured state; mounting means for mounting the electronic component at a predetermined position on a circuit board on which the solder paste is disposed; Is a device having heating means for completely curing the thermosetting adhesive or the thermosetting anisotropic conductive adhesive at the same time as reflowing, so that the electronic component mounting method of the first invention can be completely implemented. It is.
【００１５】[0015]
【発明の実施の形態】本発明の請求項１に記載の発明
は、接続パッド上に突起状電極を形成した半導体素子等
の電子部品を熱硬化性接着剤を介して接着後加圧加熱し
接着剤を半硬化状態にする第１の工程と、チップ型抵抗
等のはんだ実装の部品をはんだペーストを用いて回路基
板に装着する第２の工程と、はんだペーストをリフロー
すると同時に前記接着剤を完全に硬化させる加熱工程の
３工程からなる電子部品の実装方法である。DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the first aspect of the present invention, an electronic component such as a semiconductor device having a protruding electrode formed on a connection pad is bonded by a thermosetting adhesive and then heated under pressure. A first step of bringing the adhesive into a semi-cured state, a second step of mounting a solder-mounted component such as a chip-type resistor on a circuit board using a solder paste, and reflowing the solder paste and simultaneously applying the adhesive. This is a method for mounting an electronic component comprising three steps of a heating step of completely curing.
【００１６】第１の熱硬化性接着剤を介して加圧加熱し
半硬化状態にする工程は完全硬化する従来方法に比べ著
しく時間が短いものであり、複数個の部品を装着しても
工程時間の増加はわずかなものである。また、第３の加
熱工程は従来のはんだリフロー工程と同時にフリップチ
ップ用接着剤を完全硬化させる工程であり時間的に従来
工法と同等であり、結果的に従来工法に比べ工程全体の
合計時間が著しく短いという作用を有する。The step of applying pressure and heating to the semi-cured state through the first thermosetting adhesive is significantly shorter in time than the conventional method of completely curing, and even if a plurality of parts are mounted, The increase in time is small. In addition, the third heating step is a step of completely curing the adhesive for flip chips simultaneously with the conventional solder reflow step, and is equivalent in time to the conventional method. As a result, the total time of the entire process is shorter than the conventional method. It has the effect of being extremely short.
【００１７】さらに、熱硬化性接着剤を異方導電性接着
剤にすると、メッキ法のように高さが低くかつ表面積が
広い突起状電極の場合でも接着剤に分散された導電粒子
によって、より安定した電気的接続が得られる。Further, when the thermosetting adhesive is made of an anisotropic conductive adhesive, even in the case of a protruding electrode having a low height and a large surface area as in the case of a plating method, the conductive particles dispersed in the adhesive make it possible to further improve the performance. A stable electrical connection is obtained.
【００１８】本発明の実施の形態を図を用いて説明す
る。An embodiment of the present invention will be described with reference to the drawings.
【００１９】（実施の形態１）図１は本実施の形態の一
例であり、半導体素子と受動部品が１枚の回路基板上に
混在実装された回路モジュールを作成する工程を、順を
追って図示したものである。(Embodiment 1) FIG. 1 is an example of the present embodiment, and illustrates a step-by-step process of producing a circuit module in which a semiconductor element and a passive component are mixedly mounted on one circuit board. It was done.
【００２０】図１（ａ）は回路基板１上の半導体素子接
続用ランド８ａ部分に熱硬化性接着剤シート２を仮止め
し、さらにチップ型部品接続用ランド８ｂ部分にはんだ
ペースト３を設置した状態である。FIG. 1A shows that the thermosetting adhesive sheet 2 is temporarily fixed to the semiconductor element connecting lands 8a on the circuit board 1, and the solder paste 3 is further set to the chip type component connecting lands 8b. State.
【００２１】はんだペースト３はメタルマスクを用いて
所定の位置にスクリーン印刷法で設置した。熱硬化性接
着剤シートはエポキシ樹脂基材と硬化剤の混合物を厚さ
５０μｍのシート状に成形したものであり、架橋開始温
度は約１００℃である。このシートを表面温度８０℃に
保った圧着ツールを使用し、加圧時間２秒、圧力９８ｋ
Ｐａの条件で加圧加熱し仮止めした。The solder paste 3 was set at a predetermined position by a screen printing method using a metal mask. The thermosetting adhesive sheet is obtained by molding a mixture of an epoxy resin base material and a curing agent into a sheet having a thickness of 50 μm, and has a crosslinking start temperature of about 100 ° C. Using a crimping tool that maintains the sheet at a surface temperature of 80 ° C., pressurizing time is 2 seconds, and pressure is 98k.
It was heated under pressure and temporarily fixed under Pa conditions.
【００２２】図１（ｂ）は接続パッド上に金線ボールボ
ンディング法を用いて、高さ約７０μｍの突起状電極５
を形成した半導体素子４を、圧着ツール６に吸着し、回
路基板のランド８ａに対して位置合わせを行った状態で
ある。圧着ツールはヒーターが内蔵してあり、通電する
ことによって急速に昇温でき、また、回路基板との平行
度は半導体素子面内で±５μｍ以内に調整している。使
用した半導体素子は、周囲配置型で各辺に０．１ｍｍピ
ッチ、各５０パッド、計２００パッドを設けたテストチ
ップである。FIG. 1B shows a protruding electrode 5 having a height of about 70 μm on a connection pad by using a gold wire ball bonding method.
This is a state in which the semiconductor element 4 on which is formed is adsorbed to the crimping tool 6 and is aligned with the land 8a of the circuit board. The crimping tool has a built-in heater and can rapidly raise the temperature when energized. The parallelism with the circuit board is adjusted within ± 5 μm within the semiconductor element surface. The semiconductor element used is a test chip of a peripheral arrangement type having a pitch of 0.1 mm on each side and a total of 200 pads, each having 50 pads.
【００２３】次に、図１（ｃ）に示すように、圧着ツー
ルを下ろし、半導体素子に各突起状電極当たり０．６８
６Ｎ（７０ｇ）、２００個の電極全体で計１３７．２Ｎ
（１４．０ｋｇ）の荷重を加えながら、ヒーターに通電
して１６０℃にまで昇温し、２秒間保持した。その結
果、圧力により突起状電極と回路基板ランド間の余分な
接着剤は排除され、さらに突起状電極が変形することに
より、突起高さのばらつき等を吸収し、電気的導通が得
られた。また、接着剤の硬化が進行したが完全硬化に至
らず、未反応の硬化剤および主剤が残った状態である。Next, as shown in FIG. 1 (c), the crimping tool is lowered, and 0.68
6N (70 g), 137.2 N in total over 200 electrodes
While applying a load of (14.0 kg), the heater was energized to raise the temperature to 160 ° C. and held for 2 seconds. As a result, the extra adhesive between the protruding electrode and the circuit board land was removed by the pressure, and the protruding electrode was further deformed, thereby absorbing variations in the height of the protruding portion, and electrical conduction was obtained. In addition, the curing of the adhesive progressed but did not reach complete curing, and the unreacted curing agent and main agent remained.
【００２４】次に、図１（ｄ）に示すように、チップ型
抵抗７ａをはんだペーストを印刷したランド部にマウン
トした。Next, as shown in FIG. 1D, the chip type resistor 7a was mounted on the land portion on which the solder paste was printed.
【００２５】この後、基板全体をピーク温度２４０℃に
設定した、はんだリフロー炉に通した。Thereafter, the entire substrate was passed through a solder reflow furnace set at a peak temperature of 240.degree.
【００２６】その結果、図１（ｅ）に示すように、はん
だペースト３はリフロー後チップ型抵抗７ａの電極部７
ｂ部でフィレットを形成し、熱硬化性接着剤シート２は
完全硬化しほぼ１００％の架橋率が得られた。接着剤は
硬化が進行するに伴いわずかに体積収縮するため、突起
状電極と回路基板上のランド間は圧縮応力が残留し安定
した接続が得られる。As a result, as shown in FIG. 1E, after the reflow, the solder paste 3 is applied to the electrode portion 7 of the chip type resistor 7a.
A fillet was formed at part b, and the thermosetting adhesive sheet 2 was completely cured, and a crosslink rate of almost 100% was obtained. Since the adhesive slightly shrinks in volume as the curing proceeds, a compressive stress remains between the protruding electrode and the land on the circuit board, and a stable connection is obtained.
【００２７】前記実装が終了した回路基板を−４０℃／
＋１５０℃ 各３０分の熱衝撃試験を行ったところ、不
良発生は２５００サイクル以上という高信頼性が得られ
た。The circuit board on which the mounting has been completed is placed at -40 ° C. /
When a thermal shock test was performed at + 150 ° C. for 30 minutes each, high reliability was obtained with 2500 cycles or more of failures.
【００２８】本実施の形態では接着剤実装する電子部品
に半導体素子を使用したが、これに限定するものではな
い。また、熱硬化性接着剤はシート状に限るものではな
く、ペースト状のものをディスペンサ装着しても同様の
効果を得ることができる。In this embodiment, a semiconductor element is used for an electronic component to be mounted with an adhesive, but the present invention is not limited to this. Further, the thermosetting adhesive is not limited to a sheet-like adhesive, and the same effect can be obtained by attaching a paste-like adhesive to a dispenser.
【００２９】（実施の形態２）図２は本実施の形態の他
の例であり、半導体素子と受動部品が１枚の回路基板上
に混在実装された回路モジュールを作成する工程を、順
を追って図示したものである。(Embodiment 2) FIG. 2 shows another example of the present embodiment, in which the steps of producing a circuit module in which semiconductor elements and passive components are mixedly mounted on a single circuit board will be described. This is shown later.
【００３０】図２（ａ）は回路基板１上の半導体素子接
続用ランド８ａ部分に異方導電性接着剤９を仮止めし、
さらにチップ型部品接続用ランド８ｂ部分にはんだペー
スト３を設置した状態である。はんだペーストはメタル
マスクを用いて所定の位置にスクリーン印刷法で設置し
た。異方導電性接着剤はエポキシ樹脂基材と硬化剤の混
合物に金メッキされた粒径約５μｍの樹脂粒子を混錬
し、厚さ５０μｍのシート状に成形したものであり、架
橋開始温度は約１００℃である。このシートを表面温度
８０℃に保った圧着ツールを使用し、加圧時間２秒、圧
力９８ｋＰａの条件で加圧加熱し仮止めした。FIG. 2A shows an anisotropic conductive adhesive 9 temporarily fixed to the semiconductor element connecting lands 8 a on the circuit board 1.
Further, the solder paste 3 is placed on the chip-type component connection lands 8b. The solder paste was set at a predetermined position using a metal mask by a screen printing method. The anisotropic conductive adhesive is obtained by kneading a mixture of an epoxy resin base material and a curing agent with gold-plated resin particles having a particle size of about 5 μm and molding the mixture into a sheet having a thickness of 50 μm. 100 ° C. This sheet was pressurized and heated under a condition of a pressurization time of 2 seconds and a pressure of 98 kPa using a pressure bonding tool maintained at a surface temperature of 80 ° C., and temporarily fixed.
【００３１】図２（ｂ）は接続パッド上に金メッキ法を
用いて、高さ約２５μｍの突起状電極５を形成した半導
体素子４を、圧着ツール６に吸着し、回路基板のランド
８ａに対して位置合わせを行った状態である。圧着ツー
ルはヒーターが内蔵してあり、通電することによって急
速に昇温できるものであり、また、回路基板との平行度
は半導体素子面内で±５μｍ以内に調整している。使用
した半導体素子は、周囲配置型で各辺に０．１ｍｍピッ
チ、各５０パッド、計２００パッドを設けたテストチッ
プである。FIG. 2B shows a semiconductor element 4 having a protruding electrode 5 having a height of about 25 μm formed on a connection pad by using a gold plating method. In this state. The crimping tool has a built-in heater and can rapidly raise the temperature when energized. The parallelism with the circuit board is adjusted within ± 5 μm within the semiconductor element surface. The semiconductor element used is a test chip of a peripheral arrangement type having a pitch of 0.1 mm on each side and a total of 200 pads, each having 50 pads.
【００３２】次に、図２（ｃ）に示すように、圧着ツー
ルを下ろし、半導体素子に各突起電極当たり０．４９Ｎ
（５０ｇ）、２００個の電極全体で計９８．０Ｎ（１
０．０ｋｇ）の荷重を加えながら、ヒーターに通電し１
６０℃にて保持時間２秒の圧着を行った。その結果、突
起状電極と回路基板ランド間に導電粒子が挟持され、電
気的導通が得られた。しかし、異方導電性接着剤は完全
硬化に至らず、未反応の硬化剤および主剤が残った状態
である。Next, as shown in FIG. 2 (c), the crimping tool is lowered and the semiconductor device is exposed to 0.49N for each protruding electrode.
(50 g), a total of 98.0 N (1
0.0kg) while applying a load,
Crimping was performed at 60 ° C. for a holding time of 2 seconds. As a result, the conductive particles were sandwiched between the protruding electrodes and the circuit board lands, and electrical continuity was obtained. However, the anisotropic conductive adhesive is not completely cured, and the unreacted curing agent and the main agent remain.
【００３３】次に、図２（ｄ）に示すように、チップ型
抵抗７ａをはんだペーストを印刷したランド部にマウン
トした。Next, as shown in FIG. 2D, the chip type resistor 7a was mounted on the land portion on which the solder paste was printed.
【００３４】この後、基板全体をピーク温度２４０℃に
設定した、はんだリフロー炉に通した。Thereafter, the entire substrate was passed through a solder reflow furnace set at a peak temperature of 240 ° C.
【００３５】その結果、図２（ｅ）に示すように、はん
だペースト３はリフロー後チップ型抵抗７ａの電極部７
ｂ部でフィレットを形成し、異方導電性接着剤９は完全
硬化しほぼ１００％の架橋率が得られた。As a result, as shown in FIG. 2E, after the reflow, the solder paste 3 is applied to the electrode portion 7 of the chip resistor 7a.
A fillet was formed in part b, and the anisotropic conductive adhesive 9 was completely cured, and a cross-linking rate of almost 100% was obtained.
【００３６】実装が終了した回路基板を−４０℃／＋１
５０℃ 各３０分の熱衝撃試験を行ったところ、不良発
生は３０００サイクル以上という高信頼性が得られた。The circuit board after completion of mounting is set at -40 ° C./+1.
As a result of performing a thermal shock test at 50 ° C. for 30 minutes each, high reliability was obtained with 3000 cycles or more of failures.
【００３７】本実施の形態では接着剤実装する電子部品
に半導体素子を使用したが、これに限定するものではな
い。また、異方導電性接着剤はシート状に限るものでは
なく、ペースト状のものをディスペンサ装着しても同様
の効果を得ることができる。In this embodiment, a semiconductor element is used for an electronic component to be mounted with an adhesive, but the present invention is not limited to this. Further, the anisotropic conductive adhesive is not limited to a sheet-like one, and the same effect can be obtained even when a paste-like one is attached to a dispenser.
【００３８】[0038]
【発明の効果】以上の説明から明らかなように、本発明
の電子部品の実装方法によれば、多ピン狭ピッチ電極の
半導体素子のようにはんだリフロー法では対応できない
フリップチップ実装の電子部品とはんだリフロー法が適
する受動部品等が混載した回路基板の実装工程におい
て、フリップチップ実装に熱硬化性接着剤や異方導電性
接着剤を用いるにもかかわらず、すべてはんだリフロー
実装で行う場合に比べ最低限の工程時間増加に抑えるこ
とができ、また、熱硬化性接着剤や異方導電性接着剤を
用いる従来の工法より著しく工程時間を短縮できるとい
う効果が得られる。As is clear from the above description, according to the electronic component mounting method of the present invention, the flip-chip mounted electronic component which cannot be handled by the solder reflow method, such as a semiconductor device having a multi-pin narrow-pitch electrode, can be used. In the process of mounting a circuit board with passive components that are suitable for the solder reflow method, even though a thermosetting adhesive or an anisotropic conductive adhesive is used for flip chip mounting, compared to the case where all solder reflow mounting is used The effect that the process time can be suppressed to the minimum increase and the process time can be remarkably reduced as compared with the conventional method using a thermosetting adhesive or an anisotropic conductive adhesive can be obtained.
【００３９】またより安定した高信頼性の電気的接続が
得られるという効果を有するものである。Further, the present invention has an effect that a more stable and highly reliable electrical connection can be obtained.
【００４０】さらに、本発明の電子部品の実装装置によ
れば、多ピン狭ピッチ電極の半導体素子のようにはんだ
リフロー法では対応できないフリップチップ実装の電子
部品とはんだリフロー実装が適する受動部品等が混載し
た回路基板の実装工程において、熱硬化性接着剤や異方
導電性接着剤を用いるにもかかわらず、すべてはんだリ
フロー実装で行う場合に比べ最低限の工程時間増加に抑
えることができ、また、熱硬化性接着剤や異方導電性接
着剤を用いる従来の工法より著しく工程時間を短縮でき
るという効果が得られる。Further, according to the electronic component mounting apparatus of the present invention, flip-chip mounted electronic components which cannot be handled by the solder reflow method, such as multi-pin narrow-pitch electrode semiconductor devices, and passive components suitable for solder reflow mounting, are provided. Despite the use of a thermosetting adhesive or an anisotropic conductive adhesive in the mounting process of the mixed circuit board, it is possible to suppress the process time to a minimum increase compared to the case of performing all solder reflow mounting, In addition, the process time can be remarkably reduced as compared with the conventional method using a thermosetting adhesive or an anisotropic conductive adhesive.
【図１】本発明の一実施の形態を説明するための工程断
面図FIG. 1 is a process cross-sectional view illustrating one embodiment of the present invention.
【図２】本発明の他の実施の形態を説明するための工程
断面図FIG. 2 is a process sectional view illustrating another embodiment of the present invention.
【図３】従来のフリップチップ実装方法を説明するため
の工程断面図FIG. 3 is a process sectional view for explaining a conventional flip chip mounting method.
１ 回路基板 ２ 熱硬化性接着剤シート ３ はんだペースト ４ 半導体素子 ５ 突起状電極 ６ 圧着ツール ８，８ａ，８ｂ 回路基板上の接続用ランド ９ 異方導電性接着剤 DESCRIPTION OF SYMBOLS 1 Circuit board 2 Thermosetting adhesive sheet 3 Solder paste 4 Semiconductor element 5 Protruding electrode 6 Crimping tool 8, 8a, 8b Land for connection on circuit board 9 Anisotropic conductive adhesive
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5E319 AA03 AB05 BB16 CC33 CD15 GG15 5F044 LL01 LL04 LL09 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E319 AA03 AB05 BB16 CC33 CD15 GG15 5F044 LL01 LL04 LL09
Claims (4)
性接着剤を用いて回路基板に装着し半硬化状態まで加圧
加熱する工程と、はんだペーストを前記回路基板上に所
定位置に配置する工程と、前記はんだペーストが配置さ
れた回路基板上に電子部品を装着する工程と、前記はん
だペーストをリフローすると同時に前記熱硬化性接着剤
を完全に硬化させる加熱工程からなることを特徴とする
電子部品の実装方法。1. A step of mounting an electronic component on which a protruding electrode is formed on a circuit board by using a thermosetting adhesive and heating under pressure to a semi-cured state, and disposing a solder paste at a predetermined position on the circuit board. And mounting the electronic component on the circuit board on which the solder paste is disposed, and a heating step of completely curing the thermosetting adhesive while reflowing the solder paste. How to mount electronic components.
であることを特徴とする請求項１記載の電子部品の実装
方法。2. The method according to claim 1, wherein the thermosetting adhesive is an anisotropic conductive adhesive.
子部品が半導体素子であることを特徴とする請求項１記
載の電子部品の実装方法。3. The electronic component mounting method according to claim 1, wherein the electronic component mounted using the thermosetting adhesive is a semiconductor element.
性接着剤およびはんだペーストを回路基板上の所定位置
に配置する手段と、前記熱硬化性接着剤または熱硬化型
異方導電性接着剤が配置された回路基板上の所定位置に
突起状電極を形成した電子部品を装着し半硬化状態まで
加圧加熱する手段と、前記はんだペーストが配置された
回路基板上の所定位置に電子部品を装着する手段と、前
記はんだペーストをリフローすると同時に前記熱硬化性
接着剤または熱硬化型異方導電性接着剤を完全に硬化さ
せる加熱手段からなることを特徴とする電子部品の実装
装置。4. A means for disposing a thermosetting adhesive or a thermosetting anisotropic conductive adhesive and a solder paste at predetermined positions on a circuit board; Means for mounting an electronic component on which a protruding electrode is formed at a predetermined position on the circuit board on which the adhesive is disposed and pressurizing and heating it to a semi-cured state; An electronic component mounting apparatus, comprising: means for mounting a component; and heating means for completely curing the thermosetting adhesive or thermosetting anisotropic conductive adhesive while reflowing the solder paste.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001095739A JP2002299809A (en) | 2001-03-29 | 2001-03-29 | Electronic component mounting method and equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001095739A JP2002299809A (en) | 2001-03-29 | 2001-03-29 | Electronic component mounting method and equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002299809A true JP2002299809A (en) | 2002-10-11 |
Family
ID=18949750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001095739A Pending JP2002299809A (en) | 2001-03-29 | 2001-03-29 | Electronic component mounting method and equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002299809A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6911606B2 (en) | 2003-03-04 | 2005-06-28 | Yushi Suda | Electronic component for adhesion of a plurality of electrodes and method of mounting the same |
| GB2412790A (en) * | 2004-04-02 | 2005-10-05 | Univ City Hong Kong | Process for the assembly of electronic devices |
| JP2010510644A (en) * | 2006-11-16 | 2010-04-02 | エプコス アクチエンゲゼルシャフト | Component structure |
| WO2010140469A1 (en) * | 2009-06-01 | 2010-12-09 | 住友電気工業株式会社 | Connection method, connection structure, and electronic device |
| JP2010278388A (en) * | 2009-06-01 | 2010-12-09 | Sumitomo Electric Ind Ltd | Method and structure of connection, and electronic device |
| WO2010147001A1 (en) * | 2009-06-15 | 2010-12-23 | 住友電気工業株式会社 | Electrode connection method, electrode connection structure, conductive adhesive used therefor, and electronic device |
| US8470438B2 (en) | 2009-06-15 | 2013-06-25 | Sumitomo Electric Industries, Ltd. | Electrode-connecting structure, conductive adhesive used for the same, and electronic apparatus |
| JPWO2017077958A1 (en) * | 2015-11-04 | 2018-08-23 | リンテック株式会社 | Manufacturing method of semiconductor device |
-
2001
- 2001-03-29 JP JP2001095739A patent/JP2002299809A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6911606B2 (en) | 2003-03-04 | 2005-06-28 | Yushi Suda | Electronic component for adhesion of a plurality of electrodes and method of mounting the same |
| GB2412790A (en) * | 2004-04-02 | 2005-10-05 | Univ City Hong Kong | Process for the assembly of electronic devices |
| GB2412790B (en) * | 2004-04-02 | 2007-12-05 | Univ City Hong Kong | Process for assembly of electronic devices |
| JP2010510644A (en) * | 2006-11-16 | 2010-04-02 | エプコス アクチエンゲゼルシャフト | Component structure |
| CN102450112A (en) * | 2009-06-01 | 2012-05-09 | 住友电气工业株式会社 | Connection method, connection structure, and electronic device |
| JP2010278388A (en) * | 2009-06-01 | 2010-12-09 | Sumitomo Electric Ind Ltd | Method and structure of connection, and electronic device |
| JP4746687B2 (en) * | 2009-06-01 | 2011-08-10 | 住友電気工業株式会社 | Connection method, connection structure, and electronic device |
| EP2445322A1 (en) * | 2009-06-01 | 2012-04-25 | Sumitomo Electric Industries, Ltd. | Connection method, connection structure, and electronic device |
| WO2010140469A1 (en) * | 2009-06-01 | 2010-12-09 | 住友電気工業株式会社 | Connection method, connection structure, and electronic device |
| WO2010147001A1 (en) * | 2009-06-15 | 2010-12-23 | 住友電気工業株式会社 | Electrode connection method, electrode connection structure, conductive adhesive used therefor, and electronic device |
| US8470438B2 (en) | 2009-06-15 | 2013-06-25 | Sumitomo Electric Industries, Ltd. | Electrode-connecting structure, conductive adhesive used for the same, and electronic apparatus |
| US9226406B2 (en) | 2009-06-15 | 2015-12-29 | Sumitomo Electric Industries, Ltd. | Electrode connection method, electrode connection structure, conductive adhesive used therefor, and electronic device |
| JPWO2017077958A1 (en) * | 2015-11-04 | 2018-08-23 | リンテック株式会社 | Manufacturing method of semiconductor device |
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