JP2002289853A - Semiconductor device and manufacturing method therefor - Google Patents
Semiconductor device and manufacturing method thereforInfo
- Publication number
- JP2002289853A JP2002289853A JP2001092163A JP2001092163A JP2002289853A JP 2002289853 A JP2002289853 A JP 2002289853A JP 2001092163 A JP2001092163 A JP 2001092163A JP 2001092163 A JP2001092163 A JP 2001092163A JP 2002289853 A JP2002289853 A JP 2002289853A
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- Japan
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- region
- source
- forming
- semiconductor layer
- electrode
- Prior art date
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- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 91
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000009792 diffusion process Methods 0.000 claims abstract description 62
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 25
- 239000000956 alloy Substances 0.000 claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 239000012535 impurity Substances 0.000 claims description 17
- 238000010438 heat treatment Methods 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 230000001965 increasing effect Effects 0.000 abstract description 15
- 238000009413 insulation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 65
- 108091006146 Channels Proteins 0.000 description 54
- 239000000758 substrate Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000012421 spiking Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- 210000000746 body region Anatomy 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000005275 alloying Methods 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、縦型ＭＯＳＦＥＴ
や絶縁ゲート型バイポーラトランジスタ（ＩＧＢＴ）な
どのゲート駆動型素子を有するパワー半導体装置および
その製法に関する。さらに詳しくは、オン抵抗が小さ
く、大電流が得られるパワー用のゲート駆動型半導体装
置およびその製法に関する。The present invention relates to a vertical MOSFET
Semiconductor device having a gate drive type element such as a semiconductor device and an insulated gate bipolar transistor (IGBT) and a method for manufacturing the same. More particularly, the present invention relates to a power gate drive type semiconductor device having a low on-resistance and a large current, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】従来、ハイパワー用ゲート駆動型パワー
ＭＯＳトランジスタは、大電流化のため、トランジスタ
セルを多数個マトリクス状に並列に形成する構造が採ら
れている。たとえばプレーナ構造のトランジスタは、図
４に示されるように、たとえばｎ+形の半導体基板２１
ａ上に、ドレイン領域とするｎ形の半導体層（エピタキ
シャル成長層）２１がエピタキシャル成長され、その表
面側にｐ形不純物を拡散することによりｐ形のボディ領
域２２が形成され、そのボディ領域２２の外周部にｎ+
形のソース領域２３が形成されている。ボディ領域２２
の端部およびその外側に位置する半導体層２１の表面側
にゲート酸化膜２４を介してゲート電極２５が設けら
れ、ボディ領域の外周部にチャネル領域２２ａが形成さ
れている。そして、ソース領域２３と接続するように層
間絶縁膜２６に設けられるコンタクト孔を介してＡｌな
どによりソース電極（ソース配線）２７が形成され、半
導体基板２１ａの裏面にドレイン電極２８が形成される
ことにより形成されている。2. Description of the Related Art Hitherto, a high-power gate drive type power MOS transistor has a structure in which a large number of transistor cells are formed in parallel in a matrix to increase the current. For example, as shown in FIG. 4, a transistor having a planar structure is, for example, an n + type semiconductor substrate 21.
An n-type semiconductor layer (epitaxial growth layer) 21 serving as a drain region is epitaxially grown on a, and a p-type body region 22 is formed by diffusing a p-type impurity on the surface side thereof. N +
A source region 23 is formed. Body region 22
A gate electrode 25 is provided via a gate oxide film 24 on an end portion of the semiconductor layer 21 and a surface side of the semiconductor layer 21 located outside the end portion, and a channel region 22a is formed on an outer peripheral portion of the body region. Then, a source electrode (source wiring) 27 of Al or the like is formed through a contact hole provided in the interlayer insulating film 26 so as to be connected to the source region 23, and a drain electrode 28 is formed on the back surface of the semiconductor substrate 21a. Is formed.
【０００３】一方、ゲート電極を半導体層に形成した溝
内に埋め込むトレンチ構造のパワー用ＭＯＳＦＥＴは、
図５にその一例が示されるように、半導体層２１に凹溝
が格子状に形成され、その内部にゲート電極２５とする
ポリシリコンが埋め込まれ、酸化によりその周囲にゲー
ト酸化膜２４が形成され、その周囲にｐ形のチャネル拡
散領域２２とｎ+形ソース領域２３が形成され、縦方向
にチャネル領域２２ａが形成されている。そのソース領
域２３およびチャネル拡散領域２２とオーミックコンタ
クトするようにソース電極２７が形成され、半導体基板
２１ａの裏面にドレイン電極２８が形成されることは図
４と同様である。On the other hand, a power MOSFET having a trench structure in which a gate electrode is buried in a groove formed in a semiconductor layer,
As shown in an example in FIG. 5, concave grooves are formed in the semiconductor layer 21 in a lattice shape, polysilicon as the gate electrode 25 is buried therein, and a gate oxide film 24 is formed therearound by oxidation. A p-type channel diffusion region 22 and an n + -type source region 23 are formed therearound, and a channel region 22a is formed in the vertical direction. A source electrode 27 is formed so as to make ohmic contact with the source region 23 and the channel diffusion region 22, and a drain electrode 28 is formed on the back surface of the semiconductor substrate 21a as in FIG.
【０００４】なお、これらのトランジスタにおけるゲー
ト電極の平面的構造は、正方形や５角形、６角形などの
任意の形状に形成される。また、これらのトランジスタ
では、モータのような誘導性負荷に接続されることが多
く、その場合、動作をオフにするとき、逆方向の起電力
が印加されることがあり、トランジスタが破壊するのを
防止するため、前述のように、ソース電極２７をチャネ
ル拡散領域２２とも接続させることにより、ソース・ド
レイン間に逆方向の保護用ダイオードを形成する方法が
採られている。The planar structure of the gate electrode in these transistors is formed in an arbitrary shape such as a square, a pentagon or a hexagon. In addition, these transistors are often connected to an inductive load such as a motor. In that case, when the operation is turned off, an electromotive force in the opposite direction may be applied, and the transistor may be destroyed. In order to prevent this, as described above, a method is adopted in which the source electrode 27 is also connected to the channel diffusion region 22 to form a protection diode in the reverse direction between the source and the drain.
【０００５】[0005]
【発明が解決しようとする課題】前述のような大電流用
のトランジスタでは、定められた大きさのチップ内にで
きるだけ多くのトランジスタセルを作り、オン抵抗を下
げることが重要である。オン抵抗を小さくするために
は、チャネル幅をできるだけ大きくすることが効果的で
あり、前述の構造のトランジスタでは、ゲート電極周囲
に形成されるチャネル領域２２ａの幅（ゲート電極周囲
の長さ）の合計をできるだけ多くすることが好ましい。
しかし、従来のこの種のトランジスタでは、半導体層の
表面で、チャネル拡散領域にソース電極をオーミックコ
ンタクトさせるため、ソース領域とチャネル拡散領域の
両方を半導体層の表面に露出させる必要があると共に、
ソース領域を拡散するときのマスク重ね合せのマージ
ン、コンタクト孔とソース領域とのマスク重ね合せマー
ジンが必要なことから、たとえば図５に示される構造
で、コンタクト孔の大きさＣが２〜２.５μｍ程度とな
り、セル間隔（ゲート電極間のピッチ）Ａは、４.５〜
５μｍ程度が限界である。この場合、ソース領域の幅Ｂ
は０.８〜１μｍ程度である。そのため、セルの小形化
を充分に行うことができず、オン抵抗の低減化を充分に
図れないという問題がある。In a transistor for a large current as described above, it is important to make as many transistor cells as possible in a chip of a predetermined size to reduce the on-resistance. In order to reduce the on-resistance, it is effective to increase the channel width as much as possible. In the transistor having the above-described structure, the width (length around the gate electrode) of the channel region 22a formed around the gate electrode is reduced. It is preferred that the sum be as large as possible.
However, in this type of conventional transistor, since the source electrode is in ohmic contact with the channel diffusion region on the surface of the semiconductor layer, it is necessary to expose both the source region and the channel diffusion region to the surface of the semiconductor layer.
Since a margin for overlapping the mask when diffusing the source region and a margin for overlapping the mask between the contact hole and the source region are required, for example, in the structure shown in FIG. The cell spacing (pitch between gate electrodes) A is 4.5 to 5 μm.
The limit is about 5 μm. In this case, the width B of the source region
Is about 0.8 to 1 μm. Therefore, there is a problem that the size of the cell cannot be sufficiently reduced, and the on-resistance cannot be sufficiently reduced.
【０００６】本発明は、このような問題を解決するため
になされたもので、同じ大きさのチップ面積で、ゲート
幅を大きくしてオン抵抗を小さくし、大電流化を図るこ
とができる構造の絶縁ゲート駆動型素子を有する半導体
装置を提供することを目的とする。The present invention has been made to solve such a problem, and has a structure in which a gate width can be increased, an on-resistance can be reduced, and a large current can be achieved with the same chip area. It is an object of the present invention to provide a semiconductor device having the insulated gate driving type element.
【０００７】本発明の他の目的は、チャネル拡散領域と
ソース領域の両方にソース電極をコンタクトさせる素子
を有する場合に、非常に小さい面積で、しかも簡単な工
程でコンタクトさせ得る半導体装置の製法を提供するこ
とにある。Another object of the present invention is to provide a method of manufacturing a semiconductor device which has a very small area and can be contacted by a simple process when an element for contacting a source electrode with both a channel diffusion region and a source region is provided. To provide.
【０００８】[0008]
【課題を解決するための手段】本発明者は、絶縁ゲート
型半導体装置のオン抵抗を小さくして、小さなチップサ
イズで大きな電流を得ることができる半導体装置を得る
ため鋭意検討を重ねた結果、通常、半導体層の表面にＡ
ｌなどの金属膜を直接電極として設けると、半導体層の
中にスパイクしてショートなどの問題を引き起こすた
め、バリアメタル層を介在させることが常識になってい
るが、このスパイクにより半導体層中に入り込む量が成
膜する金属膜の厚さおよび熱処理などの条件を制御する
ことにより、コントロールすることができ、そのスパイ
クした合金層が半導体層と充分にオーミックコンタクト
が得られることを見出した。そして、ソース領域とチャ
ネル拡散領域の両方にソース電極をコンタクトさせる場
合でも、ソース領域とチャネル拡散領域を縦方向に形成
し、ソース電極を下層のチャネル拡散領域までスパイク
させることにより、両層共に良好なオーミックコンタク
トが得られることを見出した。The inventor of the present invention has made intensive studies to reduce the on-resistance of an insulated gate semiconductor device and obtain a semiconductor device capable of obtaining a large current with a small chip size. Usually, A is applied to the surface of the semiconductor layer.
When a metal film such as 1 is directly provided as an electrode, spikes in the semiconductor layer cause problems such as short-circuiting. Therefore, it is common knowledge that a barrier metal layer is interposed. By controlling the conditions such as the thickness of the metal film to be formed and the heat treatment, the amount of penetration can be controlled, and it has been found that the spiked alloy layer can obtain sufficient ohmic contact with the semiconductor layer. Even when the source electrode is in contact with both the source region and the channel diffusion region, the source region and the channel diffusion region are formed in the vertical direction, and the source electrode is spiked to the lower channel diffusion region. We found that a good ohmic contact could be obtained.
【０００９】本発明による半導体装置は、ソース領域と
ドレイン領域とで挟まれるチャネル領域を絶縁ゲート電
極により制御する絶縁ゲート駆動型素子を有する半導体
装置であって、前記チャネル領域を形成するチャネル拡
散領域上にソース領域が形成される部分を少なくとも有
し、該ソース領域表面にソース電極が金属膜により形成
され、該ソース電極の金属が前記ソース領域および前記
チャネル拡散領域内にスパイクして半導体層との合金層
が形成され、該合金層を介して前記ソース電極が前記ソ
ース領域および前記チャネル拡散領域との両方にオーミ
ックコンタクトされている。A semiconductor device according to the present invention is a semiconductor device having an insulated gate driving element for controlling a channel region sandwiched between a source region and a drain region by an insulated gate electrode, wherein the channel diffusion region forms the channel region. A source region is formed on the surface of the source region by a metal film, and a metal of the source electrode spikes into the source region and the channel diffusion region to form a semiconductor layer; Is formed, and the source electrode is in ohmic contact with both the source region and the channel diffusion region via the alloy layer.
【００１０】この構造にすることにより、ソース領域拡
散のためのマスキングは必要がなく、アライメントマー
ジンもコンタクト孔形成の際だけでよく、それほど必要
としないと共に、半導体層の表面にソース領域とチャネ
ル拡散領域の両方にコンタクトするための領域を設ける
必要もなく、表面にソース領域のみが露出しておればよ
いため、コンタクト孔を非常に小さくすることができ
る。その結果、ゲート電極間隔を非常に狭くすることが
でき、セルの数を増やすことができるため、ゲート幅が
大きくなり、オン抵抗を小さくすることができ、大電流
が得られるハイパワーの半導体装置とすることができ
る。With this structure, masking for diffusion of the source region is not required, and an alignment margin is only required when forming the contact hole. Not so much is required, and the source region and the channel diffusion are formed on the surface of the semiconductor layer. There is no need to provide a region for contacting both regions, and only the source region needs to be exposed on the surface, so that the contact hole can be made very small. As a result, the interval between gate electrodes can be extremely narrowed, and the number of cells can be increased. Therefore, the gate width can be increased, the on-resistance can be reduced, and a high-power semiconductor device capable of obtaining a large current can be obtained. It can be.
【００１１】具体的には、前記絶縁ゲート駆動型素子
が、半導体層の凹溝内に前記ゲート電極が形成され、該
凹溝の横に前記チャネル拡散領域とソース領域が縦方向
に形成されるトレンチ構造の素子であったり、半導体層
の表面にゲート酸化膜を介して前記ゲート電極が形成さ
れるプレーナ型素子であってもよい。Specifically, in the insulated gate drive element, the gate electrode is formed in a concave groove of a semiconductor layer, and the channel diffusion region and the source region are formed in a vertical direction beside the concave groove. The device may be a device having a trench structure or a planar device in which the gate electrode is formed on the surface of a semiconductor layer via a gate oxide film.
【００１２】また、前記半導体層は、シリコンの他、炭
化シリコンなどを用いることもでき、前記ソース電極が
アルミニウムであれば、シリコンまたは炭化シリコンと
合金化しやすく、スパイクによる合金層を形成しやす
い。The semiconductor layer may be made of silicon carbide or the like in addition to silicon. If the source electrode is aluminum, it is easy to alloy with silicon or silicon carbide, and it is easy to form an alloy layer by spikes.
【００１３】本発明による半導体装置の製法は、（ａ）
ドレイン領域とする第１導電形の半導体層に凹溝を形成
し、該凹溝内にゲート酸化膜を介してゲート電極を形成
する工程と、（ｂ）前記ゲート電極周囲の前記半導体層
に第２導電形不純物および第１導電形不純物を順次拡散
することによりチャネル拡散領域およびソース領域を縦
方向に形成する工程と、（ｃ）前記ソース領域表面に金
属膜からなるソース電極を形成する工程と、（ｄ）熱処
理を施し、前記ソース電極の金属膜を前記ソース領域お
よびチャネル拡散領域にスパイクさせることにより、前
記ソース電極が該ソース領域およびチャネル拡散領域と
それぞれオーミックコンタクトする合金層を形成する工
程と、（ｅ）前記第１導電形半導体層と電気的に接続し
てドレイン電極を形成する工程とを有することを特徴と
する。ここに各工程の順序は限定されず、たとえば
（ａ）と（ｂ）とが逆に行われてもよい。The method of manufacturing a semiconductor device according to the present invention comprises the steps of (a)
Forming a groove in a semiconductor layer of the first conductivity type serving as a drain region, and forming a gate electrode in the groove via a gate oxide film; and (b) forming a gate electrode in the semiconductor layer around the gate electrode. Forming a channel diffusion region and a source region in the vertical direction by sequentially diffusing a two-conductivity-type impurity and a first-conductivity-type impurity; and (c) forming a source electrode made of a metal film on the surface of the source region. (D) forming an alloy layer in which the source electrode makes ohmic contact with the source region and the channel diffusion region, respectively, by performing a heat treatment and spiking the metal film of the source electrode with the source region and the channel diffusion region. And (e) forming a drain electrode by electrically connecting to the first conductivity type semiconductor layer. Here, the order of each step is not limited, and for example, (a) and (b) may be performed in reverse.
【００１４】この方法で行うことにより、チャネル拡散
領域とソース領域とを完全に縦方向に形成することがで
き、トレンチ構造のゲート駆動型半導体装置を非常に小
さな面積で形成することができる。According to this method, the channel diffusion region and the source region can be completely formed in the vertical direction, and a gate-driven semiconductor device having a trench structure can be formed with a very small area.
【００１５】前記ソース電極の形成を、前記半導体層表
面に形成した絶縁膜に前記ゲート酸化膜から離間するよ
うにコンタクト孔を形成してから行うことにより、チャ
ネル領域が合金層により侵食される虞がなく好ましい。By forming the source electrode after forming a contact hole in the insulating film formed on the surface of the semiconductor layer so as to be separated from the gate oxide film, the channel region may be eroded by the alloy layer. Is preferred because there is no
【００１６】本発明による半導体装置の製法における他
の形態は、プレーナタイプのゲート駆動型半導体装置の
製法で、（ａ'）ドレイン領域とする第１導電形の半導
体層の表面にゲート酸化膜を介してゲート電極を形成す
る工程と、（ｂ'）前記ゲート電極周囲の前記半導体層
に第２導電形不純物および第１導電形不純物を順次拡散
することにより、前記ゲート電極の下側にチャネル領域
が形成されるようにチャネル拡散領域およびソース領域
を形成する工程と、（ｃ）前記ソース領域表面に金属膜
からなるソース電極を形成する工程と、（ｄ）熱処理を
し、前記ソース電極の金属膜を前記ソース領域およびチ
ャネル拡散領域にスパイクさせることにより、該ソース
領域およびチャネル拡散領域とそれぞれオーミックコン
タクトさせる合金層を形成する工程と、（ｅ）前記第１
導電形半導体層と電気的に接続してドレイン電極を形成
する工程とを有することを特徴とする。Another embodiment of the method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a planar-type gate-driven semiconductor device, in which (a ') a gate oxide film is formed on the surface of a first conductivity type semiconductor layer serving as a drain region. Forming a gate electrode through the gate electrode; and (b ′) sequentially diffusing a second conductivity type impurity and a first conductivity type impurity into the semiconductor layer around the gate electrode, thereby forming a channel region below the gate electrode. Forming a channel diffusion region and a source region so as to form a source electrode; (c) forming a source electrode made of a metal film on the surface of the source region; and (d) performing heat treatment to form a metal of the source electrode. An alloy layer that makes the source region and the channel diffusion region come into ohmic contact with the source region and the channel diffusion region by spiking the film with the source region and the channel diffusion region. Forming, (e) said first
Forming a drain electrode by being electrically connected to the conductive semiconductor layer.
【００１７】この方法によっても、チャネル拡散領域を
ソース電極とコンタクトさせるために半導体層の表面に
露出させる必要がなく、非常にセルの間隔を小さくする
ことができ、セルの数を増やしてゲート幅を大きくし、
大電流化が可能となる。According to this method, it is not necessary to expose the channel diffusion region to the surface of the semiconductor layer in order to make contact with the source electrode. Therefore, the interval between cells can be extremely reduced, the number of cells can be increased, and the gate width can be increased. And increase
It is possible to increase the current.
【００１８】[0018]
【発明の実施の形態】つぎに、図面を参照しながら本発
明の半導体装置およびその製法について説明をする。本
発明による半導体装置は、図１にその一実施形態である
ゲート電極がトレンチ構造であるＭＯＳＦＥＴの一部の
断面説明図が示されるように、半導体層１にチャネル領
域２ａを形成するチャネル拡散領域２が設けられ、その
上にソース領域３が形成されており、ソース領域３表面
にソース電極７が金属膜により形成されている。そし
て、ソース電極７の金属がソース領域３およびチャネル
拡散領域２内にスパイクして半導体層との合金層７ａが
形成され、その合金層７ａを介してソース電極７がソー
ス領域３およびチャネル拡散領域２との両方にオーミッ
クコンタクトされている。Next, a semiconductor device of the present invention and a method of manufacturing the same will be described with reference to the drawings. A semiconductor device according to the present invention has a channel diffusion region in which a channel region 2a is formed in a semiconductor layer 1 as shown in FIG. 2, a source region 3 is formed thereon, and a source electrode 7 is formed of a metal film on the surface of the source region 3. Then, the metal of the source electrode 7 spikes into the source region 3 and the channel diffusion region 2 to form an alloy layer 7a with the semiconductor layer. The source electrode 7 is connected to the source region 3 and the channel diffusion region via the alloy layer 7a. Ohmic contact with both of them.
【００１９】半導体層１は、たとえばシリコンからなり
不純物濃度の大きいｎ+形半導体基板１ａに５μｍ程度
の厚さにエピタキシャル成長されたシリコンからなるｎ
形半導体層で、その表面にボロンなどからなるｐ形不純
物が拡散され、さらにリンなどからなるｎ形不純物が拡
散されることにより、ｐ形のチャネル拡散領域２が１μ
ｍ程度の厚さで、ｎ+形のソース領域３が０.３μｍ程度
の厚さにそれぞれ形成されている。The semiconductor layer 1 is made of, for example, silicon and epitaxially grown to a thickness of about 5 μm on an n + type semiconductor substrate 1a having a high impurity concentration.
In the p-type semiconductor layer, a p-type impurity made of boron or the like is diffused on the surface thereof, and an n-type impurity made of phosphorus or the like is further diffused.
Each of the n + -type source regions 3 is formed to a thickness of about 0.3 μm with a thickness of about m.
【００２０】そして、図１（ｂ）に平面説明図が示され
るように、ピッチが２μｍ程度の間隔（Ａ）で格子状に
０.５μｍ幅（Ｅ）程度で、１.５μｍ程度の深さに凹溝
が形成され、その凹溝内にゲート酸化膜４を介してポリ
シリコンなどからなるゲート電極５が形成されている。
半導体層の表面全面にＳｉＯ2などからなる絶縁膜６が
形成され、ソース領域３が露出するようにコンタクト孔
６ａが形成され、その表面にソース電極７とするための
Ａｌなどからなる金属膜を３μｍ程度の厚さ成膜されて
いる。As shown in the plan view of FIG. 1B, the pitch is about 0.5 μm, the pitch is about 2 μm, the width is about 0.5 μm, and the depth is about 1.5 μm. A gate electrode 5 made of polysilicon or the like is formed in the groove with a gate oxide film 4 interposed therebetween.
An insulating film 6 made of SiO 2 or the like is formed on the entire surface of the semiconductor layer, a contact hole 6a is formed so that the source region 3 is exposed, and a metal film made of Al or the like for forming a source electrode 7 is formed on the surface. The film is formed to a thickness of about 3 μm.
【００２１】この状態で、４００℃程度、３０分程度の
熱処理を行うことにより、ソース電極７とソース領域３
との界面における相互作用と相俟って、ＳｉがＡｌ中に
拡散されることにより、ＡｌとＳｉとの合金層が半導体
層の内部に進み、図１（ａ）に示されるように先端が尖
った合金層７ａが形成される。この合金層７ａは、熱処
理の温度および時間により、その内部へのスパイク深さ
が変化し、チャネル拡散領域２内に入り込み、かつ、チ
ャネル拡散領域２を突き抜けないように形成されてい
る。In this state, a heat treatment is performed at about 400 ° C. for about 30 minutes, so that the source electrode 7 and the source region 3 are formed.
In combination with the interaction at the interface with Al, Si is diffused into Al, whereby the alloy layer of Al and Si advances into the inside of the semiconductor layer, and the tip ends as shown in FIG. A sharp alloy layer 7a is formed. The alloy layer 7a is formed such that the spike depth into the alloy layer 7a changes depending on the temperature and time of the heat treatment, so that the alloy layer 7a enters the channel diffusion region 2 and does not penetrate the channel diffusion region 2.
【００２２】すなわち、前述のように、本発明者は、絶
縁ゲート型半導体装置のオン抵抗を小さくして、小さな
チップサイズで大きな電流を得ることができる半導体装
置を得るため鋭意検討を重ねた結果、半導体層表面に設
けられる金属膜がスパイクにより半導体層中に入り込む
量は、成膜する金属膜の厚さおよび熱処理などの条件を
制御することにより、コントロールすることができ、そ
の制御により図１（ａ）に示されるように、ソース領域
３およびチャネル拡散領域２のみにオーミックコンタク
トをさせることができ、しかもチャネル拡散領域２を突
き抜けないようにすることができることを見出した。That is, as described above, the present inventor has conducted intensive studies to reduce the on-resistance of the insulated gate semiconductor device and obtain a semiconductor device capable of obtaining a large current with a small chip size. The amount of the metal film provided on the surface of the semiconductor layer penetrating into the semiconductor layer by spikes can be controlled by controlling conditions such as the thickness of the metal film to be formed and heat treatment. As shown in (a), it has been found that an ohmic contact can be made only to the source region 3 and the channel diffusion region 2 and that the channel region can be prevented from penetrating.
【００２３】この合金層の深さ、すなわち、いわゆるス
パイクの深さは、熱処理の温度を高く、または熱処理の
時間を長くすることにより深くなり、非常に精度よく制
御できた。たとえばＳｉに対してＡｌ膜を設ける場合、
３００℃程度からスパイクは始まるが、４００℃程度で
行うのが最も効率的で、しかも精度よくスパイクの深さ
を制御することができた。たとえば４００℃程度で３０
分程度の熱処理を行うことにより、０.６〜０.８μｍ程
度の深さだけスパイクし、前述の０.３μｍ程度のソー
ス領域３と、１μｍ程度のチャネル拡散領域２の拡散深
さであれば、この条件で合金化処理を行うことにより、
両層にオーミックコンタクトを採りながら、チャネル拡
散領域２を突き抜ける虞は全然生じない。その結果、前
述のように、チャネル拡散領域２とソース領域３とが縦
方向に重なる部分を形成しておくことにより、その表面
からＡｌなどの金属をスパイクさせれば、両層と直接オ
ーミックコンタクトをさせることができた。The depth of the alloy layer, that is, the depth of the so-called spike, was increased by increasing the temperature of the heat treatment or lengthening the time of the heat treatment, and could be controlled very precisely. For example, when providing an Al film on Si,
The spike starts at about 300 ° C., but it is most efficient to perform the spike at about 400 ° C., and the spike depth can be controlled with high accuracy. For example, 30
By performing a heat treatment for about a minute, spikes are made to a depth of about 0.6 to 0.8 μm, and if the diffusion depth of the source region 3 of about 0.3 μm and the channel diffusion region 2 of about 1 μm is obtained. By performing the alloying process under these conditions,
There is no danger of penetrating through the channel diffusion region 2 while using ohmic contacts in both layers. As a result, as described above, by forming a portion where the channel diffusion region 2 and the source region 3 vertically overlap with each other, and by spiking a metal such as Al from the surface, direct ohmic contact with both layers is achieved. Was able to be.
【００２４】また、コンタクト孔の大きさが、１辺１μ
ｍ程度以下であれば、殆ど全体的に１本のスパイクで入
り込み、それより大きい１０μｍ程度のコンタクト孔で
は、全体で均一にスパイクしないで、何本にも分れてス
パイクすることも判明した。The size of the contact hole is 1 μm per side.
It is also found that if the length is about m or less, the spike enters almost entirely with one spike, and the contact hole of about 10 μm larger than that does not spike uniformly as a whole, but splits into several spikes.
【００２５】図１に示される構造にすることにより、コ
ンタクト孔６ａ形成用のマスクと凹溝形成用のマスクと
の重ね合せのマージンだけを考慮すればよいため、ま
た、半導体層表面のコンタクト孔はソース領域だけにコ
ンタクトさせれば良いため、非常にセル間隔を小さく形
成することができる。たとえば、コンタクト孔の大きさ
Ｃを１μｍ程度にすることができ、セル間隔Ａは、１.
５〜２μｍに形成することができる。図１に示される例
では、ソース電極７とゲート電極５とのショートを避け
るため、また、チャネル領域２ａが合金層で侵食されな
いようにするため、ゲート電極５上も含めた半導体層の
表面にＳｉＯ2などの絶縁膜６を形成し、ゲート酸化膜
４と離間してコンタクト孔を形成し、ソース電極７が形
成されているが、ゲート電極５の上部を充分に酸化して
酸化膜を形成しておくことにより、絶縁膜６を設けない
で、すなわちコンタクト孔を形成しないで、ソース電極
７を形成することができ、マスク精度ギリギリの大き
さ、たとえばＤ＝０.４μｍ、Ｅ＝０.３μｍ程度、セル
間隔Ａを０.７μｍ程度に小さくすることも可能であ
る。By adopting the structure shown in FIG. 1, only the margin for overlapping the mask for forming the contact hole 6a and the mask for forming the concave groove needs to be considered, and the contact hole on the surface of the semiconductor layer can be considered. Need only be contacted with the source region, the cell spacing can be made very small. For example, the size C of the contact hole can be about 1 μm, and the cell interval A is 1.
It can be formed to have a thickness of 5 to 2 μm. In the example shown in FIG. 1, in order to avoid a short circuit between the source electrode 7 and the gate electrode 5, and to prevent the channel region 2a from being eroded by the alloy layer, the surface of the semiconductor layer including the gate electrode 5 is formed. An insulating film 6 such as SiO 2 is formed, a contact hole is formed apart from the gate oxide film 4, and a source electrode 7 is formed. An oxide film is formed by sufficiently oxidizing an upper portion of the gate electrode 5. By doing so, the source electrode 7 can be formed without providing the insulating film 6, that is, without forming the contact hole, and the size of the mask accuracy is barely reached, for example, D = 0.4 μm, E = 0. It is also possible to reduce the cell interval A to about 3 μm and the cell interval A to about 0.7 μm.
【００２６】たとえば従来構造でゲート電極５周囲のゲ
ート酸化膜４の幅Ｅ（図１（ｂ）参照）が０.５μｍ、
隣接するゲート酸化膜４の間隔Ｄが４.５μｍ（セル間
隔Ａが５μｍ）であったのを、本発明によりＥは同じ
で、Ｄを２μｍに狭くすると、トランジスタセルの間隔
Ａは、５μｍから２.５μｍと半分になり、単位面積当
り、セルの数を４倍にすることができる。一方、オン抵
抗に影響するゲート幅となるゲート酸化膜周囲の長さ
は、２／４.５×４（単位面積当りのセルの数）＝１.７
８となり、抵抗が１.７８分の１、すなわち電流を１.７
８倍にすることができる。同様に、Ｄを１.５μｍ、１
μｍ、０.５μｍにすると、それぞれ電流を２.０８倍、
２.４７倍、２.７８倍と増やすことができる。現在のた
とえばｉ線による微細加工における露光技術の精度で
は、０.３５μｍ程度にすることができ、この技術を適
用すれば、Ｄを０.３５μｍにできるのみならず、ゲー
ト電極の幅Ｅも０.３５μｍ程度にすることができるた
め、より一層単位面積当りのセルの数を増やすことがで
き、大電流化することができる。For example, in the conventional structure, the width E of the gate oxide film 4 around the gate electrode 5 (see FIG. 1B) is 0.5 μm,
Although the distance D between adjacent gate oxide films 4 is 4.5 μm (cell distance A is 5 μm), E is the same according to the present invention. When D is narrowed to 2 μm, the distance A between transistor cells becomes 5 μm. This is a half of 2.5 μm, and the number of cells per unit area can be quadrupled. On the other hand, the length around the gate oxide film, which is the gate width affecting the on-resistance, is 2 / 4.5 × 4 (the number of cells per unit area) = 1.7.
8 and the resistance is 1/78, that is, the current is 1.7.
It can be eight times. Similarly, D is 1.5 μm, 1
μm and 0.5 μm, the current is increased by 2.08 times,
It can be increased to 2.47 times and 2.78 times. At present, the accuracy of the exposure technique in the fine processing by i-line, for example, can be about 0.35 μm, and if this technique is applied, not only can D be 0.35 μm, but also the width E of the gate electrode can be 0 μm. Since the thickness can be reduced to about 0.35 μm, the number of cells per unit area can be further increased, and the current can be increased.
【００２７】つぎに、このトレンチ構造のＭＯＳＦＥＴ
の製造方法について、図２を参照しながら説明をする。
まず図２（ａ）に示されるように、ｎ+形半導体基板１
ａ上にｎ形半導体層１を５μｍ程度エピタキシャル成長
する。そして、その表面からボロンなどのｐ形不純物を
拡散しｐ形のチャネル拡散領域２を形成し、ついで、リ
ンなどのｎ形不純物を拡散してｎ+形のソース領域３を
形成する。Next, the MOSFET having the trench structure
Will be described with reference to FIG.
First, as shown in FIG. 2 (a), n + -type semiconductor substrate 1
An n-type semiconductor layer 1 is epitaxially grown on a by about 5 μm. Then, a p-type impurity such as boron is diffused from the surface thereof to form a p-type channel diffusion region 2, and then an n-type impurity such as phosphorus is diffused to form an n + -type source region 3.
【００２８】その後、図１（ｂ）にゲート電極のパター
ンが示されるような格子状の開口部を有するレジスト膜
を半導体層表面全面に形成し、ＲＩＥなどのドライエッ
チングにより１.５μｍ程度の深さの凹溝を形成する。
その後、レジスト膜を除去し、全面にポリシリコンを堆
積して凹溝内にポリシリコンを埋め込み、エッチバック
などにより表面のポリシリコン膜を除去する。その後、
９００℃程度で、３０分程度の熱処理を行うことによ
り、図２（ｂ）に示されるように、凹溝内にゲート電極
５および０.０５μｍ程度の厚さのゲート酸化膜４を形
成する。Thereafter, a resist film having a lattice-shaped opening as shown in FIG. 1B with a gate electrode pattern is formed on the entire surface of the semiconductor layer, and is subjected to dry etching such as RIE to a depth of about 1.5 μm. A concave groove is formed.
Thereafter, the resist film is removed, polysilicon is deposited on the entire surface, polysilicon is buried in the concave groove, and the surface polysilicon film is removed by etch back or the like. afterwards,
By performing a heat treatment at about 900 ° C. for about 30 minutes, as shown in FIG. 2B, a gate electrode 5 and a gate oxide film 4 having a thickness of about 0.05 μm are formed in the concave groove.
【００２９】ついで、図２（ｃ）に示されるように、半
導体層の表面にＳｉＯ2などの絶縁膜６をＣＶＤ法など
により、０.５μｍ程度成膜し、ゲート電極５上を被覆
し、その周囲にソース領域３が露出するように開口部６
ａを形成する。そして、全面にＡｌなどの金属膜をスパ
ッタリング法などにより３μｍ程度の厚さ成膜し、ソー
ス電極７を形成する。Then, as shown in FIG. 2C, an insulating film 6 such as SiO 2 is formed on the surface of the semiconductor layer to a thickness of about 0.5 μm by a CVD method or the like to cover the gate electrode 5. The opening 6 is formed so that the source region 3 is exposed therearound.
a is formed. Then, a metal film such as Al is formed on the entire surface to a thickness of about 3 μm by a sputtering method or the like, and the source electrode 7 is formed.
【００３０】ついで、チッ素（Ｎ2）の雰囲気で、４０
０℃程度、３０分程度の熱処理を行うことにより、ソー
ス電極７の金属材料が、図２（ｄ）に示されるように、
半導体層のＳｉと合金化し、ソース領域３およびチャネ
ル拡散領域２内にスパイクして、合金層７ａを形成す
る。この場合、前述のように、この熱処理の温度および
時間により、スパイクの深さが変るため、チャネル拡散
領域２内に入り込んでオーミックコンタクトが得られる
と共に、チャネル拡散領域２を突き抜けて半導体層１に
達しないように熱処理の条件を制御する必要がある。そ
の後、半導体基板１ａの裏面に、Ｔｉなどの金属をスパ
ッタリングなどにより成膜して、ドレイン電極８を形成
することにより、図１（ａ）に示されるトレンチ構造の
ＭＯＳＦＥＴが得られる。Next, in an atmosphere of nitrogen (N 2 ), 40
By performing the heat treatment at about 0 ° C. for about 30 minutes, the metal material of the source electrode 7 becomes as shown in FIG.
Alloying with Si of the semiconductor layer and spiking into the source region 3 and the channel diffusion region 2 to form an alloy layer 7a. In this case, as described above, the depth of the spike changes depending on the temperature and time of the heat treatment, so that the semiconductor layer 1 penetrates through the channel diffusion region 2 and penetrates the channel diffusion region 2 to obtain an ohmic contact. It is necessary to control the conditions of the heat treatment so as not to reach. Thereafter, a metal such as Ti is formed on the back surface of the semiconductor substrate 1a by sputtering or the like, and the drain electrode 8 is formed, whereby the MOSFET having the trench structure shown in FIG. 1A is obtained.
【００３１】なお、図２に示される例では、チャネル拡
散領域２およびソース領域３用の拡散をしてから、凹溝
を形成してゲート電極５を形成したが、半導体層１をエ
ピタキシャル成長した後に、ゲート電極５形成してから
チャネル拡散領域２およびソース領域３用の拡散を行っ
てもよい。In the example shown in FIG. 2, after the diffusion for the channel diffusion region 2 and the source region 3 is performed, a concave groove is formed to form the gate electrode 5, but after the semiconductor layer 1 is epitaxially grown, The diffusion for the channel diffusion region 2 and the source region 3 may be performed after the gate electrode 5 is formed.
【００３２】前述の例は、トレンチ構造のＭＯＳＦＥＴ
であったが、プレーナ型のＭＯＳＦＥＴの例が図３に示
されている。このプレーナ型のＭＯＳＦＥＴを得るに
は、前述の例と同様に、ｎ+形の半導体基板１ａにｎ形
の半導体層１をエピタキシャル成長し、その表面にゲー
ト酸化膜４を介してゲート電極５を形成する。そして、
そのゲート電極５をマスクとしてｐ形不純物を拡散し、
ついでｎ形不純物を拡散することにより、等方的に、し
かも最初に拡散した不純物は後の拡散でも再度拡散する
ため、チャネル拡散領域２は図３に示されるようにゲー
ト電極５の下まで拡散し、ソース領域３との間に間隙部
を有してゲート電極５の下にチャネル領域２ａが形成さ
れる。The above example is a MOSFET having a trench structure.
However, an example of a planar type MOSFET is shown in FIG. In order to obtain this planar MOSFET, an n-type semiconductor layer 1 is epitaxially grown on an n + -type semiconductor substrate 1a, and a gate electrode 5 is formed on the surface thereof via a gate oxide film 4, as in the above-described example. I do. And
Using the gate electrode 5 as a mask, a p-type impurity is diffused,
Then, by diffusing the n-type impurity, the impurity diffused isotropically and initially diffused again in the subsequent diffusion, so that the channel diffusion region 2 is diffused below the gate electrode 5 as shown in FIG. Then, channel region 2a is formed below gate electrode 5 with a gap between source region 3 and source electrode 3.
【００３３】そして、前述の例と同様に、全面に絶縁膜
６を成膜し、ソース領域３を露出させる開口部６ａを形
成してソース電極７を形成する。さらに、前述と同様の
熱処理を行うことにより、スパイクさせ、チャネル拡散
領域２およびソース領域３とオーミックコンタクトが得
られる合金層７ａを形成し、半導体基板１ａの裏面にド
レイン電極８を形成することにより、図３に示されるプ
レーナ型のＭＯＳＦＥＴが得られる。Then, similarly to the above-described example, an insulating film 6 is formed on the entire surface, an opening 6a for exposing the source region 3 is formed, and a source electrode 7 is formed. Further, by performing the same heat treatment as described above, spikes are formed to form an alloy layer 7a capable of obtaining an ohmic contact with the channel diffusion region 2 and the source region 3, and a drain electrode 8 is formed on the back surface of the semiconductor substrate 1a. 3 is obtained.
【００３４】前述の例は、縦型ＭＯＳＦＥＴの例であっ
たが、この縦型ＭＯＳＦＥＴにさらにバイポーラトラン
ジスタが作り込まれる絶縁ゲート型バイポーラトランジ
スタ（ＩＧＢＴ）でも同様である。Although the above-described example is an example of a vertical MOSFET, the same applies to an insulated gate bipolar transistor (IGBT) in which a bipolar transistor is further formed in this vertical MOSFET.
【００３５】[0035]
【発明の効果】本発明によれば、ＭＯＳＦＥＴのチャネ
ル拡散領域とソース領域との両方にオーミックコンタク
トを得るのに、チャネル拡散領域とソース領域とが縦方
向に重なるように形成した部分の表面にソース電極を設
け、その金属材料を下層のチャネル拡散領域までスパイ
クさせてオーミックコンタクトを得ているため、非常に
小さな面積で両層にコンタクトさせることができる。そ
の結果、単位面積当りのトランジスタセルの数を非常に
増やすことができ、オン抵抗を１／２以下にすることが
でき、同じ動作電圧で電流を２倍以上に増やすことがで
きる。According to the present invention, in order to obtain ohmic contact with both the channel diffusion region and the source region of the MOSFET, the surface of the portion where the channel diffusion region and the source region are formed so as to vertically overlap each other is formed. Since an ohmic contact is obtained by providing the source electrode and spiking the metal material to the channel diffusion region in the lower layer, it is possible to contact both layers with a very small area. As a result, the number of transistor cells per unit area can be greatly increased, the on-resistance can be reduced to 以下 or less, and the current can be increased to twice or more at the same operating voltage.
【図１】本発明の半導体装置の一実施形態であるトレン
チ型ＭＯＳＦＥＴの断面および平面の説明図である。FIG. 1 is an explanatory view of a cross section and a plane of a trench MOSFET which is one embodiment of a semiconductor device of the present invention.
【図２】図１に示されるＭＯＳＦＥＴの製造工程を示す
断面説明図である。FIG. 2 is an explanatory sectional view showing a manufacturing process of the MOSFET shown in FIG. 1;
【図３】本発明による半導体装置のプレーナ型の例を示
す断面説明図である。FIG. 3 is an explanatory sectional view showing a planar type semiconductor device according to the present invention;
【図４】従来のプレーナ型ＭＯＳＦＥＴの構造を示す断
面説明図である。FIG. 4 is an explanatory sectional view showing the structure of a conventional planar MOSFET.
【図５】従来のトレンチ構造によるＭＯＳＦＥＴの構造
を示す断面説明図である。FIG. 5 is an explanatory sectional view showing a structure of a MOSFET having a conventional trench structure.
１ 半導体層 ２ チャネル拡散領域 ３ ソース領域 ４ ゲート酸化膜 ５ ゲート電極 ７ ソース電極 ７ａ 合金層 Reference Signs List 1 semiconductor layer 2 channel diffusion region 3 source region 4 gate oxide film 5 gate electrode 7 source electrode 7a alloy layer
Claims (7)
チャネル領域を絶縁ゲート電極により制御する絶縁ゲー
ト駆動型素子を有する半導体装置であって、前記チャネ
ル領域を形成するチャネル拡散領域上にソース領域が形
成される部分を少なくとも有し、該ソース領域表面にソ
ース電極が金属膜により形成され、該ソース電極の金属
が前記ソース領域および前記チャネル拡散領域内にスパ
イクして半導体層との合金層が形成され、該合金層を介
して前記ソース電極が前記ソース領域および前記チャネ
ル拡散領域との両方にオーミックコンタクトされてなる
半導体装置。1. A semiconductor device having an insulated gate driving element for controlling a channel region sandwiched between a source region and a drain region by an insulated gate electrode, wherein a source region is formed on a channel diffusion region forming the channel region. A source electrode is formed of a metal film on the surface of the source region, and a metal of the source electrode spikes into the source region and the channel diffusion region to form an alloy layer with a semiconductor layer. A semiconductor device in which the source electrode is in ohmic contact with both the source region and the channel diffusion region via the alloy layer.
の凹溝内にゲート酸化膜を介して前記ゲート電極が形成
され、該凹溝の横に前記チャネル拡散領域とソース領域
が縦方向に形成されるトレンチ構造の素子である請求項
１記載の半導体装置。2. The insulated gate drive type device according to claim 1, wherein the gate electrode is formed in a concave groove of the semiconductor layer via a gate oxide film, and the channel diffusion region and the source region are arranged vertically in the lateral direction of the concave groove. 2. The semiconductor device according to claim 1, wherein the semiconductor device is an element having a trench structure to be formed.
の表面にゲート酸化膜を介して前記ゲート電極が形成さ
れるプレーナ型素子である請求項１記載の半導体装置。3. The semiconductor device according to claim 1, wherein the insulated gate drive element is a planar element in which the gate electrode is formed on a surface of a semiconductor layer via a gate oxide film.
コンであり、前記ソース電極がアルミニウムからなる請
求項１、２または３記載の半導体装置。4. The semiconductor device according to claim 1, wherein said semiconductor layer is made of silicon or silicon carbide, and said source electrode is made of aluminum.
半導体層にトレンチを形成し、該トレンチ内にゲート酸
化膜を介してゲート電極を形成する工程と、（ｂ）前記
ゲート電極周囲の前記半導体層に第２導電形不純物およ
び第１導電形不純物を順次拡散することによりチャネル
拡散領域およびソース領域を縦方向に形成する工程と、
（ｃ）前記ソース領域表面に金属膜からなるソース電極
を形成する工程と、（ｄ）熱処理を施し、前記ソース電
極の金属膜を前記ソース領域およびチャネル拡散領域に
スパイクさせることにより、前記ソース電極が該ソース
領域およびチャネル拡散領域とそれぞれオーミックコン
タクトする合金層を形成する工程と、（ｅ）前記第１導
電形半導体層と電気的に接続してドレイン電極を形成す
る工程とを有する半導体装置の製法。5. A step of (a) forming a trench in a semiconductor layer of a first conductivity type serving as a drain region, and forming a gate electrode in the trench via a gate oxide film; and (b) surrounding the gate electrode. Forming a channel diffusion region and a source region in the vertical direction by sequentially diffusing a second conductivity type impurity and a first conductivity type impurity into the semiconductor layer;
(C) forming a source electrode made of a metal film on the surface of the source region; and (d) performing a heat treatment to spike the metal film of the source electrode into the source region and the channel diffusion region. Forming an alloy layer in ohmic contact with the source region and the channel diffusion region, respectively, and (e) forming a drain electrode by electrically connecting to the first conductivity type semiconductor layer. Manufacturing method.
表面に形成した絶縁膜に前記ゲート酸化膜から離間する
ようにコンタクト孔を形成してから行う請求項５記載の
半導体装置の製法。6. The method of manufacturing a semiconductor device according to claim 5, wherein the formation of the source electrode is performed after forming a contact hole in the insulating film formed on the surface of the semiconductor layer so as to be separated from the gate oxide film.
の半導体層の表面にゲート酸化膜を介してゲート電極を
形成する工程と、（ｂ'）前記ゲート電極周囲の前記半
導体層に第２導電形不純物および第１導電形不純物を順
次拡散することにより、前記ゲート電極の下側にチャネ
ル領域が形成されるようにチャネル拡散領域およびソー
ス領域を形成する工程と、（ｃ）前記ソース領域表面に
金属膜からなるソース電極を形成する工程と、（ｄ）熱
処理を施し、前記ソース電極の金属膜を前記ソース領域
およびチャネル拡散領域にスパイクさせることにより、
前記ソース電極が該ソース領域およびチャネル拡散領域
とそれぞれオーミックコンタクトする合金層を形成する
工程と、（ｅ）前記第１導電形半導体層と電気的に接続
してドレイン電極を形成する工程とを有する半導体装置
の製法。7. A step (a ′) of forming a gate electrode on a surface of a semiconductor layer of the first conductivity type serving as a drain region via a gate oxide film; and (b ′) forming a gate electrode around the gate electrode. Forming a channel diffusion region and a source region such that a channel region is formed below the gate electrode by sequentially diffusing a second conductivity type impurity and a first conductivity type impurity; Forming a source electrode made of a metal film on the surface of the region, and (d) performing a heat treatment to spike the metal film of the source electrode into the source region and the channel diffusion region.
Forming an alloy layer in which the source electrode makes ohmic contact with the source region and the channel diffusion region, respectively; and (e) forming a drain electrode electrically connected to the first conductivity type semiconductor layer. Manufacturing method of semiconductor device.
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Cited By (3)
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|---|---|---|---|---|
| US7091555B2 (en) | 2003-04-02 | 2006-08-15 | Rohm Co., Ltd. | Semiconductor device for switching |
| JP2014187192A (en) * | 2013-03-22 | 2014-10-02 | Toshiba Corp | Semiconductor device |
| JP2019091912A (en) * | 2019-01-28 | 2019-06-13 | 富士電機株式会社 | Semiconductor device |
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|---|---|
| JP4909465B2 (en) | 2012-04-04 |
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