JP2002280554A - Method for manufacturing vertical field-effect transistor - Google Patents
Method for manufacturing vertical field-effect transistorInfo
- Publication number
- JP2002280554A JP2002280554A JP2001081111A JP2001081111A JP2002280554A JP 2002280554 A JP2002280554 A JP 2002280554A JP 2001081111 A JP2001081111 A JP 2001081111A JP 2001081111 A JP2001081111 A JP 2001081111A JP 2002280554 A JP2002280554 A JP 2002280554A
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- JP
- Japan
- Prior art keywords
- region
- type
- semiconductor layer
- insulating film
- gate insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、縦型電界効果トラ
ンジスタの製造方法に関し、特に、珪素よりバンドギャ
ップが大きい半導体材料から形成される縦型電界効果ト
ランジスタの製造方法に関する。The present invention relates to a method of manufacturing a vertical field effect transistor, and more particularly to a method of manufacturing a vertical field effect transistor formed of a semiconductor material having a band gap larger than that of silicon.
【０００２】[0002]
【従来の技術】従来、炭化珪素（ＳｉＣ）などの珪素
（Ｓｉ）よりバンドギャップが大きい半導体材料を用い
た縦型電界効果トランジスタ（Field Effect Transisto
r，以下ＦＥＴ）では、ドレイン領域となるｎ型の半導
体基板上にｎ型のドリフト領域を形成した後、イオン注
入法を用いてドリフト領域の表面に選択的にｐ型のウェ
ル領域を形成し、このウェル領域にｎ型のソース領域を
イオン注入法を用いて形成していた。一般的に、バンド
ギャップが大きい半導体材料は、結晶同士の結合が強固
であるため、イオンを結晶間に注入するためには、５０
０〜８００℃程度の高温下でイオンを注入する高温イオ
ン注入を行なう必要がある。2. Description of the Related Art Conventionally, a vertical field effect transistor (Field Effect Transistor) using a semiconductor material having a larger band gap than silicon (Si) such as silicon carbide (SiC) is known.
r, hereinafter referred to as FET), after forming an n-type drift region on an n-type semiconductor substrate serving as a drain region, a p-type well region is selectively formed on the surface of the drift region by ion implantation. An n-type source region is formed in this well region by using an ion implantation method. In general, a semiconductor material having a large band gap has a strong bond between crystals.
It is necessary to perform high-temperature ion implantation for implanting ions at a high temperature of about 0 to 800 ° C.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、このよ
うな高温イオン注入によりウェル領域を形成すると、ウ
ェル領域の表面が荒れてしまうため、ウェル領域の表面
に形成される反転層（チャネル）での移動度（チャネル
移動度）が低下してしまう。この結果、縦型ＦＥＴのチ
ャネル抵抗が増加し、オン抵抗が高くなるという問題が
あった。However, when the well region is formed by such high-temperature ion implantation, the surface of the well region is roughened, and the movement in the inversion layer (channel) formed on the surface of the well region is caused. Degree (channel mobility) is reduced. As a result, there is a problem that the channel resistance of the vertical FET increases and the on-resistance increases.
【０００４】本発明は、上記課題を解決するためになさ
れたものであり、チャネル抵抗が低くオン抵抗が低い縦
型ＦＥＴを製造することを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to manufacture a vertical FET having a low channel resistance and a low on-resistance.
【０００５】[0005]
【課題を解決するための手段】本発明の縦型電界効果ト
ランジスタの製造方法は、珪素よりバンドギャップが大
きい半導体材料から形成され、ドレイン領域となる一導
電型の半導体基板に設けた一導電型の第１ドリフト領域
と、前記第１ドリフト領域上に互いに接して設けた一導
電型の第２ドリフト領域及び他導電型のウェル領域と、
前記ウェル領域の表面に前記第２ドリフト領域と所定距
離離して設けた一導電型のソース領域と、前記ウェル領
域の表面であって前記第２ドリフト領域と前記ソース領
域とにより挟持されたチャネル形成領域上に形成され上
部にゲート電極が形成されるゲート絶縁膜とを備える縦
型電界効果トランジスタの製造方法であって、前記第１
ドリフト領域上に前記ウェル領域になる他導電型の半導
体層と前記ゲート絶縁膜になる絶縁層とを順に成膜した
後、前記絶縁層と前記半導体層とを順にパターニングし
て前記ウェル領域及び前記チャネル形成領域上のゲート
絶縁膜を形成するウェル−ゲート絶縁膜形成工程を備え
ることを特徴とする。A method of manufacturing a vertical field effect transistor according to the present invention is directed to a method of manufacturing a vertical field effect transistor which is formed from a semiconductor material having a band gap larger than that of silicon and is provided on a semiconductor substrate of one conductivity type serving as a drain region. A first drift region, a second drift region of one conductivity type and a well region of another conductivity type provided in contact with each other on the first drift region,
A source region of one conductivity type provided on the surface of the well region at a predetermined distance from the second drift region, and a channel formed on the surface of the well region and sandwiched by the second drift region and the source region A method for manufacturing a vertical field effect transistor, comprising: a gate insulating film formed on a region and having a gate electrode formed thereon;
After sequentially forming a semiconductor layer of another conductivity type that becomes the well region and an insulating layer that becomes the gate insulating film on the drift region, the insulating layer and the semiconductor layer are sequentially patterned to form the well region and the semiconductor layer. A step of forming a well-gate insulating film for forming a gate insulating film over the channel formation region;
【０００６】本発明の縦型電界効果トランジスタの製造
方法では、ウェル領域になる半導体層とゲート絶縁膜に
なる絶縁層とを順に成膜した後パターニングして、ウェ
ル領域とチャネル形成領域上のゲート絶縁膜とを形成す
るので、チャネル形成領域の表面の荒れを抑えることが
でき、チャネル形成領域とゲート絶縁膜との界面状態を
良くすることができる。この結果、チャネル移動度の低
下を抑えることができ、チャネル抵抗が低くオン抵抗が
低い縦型電界効果トランジスタを製造することができ
る。尚、珪素よりバンドギャップが大きい半導体材料
は、ＩｎＰ，ＧａＡｓ，ＣｄＴｅ，ＡｌＳｂ，ＣｄＳ
ｅ，ＩｎＮ，ＳｉＣ，ＧａＰ，ＣｄＳ，ＡｇＩ，Ｚｎ
Ｏ，ＡｇＣｌ，ＧａＮ，ＺｎＳ，ダイアモンド，ＢＮ，
ＡｌＮなどを含むものとし、特にＳｉＣとするのが好適
である。In the method of manufacturing a vertical field effect transistor according to the present invention, a semiconductor layer serving as a well region and an insulating layer serving as a gate insulating film are sequentially formed and then patterned to form a gate on the well region and a channel forming region. Since the insulating film is formed, roughness of the surface of the channel formation region can be suppressed, and the interface state between the channel formation region and the gate insulating film can be improved. As a result, a reduction in channel mobility can be suppressed, and a vertical field-effect transistor having low channel resistance and low on-resistance can be manufactured. Note that semiconductor materials having a band gap larger than that of silicon include InP, GaAs, CdTe, AlSb, and CdS.
e, InN, SiC, GaP, CdS, AgI, Zn
O, AgCl, GaN, ZnS, diamond, BN,
It is preferable to include AlN and the like, and particularly to use SiC.
【０００７】本発明の縦型電界効果トランジスタにおい
て、前記ウェル−ゲート絶縁膜形成工程は、前記半導体
層の不純物濃度を変化させながら前記半導体層を成膜し
てもよい。こうすれば、性能の良い縦型電界効果トラン
ジスタを製造することができる。In the vertical field effect transistor according to the present invention, in the well-gate insulating film forming step, the semiconductor layer may be formed while changing an impurity concentration of the semiconductor layer. In this case, a vertical field-effect transistor having good performance can be manufactured.
【０００８】[0008]
【発明の実施の形態】以下、本発明の実施の形態（以下
実施形態という）を、図面に従って説明する。尚、各図
において同一の部材には同一の符号を付し説明を省略す
る。Embodiments of the present invention (hereinafter referred to as embodiments) will be described below with reference to the drawings. In the drawings, the same members are denoted by the same reference numerals, and description thereof will be omitted.
【０００９】図１は、本実施形態の縦型電界効果トラン
ジスタの一例として、ＳｉＣからなる縦型パワーＭＯＳ
ＦＥＴ（Metal Oxide Semiconductor Field Effect Tra
nsistor）の製造方法を示すフローチャートであり、図
２〜図１０は、各工程での縦型パワーＭＯＳＦＥＴの断
面図である。縦型パワーＭＯＳＦＥＴの製造方法は、不
純物濃度が１０18〜１０20ｃｍ-3程度のｎ型基板１０
に、ＣＶＤ（Chemical Vapor Deposition）法を用いて
ｎ型基板１０と同多形で層厚が５〜５０μｍ程度であり
不純物濃度が１０15〜１０18ｃｍ-3程度のｎ型の半導体
層を形成し、この半導体層からなるｎ型ドリフト領域１
２ａを形成する工程（工程Ｓ１０，図２）から始める。
尚、ｎ型基板１０は、多形が４Ｈ又は６Ｈ，面方位が
（０００１）又は（０００１），ｏｆｆ角度が１度〜１
０度，ｏｆｆ方向が［１１２０］の基板や、多形が４Ｈ
又は６Ｈ，面方位が（１１−２０）の基板や、多形が３
Ｃの基板などを用いるのがよい。また、ｎ型ドリフト領
域１２ａの厚さは、製造する縦型パワーＭＯＳＦＥＴの
耐圧に応じて適宜設定する。FIG. 1 shows a vertical power MOS transistor made of SiC as an example of a vertical field effect transistor of this embodiment.
FET (Metal Oxide Semiconductor Field Effect Tra)
FIGS. 2 to 10 are cross-sectional views of a vertical power MOSFET in respective steps. The manufacturing method of the vertical power MOSFET is based on an n-type substrate 10 having an impurity concentration of about 10 18 to 10 20 cm −3.
Then, an n-type semiconductor layer having the same polymorphism as the n-type substrate 10 having a layer thickness of about 5 to 50 μm and an impurity concentration of about 10 15 to 10 18 cm −3 is formed by using a CVD (Chemical Vapor Deposition) method. The n-type drift region 1 made of the semiconductor layer
The process starts with the step of forming 2a (step S10, FIG. 2).
The n-type substrate 10 has a polymorph of 4H or 6H, a plane orientation of (0001) or (0001), and an off angle of 1 degree to 1 degree.
Substrate with 0 degree, off direction of [1120] or polymorph 4H
Or 6H, a substrate with a plane orientation of (11-20) or a polymorph of 3
It is preferable to use a C substrate or the like. The thickness of the n-type drift region 12a is appropriately set according to the withstand voltage of the vertical power MOSFET to be manufactured.
【００１０】次に、ｎ型ドリフト領域１２ａ上にＣＶＤ
法を用いてｎ型ドリフト領域１２ａと同多形であり層厚
が１〜１０μｍ程度で不純物濃度が１０15〜１０18ｃｍ
-3程度のｐ型ウェル領域となるｐ型半導体層１４ａを形
成する（工程Ｓ１２，図３）。そして、ｐ型半導体層１
４ａ上に、ＣＶＤ法を用いて層厚が０．０３μｍ程度で
ＳｉＯ2からなりゲート絶縁膜の一部をなす絶縁層１６
ａを形成する（工程Ｓ１４，図４）。Next, CVD is performed on the n-type drift region 12a.
The same polymorphism as the n-type drift region 12a, a layer thickness of about 1 to 10 μm, and an impurity concentration of 10 15 to 10 18 cm
A p-type semiconductor layer 14a serving as a p-type well region of about -3 is formed (step S12, FIG. 3). And the p-type semiconductor layer 1
An insulating layer 16 made of SiO 2 and having a thickness of about 0.03 μm and forming a part of the gate insulating film is formed on
a is formed (step S14, FIG. 4).
【００１１】そして、絶縁層１６ａ上にレジストを塗布
しフォトリソグラフィ法を用いてレジストに開口を形成
し、このレジストをマスクとしてフッ酸又はＲＩＥ（Re
active Ion etching）法などの異方性エッチング法を用
いて、絶縁層１６ａとｐ型半導体層１４ａとをパターニ
ングし、残余のｐ型半導体層１４ａからなるｐ型ウェル
領域１４を形成すると共にトレンチ１８を形成する（工
程Ｓ１６，図５）。尚、ＲＩＥ法を行なう場合、反応ガ
スは、ＣＦ4とＯ2との混合ガス又はＣＦ4とＨ2との混合
ガスなどから適宜選択する。Then, a resist is applied on the insulating layer 16a, an opening is formed in the resist by photolithography, and hydrofluoric acid or RIE (Re
The insulating layer 16a and the p-type semiconductor layer 14a are patterned by using an anisotropic etching method such as an active ion etching method to form a p-type well region 14 including the remaining p-type semiconductor layer 14a and a trench 18 Is formed (step S16, FIG. 5). When the RIE method is performed, a reaction gas is appropriately selected from a mixed gas of CF 4 and O 2 or a mixed gas of CF 4 and H 2 .
【００１２】次に、トレンチ１８内にＣＶＤ法を用いて
ｎ型半導体層を成長させＣＭＰ（Chemical Mechanical
Polishing）により表面を平坦化し、ｎ型ドリフト領域
１２ｂを形成する（工程Ｓ１８，図６）。このとき、ｎ
型ドリフト領域１２ｂは、トレンチ１８の底部の部位か
ら表面にかけて不純物濃度が徐々に低くなるように形成
する。Next, an n-type semiconductor layer is grown in the trench 18 by using a CVD method, and a CMP (Chemical Mechanical
Polishing) to form a flat surface to form an n-type drift region 12b (step S18, FIG. 6). At this time, n
The mold drift region 12b is formed such that the impurity concentration gradually decreases from the bottom portion of the trench 18 to the surface.
【００１３】そして、表面にＣＶＤ法を用いて０．０２
μｍ程度のＳｉＯ2からなりゲート絶縁膜の一部をなす
絶縁層１６ｂを形成する（工程Ｓ２０，図７）。その
後、レジストを塗布してフォトリソグラフィ法を用いて
レジストに開口を形成し、このレジストをマスクとして
フッ酸又はＲＩＥ法などの異方性エッチング法を用いて
絶縁層１６ｂ，１６ａ，ｐ型ウェル領域１４を順にエッ
チングし、トレンチ２０を形成する。そして、このトレ
ンチ２０にＣＶＤ法を用いてｎ型ソース領域２２となる
ｎ型半導体層２２ａを形成し、レジストを除去しＣＭＰ
により表面を平坦化する（図８）。次に、レジストを塗
布しフォトリソグラフィ法を用いて絶縁層１６ａ，１６
ｂのゲート絶縁膜として残す部分上のレジストを残し、
このレジストをマスクとしてＲＩＥ法を用いて絶縁層１
６ｂ，１６ａ，ｎ型半導体層２２ａを除去し、残余のｎ
型半導体層２２ａからなるｎ型ソース領域２２と残余の
絶縁層１６ａ，１６ｂとからなるゲート絶縁膜を形成す
る（工程Ｓ２２，図９）。その後、ｎ型基板１０の裏面
にドレイン電極２４を形成し、絶縁層１６ｂ上にゲート
電極２６を形成し、ｎ型ソース領域２２上にソース電極
２８を形成し（工程Ｓ２４，図１０）、縦型パワーＭＯ
ＳＦＥＴの製造工程を終了する。Then, the surface is formed to a thickness of 0.02 by CVD.
An insulating layer 16b made of SiO 2 of about μm and forming a part of the gate insulating film is formed (Step S20, FIG. 7). Thereafter, a resist is applied, openings are formed in the resist by using a photolithography method, and the insulating layers 16b, 16a, and p-type well regions are formed by using the resist as a mask and using an anisotropic etching method such as hydrofluoric acid or RIE. 14 are sequentially etched to form a trench 20. Then, an n-type semiconductor layer 22a to be an n-type source region 22 is formed in the trench 20 by using the CVD method, and the resist is removed.
To flatten the surface (FIG. 8). Next, a resist is applied and the insulating layers 16a and 16
b, leaving the resist on the portion to be left as the gate insulating film,
Using this resist as a mask, the insulating layer 1 is formed by RIE.
6b, 16a and the n-type semiconductor layer 22a are removed, and the remaining n-type semiconductor layer 22a is removed.
A gate insulating film including the n-type source region 22 composed of the type semiconductor layer 22a and the remaining insulating layers 16a and 16b is formed (step S22, FIG. 9). Thereafter, a drain electrode 24 is formed on the back surface of the n-type substrate 10, a gate electrode 26 is formed on the insulating layer 16b, and a source electrode 28 is formed on the n-type source region 22 (step S24, FIG. 10). Type power MO
The manufacturing process of the SFET is completed.
【００１４】以上説明した方法で製造した縦型パワーＭ
ＯＳＦＥＴにおいて、オン状態になると、ｐ型ウェル領
域１４の表面のｎ型ソース領域２２とｎ型ドリフト領域
１２ｂとで挟持された領域に反転層が形成され（この領
域をチャネル形成領域とする）、ソース電極２８から注
入された電子は、ｎ型ソース領域２２，ｐ型ウェル領域
１４のチャネル形成領域，ｎ型ドリフト領域１２ｂ，１
２ａ，ｎ型基板１０を介してドレイン電極２４へ流れ
る。ｐ型ウェル領域１４と絶縁層１６ａとは、図１に示
した工程Ｓ１２，Ｓ１４においてＣＶＤ法により形成し
ている。更に、ｐ型ウェル領域１４のチャネル形成領域
は、工程Ｓ１６以降、上部に絶縁層１６ａを形成した状
態で処理されている。このため、チャネル形成領域の表
面の荒れを抑えることができ、チャネル形成領域と絶縁
層１６ａとの界面状態を良くすることができる。従っ
て、このような方法で縦型パワーＭＯＳＦＥＴを製造す
ると、チャネル移動度の低下を抑えることができ、チャ
ネル抵抗が低くオン抵抗が低い縦型パワーＭＯＳＦＥＴ
を製造することができる。また、ｎ型ドリフト領域１２
ｂは、不純物濃度を変化させながら形成したので、パワ
ーＭＯＳＦＥＴの性能の向上を図ることもできる。The vertical power M manufactured by the method described above
When the OSFET is turned on, an inversion layer is formed on the surface of the p-type well region 14 between the n-type source region 22 and the n-type drift region 12b (this region is referred to as a channel formation region). The electrons injected from the source electrode 28 are supplied to the n-type source region 22, the channel forming region of the p-type well region 14, and the n-type drift regions 12b, 1
2a, it flows to the drain electrode 24 via the n-type substrate 10. The p-type well region 14 and the insulating layer 16a are formed by the CVD method in steps S12 and S14 shown in FIG. Further, the channel formation region of the p-type well region 14 is processed after the step S16, with the insulating layer 16a formed thereon. Therefore, roughness of the surface of the channel formation region can be suppressed, and the interface state between the channel formation region and the insulating layer 16a can be improved. Therefore, when a vertical power MOSFET is manufactured by such a method, a decrease in channel mobility can be suppressed, and a vertical power MOSFET having low channel resistance and low on-resistance can be suppressed.
Can be manufactured. The n-type drift region 12
Since b is formed while changing the impurity concentration, the performance of the power MOSFET can be improved.
【００１５】尚、本実施形態の製造方法では、縦型パワ
ーＭＯＳＦＥＴをＳｉＣからなるものとしたが、図１１
に示すような他のＳｉよりバンドギャップの大きい半導
体材料からなるものとしてもよい。In the manufacturing method of this embodiment, the vertical power MOSFET is made of SiC.
It may be made of a semiconductor material having a larger band gap than other Si as shown in FIG.
【００１６】また、本実施形態では、縦型電界効果トラ
ンジスタの一例として、縦型パワーＭＯＳＦＥＴを例示
したが、これに限定したものではなく、ＩＧＢＴ（Insu
lated Gate Bipolar Transistor）などｐ型ウェル領域
１４の表面に反転層を形成する他の縦型電界効果トラン
ジスタとしてもよい。In the present embodiment, a vertical power MOSFET has been exemplified as an example of a vertical field effect transistor. However, the present invention is not limited to this, and an IGBT (Insu
Other vertical field-effect transistors that form an inversion layer on the surface of the p-type well region 14, such as a lated Gate Bipolar Transistor, may be used.
【００１７】以上、本実施形態を説明したが、本発明は
こうした実施形態に何等限定されるものではなく、例え
ば、各半導体層の導電型を異なるものとした形態など、
本発明の要旨を逸脱しない範囲内において、種々なる形
態で実施し得ることは勿論である。Although the present embodiment has been described above, the present invention is not limited to such an embodiment. For example, an embodiment in which the conductivity type of each semiconductor layer is different.
It goes without saying that the present invention can be implemented in various forms without departing from the gist of the present invention.
【００１８】[0018]
【発明の効果】以上説明したように、本発明の縦型電界
効果トランジスタの製造方法では、ウェル領域になる半
導体層とゲート絶縁膜になる絶縁層とを順に成膜した後
パターニングして、ウェル領域とチャネル形成領域上の
ゲート絶縁膜とを形成するので、チャネル形成領域の表
面の荒れを抑えることができ、チャネル形成領域とゲー
ト絶縁膜との界面状態を良くすることができる。この結
果、チャネル移動度の低下を抑えることができ、チャネ
ル抵抗が低くオン抵抗が低い縦型電界効果トランジスタ
を製造することができる。As described above, in the method of manufacturing a vertical field effect transistor according to the present invention, a semiconductor layer serving as a well region and an insulating layer serving as a gate insulating film are sequentially formed and then patterned to form a well. Since the region and the gate insulating film over the channel formation region are formed, roughness of the surface of the channel formation region can be suppressed, and the interface state between the channel formation region and the gate insulating film can be improved. As a result, a decrease in channel mobility can be suppressed, and a vertical field-effect transistor having low channel resistance and low on-resistance can be manufactured.
【図１】 ＳｉＣからなる縦型パワーＭＯＳＦＥＴの製
造方法を示すフローチャートである。FIG. 1 is a flowchart showing a method for manufacturing a vertical power MOSFET made of SiC.
【図２】 工程Ｓ１０を終えたときのパワーＭＯＳＦＥ
Ｔの断面図である。FIG. 2 shows a power MOSFET when a process S10 is completed.
It is sectional drawing of T.
【図３】 工程Ｓ１２を終えたときのパワーＭＯＳＦＥ
Ｔの断面図である。FIG. 3 shows a power MOSFET when a process S12 is completed.
It is sectional drawing of T.
【図４】 工程Ｓ１４を終えたときのパワーＭＯＳＦＥ
Ｔの断面図である。FIG. 4 shows a power MOSFE after step S14 is completed.
It is sectional drawing of T.
【図５】 工程Ｓ１６を終えたときのパワーＭＯＳＦＥ
Ｔの断面図である。FIG. 5 shows a power MOSFE after step S16 is completed.
It is sectional drawing of T.
【図６】 工程Ｓ１８を終えたときのパワーＭＯＳＦＥ
Ｔの断面図である。FIG. 6 shows a power MOSFE after step S18 is completed.
It is sectional drawing of T.
【図７】 工程Ｓ２０を終えたときのパワーＭＯＳＦＥ
Ｔの断面図である。FIG. 7 shows a power MOSFE after step S20 is completed.
It is sectional drawing of T.
【図８】 工程Ｓ２２を行なっている途中のパワーＭＯ
ＳＦＥＴの断面図である。FIG. 8 shows a power MO in the middle of performing step S22.
It is sectional drawing of SFET.
【図９】 工程Ｓ２２を終えたときのパワーＭＯＳＦＥ
Ｔの断面図である。FIG. 9 shows a power MOSFE after step S22 is completed.
It is sectional drawing of T.
【図１０】 工程Ｓ２４を終えたときのパワーＭＯＳＦ
ＥＴの断面図である。FIG. 10 shows a power MOSF when step S24 is completed.
It is sectional drawing of ET.
【図１１】 Ｓｉよりバンドギャップの大きい半導体材
料を示す表である。FIG. 11 is a table showing semiconductor materials having a larger band gap than Si.
１０ ｎ型基板、１２ａ，１２ｂ ｎ型ドリフト領域、
１４ ｐ型ウェル領域、１４ａ ｐ型半導体層、１６
ａ，１６ｂ 絶縁層、２２ ｎ型ソース領域。10 n-type substrate, 12a, 12b n-type drift region,
14 p-type well region, 14 a p-type semiconductor layer, 16
a, 16b Insulating layer, 22 n-type source region.
Claims (2)
材料から形成され、ドレイン領域となる一導電型の半導
体基板に設けた一導電型の第１ドリフト領域と、前記第
１ドリフト領域上に互いに接して設けた一導電型の第２
ドリフト領域及び他導電型のウェル領域と、前記ウェル
領域の表面に前記第２ドリフト領域と所定距離離して設
けた一導電型のソース領域と、前記ウェル領域の表面で
あって前記第２ドリフト領域と前記ソース領域とにより
挟持されたチャネル形成領域上に形成され上部にゲート
電極が形成されるゲート絶縁膜とを備える縦型電界効果
トランジスタの製造方法であって、 前記第１ドリフト領域上に前記ウェル領域になる他導電
型の半導体層と前記ゲート絶縁膜になる絶縁層とを順に
成膜した後、前記絶縁層と前記半導体層とを順にパター
ニングして前記ウェル領域及び前記チャネル形成領域上
のゲート絶縁膜を形成するウェル−ゲート絶縁膜形成工
程を備えることを特徴とする縦型電界効果トランジスタ
の製造方法。1. A first conductivity type first drift region provided on a one conductivity type semiconductor substrate which is formed of a semiconductor material having a band gap larger than that of silicon and serves as a drain region, and is in contact with each other on the first drift region. Provided one conductivity type second
A drift region and a well region of another conductivity type; a source region of one conductivity type provided on the surface of the well region at a predetermined distance from the second drift region; and a second drift region on the surface of the well region. And a gate insulating film formed on a channel formation region sandwiched by the source region and having a gate electrode formed thereon. The method of manufacturing a vertical field effect transistor, comprising: After sequentially forming a semiconductor layer of another conductivity type to be a well region and an insulating layer to be the gate insulating film, the insulating layer and the semiconductor layer are sequentially patterned to form a semiconductor layer on the well region and the channel forming region. A method for manufacturing a vertical field effect transistor, comprising a step of forming a well-gate insulating film for forming a gate insulating film.
前記半導体層の不純物濃度を変化させながら前記半導体
層を成膜することを特徴とする請求項１に記載の縦型電
界効果トランジスタの製造方法。2. The step of forming a well-gate insulating film,
2. The method according to claim 1, wherein the semiconductor layer is formed while changing an impurity concentration of the semiconductor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001081111A JP2002280554A (en) | 2001-03-21 | 2001-03-21 | Method for manufacturing vertical field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001081111A JP2002280554A (en) | 2001-03-21 | 2001-03-21 | Method for manufacturing vertical field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002280554A true JP2002280554A (en) | 2002-09-27 |
Family
ID=18937270
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001081111A Pending JP2002280554A (en) | 2001-03-21 | 2001-03-21 | Method for manufacturing vertical field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002280554A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007189078A (en) * | 2006-01-13 | 2007-07-26 | Sumitomo Electric Ind Ltd | Vertical transistor, manufacturing method thereof, and growing method of nitride semiconductor |
| JP2008103636A (en) * | 2006-10-20 | 2008-05-01 | Sumitomo Electric Ind Ltd | Vertical transistor and its producing method |
| JP2010067670A (en) * | 2008-09-09 | 2010-03-25 | Sumitomo Electric Ind Ltd | Well structure, method for generating the same, and semiconductor device |
| CN102468327A (en) * | 2010-11-10 | 2012-05-23 | 三菱电机株式会社 | Semiconductor device and method for manufacturing the same |
| WO2016132987A1 (en) * | 2015-02-20 | 2016-08-25 | 住友電気工業株式会社 | Silicon carbide semiconductor device |
| EP3651206A1 (en) * | 2010-03-30 | 2020-05-13 | Rohm Co., Ltd. | Semiconductor device |
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2001
- 2001-03-21 JP JP2001081111A patent/JP2002280554A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007189078A (en) * | 2006-01-13 | 2007-07-26 | Sumitomo Electric Ind Ltd | Vertical transistor, manufacturing method thereof, and growing method of nitride semiconductor |
| JP2008103636A (en) * | 2006-10-20 | 2008-05-01 | Sumitomo Electric Ind Ltd | Vertical transistor and its producing method |
| JP2010067670A (en) * | 2008-09-09 | 2010-03-25 | Sumitomo Electric Ind Ltd | Well structure, method for generating the same, and semiconductor device |
| EP3651206A1 (en) * | 2010-03-30 | 2020-05-13 | Rohm Co., Ltd. | Semiconductor device |
| US10727318B2 (en) | 2010-03-30 | 2020-07-28 | Rohm Co., Ltd. | Semiconductor device VDMOS having a gate insulating film having a high dielectric constant portion contacting the drift region for relaxing an electric field generated in the gate insulating film |
| EP4012783A1 (en) * | 2010-03-30 | 2022-06-15 | Rohm Co., Ltd. | Semiconductor device |
| CN102468327A (en) * | 2010-11-10 | 2012-05-23 | 三菱电机株式会社 | Semiconductor device and method for manufacturing the same |
| JP2012104648A (en) * | 2010-11-10 | 2012-05-31 | Mitsubishi Electric Corp | Semiconductor device and method of manufacturing the same |
| US8987817B2 (en) | 2010-11-10 | 2015-03-24 | Mitsubishi Electric Corporation | Semiconductor device having a gate insulating film with a thicker portion covering a surface of an epitaxial protrusion and manufacturing method thereof |
| WO2016132987A1 (en) * | 2015-02-20 | 2016-08-25 | 住友電気工業株式会社 | Silicon carbide semiconductor device |
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