JP2002270760A - Electronic component, assembly thereof and its manufacturing method - Google Patents
Electronic component, assembly thereof and its manufacturing methodInfo
- Publication number
- JP2002270760A JP2002270760A JP2001064038A JP2001064038A JP2002270760A JP 2002270760 A JP2002270760 A JP 2002270760A JP 2001064038 A JP2001064038 A JP 2001064038A JP 2001064038 A JP2001064038 A JP 2001064038A JP 2002270760 A JP2002270760 A JP 2002270760A
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- electrode
- electrodes
- wiring electrodes
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、サイズが異なる電
子部品、例えば、ベアの半導体集積回路チップ（以下、
単に「ＩＣチップ」と記す）を積層して回路基板上に実
装することができる電子部品及びその製造方法に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to electronic components of different sizes, for example, bare semiconductor integrated circuit chips
The present invention relates to an electronic component which can be mounted on a circuit board by stacking (hereinafter simply referred to as "IC chip") and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】先ず、図７乃至図９を参照しながら、従
来技術の電子部品を説明する。なお、以下の説明におい
ては、電子部品の一例として、サイズが異なる２個の半
導体装置が積層された複合体の半導体装置を採り上げ、
それがインターポーザなどへ実装されている構造のもの
を説明する。2. Description of the Related Art First, a conventional electronic component will be described with reference to FIGS. In the following description, a composite semiconductor device in which two semiconductor devices having different sizes are stacked as an example of an electronic component will be described.
A structure in which it is mounted on an interposer or the like will be described.
【０００３】図７は従来技術の第１形態の半導体装置の
積層構造を示す断面側面図、図８は従来技術の第２形態
の半導体装置の積層構造を示す断面側面図、そして図９
は従来技術の第３形態の半導体装置の積層構造を示す断
面側面図である。FIG. 7 is a cross-sectional side view showing a laminated structure of a semiconductor device according to a first prior art, FIG. 8 is a cross-sectional side view showing a laminated structure of a semiconductor device according to a second embodiment of the prior art, and FIG.
FIG. 4 is a cross-sectional side view showing a laminated structure of a semiconductor device according to a third embodiment of the related art.
【０００４】先ず、図７を参照しながら従来技術の第１
形態の半導体装置の積層構造を説明する。First, a first prior art will be described with reference to FIG.
The stacked structure of the semiconductor device according to the embodiment will be described.
【０００５】図７において、符号１Ｂは全体としてこの
第１形態の半導体装置を指す。この半導体装置１Ｂはサ
イズの異なるベアのＩＣチップ１０、２０から構成され
ていて、それぞれのＩＣチップ１０、２０の電子回路が
形成されている表面には複数のバンプ１１、２１がそれ
ぞれ形成されている。そしてこの半導体装置１Ｂは、こ
れらのＩＣチップ１０、２０の内、サイズの大きいＩＣ
チップ１０が、その表面を上向きにしてインターポーザ
２の上に絶縁ペースト３を介してダイボンドされてお
り、そのＩＣチップ１０の上に、サイズの小さいＩＣチ
ップ２０が、その表面を上向きにし、絶縁ペースト３を
介してダイボンドされており、それぞれのバンプ１１、
２１がインターポーザ２の異なる位置に形成されている
回路パターンにワイヤ４を用いて接続され、そして全体
を電気絶縁樹脂５で封止した構造のものである。In FIG. 7, reference numeral 1B indicates the semiconductor device of the first embodiment as a whole. The semiconductor device 1B is composed of bare IC chips 10 and 20 having different sizes, and a plurality of bumps 11 and 21 are formed on the surface of each of the IC chips 10 and 20 on which electronic circuits are formed. I have. The semiconductor device 1B is one of the IC chips 10 and 20 which has a large IC
A chip 10 is die-bonded on the interposer 2 with the surface thereof facing upward via the insulating paste 3. On the IC chip 10, a small-sized IC chip 20 has its surface facing upward and the insulating paste 3, and the respective bumps 11,
Reference numeral 21 denotes a structure which is connected to the circuit patterns formed at different positions of the interposer 2 using the wires 4, and is entirely sealed with the electrically insulating resin 5.
【０００６】図８に示した第２形態の半導体装置１Ｃ
は、サイズの大きいＩＣチップ１０の表面を下向きにし
て、そのバンプ１１をインターポーザ２の回路パターン
に超音波振動による接合方法などを用いて直接接続し、
その裏面上に絶縁ペースト３を用いてサイズの小さいＩ
Ｃチップ２０を、その表面を上向きにしてダイボンド
し、そのバンプ２１をそれぞれインターポーザ２の回路
パターンにワイヤ４で接続し、そして全体を絶縁樹脂５
で封止しれた構造のものである。The semiconductor device 1C of the second embodiment shown in FIG.
Is connected directly to the circuit pattern of the interposer 2 with the surface of the large-sized IC chip 10 facing down using a bonding method by ultrasonic vibration or the like,
Using the insulating paste 3 on the back surface, a small I
The C chip 20 is die-bonded with its surface facing upward, the bumps 21 are respectively connected to the circuit patterns of the interposer 2 by wires 4, and the whole is
It is a structure sealed with.
【０００７】そして、図９に示した半導体装置１Ｄは、
2枚のインターポーザ２Ａ、２Ｂの回路パターン２ａ、
２ｂに複数の半田ボール６が所定の配列で形成され、そ
の同一面内に異方性導電材７を用いて、そのバンプ１１
がダイボンドされて、それぞれのＩＣチップ１０、２０
が実装されているインターポーザ２Ａ、２Ｂを、先ず、
サイズの小さいＩＣチップ２０が実装されているインタ
ーポーザ２Ｂを、回路パターンが内外面に形成されてい
るマザーボード８の内面に直接フリップチップボンド
し、次いでＩＣチップ２０のインターポーザ２Ｂの外面
の回路パターンに、ＩＣチップ１０を直接フリップチッ
プボンドした構造のものである。The semiconductor device 1D shown in FIG.
The circuit patterns 2a of the two interposers 2A and 2B,
2b, a plurality of solder balls 6 are formed in a predetermined arrangement, and the bumps 11 are formed in the same plane by using an anisotropic conductive material 7.
Are die-bonded, and the respective IC chips 10, 20
First, the interposers 2A and 2B in which
The interposer 2B on which the small-sized IC chip 20 is mounted is directly flip-chip bonded to the inner surface of the motherboard 8 on which the circuit pattern is formed on the inner and outer surfaces. It has a structure in which the IC chip 10 is directly flip-chip bonded.
【０００８】[0008]
【発明が解決しようとする課題】前記の第１形態の半導
体装置１Ｂ及び第２形態の半導体装置は、ＩＣチップ２
０のバンプ２１に接続されているワイヤ４が山なりにな
って存在するために、構造上、全体として積層の高さが
高くなり、また、ワイヤ４を広げてインターポーザ２に
接合しているため、広い実装面積（或いは占有面積）が
必要となる。そしてＩＣチップ１０、２０のそれぞれの
電極数が多くなると、ワイヤボンドによる接合では対応
できない。The semiconductor device 1B according to the first embodiment and the semiconductor device according to the second embodiment include an IC chip 2
Since the wires 4 connected to the 0 bumps 21 are present in the form of a mountain, the stack height is increased as a whole, and the wires 4 are spread and joined to the interposer 2. Therefore, a large mounting area (or occupied area) is required. If the number of electrodes of each of the IC chips 10 and 20 increases, bonding by wire bonding cannot be used.
【０００９】また、第３形態の半導体装置１Ｄは、イン
ターポーザ２Ａ、２Ｂ及び半田ボール６を使用している
ため、やはり全体の積層の高さを低くすることができな
いばかりか、コストが嵩む。Further, since the semiconductor device 1D of the third embodiment uses the interposers 2A and 2B and the solder balls 6, the overall height of the laminated structure cannot be reduced, and the cost increases.
【００１０】従って、本発明は前記のような課題を解決
しようとするものであって、厚みを薄くできる構造の複
合型電子部品及びその製造方法を得ることを目的とする
ものである。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned problems, and an object of the present invention is to provide a composite electronic component having a structure that can be reduced in thickness and a method of manufacturing the same.
【００１１】[0011]
【課題を解決するための手段】それ故、本発明の電子部
品では、所定の間隔を開けて互いに対向した平行な線上
に、それぞれ複数の電極が所定の隣接間隔で電極列とな
って形成され、前記複数の電極列上の各電極が、前記電
極列の長さより長い角材の端子板の複数の配線電極にそ
れぞれ接続されていて、前記複数の配線電極が前記端子
板の上下面に連通して形成されていることを特徴とす
る。Therefore, in the electronic component of the present invention, a plurality of electrodes are formed in a row of electrodes at predetermined adjacent intervals on parallel lines facing each other at predetermined intervals. The electrodes on the plurality of electrode rows are respectively connected to a plurality of wiring electrodes of a square terminal plate longer than the length of the electrode rows, and the plurality of wiring electrodes communicate with upper and lower surfaces of the terminal plate. It is characterized by being formed.
【００１２】そして、本発明の電子部品のアセンブリで
は、所定の間隔を開けて互いに対向した平行な線上に、
それぞれ複数の電極が所定の隣接間隔で電極列となって
形成され、前記複数の電極列上の各電極が、前記電極列
の長さより長い角材の端子板の複数の配線電極にそれぞ
れ接続されていて、前記複数の配線電極が前記端子板の
上下面に連通して形成されている第１の電子部品と、前
記電極列の所定の間隔幅内の空間に収容できる大きさの
第２の電子部品とが回路基板上に組み合わされた電子部
品のアセンブリにおいて、前記第１の電子部品の前記端
子板下面の各配線電極が前記回路基板に形成されている
それぞれの配線電極に接続されており、そして前記第１
の電子部品の下面と前記両端子板の内面とで区画された
空間内に前記第２の電子部品が収容され、その各電極が
前記回路基板の配線電極に接続されていることを特徴と
する。In the assembly of the electronic component of the present invention, on the parallel lines facing each other at a predetermined interval,
Each of the plurality of electrodes is formed as an electrode row at a predetermined adjacent interval, and each of the electrodes on the plurality of electrode rows is connected to each of a plurality of wiring electrodes of a square terminal plate longer than the length of the electrode row. A first electronic component in which the plurality of wiring electrodes communicate with upper and lower surfaces of the terminal plate; and a second electronic component having a size that can be accommodated in a space within a predetermined interval width of the electrode row. In the assembly of an electronic component in which components are combined on a circuit board, each wiring electrode on the lower surface of the terminal board of the first electronic component is connected to each wiring electrode formed on the circuit board, And the first
Wherein the second electronic component is accommodated in a space defined by the lower surface of the electronic component and the inner surfaces of the two terminal boards, and each electrode thereof is connected to a wiring electrode of the circuit board. .
【００１３】また、本発明の電子部品のアセンブル方法
では、所定の間隔を開けて互いに対向した平行な線上
に、それぞれ複数の電極が所定の隣接間隔で電極列とな
って形成され、前記複数の電極列上の各電極が、前記電
極列の長さより長い角材の端子板の複数の配線電極にそ
れぞれ接続されていて、前記複数の配線電極が前記端子
板の上下面に連通して形成されている第１の電子部品
と、前記電極列の所定の間隔幅内の空間に収容できる大
きさの第２の電子部品とを回路基板上に実装するに当た
り、先ず、前記第２の電子部品を前記回路基板の所定の
位置に実装し、次に、実装された前記第２の電子部品を
跨いで前記第１の電子部品を前記回路基板に実装するこ
とを特徴とする。In the method of assembling an electronic component according to the present invention, a plurality of electrodes are formed as electrode rows at predetermined adjacent intervals on parallel lines facing each other at a predetermined interval. Each electrode on the electrode row is connected to a plurality of wiring electrodes of a square terminal plate longer than the length of the electrode row, and the plurality of wiring electrodes are formed to communicate with upper and lower surfaces of the terminal plate. In mounting a first electronic component and a second electronic component having a size that can be accommodated in a space within a predetermined interval width of the electrode row on a circuit board, first, the second electronic component is mounted on the circuit board. It is characterized in that it is mounted on a predetermined position on a circuit board, and then the first electronic component is mounted on the circuit board across the mounted second electronic component.
【００１４】更に、本発明の電子部品の製造方法では、
所定の間隔を開けて互いに対向した平行な線上に、それ
ぞれ複数の電極が所定の隣接間隔で電極列となって形成
されている電子部品と、前記所定の間隔とほぼ同等の間
隔を開けて互いに対向した平行な枠辺の上下面に連通し
て、前記電子部品のそれぞれの電極位置に対応して配線
電極がそれぞれ形成されている枠型基板を用意する工程
と、該枠型基板の前記両枠辺の配線電極に前記電子部品
のそれぞれ電極を接続し、固定する工程と、前記枠型基
板の前記両枠辺を除く他の一対の枠辺を切断する工程と
を含む。Further, according to the method for manufacturing an electronic component of the present invention,
An electronic component in which a plurality of electrodes are formed in an electrode row at a predetermined adjacent interval on parallel lines facing each other at a predetermined interval, and an electronic component formed at an interval substantially equal to the predetermined interval. A step of preparing a frame type substrate in which wiring electrodes are respectively formed corresponding to the respective electrode positions of the electronic component in communication with the upper and lower surfaces of the opposed parallel frame sides; The method includes a step of connecting and fixing the respective electrodes of the electronic component to the wiring electrodes on the frame side, and a step of cutting a pair of frame sides other than the both frame sides of the frame type substrate.
【００１５】それ故、本発明によれば、電子部品及びそ
のアセンブリ全体を小型化でき、しかもその全体の厚み
を薄くでき、また、特に回路基板上に直接実装でき、よ
り一層薄くアセンブルすることができる。また、製造方
法も簡単な工程のみで行えるので、製造コストも安価で
ある。Therefore, according to the present invention, the entire electronic component and its assembly can be reduced in size, the overall thickness can be reduced, and particularly, the electronic component and the assembly can be directly mounted on a circuit board, and can be assembled more thinly. it can. Also, since the manufacturing method can be performed only by simple steps, the manufacturing cost is low.
【００１６】[0016]
【発明の実施の形態】以下、図を用いて、本発明の一実
施形態の電子部品、そのアセンブリ及びその製造方法を
説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an electronic component, an assembly thereof, and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings.
【００１７】図１は本発明の電子部品に用いる枠型基板
の一単位部分を示していて、同図Ａはその平面図、同図
Ｂは同図ＡのＡ―Ａ線上における断面側面図、図２は図
１に示した枠型基板の配線電極に導電性ペーストを塗布
した状態を示した断面側面図、図３は図２に示した枠型
基板上にＩＣチップを実装する状態を示した断面側面
図、図４は図３に示した状態からＩＣチップを実装し終
えた状態を示していて、同図Ａはその平面図、同図Ｂは
同図ＡのＡ―Ａ線上における断面側面図、図５は本発明
の一実施形態の電子部品を示していて、同図Ａはその平
面図、同図Ｂは同図ＡのＡ―Ａ線上における断面側面
図、そして図６は大小２個の電子部品を回路基板上にア
センブルする工程を示していて、同図Ａはその小型電子
部品を回路基板に実装しようとする状態の断面側面図、
同図Ｂはその小型電子部品が回路基板に実装された状態
の断面側面図、同図Ｃは同図Ｂに示した状態の小型電子
部品を跨いで本発明の電子部品を回路基板に実装しよう
とする状態の断面側面図、同図Ｄはその電子部品が回路
基板に実装された状態の断面側面図である。FIG. 1 shows one unit portion of a frame type substrate used for an electronic component of the present invention, FIG. 1A is a plan view thereof, FIG. 1B is a cross-sectional side view taken along line AA of FIG. FIG. 2 is a sectional side view showing a state where a conductive paste is applied to the wiring electrodes of the frame type substrate shown in FIG. 1, and FIG. 3 shows a state where an IC chip is mounted on the frame type substrate shown in FIG. FIG. 4 shows a state in which the IC chip has been mounted from the state shown in FIG. 3, FIG. 4A shows a plan view thereof, and FIG. 4B shows a cross section taken along line AA of FIG. FIG. 5 shows an electronic component according to an embodiment of the present invention, FIG. 5A shows a plan view thereof, FIG. 5B shows a cross-sectional side view taken along line AA of FIG. 5A, and FIG. Fig. A shows the process of assembling two electronic components on a circuit board, and Fig. A shows the mounting of the small electronic components on the circuit board. Sectional side view of a state intoxicated that,
FIG. B is a cross-sectional side view of a state in which the small electronic component is mounted on a circuit board, and FIG. C is a plan view of mounting the electronic component of the present invention on the circuit board straddling the small electronic component in the state shown in FIG. D is a cross-sectional side view in a state where the electronic component is mounted on a circuit board.
【００１８】先ず、図１を用いて、本発明の電子部品の
一構成要素となる枠型基板の構造を説明する。First, the structure of a frame type substrate which is one component of the electronic component of the present invention will be described with reference to FIG.
【００１９】図１において、符号３０は全体として一単
位部分の枠型基板を指していて、実際には大判の印刷配
線基板にこの枠型基板３０が複数単位形成されているも
のであることを予め断っておく。枠型基板３０は、ＩＣ
チップ１０にアセンブルしようとする小型の電子部品で
あるＩＣチップ２０の厚みより厚い厚さの板であって、
その中央部に所定の面積の矩形状開口３１が開けられて
おり、その開口３１の対向した短辺の周辺部の表面に、
実装しようとするＩＣチップ１０のそれぞれ複数の電極
が接続できる複数の配線電極３２が所定の隣接間隔で一
列に形成されれている。そしてまた、両側のそれぞれの
配線電極３２に対応して、それぞれの外側に接続配線３
３でそれぞれ接続されている接続端子３４の列と、それ
ぞれの接続端子３４の中心を貫通する貫通孔３５が開け
られている。また、枠型基板３０の前記周辺部の裏面に
も、前記貫通孔３５が中心に開口する配線電極３６（図
１Ｃ）が形成されている。これらの配線電極３６はそれ
ぞれの貫通孔３５を介して接続端子３４にそれぞれ電気
的に接続されており、引いてはそれぞれの配線電極３２
に電気的に接続されているものである。In FIG. 1, reference numeral 30 indicates a frame-shaped substrate of one unit as a whole. In practice, a plurality of frame-shaped substrates 30 are formed on a large-sized printed wiring board. Refuse in advance. The frame type substrate 30 is an IC
A plate having a thickness greater than the thickness of the IC chip 20, which is a small electronic component to be assembled into the chip 10,
A rectangular opening 31 having a predetermined area is opened at the center thereof, and a surface of a peripheral portion of a short side opposed to the opening 31 is
A plurality of wiring electrodes 32 to which a plurality of electrodes of the IC chip 10 to be mounted can be connected are formed in a row at predetermined adjacent intervals. Further, corresponding to the respective wiring electrodes 32 on both sides, the connection wiring 3 is provided on the outside of each.
3, a row of connection terminals 34 connected to each other and a through-hole 35 penetrating the center of each connection terminal 34 is formed. A wiring electrode 36 (FIG. 1C) having the through hole 35 opened at the center is also formed on the back surface of the peripheral portion of the frame type substrate 30. These wiring electrodes 36 are electrically connected to the connection terminals 34 via the respective through-holes 35, and thus the respective wiring electrodes 32
Are electrically connected to the
【００２０】なお、図１における複数の配線電極３２は
開口３１側に、接続端子３４はそれらの外方に形成され
ているが、後記するマザー基板５０に形成されている電
子回路パターンとの関係で、これらは逆の位置関係で、
即ち、複数の接続端子３４は開口３１側に、配線電極３
２はそれらの外方に形成してもよいことを付言してお
く。Although the plurality of wiring electrodes 32 in FIG. 1 are formed on the opening 31 side and the connection terminals 34 are formed on the outside thereof, the relationship with an electronic circuit pattern formed on a mother substrate 50 described later will be described. And these are the opposite positions,
That is, the plurality of connection terminals 34 are provided on the opening 31 side,
Note that 2 may be formed outside of them.
【００２１】これらの開口３１、配線電極３２、接続配
線３３、接続端子３４、貫通孔３５、及び配線電極３６
は大判の印刷配線基板に、単位毎に、例えば、マトリッ
クス状に配列されて予め形成されているものである。以
下の説明では、その一単位の枠型基板３０を採り上げて
説明する。The opening 31, the wiring electrode 32, the connection wiring 33, the connection terminal 34, the through hole 35, and the wiring electrode 36
Are formed in advance on a large-sized printed wiring board, for example, arranged in a matrix in units. In the following description, one unit of the frame type substrate 30 will be described.
【００２２】次に、この枠型基板３０を用いて本発明の
電子部品の製造方法を説明する。Next, a method of manufacturing an electronic component according to the present invention using the frame type substrate 30 will be described.
【００２３】先ず、図２に示したように、枠型基板３０
の各配線電極３２上に半田ペースト、銀ペーストなどの
ような導電性ペースト４０を塗布する。First, as shown in FIG.
A conductive paste 40 such as a solder paste or a silver paste is applied on each of the wiring electrodes 32.
【００２４】次に、大型のＩＣチップ１０を枠型基板３
０に実装する。ＩＣチップ１０はこの実施例では、デュ
アルインライ（Ｄｕａｌ ｉｎ−ｌｉｎｅ）で複数の電
極が所定の隣接間隔で形成されているものとし、それぞ
れの電極にバンプ１１が形成されている。そのＩＣチッ
プ１０を、図３に示したように、枠型基板３０のそれぞ
れの配線電極３２に塗布された導電性ペースト４０に対
応してＩＣチップ１０のバンプ１１を合わせて載置し、
その導電性ペースト４０を加熱、溶融した後、冷却して
ＩＣチップ１０を枠型基板３０上に接続、固定する。そ
の固定した構造を図４に示した。Next, the large-sized IC chip 10 is
0 is implemented. In this embodiment, the IC chip 10 has a plurality of electrodes formed at predetermined adjacent intervals in a dual in-line manner, and bumps 11 are formed on each of the electrodes. As shown in FIG. 3, the IC chip 10 is mounted with the bumps 11 of the IC chip 10 corresponding to the conductive pastes 40 applied to the respective wiring electrodes 32 of the frame type substrate 30,
After the conductive paste 40 is heated and melted, it is cooled to connect and fix the IC chip 10 on the frame substrate 30. The fixed structure is shown in FIG.
【００２５】次に、図４におけるＢ―Ｂ線、Ｃ―Ｃ線、
Ｄ―Ｄ線、及びＥ―Ｅ線に沿ってダイシングして、長辺
に存在する枠と短辺に存在する余分な枠の部分を除去す
る。このようにして本発明の一実施形態の電子部品１０
Ａが完成する。この電子部品１０ＡはＩＣチップ１０の
電極列部分に残っている枠型基板３０の両短辺部分の一
対の枠が前記電極列の長さより長い角材の端子板３７と
して組み込まれた構造となっている。その端子板３７の
高さは小型の電子部品であるＩＣチップ２０の厚みより
高い高さである。Next, line BB, line CC in FIG.
Dicing is performed along the DD line and the EE line to remove a portion of the frame existing on the long side and an extra frame existing on the short side. Thus, the electronic component 10 according to one embodiment of the present invention
A is completed. The electronic component 10A has a structure in which a pair of frames on both short sides of the frame substrate 30 remaining in the electrode array portion of the IC chip 10 are incorporated as a rectangular terminal plate 37 longer than the length of the electrode array. I have. The height of the terminal plate 37 is higher than the thickness of the IC chip 20 which is a small electronic component.
【００２６】次に、図６を用いて、比較的大型のＩＣチ
ップ１０ＡとこのＩＣチップ１０Ａの端子板３７間に入
る比較的小型のＩＣチップ２０とをアセンブルする方法
を説明する。Next, a method of assembling a relatively large IC chip 10A and a relatively small IC chip 20 inserted between the terminal plates 37 of the IC chip 10A will be described with reference to FIG.
【００２７】先ず、マザー基板５０とＩＣチップ２０と
を用意する（図６Ａ）。このマザー基板５０の表面には
所定のパターンで複数の配線電極５１を含む配線パター
ンが予め形成されている。複数の配線電極５１の内の内
側の電極列の間隔はＩＣチップ２０のバンプ２１の間隔
幅と一致し、各電極列の隣接配線電極５１の間隔もＩＣ
チップ２０のバンプ２１のそれと一致するものである。
そしてそれぞれの配線電極５１の上に導電性ペースト５
２が塗布されている。First, a mother board 50 and an IC chip 20 are prepared (FIG. 6A). On the surface of the mother substrate 50, a wiring pattern including a plurality of wiring electrodes 51 in a predetermined pattern is formed in advance. The spacing between the inner electrode rows of the plurality of wiring electrodes 51 matches the spacing between the bumps 21 of the IC chip 20, and the spacing between adjacent wiring electrodes 51 in each electrode row is also IC
This is the same as that of the bump 21 of the chip 20.
Then, a conductive paste 5 is formed on each wiring electrode 51.
2 is applied.
【００２８】次に、その複数の配線電極５１の内の内側
の電極列にＩＣチップ２０のバンプ２１が載るように装
着する（図６Ｂ）。Next, mounting is performed so that the bumps 21 of the IC chip 20 are mounted on the inner electrode rows of the plurality of wiring electrodes 51 (FIG. 6B).
【００２９】次に、マザー基板５０上に既に装着されて
いるＩＣチップ２０を跨ぐようにして前記のＩＣチップ
１０Ａをマザー基板５０上の外側に存在する配線電極５
１に装着する（図６Ｃ）。Next, the IC chip 10A is connected to the wiring electrodes 5 existing outside the mother substrate 50 so as to straddle the IC chip 20 already mounted on the mother substrate 50.
1 (FIG. 6C).
【００３０】そして、ＩＣチップ２０とＩＣチップ１０
Ａとが載置された状態で、例えば、リフロー炉を用いて
導電性ペースト５２を加熱、溶融し、その後冷却してＩ
Ｃチップ２０、１０Ａを配線電極５１上に接続、固定す
る。Then, the IC chip 20 and the IC chip 10
In the state where A is placed, the conductive paste 52 is heated and melted using, for example, a reflow furnace, and then cooled and cooled.
The C chips 20, 10A are connected and fixed on the wiring electrodes 51.
【００３１】かくして、大型のＩＣチップ１０Ａが上
に、小型のＩＣチップ２０が下にアセンブルされてマザ
ー基板５０上に実装された本発明の電子部品のアセンブ
リ１Ａが完成する。Thus, the electronic component assembly 1A of the present invention in which the large IC chip 10A is assembled on the upper side and the small IC chip 20 is assembled on the lower side and mounted on the mother board 50 is completed.
【００３２】この電子部品のアセンブリ１Ａは大小のＩ
Ｃチップ１０ＡとＩＣチップ２０とが直接マザー基板５
０に実装されて組み立てられており、そして従来技術の
ようにインターポーザ２、電気絶縁樹脂５、異方性導電
材７を使用しないでアセンブルされているので全体の高
さ（厚さ）を薄くできる。また、占有（実装）面積もほ
ぼ大型のＩＣチップ１０Ａの面積で済む。従って、この
アセンブリ１Ａは収容スペースの少ない、かつ超薄型の
電子機器に搭載する電子部品として好適である。The electronic component assembly 1A is large or small I
The C chip 10A and the IC chip 20 are directly connected to the mother substrate 5
0, and is assembled without using the interposer 2, the electrically insulating resin 5, and the anisotropic conductive material 7 as in the prior art, so that the overall height (thickness) can be reduced. . In addition, the area occupied (mounted) can be substantially the same as that of the large-sized IC chip 10A. Therefore, the assembly 1A is suitable as an electronic component mounted on an ultra-thin electronic device with a small accommodation space.
【００３３】なお、図６に示したＩＣチップ２０の向き
は、この例に限らず、９０°回した状態でアセンブルし
てもよいことを付言しておく。It should be noted that the orientation of the IC chip 20 shown in FIG. 6 is not limited to this example, and that the IC chip 20 may be assembled while being rotated by 90 °.
【００３４】また、図３に示した実施形態では、ＩＣチ
ップ１０の枠型基板３０への接続、固定、図６に示した
ＩＣチップ２０のマザー基板５０への接続、固定及び本
発明の電子部品１０Ａのマザー基板５０への接続、固定
は、それぞれ導電性ペースト４０、５２を用いて行って
いるが、ＩＣチップ１０のバンプ１１及びＩＣチップ２
０のバンプ２１を金バンプで形成し、また、電子部品１
０Ａの配線電極３６の表面に金メッキを施し、一方の枠
型基板３０の配線電極３２及びマザー基板５０の配線電
極５１のそれぞれの表面に金メッキを施し、超音波接合
法を用いて、金バンプ及び配線電極を接続、固定する方
法を採ってもよいことを付言しておく。そして、電子部
品はＩＣチップに限られるものではなく、また、ＩＣチ
ップ１０、２０は複数の電極がチップの２辺に沿って形
成されているものに限定されるものではなく、４辺に沿
って形成されたものであってもよいことも断っておく。In the embodiment shown in FIG. 3, the connection and fixation of the IC chip 10 to the frame substrate 30, the connection and fixation of the IC chip 20 to the mother board 50 shown in FIG. The connection and fixing of the component 10A to the mother board 50 are performed using the conductive pastes 40 and 52, respectively.
0 bumps 21 are formed of gold bumps, and the electronic component 1
The surface of the wiring electrode 36 of 0A is plated with gold, and the surfaces of the wiring electrode 32 of one frame type substrate 30 and the wiring electrode 51 of the mother substrate 50 are plated with gold. Note that a method of connecting and fixing the wiring electrodes may be adopted. The electronic components are not limited to IC chips, and the IC chips 10 and 20 are not limited to those in which a plurality of electrodes are formed along two sides of the chip. It should also be refused that they may be formed by using the above method.
【００３５】[0035]
【発明の効果】以上説明したように、本発明によれば、
従来技術の電子部品に見受けられるワイヤやインターポ
ーザは存在しないので、これらによって生じていた嵩高
さやコスト高は無く、大きさの異なる電子部品であれ
ば、枠型基板を用いることにより機器用回路基板上に、
いわゆるフリップチップ実装のように直接表面実装で
き、従って、全体の電子部品の厚みを薄く、そして小型
化することができる。As described above, according to the present invention,
Since there are no wires or interposers found in conventional electronic components, there is no bulkiness or high cost caused by these, and electronic components having different sizes can be mounted on a circuit board for equipment by using a frame type substrate. To
It can be directly surface-mounted as in the so-called flip-chip mounting, so that the thickness of the entire electronic component can be reduced and the size can be reduced.
【００３６】しかも、枠型基板は通常の大判の回路基板
から形成でき、特殊な材料、部品を用いることなく、そ
して特殊な設備を用いることなく製造できるので、本発
明の電子部品のアセンブリは比較的安価に抑えることが
できるなど、数々の優れた効果が得られる。Further, since the frame type substrate can be formed from a normal large-sized circuit board and can be manufactured without using special materials and parts and without using special equipment, the assembly of the electronic parts of the present invention can be compared. Numerous excellent effects can be obtained, such as being able to keep costs low.
【図１】 本発明の電子部品に用いる枠型基板の一単位
部分を示していて、同図Ａはその平面図、同図Ｂは同図
ＡのＡ―Ａ線上における断面側面図である。FIG. 1 shows one unit portion of a frame type substrate used for an electronic component of the present invention. FIG. 1A is a plan view thereof, and FIG. 1B is a cross-sectional side view taken along line AA of FIG.
【図２】 図１に示した枠型基板の配線電極に導電性ペ
ーストを塗布した状態を示した断面側面図である。FIG. 2 is a cross-sectional side view showing a state where a conductive paste is applied to the wiring electrodes of the frame-type substrate shown in FIG.
【図３】 図２に示した枠型基板上にＩＣチップを実装
する状態を示した断面側面図である。FIG. 3 is a cross-sectional side view showing a state where an IC chip is mounted on the frame type substrate shown in FIG. 2;
【図４】 図３に示した状態からＩＣチップを実装し終
えた状態を示していて、同図Ａはその平面図、同図Ｂは
同図ＡのＡ―Ａ線上における断面側面図である。4 shows a state in which the IC chip has been mounted from the state shown in FIG. 3; FIG. 4A is a plan view thereof; FIG. 4B is a cross-sectional side view taken along line AA of FIG. .
【図５】 本発明の一実施形態の電子部品を示してい
て、同図Ａはその平面図、同図Ｂは同図ＡのＡ―Ａ線上
における断面側面図である。5A and 5B show an electronic component according to an embodiment of the present invention, wherein FIG. A is a plan view thereof, and FIG. 5B is a cross-sectional side view taken along line AA of FIG.
【図６】 大小２個の電子部品を回路基板上にアセンブ
ルする工程を示していて、同図Ａはその小型電子部品を
回路基板に実装しようとする状態の断面側面図、同図Ｂ
はその小型電子部品が回路基板に実装された状態の断面
側面図、同図Ｃは同図Ｂに示した状態の小型電子部品を
跨いで本発明の電子部品を回路基板に実装しようとする
状態の断面側面図、同図Ｄはその電子部品が回路基板に
実装された状態の断面側面図である。6A and 6B show a process of assembling two large and small electronic components on a circuit board, and FIG. 6A is a cross-sectional side view showing a state where the small electronic components are to be mounted on the circuit board;
Is a cross-sectional side view of the state in which the small electronic component is mounted on the circuit board, and FIG. C is a state in which the electronic component of the present invention is to be mounted on the circuit board across the small electronic component in the state shown in FIG. D is a sectional side view of the electronic component mounted on a circuit board.
【図７】 従来技術の第１形態の半導体装置の積層構造
を示す断面側面図である。FIG. 7 is a cross-sectional side view illustrating a stacked structure of a semiconductor device according to a first embodiment of the related art.
【図８】 従来技術の第２形態の半導体装置の積層構造
を示す断面側面図である。FIG. 8 is a cross-sectional side view illustrating a stacked structure of a semiconductor device according to a second embodiment of the related art.
【図９】 従来技術の第３形態の半導体装置の積層構造
を示す断面側面図である。FIG. 9 is a sectional side view showing a laminated structure of a semiconductor device according to a third embodiment of the related art.
１Ａ…本発明の一実施形態の１０，２０…ＩＣチップ、
１０Ａ…本発明の一実施形態の電子部品、３０…枠型基
板、３１…開口、３２…回路基板、３３…接続配線、３
４…接続端子、３５…貫通孔、３６…配線電極、４０…
導電性ペースト1A: 10, 20, an IC chip according to an embodiment of the present invention;
10A: Electronic component of one embodiment of the present invention, 30: Frame type substrate, 31: Opening, 32: Circuit board, 33: Connection wiring, 3
4: Connection terminal, 35: Through hole, 36: Wiring electrode, 40:
Conductive paste
Claims (8)
な線上に、それぞれ複数の電極が所定の隣接間隔で電極
列となって形成され、前記複数の電極列上の各電極が、
前記電極列の長さより長い角材の端子板の複数の配線電
極にそれぞれ接続されていて、前記複数の配線電極が前
記端子板の上下面に連通して形成されていることを特徴
とする電子部品。1. A plurality of electrodes are formed in an electrode row at a predetermined adjacent interval on parallel lines facing each other at a predetermined interval, and each electrode on the plurality of electrode rows is
An electronic component, wherein each of the plurality of wiring electrodes is connected to a plurality of wiring electrodes of a rectangular terminal plate longer than the length of the electrode row, and the plurality of wiring electrodes are formed to communicate with upper and lower surfaces of the terminal plate. .
あることを特徴とする請求項１に記載の電子部品。2. The electronic component according to claim 1, wherein the electronic component is a semiconductor integrated circuit chip.
な線上に、それぞれ複数の電極が所定の隣接間隔で電極
列となって形成され、前記複数の電極列上の各電極が、
前記電極列の長さより長い角材の端子板の複数の配線電
極にそれぞれ接続されていて、前記複数の配線電極が前
記端子板の上下面に連通して形成されている第１の電子
部品と、前記電極列の所定の間隔幅内の空間に収容でき
る大きさの第２の電子部品とが回路基板上に組み合わさ
れた電子部品のアセンブリにおいて、 前記第１の電子部品の前記端子板下面の各配線電極が前
記回路基板に形成されているそれぞれの配線電極に接続
されており、 そして前記第１の電子部品の下面と前記両端子板の内面
とで区画された空間内に前記第２の電子部品が収容さ
れ、その各電極が前記回路基板の配線電極に接続されて
いることを特徴とする電子部品のアセンブリ。3. A plurality of electrodes are formed in an electrode row at a predetermined adjacent interval on parallel lines facing each other at a predetermined interval, and each electrode on the plurality of electrode rows is
A first electronic component connected to a plurality of wiring electrodes of a square terminal plate longer than the length of the electrode row, wherein the plurality of wiring electrodes communicate with upper and lower surfaces of the terminal plate; In an assembly of an electronic component in which a second electronic component having a size that can be accommodated in a space within a predetermined interval width of the electrode row is combined on a circuit board, each of the lower surfaces of the terminal boards of the first electronic component Wiring electrodes are connected to respective wiring electrodes formed on the circuit board, and the second electronic component is disposed in a space defined by a lower surface of the first electronic component and inner surfaces of the terminal boards. An assembly of an electronic component, wherein the component is accommodated, and each electrode thereof is connected to a wiring electrode of the circuit board.
ップであることを特徴とする請求項３に記載の電子部品
のアセンブリ。4. The electronic component assembly according to claim 3, wherein said first electronic component is a semiconductor integrated circuit chip.
な線上に、それぞれ複数の電極が所定の隣接間隔で電極
列となって形成され、 前記複数の電極列上の各電極が、前記電極列の長さより
長い角材の端子板の複数の配線電極にそれぞれ接続され
ていて、前記複数の配線電極が前記端子板の上下面に連
通して形成されている第１の電子部品と、前記電極列の
所定の間隔幅内の空間に収容できる大きさの第２の電子
部品とを回路基板上に実装するに当たり、先ず、前記第
２の電子部品を前記回路基板の所定の位置に実装し、次
に、実装された前記第２の電子部品を跨いで前記第１の
電子部品を前記回路基板に実装することを特徴とする電
子部品のアセンブル方法。5. A plurality of electrodes are formed as electrode rows at predetermined adjacent intervals on parallel lines facing each other at a predetermined interval, and each electrode on the plurality of electrode rows is the electrode A first electronic component connected to a plurality of wiring electrodes of a square terminal plate longer than the length of the row, wherein the plurality of wiring electrodes communicate with upper and lower surfaces of the terminal plate; In mounting a second electronic component having a size that can be accommodated in a space within a predetermined interval width of the row on a circuit board, first, mounting the second electronic component at a predetermined position on the circuit board, Next, a method of assembling an electronic component, wherein the first electronic component is mounted on the circuit board across the mounted second electronic component.
集積回路チップであることを特徴とする請求項５に記載
の電子部品のアセンブリ。6. The electronic component assembly according to claim 5, wherein at least the first electronic component is a semiconductor integrated circuit chip.
な線上に、それぞれ複数の電極が所定の隣接間隔で電極
列となって形成されている電子部品と、前記所定の間隔
とほぼ同等の間隔を開けて互いに対向した平行な枠辺の
上下面に連通して、前記電子部品のそれぞれの電極位置
に対応して配線電極がそれぞれ形成されている枠型基板
を用意する工程と、 該枠型基板の前記両枠辺の配線電極に前記電子部品のそ
れぞれ電極を接続し、固定する工程と、 前記枠型基板の前記両枠辺を除く他の一対の枠辺を切断
する工程とを含む電子部品の製造方法。7. An electronic component in which a plurality of electrodes are formed in an electrode row at a predetermined adjacent interval on parallel lines facing each other at a predetermined interval, and an electronic component substantially equal to the predetermined interval. A step of preparing a frame type substrate in which wiring electrodes are respectively formed corresponding to the respective electrode positions of the electronic component by communicating with upper and lower surfaces of parallel frame sides facing each other at an interval; Connecting the electrodes of the electronic component to the wiring electrodes on both sides of the mold substrate and fixing them; and cutting a pair of other sides of the frame substrate other than the two sides of the frame substrate. Manufacturing method of electronic components.
あることを特徴とする請求項５に記載の電子部品の製造
方法。8. The method according to claim 5, wherein the electronic component is a semiconductor integrated circuit chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001064038A JP2002270760A (en) | 2001-03-07 | 2001-03-07 | Electronic component, assembly thereof and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001064038A JP2002270760A (en) | 2001-03-07 | 2001-03-07 | Electronic component, assembly thereof and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002270760A true JP2002270760A (en) | 2002-09-20 |
Family
ID=18922928
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001064038A Pending JP2002270760A (en) | 2001-03-07 | 2001-03-07 | Electronic component, assembly thereof and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002270760A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006310649A (en) * | 2005-04-28 | 2006-11-09 | Sharp Corp | Semiconductor device package and its manufacturing method |
| JP2007081108A (en) * | 2005-09-14 | 2007-03-29 | Yaskawa Electric Corp | Laminated structure of semiconductor chip and semiconductor device using same |
| US7999376B2 (en) | 2005-01-25 | 2011-08-16 | Panasonic Corporation | Semiconductor device and its manufacturing method |
-
2001
- 2001-03-07 JP JP2001064038A patent/JP2002270760A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7999376B2 (en) | 2005-01-25 | 2011-08-16 | Panasonic Corporation | Semiconductor device and its manufacturing method |
| JP2006310649A (en) * | 2005-04-28 | 2006-11-09 | Sharp Corp | Semiconductor device package and its manufacturing method |
| JP2007081108A (en) * | 2005-09-14 | 2007-03-29 | Yaskawa Electric Corp | Laminated structure of semiconductor chip and semiconductor device using same |
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