JP2002270719A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing methodInfo
- Publication number
- JP2002270719A JP2002270719A JP2001064039A JP2001064039A JP2002270719A JP 2002270719 A JP2002270719 A JP 2002270719A JP 2001064039 A JP2001064039 A JP 2001064039A JP 2001064039 A JP2001064039 A JP 2001064039A JP 2002270719 A JP2002270719 A JP 2002270719A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor wafer
- semiconductor device
- bumps
- resin layer
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Dicing (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、厚さの薄い半導体
装置及びそのような半導体装置の製造方法に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin semiconductor device and a method for manufacturing such a semiconductor device.
【０００２】[0002]
【従来の技術】先ず、図６を参照しながら、従来技術の
半導体装置及びその製造方法を説明する。なお、本明細
書に記す半導体装置とは半導体ウェーハの表面に電子回
路が集積形成されたいわゆる半導体集積回路装置（Ｉ
Ｃ）であって、本発明においては電子回路の集積密度を
問わないが、高密度に積層されたＩＣほど効果的であ
る。以下、本明細書においては、このようなＩＣを半導
体装置と記す。2. Description of the Related Art First, a conventional semiconductor device and a method of manufacturing the same will be described with reference to FIG. Note that a semiconductor device described in this specification is a so-called semiconductor integrated circuit device (I) in which electronic circuits are integrated and formed on the surface of a semiconductor wafer.
C) In the present invention, although the integration density of electronic circuits is not limited, ICs stacked with higher density are more effective. Hereinafter, such an IC is referred to as a semiconductor device in this specification.
【０００３】図６は従来技術の半導体装置が一部分の回
路基板の表面に実装された構造を示した断面側面図であ
る。FIG. 6 is a sectional side view showing a structure in which a conventional semiconductor device is mounted on the surface of a part of a circuit board.
【０００４】近年、パーソナルコンピュータ、携帯電話
機など電子機器においては、半導体装置を高密度に実装
するために、モジュールパッケージ、表面実装型パッケ
ージなどの構造で小型化及び薄型化されたものの出現が
望まれている。[0004] In recent years, in electronic devices such as personal computers and mobile phones, it has been desired that compact and thin structures such as a module package and a surface-mount type package appear in order to mount a semiconductor device at a high density. ing.
【０００５】集積回路の集積度の増加は、集積回路のた
めの要素と、その要素をそれぞれ連結する金属の配線を
半導体（シリコン）ウェーハ上に２次元的により微細に
形成することによって行われているが、最近、より微細
化が進み、半導体製造工程の技術上、限界が見えてきて
いる。このような課題を解決するために、印刷配線回路
基板にパッケージ化された高密度のモジュールの半導体
装置を実装したり、３次元的に高密度の半導体素子（チ
ップ）を積層して集積度を増加する方法が必要とされて
きた。しかし、このような構造或いは方法では、半導体
装置の厚みを薄くすることするにも限界がある。The degree of integration of an integrated circuit is increased by forming two-dimensionally finer elements for an integrated circuit and metal wiring connecting the elements on a semiconductor (silicon) wafer. However, recently, miniaturization has progressed, and the technical limit of the semiconductor manufacturing process is becoming apparent. In order to solve such a problem, a high-density module semiconductor device packaged on a printed circuit board is mounted, or a three-dimensionally high-density semiconductor element (chip) is stacked to reduce the degree of integration. There is a need for an increasing way. However, such a structure or method has a limit in reducing the thickness of the semiconductor device.
【０００６】これまで半導体装置１は、図６に示したよ
うに、所定のピッチで複数のバンプ２が形成されている
ベアチップ構造のものであっても、その厚みは、８イン
チ径の半導体ウェーハに換算して、精々１００μｍ止ま
りである。このような半導体装置１を回路基板Ｐに実装
する場合には、図６に示したように、前記のバンプ２の
数、位置に対応したピッチで複数の回路電極が形成され
ている回路基板Ｐのそれぞれの回路電極に、例えば、超
音波接合により前記バンプ２を接合し、そして回路基板
Ｐの表面と半導体装置１との間にフェノール樹脂のよう
な液状の緩衝樹脂Ｍを注入、硬化させる実装構造を採っ
ていて、緩衝樹脂Ｍを存在させることによって、矢印で
示したような上方から半導体装置１に加わる外力により
半導体装置１が損傷することを防止している。Heretofore, as shown in FIG. 6, even if the semiconductor device 1 has a bare chip structure in which a plurality of bumps 2 are formed at a predetermined pitch, the thickness of the semiconductor device is 8 inches in diameter. In terms of, it is at most 100 μm. When such a semiconductor device 1 is mounted on a circuit board P, as shown in FIG. 6, a circuit board P on which a plurality of circuit electrodes are formed at a pitch corresponding to the number and positions of the bumps 2 described above. The bumps 2 are bonded to the respective circuit electrodes by, for example, ultrasonic bonding, and a liquid buffer resin M such as a phenol resin is injected and cured between the surface of the circuit board P and the semiconductor device 1. With the structure, the presence of the buffer resin M prevents the semiconductor device 1 from being damaged by an external force applied to the semiconductor device 1 from above as indicated by an arrow.
【０００７】[0007]
【発明が解決しようとする課題】半導体装置１の厚みを
薄くする場合には、その製造工程で半導体ウェーハの厚
みを裏面研磨している。しかし、前記のような実装構造
を採る限り、半導体装置１の厚みを１００μｍ以下にす
ることは困難である。When the thickness of the semiconductor device 1 is reduced, the thickness of the semiconductor wafer is polished on the back surface in the manufacturing process. However, as long as the above mounting structure is adopted, it is difficult to reduce the thickness of the semiconductor device 1 to 100 μm or less.
【０００８】また、現在、開発しようとしている半導体
ウェーハの厚みのターゲットは５．０μｍ以下に置かれ
ていて、従来技術のような裏面研磨法を採る限り、例え
ば、８インチの半導体ウェーハをそこまで裏面研磨する
と半導体ウェーハに反りが発生したり、ハンドリングの
問題が発生し、設備の投資などに莫大な費用が必要にな
る。At present, the target of the thickness of the semiconductor wafer to be developed is set at 5.0 μm or less, and as long as the backside polishing method as in the prior art is employed, for example, an 8-inch semiconductor wafer can be reduced to that level. If the back surface is polished, the semiconductor wafer may be warped or a handling problem may occur, requiring enormous costs for equipment investment and the like.
【０００９】本発明はこのような課題を解決しようとす
るものであって、全体の厚みが薄くて反りの無い半導体
装置及びその製造方法を得ることを目的とするものであ
る。An object of the present invention is to solve such a problem, and it is an object of the present invention to obtain a semiconductor device having a small thickness without warpage and a method of manufacturing the same.
【００１０】[0010]
【課題を解決するための手段】それ故、請求項１に記載
の発明では、半導体装置を、同一高さの複数のバンプが
所定の位置に形成されている半導体ウェーハの表面に、
それらのバンプの先端が露出する状態で前記バンプの高
さと同一の厚さの樹脂層を形成する構造を採って、前記
課題を解決している。According to the first aspect of the present invention, a semiconductor device is provided on a surface of a semiconductor wafer having a plurality of bumps of the same height formed at predetermined positions.
The problem is solved by adopting a structure in which a resin layer having the same thickness as the height of the bump is formed in a state where the tips of the bumps are exposed.
【００１１】また、請求項２に記載の発明では、半導体
装置の製造方法として、半導体ウェーハの表面に所定の
位置に所定の高さよりも高い複数のバンプを形成する工
程と、それらのバンプが形成された表面に樹脂層を形成
する工程と、前記バンプの高さが所定の高さになるよう
に前記複数のバンプ及び前記樹脂層を研磨する工程と、
前記半導体ウェーハの裏面を研磨する工程と、その裏面
研磨された半導体ウェーハをダイシングして個々の半導
体装置に切り離す工程とを具備せしめる方法を採って、
前記課題を解決している。According to a second aspect of the present invention, as a method of manufacturing a semiconductor device, a step of forming a plurality of bumps higher than a predetermined height at a predetermined position on a surface of a semiconductor wafer, and forming the bumps Forming a resin layer on the surface, and polishing the plurality of bumps and the resin layer so that the height of the bumps is a predetermined height,
A step of polishing the back surface of the semiconductor wafer and a method of providing a step of dicing the back-polished semiconductor wafer and separating the semiconductor wafer into individual semiconductor devices,
The above problem has been solved.
【００１２】そしてまた、請求項３に記載の発明では、
請求項２に記載の半導体装置の製造方法における前記樹
脂層が半導体ウェーハの外周部を除いて形成されている
ことを特徴とする。Further, in the invention according to claim 3,
According to a second aspect of the present invention, in the method of manufacturing a semiconductor device, the resin layer is formed except for an outer peripheral portion of the semiconductor wafer.
【００１３】それ故、請求項１に記載の発明によれば、
半導体チップ部分の厚みが薄くても、樹脂層の存在によ
り半導体チップ部分の反りを防止でき、そしてハンドリ
ングが容易で、回路基板上に既存の設備を用いて反り無
く良好に実装することができる。Therefore, according to the first aspect of the present invention,
Even if the thickness of the semiconductor chip portion is thin, warpage of the semiconductor chip portion can be prevented by the presence of the resin layer, handling is easy, and the semiconductor device can be mounted on a circuit board without warpage using existing equipment.
【００１４】また、請求項２に記載の発明によれば、樹
脂層を設けたことにより、半導体ウェーハを反らすこと
なく、その裏面を研磨でき、しかも露出した先端面を除
く部分のバンプ及び半導体ウェーハの表面を封止するこ
とができる。According to the second aspect of the present invention, since the resin layer is provided, the back surface of the semiconductor wafer can be polished without warping the semiconductor wafer. Can be sealed.
【００１５】そしてまた、請求項３に記載の発明によれ
ば、請求項２に記載の発明の他に、アライメントライン
を残すことができ、ダイシングし易くなる。According to the third aspect of the present invention, in addition to the second aspect of the present invention, alignment lines can be left and dicing is facilitated.
【００１６】[0016]
【発明の実施の形態】以下、図１乃至図５を用いて、本
発明の一実施形態の半導体装置及びその製造方法を説明
する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention and a method for manufacturing the same will be described below with reference to FIGS.
【００１７】図１は半導体ウェーハの表面にバンプを形
成する工程の断面側面図、図２はバンプが形成された半
導体ウェーハの表面に樹脂層を形成する工程の断面側面
図、図３は図２の工程て形成した樹脂層及びバンプの一
部を研磨する工程の断面側面図、図４は図３に示した工
程で得た半導体ウェーハの裏面を研磨する工程の断面側
面図、そして図５は本発明の一実施形態の半導体装置を
示す斜視図である。FIG. 1 is a sectional side view of a step of forming a bump on the surface of a semiconductor wafer, FIG. 2 is a sectional side view of a step of forming a resin layer on the surface of the semiconductor wafer on which the bump is formed, and FIG. FIG. 4 is a cross-sectional side view of a step of polishing a part of the resin layer and the bumps formed in the step of FIG. 3, FIG. 4 is a cross-sectional side view of a step of polishing the back surface of the semiconductor wafer obtained in the step of FIG. 1 is a perspective view showing a semiconductor device according to one embodiment of the present invention.
【００１８】先ず、本発明の半導体装置の製造方法を図
を用いて説明する。First, a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings.
【００１９】図１において、円盤状の半導体ウェーハ１
１Ａの電子回路などが形成されている表面の所定の位置
に、印刷バンプまたはスタッドバンプの技術を用いて複
数のバンプ１２Ａを形成する。これらのバンプ１２Ａの
高さは通常の高さより少し高めに形成する。例えば、高
さが６０〜７０μｍの金または半田のボール状バンプで
ある。なお、半導体ウェーハの厚みは７２０μｍ程度の
ものである。In FIG. 1, a disc-shaped semiconductor wafer 1
A plurality of bumps 12A are formed at predetermined positions on the surface on which the 1A electronic circuit and the like are formed by using a printing bump or stud bump technique. The height of these bumps 12A is formed slightly higher than the normal height. For example, it is a gold or solder ball-shaped bump having a height of 60 to 70 μm. The thickness of the semiconductor wafer is about 720 μm.
【００２０】次に、全てのバンプ１２Ａを覆うように半
導体ウェーハ１１Ａの表面に液状の樹脂をコーティング
し、硬化させて、樹脂層１３Ａを形成する。この樹脂を
コーティングする際に、半導体ウェーハ１１Ａの外周か
ら数ｍｍの幅の外周部分１１１をマスクして樹脂が載ら
ないようにし、後記のダイシング工程の際のアライメン
ト用に使用する。樹脂層１３Ａのコーティングの厚さと
しては、バンプ１２Ａが前記の高さであれば、例えば、
１００μｍ程度とする。Next, a liquid resin is coated on the surface of the semiconductor wafer 11A so as to cover all the bumps 12A, and is cured to form a resin layer 13A. When coating the resin, the outer peripheral portion 111 having a width of several mm from the outer periphery of the semiconductor wafer 11A is masked so that the resin is not placed thereon, and is used for alignment in a dicing step described later. As the thickness of the coating of the resin layer 13A, if the bump 12A has the above-mentioned height, for example,
It is about 100 μm.
【００２１】また、樹脂の１例としては、エポキシ樹
脂、フェノール樹脂の混合物を挙げることができる。As an example of the resin, a mixture of an epoxy resin and a phenol resin can be given.
【００２２】次に、図３に示したように、樹脂層１３Ａ
の表面をバンプ１２Ａが露出してくるまで研削、研磨す
る。この研削、研磨はバンプ１２Ａが研削、研磨され
て、所定の高さになった時に、それぞれの先端部が露出
する面積が実装しようとする回路基板Ｐに形成されてい
る回路電極に十分に強度を保って接合できる面積になる
ように樹脂層１３と共に研削、研磨する。前記の実施例
の寸法であれば、１００μｍ厚みの樹脂層１３Ａを厚さ
３０μｍ程度になるまで研削、研磨する。符号１２、１
３はこれら最終高さのバンプ、最終厚さの樹脂層をそれ
ぞれ指す。Next, as shown in FIG. 3, the resin layer 13A
Is ground and polished until the bumps 12A are exposed. In this grinding and polishing, when the bumps 12A are ground and polished to a predetermined height, the areas where the respective tips are exposed have sufficient strength for the circuit electrodes formed on the circuit board P to be mounted. Is ground and polished together with the resin layer 13 so as to have an area that can be joined while maintaining the same. With the dimensions of the above embodiment, the resin layer 13A having a thickness of 100 μm is ground and polished until the thickness becomes about 30 μm. Symbols 12, 1
Reference numeral 3 denotes a bump having a final height and a resin layer having a final thickness.
【００２３】次に、図４に示したように、半導体ウェー
ハ１１Ａの裏面を必要な厚さになるまで研削、研磨す
る。この研削、研磨を開始する場合の全体の厚さは前記
のように半導体ウェーハ１１Ａの厚さ７２０μｍと樹脂
層１３の厚さ３０μｍとの合計７５０μｍ程度であるの
で、既存の研削、研磨装置を使用して容易に研削、研磨
することができる。この研削、研磨によって、例えば、
３０μｍ〜５０μｍ程度の薄さの半導体ウェーハ１１と
する。Next, as shown in FIG. 4, the back surface of the semiconductor wafer 11A is ground and polished to a required thickness. As described above, the total thickness when starting the grinding and polishing is about 750 μm in total, that is, the thickness of the semiconductor wafer 11A of 720 μm and the thickness of the resin layer 13 of 30 μm. And can be easily ground and polished. By this grinding and polishing, for example,
The semiconductor wafer 11 has a thickness of about 30 μm to 50 μm.
【００２４】そして、半導体ウェーハ１１の外周部１１
１に残されて露出されているアライメントを目安にして
ダイシングする。そうすると、図５に示したように、独
立した個体である本発明の一実施形態の半導体装置１０
が容易に得られる。このダイシングの際にも、半導体ウ
ェーハ１１が反っていると、精度良くダイシングできな
いが、全体として６０〜８０μｍ程度の厚さがあるため
に、良好にダイシングすることができる。The outer peripheral portion 11 of the semiconductor wafer 11
Dicing is performed using the exposed alignment left as a guide. Then, as shown in FIG. 5, the semiconductor device 10 according to the embodiment of the present invention, which is an independent individual,
Can be easily obtained. Also in this dicing, if the semiconductor wafer 11 is warped, dicing cannot be performed accurately, but since the thickness is about 60 to 80 μm as a whole, dicing can be performed well.
【００２５】個々の半導体装置１０は結果として半導体
チップが樹脂層１３で補強された構造となっているた
め、容易に反り返ることがない。Each semiconductor device 10 has a structure in which the semiconductor chip is reinforced by the resin layer 13 as a result, and therefore does not easily warp.
【００２６】このようにして得られた半導体装置１０
は、前記の各部の数値であれば、全体の厚みが６０〜８
０μｍ程度となる。従って、このような厚さの半導体装
置１０を回路基板Ｐに表面実装する場合には、その取扱
いが極めて容易となり、専用設備を必要とせず、従来技
術の実装設備を用いて回路基板Ｐ上に実装することがで
きる。The semiconductor device 10 thus obtained
Is the numerical value of each part described above, the total thickness is 60 to 8
It is about 0 μm. Therefore, when the semiconductor device 10 having such a thickness is surface-mounted on the circuit board P, the handling becomes extremely easy, no special equipment is required, and the mounting equipment of the prior art is used on the circuit board P. Can be implemented.
【００２７】[0027]
【発明の効果】以上説明したように、本発明によれば、
半導体チップが樹脂層で補強された構造の半導体装置が
得られ、反りを低減でき、また、取扱いが容易となる。
従って、既存の実装装置を用いて損傷を与えることなく
実装することができる。As described above, according to the present invention,
A semiconductor device having a structure in which a semiconductor chip is reinforced with a resin layer can be obtained, warpage can be reduced, and handling is easy.
Therefore, mounting can be performed using an existing mounting apparatus without damage.
【００２８】また、製造方法においても、樹脂層の存在
により半導体ウェーハが補強された構造となるために、
その半導体ウェーハを反らすことなく、その裏面を５０
μｍ以下の薄い厚さまで既存の設備を用いて研磨するこ
とができ、歩留まり良く、そして低コストで製造するこ
とができる。Also, in the manufacturing method, since the semiconductor wafer has a structure reinforced by the presence of the resin layer,
Without warping the semiconductor wafer, the back side
It can be polished using existing equipment to a thin thickness of less than μm, and can be manufactured with good yield and at low cost.
【図１】 半導体ウェーハの表面にバンプを形成する工
程の断面側面図である。FIG. 1 is a sectional side view of a step of forming a bump on a surface of a semiconductor wafer.
【図２】 バンプが形成された半導体ウェーハの表面に
樹脂層を形成する工程の断面側面図である。FIG. 2 is a cross-sectional side view of a step of forming a resin layer on a surface of a semiconductor wafer on which bumps are formed.
【図３】 図２の工程て形成した樹脂層及びバンプの一
部を研磨する工程の断面側面図である。FIG. 3 is a sectional side view of a step of polishing a part of the resin layer and the bump formed in the step of FIG. 2;
【図４】 図３に示した工程で得た半導体ウェーハの裏
面を研磨する工程の断面側面図である。4 is a cross-sectional side view of a step of polishing the back surface of the semiconductor wafer obtained in the step shown in FIG.
【図５】 本発明の一実施形態の半導体装置を示す斜視
図である。FIG. 5 is a perspective view showing a semiconductor device according to one embodiment of the present invention.
【図６】 従来技術の半導体装置が一部分の回路基板の
表面に実装された構造を示した断面側面図である。FIG. 6 is a cross-sectional side view showing a structure in which a conventional semiconductor device is mounted on the surface of a part of a circuit board.
１０…本発明の一実施形態の半導体装置、１１…（研磨
後の）半導体ウェーハ、１１Ａ…（研磨前の）半導体ウ
ェーハ、１１１…半導体ウェーハの外周部、１２…（研
磨後の）バンプ、１２Ａ…（研磨前の）バンプ、１３…
（研磨後の）樹脂層、１３Ａ…（研磨前の）樹脂層、Ｐ
…回路基板10 semiconductor device of one embodiment of the present invention, 11 semiconductor wafer (after polishing), 11A semiconductor wafer (before polishing), 111 peripheral portion of semiconductor wafer, 12 bump (after polishing), 12A ... bumps (before polishing), 13 ...
Resin layer (after polishing), 13A ... resin layer (before polishing), P
… Circuit board
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 23/28 Ｈ０１Ｌ 21/92 ６０２Ｋ ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 23/28 H01L 21/92 602K
Claims (3)
に形成されている半導体ウェーハの表面に、該バンプの
先端が露出する状態で前記バンプの高さと同一の厚さの
樹脂層が形成されていることを特徴とする半導体装置。1. A resin layer having a thickness equal to the height of a bump is formed on a surface of a semiconductor wafer on which a plurality of bumps having the same height are formed at predetermined positions, with a tip of the bump being exposed. A semiconductor device characterized by being formed.
定の高さよりも高い複数のバンプを形成する工程と、 該バンプが形成された表面に樹脂層を形成する工程と、 前記バンプの高さが所定の高さになるように前記複数の
バンプ及び前記樹脂層を研磨する工程と、 前記半導体ウェーハの裏面を研磨する工程と該裏面研磨
された半導体ウェーハをダイシングして個々の半導体装
置に切り離す工程とを備えた半導体装置の製造装置。2. A step of forming a plurality of bumps higher than a predetermined height at a predetermined position on a surface of a semiconductor wafer; a step of forming a resin layer on a surface on which the bumps are formed; Polishing the plurality of bumps and the resin layer so that a predetermined height is obtained, polishing the back surface of the semiconductor wafer, and dicing the semiconductor wafer having the back surface diced into individual semiconductor devices. Manufacturing apparatus for semiconductor devices, comprising:
除いて形成されていることを特徴とする請求項２に記載
の半導体装置の製造方法。3. The method according to claim 2, wherein the resin layer is formed except for an outer peripheral portion of the semiconductor wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001064039A JP2002270719A (en) | 2001-03-07 | 2001-03-07 | Semiconductor device and its manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001064039A JP2002270719A (en) | 2001-03-07 | 2001-03-07 | Semiconductor device and its manufacturing method |
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| Publication Number | Publication Date |
|---|---|
| JP2002270719A true JP2002270719A (en) | 2002-09-20 |
Family
ID=18922929
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001064039A Pending JP2002270719A (en) | 2001-03-07 | 2001-03-07 | Semiconductor device and its manufacturing method |
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| Country | Link |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003065430A1 (en) * | 2002-01-28 | 2003-08-07 | Disco Corporation | Method of processing semiconductor wafer |
| JP2005338060A (en) * | 2004-05-28 | 2005-12-08 | Feinmetall Gmbh | Inspection device for electric inspection of inspection article and manufacturing method for inspection device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000053844A (en) * | 1998-08-06 | 2000-02-22 | Toshiba Chem Corp | Liquid, sealing resin composition |
| JP2000332034A (en) * | 1999-05-18 | 2000-11-30 | Japan Rec Co Ltd | Manufacture of electronic component |
| JP2001060591A (en) * | 1999-08-23 | 2001-03-06 | Rohm Co Ltd | Manufacture of semiconductor device |
-
2001
- 2001-03-07 JP JP2001064039A patent/JP2002270719A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000053844A (en) * | 1998-08-06 | 2000-02-22 | Toshiba Chem Corp | Liquid, sealing resin composition |
| JP2000332034A (en) * | 1999-05-18 | 2000-11-30 | Japan Rec Co Ltd | Manufacture of electronic component |
| JP2001060591A (en) * | 1999-08-23 | 2001-03-06 | Rohm Co Ltd | Manufacture of semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003065430A1 (en) * | 2002-01-28 | 2003-08-07 | Disco Corporation | Method of processing semiconductor wafer |
| US6944370B2 (en) | 2002-01-28 | 2005-09-13 | Disco Corporation | Method of processing a semiconductor wafer |
| JP2005338060A (en) * | 2004-05-28 | 2005-12-08 | Feinmetall Gmbh | Inspection device for electric inspection of inspection article and manufacturing method for inspection device |
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