JP2002252351A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2002252351A JP2002252351A JP2001049672A JP2001049672A JP2002252351A JP 2002252351 A JP2002252351 A JP 2002252351A JP 2001049672 A JP2001049672 A JP 2001049672A JP 2001049672 A JP2001049672 A JP 2001049672A JP 2002252351 A JP2002252351 A JP 2002252351A
- Authority
- JP
- Japan
- Prior art keywords
- electrode layer
- electrode
- stress
- semiconductor device
- metal film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置の製造方
法に関し、特にボンディングワイヤレス構造のトランジ
スタの第２電極層による応力を緩和し、Ｖgs(off)特性
の変動を解消する半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a semiconductor device capable of relieving a stress caused by a second electrode layer of a transistor having a bonding wireless structure and eliminating fluctuations in V gs (off) characteristics.
【０００２】[0002]
【従来の技術】従来の半導体装置の組立工程において
は、ウェハからダイシングして分離した半導体素子をリ
ードフレームに固着し、金型と樹脂注入によるトランス
ファーモールドによって半導体素子を封止し、リードフ
レームを切断して個々の半導体装置毎に分離する、とい
う工程が行われている。2. Description of the Related Art In a conventional semiconductor device assembling process, a semiconductor element separated by dicing from a wafer is fixed to a lead frame, and the semiconductor element is sealed by a transfer mold using a mold and resin injection. A process of cutting and separating each semiconductor device is performed.
【０００３】図４には、リードフレームを固着する前の
ＭＯＳＦＥＴを示す。図４（Ａ）は上面図であり、図４
（Ｂ）はＣ−Ｃ線の断面図である。リードフレームは、
半田又は導電ペーストにより固着されるが、ＭＯＳＦＥ
Ｔ１のソースパッド電極２ａおよびゲートパッド電極２
ｂは、アルミニウム合金であり、半田又は導電ペースト
との接着性が悪い。そのためＴｉ−Ｎｉ−Ａｕ等の金属
膜１３を介して接着される。FIG. 4 shows a MOSFET before a lead frame is fixed. FIG. 4A is a top view and FIG.
(B) is a sectional view taken along line CC. The lead frame is
It is fixed by solder or conductive paste.
T1 source pad electrode 2a and gate pad electrode 2
b is an aluminum alloy and has poor adhesion to solder or conductive paste. Therefore, they are bonded via a metal film 13 such as Ti-Ni-Au.
【０００４】図５は上記した方法により製造したＭＯＳ
ＦＥＴを示す。図５（Ａ）は上面図であり、Ｄ−Ｄ線の
断面図を図５（Ｂ）に示す。FIG. 5 shows a MOS manufactured by the above method.
2 shows an FET. FIG. 5A is a top view, and FIG. 5B is a cross-sectional view taken along line DD.
【０００５】リードフレームは、銅を素材とした打ち抜
きフレームであり、このフレームのヘッダー２１上に半
田あるいはＡｇペーストよりなるプリフォーム材２２で
パワーＭＯＳＦＥＴのベアチップ１が固着される。パワ
ーＭＯＳＦＥＴのベアチップ１の下面は金の裏張り電極
（図示せず）によりドレイン電極が形成され、上面には
アルミニウム合金の蒸着によりソースパッド電極とゲー
トパッド電極となる第１電極層２が形成される。更に、
半田および導電材料５との抵抗を下げ、且つ接着性を向
上させるためＴｉ−Ｎｉ−Ａｕ等の金属膜１３をその上
部に蒸着する。フレームのドレイン端子２５はヘッダー
２１と連結されているので、ドレイン電極と直結され、
ゲートパッド電極およびソースパッド電極の第１電極層
２は半田又は導電ペースト５によりゲート端子２６およ
びソース端子２７と電気的に接続される。The lead frame is a punched frame made of copper, and a power MOSFET bare chip 1 is fixed on a header 21 of the frame with a preform material 22 made of solder or Ag paste. A drain electrode is formed on the lower surface of the bare chip 1 of the power MOSFET by a gold backing electrode (not shown), and a first electrode layer 2 serving as a source pad electrode and a gate pad electrode is formed on the upper surface by vapor deposition of an aluminum alloy. You. Furthermore,
A metal film 13 such as Ti-Ni-Au is deposited on the upper portion of the metal film 13 in order to lower the resistance between the solder and the conductive material 5 and improve the adhesion. Since the drain terminal 25 of the frame is connected to the header 21, it is directly connected to the drain electrode,
The first electrode layer 2 of the gate pad electrode and the source pad electrode is electrically connected to the gate terminal 26 and the source terminal 27 by the solder or the conductive paste 5.
【０００６】パワーＭＯＳＦＥＴのベアチップ１および
フレームは金型およびトランスファーモールドで樹脂封
止され、樹脂層２８はパッケージ外形を構成する。The bare chip 1 and the frame of the power MOSFET are resin-sealed with a mold and a transfer mold, and the resin layer 28 forms a package outer shape.
【０００７】このように、半導体チップとリードフレー
ムの接続にボンディングワイヤを用いず、リードフレー
ムを直接固着するボンディングワイヤレス構造のトラン
ジスタは、ボンディングワイヤ自体の抵抗が半導体チッ
プのオン抵抗に加算されないので、素子の特性を妨げ
ず、ロスの少ない半導体装置を実現できる。As described above, in a transistor having a bonding wireless structure in which a lead frame is directly fixed without using a bonding wire for connection between a semiconductor chip and a lead frame, the resistance of the bonding wire itself is not added to the on-resistance of the semiconductor chip. A semiconductor device with less loss can be realized without hindering element characteristics.
【０００８】[0008]
【発明が解決しようとする課題】この構造は、ＭＯＳＦ
ＥＴのソース電極およびゲート電極とコンタクトし、動
作部全面を覆うアルミニウム合金とフレームを固着する
半田との接着性が悪いため、アルミニウム合金の上に接
着性の良いＴｉ−Ｎｉ−Ａｕ等の金属膜を設け、電極を
２層構造にしている。しかし、ＮｉやＡｕは応力の定数
であるヤング率が大きく、トランジスタ動作部全面に形
成された２層の金属電極には応力が加わるため、実動作
領域に悪影響を及ぼし、Ｖgs(off)特性（ピンチオフ特
性）に変動が生じてしまう。例えばＮチャネル型パワー
ＭＯＳＦＥＴでは、ボンディングワイヤレス構造に必要
な第２電極層の応力により、第２電極層を形成しない場
合と比較してＶgs(off)特性が変動する。Ｖgs(off)特性
が変動した場合、所望の性能に合わせるため注入条件の
変更等が発生し、不具合が生じる問題があった。This structure is a MOSF
A metal film such as Ti-Ni-Au having good adhesion is formed on the aluminum alloy because the adhesion between the aluminum alloy covering the entire surface of the operation section and the solder for fixing the frame is poor due to the contact with the source electrode and the gate electrode of the ET. And the electrode has a two-layer structure. However, Ni and Au have a large Young's modulus, which is a constant of stress, and apply stress to the two-layered metal electrode formed on the entire surface of the transistor operation part, which has an adverse effect on the actual operation area, and V gs (off) characteristics. (Pinch-off characteristics). For example, in an N-channel type power MOSFET, the V gs (off) characteristic fluctuates due to the stress of the second electrode layer required for the bonding wireless structure as compared with the case where the second electrode layer is not formed. When the V gs (off) characteristic fluctuates, the injection conditions are changed in order to meet the desired performance, and a problem occurs.
【０００９】[0009]
【課題を解決するための手段】本発明は上述した問題点
に鑑みてなされたものであり、半導体チップ上に設けら
れた第１電極層と該第１電極層上に設けた第２電極層と
を有する半導体装置において、前記第２電極層には切欠
部が多数設けられ、前記切欠部に前記第１電極層を露出
させ、前記第２電極層上にリード端子を固着することを
特徴とし、第２電極層である金属膜を格子状又はスリッ
ト状に形成することにより、応力を分断して実動作領域
への悪影響を緩和し、Ｖgs(off)特性の変動を解消する
ものである。SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a first electrode layer provided on a semiconductor chip and a second electrode layer provided on the first electrode layer. A plurality of cutouts are provided in the second electrode layer, the first electrode layer is exposed in the cutouts, and a lead terminal is fixed on the second electrode layer. By forming the metal film serving as the second electrode layer in a lattice or slit shape, the stress is divided to mitigate the adverse effect on the actual operation region and eliminate the fluctuation of the V gs (off) characteristic. .
【００１０】[0010]
【発明の実施の形態】図１および図２を参照して本発明
の実施の形態を詳述する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to FIGS.
【００１１】図１に示す、本発明の半導体装置は、ＭＯ
ＳＦＥＴ１と、第１電極層２と、第２電極層３とから構
成される。図１（Ａ）は上面図であり、図１（Ｂ）はＡ
−Ａ線の断面図である。尚、図４に示したものと同一構
成要素は同一符号とする。The semiconductor device of the present invention shown in FIG.
It comprises an SFET 1, a first electrode layer 2, and a second electrode layer 3. FIG. 1A is a top view, and FIG.
It is sectional drawing of the -A line. The same components as those shown in FIG. 4 have the same reference numerals.
【００１２】ＭＯＳＦＥＴ１は、既知の方法により設け
られ、実動作領域には多数のＭＯＳＦＥＴトランジスタ
のセルが配列され、各セルのソース電極はソースパッド
電極２ａとコンタクトし、ゲート電極は実動作領域外に
延在されてゲートパッド電極２ｂとコンタクトする。The MOSFET 1 is provided by a known method, and a large number of MOSFET transistor cells are arranged in an actual operation area, a source electrode of each cell is in contact with a source pad electrode 2a, and a gate electrode is outside the actual operation area. It extends to contact the gate pad electrode 2b.
【００１３】第１電極層２は、アルミニウム合金等から
なるソースパッド電極２ａおよびゲートパッド電極２ｂ
である。各セルのソース電極とコンタクトするソースパ
ッド電極２ａは、アルミニウム合金等の蒸着により実動
作領域を覆って設けられる。これは、オン抵抗を低減す
るためには接合面積はできるだけ大きくとる必要がある
からである。The first electrode layer 2 includes a source pad electrode 2a and a gate pad electrode 2b made of an aluminum alloy or the like.
It is. The source pad electrode 2a that is in contact with the source electrode of each cell is provided so as to cover the actual operation region by vapor deposition of an aluminum alloy or the like. This is because the junction area needs to be as large as possible to reduce the on-resistance.
【００１４】更に、実動作領域外には、ソースパッド電
極２ａと同一工程でアルミニウム合金等を蒸着し、所望
の形状にエッチングしたゲートパッド電極２ｂが設けら
れ、各セルのゲート電極が延在され、連結される。Further, outside the actual operation region, a gate pad electrode 2b is formed by depositing an aluminum alloy or the like in the same step as the source pad electrode 2a and etching it into a desired shape, and the gate electrode of each cell is extended. , Are linked.
【００１５】第２電極層３は、第１電極層であるソース
パッド電極２ａおよびゲートパッド電極２ｂにそれぞれ
重畳する大きさに設けられるが、多数の切欠部４を有
し、格子状に形成される。つまり、所望するパターンの
切欠部を設けるためフォトレジストパターンを形成し、
基板全面にＴｉ−Ｎｉ−Ａｕ又は、Ｃｒ−Ｃｕ−Ａｕ等
からなる金属膜を蒸着し、リフトオフによりフォトレジ
スト及びフォトレジスト上の不要な金属膜を除去する。
これにより切欠部４のフォトレジスト及び第２電極層３
の金属膜が除去されて、切欠部４からは第１電極層２が
露出する。The second electrode layer 3 is provided in such a size as to overlap the source pad electrode 2a and the gate pad electrode 2b, which are the first electrode layers, respectively. You. That is, a photoresist pattern is formed in order to provide a notch of a desired pattern,
A metal film made of Ti-Ni-Au or Cr-Cu-Au is deposited on the entire surface of the substrate, and the photoresist and the unnecessary metal film on the photoresist are removed by lift-off.
Thereby, the photoresist of the notch 4 and the second electrode layer 3
Is removed, and the first electrode layer 2 is exposed from the cutout 4.
【００１６】応力の定数であるヤング率は、バルク値で
Ａｕが7.9×1010Ｎ／ｍ2、Ｎｉでは23.6×1010Ｎ／ｍ2
であり、これらの金属膜を全面に設けたトランジスタの
実動作領域では大きな影響を受け、Ｖgs(off)特性が変
動してしまう。そこで、第２電極層３に切欠部を設ける
ことによりその応力を分断して、実動作領域への悪影響
を緩和することができる。The Young's modulus, which is a stress constant, is 7.9 × 10 10 N / m 2 for Au and 23.6 × 10 10 N / m 2 for Ni in bulk value.
In the actual operation region of a transistor in which these metal films are provided on the entire surface, V gs (off) characteristics are greatly affected and fluctuate. Therefore, by providing a cutout in the second electrode layer 3, the stress can be divided, and the adverse effect on the actual operation area can be reduced.
【００１７】この時、切欠部４の幅は第２電極層３の厚
みの２倍以下にすれば、フレームと固着するための半田
又は導電ペーストとの接着面積が従来と同等またはそれ
以上確保できるので、切欠部４を設けることによる接着
強度の低下を抑制することができる。At this time, if the width of the cutout portion 4 is set to be twice or less the thickness of the second electrode layer 3, a bonding area with solder or conductive paste for fixing to the frame can be secured equal to or larger than the conventional one. Therefore, it is possible to suppress a decrease in adhesive strength due to the provision of the notch 4.
【００１８】図２に、本発明のＭＯＳＦＥＴをボンディ
ングワイヤを使用せずにリードフレームと固着した断面
図を示す。図２（Ａ）は上面図であり、Ｂ−Ｂ線の断面
図を図２（Ｂ）に示す。尚、図５に示すものと同一構成
要素は同一符号とする。FIG. 2 is a cross-sectional view in which the MOSFET of the present invention is fixed to a lead frame without using a bonding wire. FIG. 2A is a top view, and FIG. 2B is a cross-sectional view taken along line BB. The same components as those shown in FIG.
【００１９】リードフレームは、ドレイン端子２５、ゲ
ート端子２６およびソース端子２７を有する銅を素材と
した打ち抜きフレームであり、このフレームのヘッダー
２１上に半田あるいはＡｇペーストよりなるプリフォー
ム材２２でパワーＭＯＳＦＥＴのベアチップ１が固着さ
れる。パワーＭＯＳＦＥＴのベアチップ１の下面は金の
裏張り電極（図示せず）によりドレイン電極が形成さ
れ、上面にはアルミニウム合金の蒸着によりソースパッ
ド電極およびゲートパッド電極である第１電極層２が形
成される。更に、半田または導電ペースト５との抵抗を
下げるためのＵＭＢ（Under Bump Metal）としてＴｉ
−Ｎｉ−Ａｕ又はＣｒ−Ｃｕ−Ａｕ等の金属膜からなる
第２電極層３をその上部に蒸着する。フレームのドレイ
ン端子２５はヘッダー２１と連結されているので、ドレ
イン電極と直結され、ソースパッド電極およびゲートパ
ッド電極は半田又は導電ペースト５によりゲート端子２
６およびソース端子２７と電気的に接続される。The lead frame is a punched frame made of copper having a drain terminal 25, a gate terminal 26, and a source terminal 27. A power MOSFET is formed on a header 21 of the frame by using a preform material 22 made of solder or Ag paste. The bare chip 1 is fixed. A drain electrode is formed by a gold backing electrode (not shown) on the lower surface of the bare chip 1 of the power MOSFET, and a first electrode layer 2 serving as a source pad electrode and a gate pad electrode is formed on the upper surface by vapor deposition of an aluminum alloy. You. Further, as UMB (Under Bump Metal) for lowering resistance with solder or conductive paste 5, Ti is used.
A second electrode layer 3 made of a metal film such as Ni-Au or Cr-Cu-Au is deposited on the second electrode layer 3; Since the drain terminal 25 of the frame is connected to the header 21, it is directly connected to the drain electrode, and the source pad electrode and the gate pad electrode are connected to the gate terminal 2 by solder or conductive paste 5.
6 and the source terminal 27.
【００２０】パワーＭＯＳＦＥＴのベアチップ１および
フレームは金型およびトランスファーモールドで樹脂封
止され、樹脂層２８はパッケージ外形を構成する。The bare chip 1 and the frame of the power MOSFET are resin-sealed with a mold and a transfer mold, and the resin layer 28 forms a package outer shape.
【００２１】このように、半導体チップとリードフレー
ムの接続にボンディングワイヤを用いず、リードフレー
ムを直接固着するボンディングワイヤレス構造のトラン
ジスタは、ボンディングワイヤ自体の抵抗が半導体チッ
プのオン抵抗に加算されないので、素子の特性を妨げ
ず、ロスの少ない半導体装置を実現できる。As described above, in a transistor having a bonding wireless structure in which a lead frame is directly fixed without using a bonding wire for connection between a semiconductor chip and a lead frame, the resistance of the bonding wire itself is not added to the on-resistance of the semiconductor chip. A semiconductor device with less loss can be realized without hindering element characteristics.
【００２２】本発明の特徴は、第２電極層３に多数の切
欠部４を設けることにある。ヤング率の高い金属膜であ
る第２電極層を全面に設けた実動作領域は、その応力に
よる悪影響を受け、Ｖgs(off)特性が変動してしまう。A feature of the present invention resides in that a large number of notches 4 are provided in the second electrode layer 3. The actual operation region in which the second electrode layer, which is a metal film having a high Young's modulus, is provided on the entire surface is adversely affected by the stress, and the V gs (off) characteristics fluctuate.
【００２３】このため、第２電極層３に切欠部４を多数
設けることにより、第２電極層全面に発生する応力を分
断し、実動作領域への悪影響を緩和させることができ
る。応力の緩和は、Ｖgs(off)特性の変動を解消し、安
定した性能を有するパワーＭＯＳＦＥＴの作製が実現で
きる。For this reason, by providing a large number of notches 4 in the second electrode layer 3, the stress generated on the entire surface of the second electrode layer can be divided, and the adverse effect on the actual operation area can be reduced. Relaxation of the stress eliminates fluctuations in V gs (off) characteristics, and enables the production of a power MOSFET having stable performance.
【００２４】具体的には、Ｎチャネル型パワーＭＯＳＦ
ＥＴでは従来Ｖgs(off)特性が設計時の値よりも０．４
Ｖ程度低くなってしまっていたが、第２電極層３を格子
状に形成した場合では、特性の変動は０となる。More specifically, an N-channel type power MOSF
In ET, the conventional V gs (off) characteristic is 0.4
Although the voltage has been lowered by about V, when the second electrode layer 3 is formed in a lattice shape, the fluctuation of the characteristic becomes zero.
【００２５】また、第２電極層３は、切欠部４の幅を第
２電極層の厚みの２倍以下になるように設けることによ
り、半田又は導電ペースト５との接着面積は従来と同等
またはそれ以上確保できるので、切欠部４を設けること
による接着強度の低下を防ぐことができる。Further, the second electrode layer 3 is provided such that the width of the notch 4 is not more than twice the thickness of the second electrode layer, so that the bonding area with the solder or the conductive paste 5 is equal to or equal to the conventional one. Since it can secure more, it is possible to prevent a decrease in adhesive strength due to the provision of the notch 4.
【００２６】ここで、図３に示す如く第２電極層３は、
スリット状に形成されてもよく、この場合でも切欠部の
幅を第２電極層の厚みの２倍以下になるような形状であ
れば、応力を緩和しつつ従来程度の接着強度を確保でき
る。Here, as shown in FIG. 3, the second electrode layer 3
It may be formed in a slit shape. Even in this case, if the width of the cutout portion is not more than twice the thickness of the second electrode layer, the conventional adhesive strength can be secured while relaxing the stress.
【００２７】更に、前述の形状に限らず、例えば、櫛歯
型やハニカム型等、切欠部を形成することにより応力を
分断できる形状であれば良い。Further, the shape is not limited to the above-mentioned shape, but may be any shape such as a comb type or a honeycomb type which can divide the stress by forming a cutout.
【００２８】[0028]
【発明の効果】本発明によれば、第２電極層３に切欠部
４を多数設けることにより、第２電極層を設けることに
より全面に発生する応力を分断して、実動作領域への悪
影響を緩和させることができる。応力の緩和は、Ｖ
gs(off)特性の変動を解消し、安定した性能を有するパ
ワーＭＯＳＦＥＴを実現できる。According to the present invention, by providing a large number of cutouts 4 in the second electrode layer 3, the stress generated on the entire surface by the provision of the second electrode layer is divided, thereby adversely affecting the actual operation area. Can be alleviated. Stress relief is V
It is possible to realize a power MOSFET having stable performance by eliminating fluctuations in gs (off) characteristics.
【００２９】具体的には、Ｎチャネル型パワーＭＯＳＦ
ＥＴでは従来Ｖgs(off)特性が設計時の値よりも０．４
Ｖ程度低くなってしまっていたが、第２電極層３を格子
状に形成した場合、Ｖgs(off)特性の変動は０となる。More specifically, an N-channel type power MOSF
In ET, the conventional V gs (off) characteristic is 0.4
Although the voltage has been lowered by about V, when the second electrode layer 3 is formed in a lattice shape, the fluctuation of the V gs (off) characteristic becomes zero.
【００３０】また、第２電極層３は、切欠部４の幅を第
２電極層の厚みの２倍以下になるように設けることによ
り、半田又は導電ペーストとの接着面積は従来と同等ま
たはそれ以上確保できるので、切欠部４を設けることに
よる接着強度の低下を防ぐことができる。Further, the second electrode layer 3 is provided such that the width of the notch 4 is not more than twice the thickness of the second electrode layer, so that the bonding area with the solder or conductive paste is equal to or smaller than that of the conventional one. Since the above can be secured, it is possible to prevent a decrease in the adhesive strength due to the provision of the notch 4.
【図１】本発明を説明するための上面図および断面図で
ある。FIG. 1 is a top view and a cross-sectional view for explaining the present invention.
【図２】本発明を説明するための上面図および断面図で
ある。FIG. 2 is a top view and a cross-sectional view for explaining the present invention.
【図３】本発明を説明するための上面図である。FIG. 3 is a top view for explaining the present invention.
【図４】従来の技術を説明するための上面図および断面
図である。FIG. 4 is a top view and a cross-sectional view for explaining a conventional technique.
【図５】従来の技術を説明するための上面図および断面
図である。FIG. 5 is a top view and a sectional view for explaining a conventional technique.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 21/60 ３２１ Ｈ０１Ｌ 21/60 ３２１Ｖ 21/3205 21/88 Ｔ 29/41 29/44 Ｆ Ｆターム(参考） 4M104 BB02 CC05 DD68 DD94 FF11 FF13 GG09 GG18 HH18 5F033 HH07 HH08 HH11 HH13 HH17 HH18 MM05 MM08 MM21 MM22 MM30 PP19 QQ41 VV06 VV07 XX09 XX10 XX12 XX19 5F044 LL01 LL07 QQ07 RR06 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 21/60 321 H01L 21/60 321V 21/3205 21/88 T 29/41 29/44 F F term ( Reference) 4M104 BB02 CC05 DD68 DD94 FF11 FF13 GG09 GG18 HH18 5F033 HH07 HH08 HH11 HH13 HH17 HH18 MM05 MM08 MM21 MM22 MM30 PP19 QQ41 VV06 VV07 XX09 XX10 XX12 XX19 5F044 LL01 LL01 06
Claims (5)
と該第１電極層上に設けた第２電極層とを有する半導体
装置において、 前記第２電極層には切欠部が多数設けられ、前記切欠部
に前記第１電極層を露出させ、前記第２電極層上にリー
ド端子を固着することを特徴とする半導体装置。1. A semiconductor device having a first electrode layer provided on a semiconductor chip and a second electrode layer provided on the first electrode layer, wherein the second electrode layer has a number of notches. A semiconductor device, wherein the first electrode layer is exposed in the cutout portion, and a lead terminal is fixed on the second electrode layer.
設けた実動作領域と前記ＭＯＳＦＥＴのソース電極およ
びゲート電極とそれぞれコンタクトし前記実動作領域を
覆って設けられた第１電極層と該第１電極層上に設けた
第２電極層とを有する半導体装置において、 前記第２電極層には切欠部が多数設けられ、前記切欠部
に前記第１電極層を露出させ、前記第２電極層上にリー
ド端子を固着することを特徴とする半導体装置。A first electrode layer provided in contact with a source electrode and a gate electrode of the MOSFET and covering the actual operation region; and a first electrode layer provided in contact with a source electrode and a gate electrode of the MOSFET. A second electrode layer provided on the second electrode layer, wherein the second electrode layer has a plurality of cutouts, the first electrode layer is exposed in the cutouts, A semiconductor device to which a lead terminal is fixed.
状であることを特徴とする請求項１または請求項２に記
載の半導体装置。3. The semiconductor device according to claim 1, wherein the second electrode layer has a lattice shape or a slit shape.
ドフレームが固着されることを特徴とする請求項１また
は請求項２に記載の半導体装置。4. The semiconductor device according to claim 1, wherein a lead frame is fixed to the second electrode layer with a conductive material.
徴とする請求項１または請求項２に記載の半導体装置。5. The semiconductor device according to claim 1, wherein the second electrode layer is a metal film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001049672A JP2002252351A (en) | 2001-02-26 | 2001-02-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001049672A JP2002252351A (en) | 2001-02-26 | 2001-02-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2002252351A true JP2002252351A (en) | 2002-09-06 |
Family
ID=18910742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001049672A Withdrawn JP2002252351A (en) | 2001-02-26 | 2001-02-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2002252351A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005101293A (en) * | 2003-09-25 | 2005-04-14 | Renesas Technology Corp | Semiconductor device |
| JP2006196839A (en) * | 2005-01-17 | 2006-07-27 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
| JP2007013034A (en) * | 2005-07-04 | 2007-01-18 | Mitsubishi Electric Corp | Semiconductor device |
| JP2007142138A (en) * | 2005-11-18 | 2007-06-07 | Mitsubishi Electric Corp | Semiconductor device |
| DE102007036044A1 (en) * | 2007-08-01 | 2009-02-05 | Siemens Ag | Chip module, particularly power module, comprises chip which is provided with main side with one or multiple chip contact surfaces, where structured sheet metal layer is provided with main side |
| DE102008025246A1 (en) * | 2008-05-27 | 2009-12-17 | Siemens Aktiengesellschaft | Method for contacting mechanical or thermal or electrical conducting connection at electrical contact surface of electronic component, involves producing contact layer between connection and contact surface |
| JP2012151287A (en) * | 2011-01-19 | 2012-08-09 | Mitsubishi Electric Corp | Insulation gate type semiconductor device |
| WO2015029638A1 (en) * | 2013-08-30 | 2015-03-05 | 株式会社日立製作所 | Semiconductor device for power generation, method for manufacturing same, and solder therefor |
| WO2022220009A1 (en) * | 2021-04-12 | 2022-10-20 | ローム株式会社 | Semiconductor device |
-
2001
- 2001-02-26 JP JP2001049672A patent/JP2002252351A/en not_active Withdrawn
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005101293A (en) * | 2003-09-25 | 2005-04-14 | Renesas Technology Corp | Semiconductor device |
| JP4559866B2 (en) * | 2005-01-17 | 2010-10-13 | パナソニック株式会社 | Manufacturing method of semiconductor device |
| JP2006196839A (en) * | 2005-01-17 | 2006-07-27 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
| US7682898B2 (en) | 2005-01-17 | 2010-03-23 | Panasonic Corporation | Semiconductor device and method for fabricating the same |
| JP2007013034A (en) * | 2005-07-04 | 2007-01-18 | Mitsubishi Electric Corp | Semiconductor device |
| DE102006015112B4 (en) * | 2005-07-04 | 2012-09-13 | Mitsubishi Denki K.K. | Semiconductor device and electric power semiconductor product |
| JP4659534B2 (en) * | 2005-07-04 | 2011-03-30 | 三菱電機株式会社 | Semiconductor device |
| JP2007142138A (en) * | 2005-11-18 | 2007-06-07 | Mitsubishi Electric Corp | Semiconductor device |
| DE102007036044A1 (en) * | 2007-08-01 | 2009-02-05 | Siemens Ag | Chip module, particularly power module, comprises chip which is provided with main side with one or multiple chip contact surfaces, where structured sheet metal layer is provided with main side |
| DE102008025246A1 (en) * | 2008-05-27 | 2009-12-17 | Siemens Aktiengesellschaft | Method for contacting mechanical or thermal or electrical conducting connection at electrical contact surface of electronic component, involves producing contact layer between connection and contact surface |
| JP2012151287A (en) * | 2011-01-19 | 2012-08-09 | Mitsubishi Electric Corp | Insulation gate type semiconductor device |
| WO2015029638A1 (en) * | 2013-08-30 | 2015-03-05 | 株式会社日立製作所 | Semiconductor device for power generation, method for manufacturing same, and solder therefor |
| JP2015050228A (en) * | 2013-08-30 | 2015-03-16 | 株式会社日立製作所 | Power semiconductor device, method of manufacturing the same, and solder therefor |
| WO2022220009A1 (en) * | 2021-04-12 | 2022-10-20 | ローム株式会社 | Semiconductor device |
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