JP2002196703A - Package structure of semiconductor elements and liquid crystal display device having the structure - Google Patents

Package structure of semiconductor elements and liquid crystal display device having the structure

Info

Publication number
JP2002196703A
JP2002196703A JP2000394189A JP2000394189A JP2002196703A JP 2002196703 A JP2002196703 A JP 2002196703A JP 2000394189 A JP2000394189 A JP 2000394189A JP 2000394189 A JP2000394189 A JP 2000394189A JP 2002196703 A JP2002196703 A JP 2002196703A
Authority
JP
Japan
Prior art keywords
conductive film
connection pad
semiconductor element
semiconductor
mounting structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000394189A
Other languages
Japanese (ja)
Inventor
Masanori Kasai
正礼 河西
Mitsuhiro Uno
光宏 宇野
Hikari Fujita
光 藤田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2000394189A priority Critical patent/JP2002196703A/en
Publication of JP2002196703A publication Critical patent/JP2002196703A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent a short circuit from occurring across a connection pad or leader wiring and a bump electrode of a semiconductor element in a COG package of a liquid crystal display device. SOLUTION: In a connection pad structure for a COG package, an upper layer conductive film 12 is made smaller than a lower layer conductive film 9 and made larger than an opening 11 of an insulating film 10 in shape, and thereby the insulating part is exposed to step parts 10a, 10b to be formed on the periphery of the lower layer conductive film 9.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体素子の実装
構造及びその構造の液晶表示装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounting structure and a liquid crystal display device having the structure.

【０００２】[0002]

【従来の技術】近年、液晶表示装置は各種コンピュータ
や携帯電話等の表示装置として様々な機器に多く利用さ
れている。また、機器の薄型化及び小型化に伴い、液晶
表示装置の狭額縁化が求められており、ＩＣやＬＳＩ等
の半導体素子の実装には様々な方法が用いられている。2. Description of the Related Art In recent years, liquid crystal display devices have been widely used in various devices as display devices for various computers and mobile phones. Further, as devices become thinner and smaller, there is a demand for narrower frames of liquid crystal display devices, and various methods are used for mounting semiconductor elements such as ICs and LSIs.

【０００３】その実装方法のうち代表的なものに、ガラ
ス基板上の電極に直接半導体素子を接続するチップオン
グラス（ＣＯＧ）実装がある。この実装方法はＴＡＢ
（TapeAutomated Bonding）よりも部品点数が少なくし
たり、微細ピッチの接続を行えたり、半導体素子を含む
基板全体の厚さを薄くできる等の利点を有する。なお、
ガラス基板の代わりにプラスチック製のフレキシブル基
板が用いられることもあり、これをＣＯＦ（chip on fl
exible）、ＣＯＰ（chip on plastic）と呼ぶことがあ
り、液晶パネルを駆動させる半導体素子は、駆動用ドラ
イバ（Driver IC、Driver LSI）と呼ばれる。A typical mounting method is chip-on-glass (COG) mounting in which a semiconductor element is directly connected to an electrode on a glass substrate. This mounting method is TAB
It has advantages over (Tape Automated Bonding) in that the number of components can be reduced, connections can be made at a fine pitch, and the thickness of the entire substrate including semiconductor elements can be reduced. In addition,
In some cases, a plastic flexible substrate is used instead of a glass substrate, and this is called COF (chip on fl
exible) and COP (chip on plastic), and a semiconductor element for driving a liquid crystal panel is called a driver IC (Driver IC, Driver LSI).

【０００４】導電性を有する接着剤としては、導電性接
着剤（導電性ペースト）に代わって異方性導電膜（ＡＣ
Ｆ）６が広く使用されるようになっている。ＣＯＧ実装
では、ＡＣＦ６と導電性接着剤が併存して使用されてお
り、回路基板一般への半導体素子の実装では、ＡＣＦ６
を用いた実装方法が多く使用されるようになっている
（特公昭６１−２７９０２号公報、特公昭６２−６６５
２号公報、特公平４−５４９３１号公報等参照）。異方
性導電膜（Anisotropic Conductive Film：ACF）６は、
絶縁性を有する接着剤中に導電性粒子が分散され厚み方
向（接続方向）に導電性を有し、面方向（横方向）に絶
縁性を有するもので、導電粒子と接着剤から構成され、
その接続は基本的には加熱圧着である。図３はＣＯＧ実
装の概略図を示す。基板１の実装パッド２を覆うように
ＡＣＦ６を貼り付け、突起電極４の施された半導体素子
５を装着して加熱圧着する。圧着することにより、ＡＣ
Ｆ６の導電粒子６ａを介して前記半導体素子５と実装パ
ッド２が導通することになる。As an adhesive having conductivity, an anisotropic conductive film (AC) is used instead of a conductive adhesive (conductive paste).
F) 6 has become widely used. In the COG mounting, the ACF6 and the conductive adhesive are used together, and in the mounting of the semiconductor element on a general circuit board, the ACF6 is used.
(Japanese Patent Publication No. 61-27902, Japanese Patent Publication No. 62-665)
No. 2, Japanese Patent Publication No. 4-54931, etc.). Anisotropic Conductive Film (ACF) 6
Conductive particles are dispersed in an adhesive having an insulating property, the conductive particles are conductive in a thickness direction (connection direction), and have an insulating property in a plane direction (lateral direction).
The connection is basically thermocompression bonding. FIG. 3 shows a schematic diagram of a COG implementation. The ACF 6 is attached so as to cover the mounting pad 2 of the substrate 1, and the semiconductor element 5 provided with the protruding electrode 4 is attached and heat-pressed. By crimping, AC
The semiconductor element 5 and the mounting pad 2 are electrically connected via the conductive particles 6a of F6.

【０００５】図４は、従来の液晶表示装置の基板におけ
る半導体素子５の接続部の配置構成図であり、図５は、
図４におけるA−A’間の断面図である。ＣＯＧにおいて
半導体素子５の突起電極（バンプ）４が接続される接続
パッド２は、複数配列され、各接続パッド２は、積層膜
構造である。つまり、ガラス基板７上に絶縁膜８が形成
されて、この絶縁膜８上に下層導電膜９がアルミニウム
にて形成されている。前記下層導電膜９上に開口部１１
を有する絶縁膜１０を形成し、さらに絶縁膜１０及び開
口部１１を覆うように上層導電膜１２がＩＴＯ（Indium
Tin Oxide）として形成され、開口部１１を介して上層
導電膜１２と下層導電膜９が導通する。また、上層導電
膜１２は下層導電膜９周辺の絶縁膜の段差部１０ｃを覆
うように形成されている。したがって、半導体素子５の
突起電極４は、上層導電膜１２の開口部１１にあたる部
分にＡＣＦ６の導電粒子６ａを介して圧着されるように
なっている。FIG. 4 is a diagram showing an arrangement of connection portions of semiconductor elements 5 on a substrate of a conventional liquid crystal display device, and FIG.
FIG. 5 is a cross-sectional view along AA ′ in FIG. 4. In the COG, a plurality of connection pads 2 to which the protruding electrodes (bumps) 4 of the semiconductor element 5 are connected are arranged, and each connection pad 2 has a laminated film structure. That is, the insulating film 8 is formed on the glass substrate 7, and the lower conductive film 9 is formed of aluminum on the insulating film 8. An opening 11 is formed on the lower conductive film 9.
Is formed, and an upper conductive film 12 is formed of ITO (Indium) so as to cover the insulating film 10 and the opening 11.
The upper conductive film 12 and the lower conductive film 9 conduct through the opening 11. The upper conductive film 12 is formed so as to cover the step 10 c of the insulating film around the lower conductive film 9. Therefore, the protruding electrode 4 of the semiconductor element 5 is pressure-bonded to the portion corresponding to the opening 11 of the upper conductive film 12 via the conductive particles 6 a of the ACF 6.

【０００６】なお、ＣＯＧ実装等により半導体素子を実
装する前に液晶パネル内を検査するための共通検査配線
１３への引き出し配線として、前記接続パッド２の上層
導電膜１２を伸ばして引き出し配線１４が形成されてい
る（図４）。引き出し配線１４は、液晶パネル内の検査
の後にレーザーカット法等によりカットされ、共通検査
配線１３と接続パッド２の導通が切り離される。そのた
め、引き出し配線１４の上部には絶縁膜１０がなく、導
電膜が露出している。[0006] As a lead-out line to a common inspection line 13 for inspecting the inside of the liquid crystal panel before mounting the semiconductor element by COG mounting or the like, the lead-out line 14 is formed by extending the upper conductive film 12 of the connection pad 2. (FIG. 4). The lead wiring 14 is cut by a laser cutting method or the like after the inspection inside the liquid crystal panel, and the conduction between the common inspection wiring 13 and the connection pad 2 is cut off. Therefore, there is no insulating film 10 above the lead wiring 14, and the conductive film is exposed.

【０００７】[0007]

【発明が解決しようとする課題】しかしながら、従来の
半導体素子の実装において、図６（ａ）および図６
（ｂ）に示すように、半導体素子５の突起電極４が開口
部１１からずれて圧着された場合、突起電極４と本来実
装されるべき接続パッド２の隣の接続パッド２が導電粒
子６ａを介してショートする危険性を有していた（図中
符号Ｄ−Ｄ’部）。このような問題は、突起電極４が正
常に実装された場合でも、ＡＣＦ６の導電粒子６ａが偶
然に多数連なった場合に発生し得る問題でもある。However, in the conventional mounting of a semiconductor device, the semiconductor device shown in FIG.
As shown in (b), when the protruding electrode 4 of the semiconductor element 5 is pressed and shifted from the opening 11, the connection pad 2 adjacent to the protruding electrode 4 and the connection pad 2 to be originally mounted has the conductive particles 6 a. There was a danger of short-circuiting through the wire (the part DD ′ in the figure). Such a problem is a problem that can occur when the conductive particles 6a of the ACF 6 are accidentally formed in a large number even when the bump electrodes 4 are normally mounted.

【０００８】また、図６（ａ）及び図６（ｃ）に示すよ
うに、突起電極４が開口部１１からずれて圧着された場
合、本来実装されるべき接続パッド２に近接する接続パ
ッド２から引き出された引き出し配線１４と突起電極４
が導電粒子６ａを介してショートする危険性も有してい
た（図中符号Ｅ−Ｅ’部）。このような問題は、接続パ
ッド２がいわゆる千鳥構成の配置となっている場合にお
いて特に問題となる。また、突起電極４が正常に実装さ
れた場合でも、ＡＣＦ６の導電粒子６ａが偶然に多数連
なった場合に発生しうる問題でもある。そして、半導体
素子５の小型化の要請から、突起電極４や接続パッド２
の間隔は更に一層狭くなることが予想され（接続パッド
のファインピッチ化）、これらのショートの問題は避け
られない問題である。As shown in FIGS. 6 (a) and 6 (c), when the protruding electrode 4 is pressed and shifted from the opening 11, the connection pad 2 which is close to the connection pad 2 to be actually mounted is provided. Wiring 14 and protruding electrode 4 extracted from
Also had the danger of short-circuiting via the conductive particles 6a (reference EE 'in the figure). Such a problem is particularly problematic when the connection pads 2 are arranged in a staggered configuration. Further, even when the bump electrode 4 is normally mounted, there is a problem that can occur when a large number of conductive particles 6a of the ACF 6 are accidentally connected. In response to a demand for miniaturization of the semiconductor element 5, the projection electrode 4 and the connection pad 2
Is expected to be even narrower (fine pitch of connection pads), and these short-circuit problems are inevitable problems.

【０００９】そこで、本発明の目的は、半導体素子の突
起電極が半導体素子実装用の基板の対応する接続パッド
からずれた場合やＡＣＦの導電粒子が偶然連なった場合
のように導電性を有する接着剤により導通が生じてもシ
ョートさせることなく安定的に実装することが可能な実
装構造及びその構造を有する液晶表示装置を提供するこ
とにある。Accordingly, an object of the present invention is to provide a conductive adhesive such as a case where a protruding electrode of a semiconductor element is shifted from a corresponding connection pad of a substrate for mounting a semiconductor element or a case where conductive particles of ACF are accidentally connected. It is an object of the present invention to provide a mounting structure capable of stably mounting without causing a short circuit even when conduction occurs due to an agent, and a liquid crystal display device having the structure.

【００１０】[0010]

【課題を解決するための手段】本発明の請求項１記載の
半導体素子の実装構造は、接続パッドが形成された半導
体実装用の基板に、導電性を有する接着剤を介して、突
起電極を有する半導体素子が実装される半導体素子の実
装構造において、上記接続パッドは、導電性を有する接
着剤を介して上記対応する半導体素子の突起電極が接続
されるべき接続パッド以外の接続パッドとの導通を防止
するための絶縁部分が少なくとも設けられていることを
特徴とする。According to a first aspect of the present invention, there is provided a mounting structure of a semiconductor device, wherein a protruding electrode is provided on a semiconductor mounting substrate on which connection pads are formed, via a conductive adhesive. In the mounting structure of the semiconductor element on which the semiconductor element is mounted, the connection pad is electrically connected to a connection pad other than the connection pad to which the projection electrode of the corresponding semiconductor element is to be connected via a conductive adhesive. Characterized in that at least an insulating portion is provided for preventing the occurrence of an electric current.

【００１１】この発明によれば、接続パッドに絶縁部分
が設けられていることから、半導体素子の突起電極が接
続パッドからずれた場合やＡＣＦの導電粒子が偶然連な
った場合のように導電性を有する接着剤により導通が生
じても突起電極と本来実装されるべき接続パッドの隣の
接続パッドが導電粒子を介してショートするおそれがな
くなる。According to the present invention, since the insulating portion is provided on the connection pad, the conductivity is improved as in the case where the protruding electrode of the semiconductor element is displaced from the connection pad or the case where the conductive particles of the ACF are accidentally connected. Even if conduction occurs due to the adhesive, there is no danger that the protruding electrode and the connection pad adjacent to the connection pad to be mounted are short-circuited through the conductive particles.

【００１２】本発明の請求項２記載の半導体素子の実装
構造は、接続パッドが形成された半導体実装用の基板
に、導電性を有する接着剤を介して、突起電極を有する
半導体素子が実装されるとともに、接続パッドから検査
用の引き出し配線が引き出された半導体素子の実装構造
において、上記接続パッドに、導電性を有する接着剤を
介して上記引き出し配線との導通を防止するための絶縁
部分が少なくとも設けられていることを特徴とする。In the semiconductor device mounting structure according to a second aspect of the present invention, a semiconductor element having a projecting electrode is mounted on a semiconductor mounting substrate on which connection pads are formed, via a conductive adhesive. In addition, in the mounting structure of the semiconductor element from which the lead-out wiring for inspection is drawn out from the connection pad, the connection pad has an insulating portion for preventing conduction with the lead-out wiring via a conductive adhesive. It is characterized by being provided at least.

【００１３】この発明によれば、接続パッドに絶縁部分
が設けられていることから、ＡＣＦの導電粒子が連なっ
た場合や半導体素子の突起電極がずれた場合でも、突起
電極と液晶パネルの検査用の引き出し配線が導電粒子を
介してショートするおそれがなくなる。According to the present invention, since the connecting pad is provided with the insulating portion, even when the conductive particles of the ACF are continuous or the projecting electrode of the semiconductor element is displaced, the projecting electrode and the liquid crystal panel are inspected. There is no danger that the lead-out wiring of this will short-circuit through the conductive particles.

【００１４】本発明の請求項３記載の半導体素子の実装
構造は、前記接続パッドは、基板上に形成した下層導電
膜を覆うようにかつ下層導電膜の***部に下層導電膜
より小さい形状の開口部を有するように絶縁膜を形成
し、その上部に開口部より大きくかつ下層導電膜より小
さい形状の上層導電膜を形成し、絶縁膜の開口部を介し
て上層導電膜と下層導電膜を導通させる構造をとること
により、下層導電膜の外周辺縁に絶縁膜を段差状に設け
たことを特徴とする。4. The mounting structure of a semiconductor device according to claim 3, wherein the connection pad has a shape smaller than the lower conductive film so as to cover the lower conductive film formed on the substrate and at an upper central portion of the lower conductive film. An insulating film is formed so as to have an opening, and an upper conductive film having a shape larger than the opening and smaller than the lower conductive film is formed thereon, and the upper conductive film and the lower conductive film are formed through the opening of the insulating film. The structure is characterized in that an insulating film is provided in a stepped shape on the outer peripheral edge of the lower conductive film by adopting a structure for conducting.

【００１５】この発明によれば、下層導電膜の外周辺縁
に生じる絶縁膜の段差部に絶縁膜のみを露出させるに際
して、開口部より大きくかつ下層導電膜より小さい形状
の上層導電膜を形成することにより、従来の積層膜構造
の接続パッドと同じように容易に形成することができ
る。According to the present invention, when only the insulating film is exposed at the step portion of the insulating film formed on the outer peripheral edge of the lower conductive film, the upper conductive film having a shape larger than the opening and smaller than the lower conductive film is formed. Thereby, it can be easily formed in the same manner as the connection pad of the conventional laminated film structure.

【００１６】本発明の請求項４記載の半導体素子の実装
構造は、請求項１乃至請求項３記載の発明において、前
記接続パッドが複数列で構成されるとともに互いの列を
ずらして千鳥配置となっていることを特徴とする。According to a fourth aspect of the present invention, there is provided the semiconductor device mounting structure according to the first to third aspects, wherein the connection pads are formed in a plurality of rows and the rows are shifted from each other in a staggered arrangement. It is characterized by becoming.

【００１７】この発明によれば、接続パッドを千鳥配置
とした場合でも、ＡＣＦの導電粒子が連なったり半導体
素子の突起電極がずれたりしても突起電極と接続パッド
もしくは引き出し配線が導電粒子を介してショートしな
いため、接続パッドのファインピッチ化に対応すること
ができる。According to the present invention, even when the connection pads are arranged in a staggered manner, even if the conductive particles of the ACF are continuous or the protrusion electrodes of the semiconductor element are displaced, the protrusion electrodes and the connection pads or the lead-out lines are connected via the conductive particles. Therefore, it is possible to cope with the fine pitch of the connection pads.

【００１８】本発明の請求項５記載の半導体素子の実装
構造は、接続パッドが形成された半導体実装用の基板
に、導電性を有する接着剤を介して、突起電極を有する
半導体素子が実装されるとともに、接続パッドから検査
用の引き出し配線が引き出された半導体素子の実装構造
において、上記引き出し配線に導電性を有する接着剤を
介して上記接続パッドとの導通を防止するための絶縁部
分が少なくとも設けられていることを特徴とする。In the semiconductor device mounting structure according to a fifth aspect of the present invention, a semiconductor element having a protruding electrode is mounted on a semiconductor mounting substrate on which connection pads are formed, via a conductive adhesive. In addition, in the mounting structure of the semiconductor element from which the lead wire for inspection is led out from the connection pad, at least an insulating portion for preventing conduction with the connection pad via a conductive adhesive is provided on the lead wire. It is characterized by being provided.

【００１９】この発明によれば、引き出し配線に絶縁部
分が設けられていることから、ＡＣＦの導電粒子が連な
った場合や半導体素子の突起電極がずれた場合でも、突
起電極と検査用の引き出し配線が導電粒子を介してショ
ートするおそれがなくなる。According to the present invention, since the insulating portion is provided in the lead-out wiring, even when the conductive particles of the ACF are continuous or the protrusion electrode of the semiconductor element is displaced, the protrusion electrode and the lead-out wiring for inspection are displaced. Can be short-circuited via conductive particles.

【００２０】本発明の請求項６記載の半導体素子の実装
構造は、前記接続パッドは少なくとも上層導電膜と下層
導電膜及びそれらの間の絶縁膜からなっており、前記引
き出し配線は接続パッドの下層導電膜から引き出される
とともに、接続パッドの絶縁膜で覆われていることを特
徴とする。According to a sixth aspect of the present invention, in the mounting structure of the semiconductor device, the connection pad includes at least an upper conductive film, a lower conductive film, and an insulating film therebetween. It is characterized by being drawn out of the conductive film and covered with an insulating film of the connection pad.

【００２１】この発明によれば、引き出し配線は接続パ
ッドの下層導電膜と同じ層で形成され、かつその上に絶
縁膜が形成されることにより、ＡＣＦの導電粒子が連な
った場合や半導体素子の突起電極がずれた場合でも、突
起電極と検査用の引き出し配線が導電粒子を介してショ
ートするおそれがなくなる。また、下層導電膜形成時と
同時に引き出し配線を形成できるため、従来の積層膜構
造の接続パッドと同じように容易に形成することができ
る。According to the present invention, the lead-out wiring is formed of the same layer as the lower conductive film of the connection pad, and the insulating film is formed thereon. Even when the protruding electrode is displaced, there is no possibility that the protruding electrode and the lead wire for inspection are short-circuited via the conductive particles. Further, since the lead-out wiring can be formed at the same time as the formation of the lower conductive film, it can be easily formed in the same manner as the connection pad of the conventional laminated film structure.

【００２２】本発明の請求項７記載の液晶表示装置は、
前記請求項１乃至請求項４記載の半導体素子の実装構造
を使用するものであって、配線パターンが形成された半
導体実装用の基板は、対向する基板間に液晶が狭持され
た液晶パネルの一方の基板と一体とされた基板であるこ
とを特徴とする。According to a seventh aspect of the present invention, there is provided a liquid crystal display device comprising:
5. The semiconductor device mounting structure according to claim 1, wherein the substrate for mounting a semiconductor on which a wiring pattern is formed is a liquid crystal panel having a liquid crystal sandwiched between opposing substrates. It is a substrate integrated with one substrate.

【００２３】この発明によれば、ＣＯＧ実装における半
導体素子実装の際にＡＣＦの導電粒子が連なった場合や
半導体素子の突起電極がずれた場合でも、突起電極と本
来実装されるべき接続パッドの隣の接続パッドもしくは
引き出し配線が導電粒子を介してショートする危険性が
なくなるため、電気的接続の信頼性の高い液晶表示装置
を提供することができる。According to the present invention, even when the conductive particles of the ACF are connected during the mounting of the semiconductor element in the COG mounting, or when the protruding electrode of the semiconductor element is displaced, the protruding electrode and the connection pad to be originally mounted are adjacent to each other. There is no danger of short-circuiting of the connection pad or the lead-out line through the conductive particles, and a liquid crystal display device with high electrical connection reliability can be provided.

【００２４】[0024]

【発明の実施の形態】（第一の実施の形態）以下、本発
明の実施の形態を、図面を引用しながら説明する。本実
施の形態における半導体素子の実装構造は、本発明をＣ
ＯＧ実装に適用したものである。すなわち本発明の実施
の形態は、図３に示すように、現在使用されている代表
的なアクティブ素子であるＴＦＴを用いた反射型の液晶
パネル３において、液晶パネル３周縁部の実装領域に半
導体素子５を実装するものである。液晶パネル３の第一
の基板（一方の基板：ＡＭ基板）１は、他方の基板１３
よりも大きく、このため両基板１，１３を重ね合わせる
と、ＡＭ基板１の周辺に一部張り出した半導体素子５の
実装領域が形成されている。この第一の基板１の実装領
域には、半導体実装用の接続パッドが形成されている。
なお、ＡＭ基板１としてはガラス基板の他、合成樹脂製
のフレキシブル基板でも良い。DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) An embodiment of the present invention will be described below with reference to the drawings. The mounting structure of the semiconductor element according to the present embodiment
This is applied to OG mounting. That is, according to the embodiment of the present invention, as shown in FIG. 3, in a reflection type liquid crystal panel 3 using a TFT which is a typical active element currently used, a semiconductor region is provided in a mounting region at a peripheral portion of the liquid crystal panel 3. The element 5 is mounted. The first substrate (one substrate: AM substrate) 1 of the liquid crystal panel 3 is
Therefore, when the two substrates 1 and 13 are overlapped with each other, a mounting region of the semiconductor element 5 which partially protrudes around the AM substrate 1 is formed. Connection pads for semiconductor mounting are formed in the mounting area of the first substrate 1.
The AM substrate 1 may be a flexible substrate made of a synthetic resin other than a glass substrate.

【００２５】図１は、本発明におけるＣＯＧ接続パッド
の構成図である。図２は接続パッドの断面図であり、そ
れぞれ（ａ）は図１におけるＡ−Ａ’断面図、（ｂ）は
Ｂ−Ｂ’断面図、（ｃ）はＣ−Ｃ’断面図である。接続
パッド２はいわゆる千鳥配置に配されている。各接続パ
ッド２からは検査用の引き出し配線１４が引き出され、
検査接続配線コンタクト１６と検査接続配線１５とを介
して共通検査配線１３に接続されている。共通検査配線
１３は半導体素子５の実装前に液晶パネル３の内部を検
査するための配線である。FIG. 1 is a configuration diagram of a COG connection pad according to the present invention. 2A and 2B are cross-sectional views of the connection pad. FIG. 2A is a cross-sectional view along AA ′ in FIG. 1, FIG. 2B is a cross-sectional view along BB ′, and FIG. 2C is a cross-sectional view along CC ′. The connection pads 2 are arranged in a so-called staggered arrangement. From each connection pad 2, a lead wire 14 for inspection is led out,
It is connected to the common test wiring 13 via the test connection wiring contact 16 and the test connection wiring 15. The common inspection wiring 13 is a wiring for inspecting the inside of the liquid crystal panel 3 before mounting the semiconductor element 5.

【００２６】積層膜の構造や膜形成方法は従来例と同じ
く一般的なものであるが、本実施の形態の接続パッド２
はその形状に特徴があり、上層導電膜１２を形成すると
きに、開口部１１を覆うように開口部１１より大きくか
つ下層導電膜９より小さい形状にて形成されている。こ
れにより、絶縁膜１０は下層導電膜９の形状に沿って段
差部１０ａ，１０ｂが生じる。一方、上層導電膜１２は
下層導電膜９より小さい形状であるため、段差部１０
ａ，１０ｂに上層導電膜１２は存在せず、絶縁膜１０が
露出するようになる。この露出した絶縁部分１０ａ，１
０ｂは、本来突起電極４が接続されるべき接続パッド２
以外の接続パッド２との導通を防止するもので、図１０
に示す成膜手順で形成される。Although the structure of the laminated film and the method of forming the film are the same as in the conventional example, the connection pad 2 of the present embodiment is used.
Is formed in a shape larger than the opening 11 and smaller than the lower conductive film 9 so as to cover the opening 11 when the upper conductive film 12 is formed. Thereby, steps 10 a and 10 b are formed in the insulating film 10 along the shape of the lower conductive film 9. On the other hand, since the upper conductive film 12 is smaller in shape than the lower conductive film 9,
The upper conductive film 12 does not exist in the layers 10a and 10b, and the insulating film 10 is exposed. The exposed insulating parts 10a, 1
0b is the connection pad 2 to which the protruding electrode 4 is to be connected.
10 to prevent conduction with connection pads 2 other than the one shown in FIG.
Is formed by the film forming procedure shown in FIG.

【００２７】まず、図１０（ａ）のようにガラス基板７
上に酸化シリコン等による絶縁膜８を形成し、図１０
（ｂ）のように絶縁膜８の上に下層導電膜９をアルミニ
ウムにて形成する。次に図１０（ｃ）のように下層導電
膜９を覆うように絶縁膜１０を酸化シリコンや窒化シリ
コン等にて形成し、フォトリソグラフィー等により図１
０（ｄ）のように開口部１１を開ける。次に図１０
（ｅ）のように絶縁膜１０の上に開口部１１より大きく
かつ下層導電膜９より小さい形状の上層導電膜１２とし
てＩＴＯを蒸着法およびエッチングで形成し、開口部１
１を介して上層導電膜１２と下層導電膜９が導通され
る。なお、下層導電膜９は、アルミニウムの他、アルミ
ニウム合金、高融点導電膜とアルミニウムとの積層膜
（例えば、Ｔｉ／Ａｌ／Ｔｉ積層膜）、Ｔａ，Ｃｒ等で
あってもよい。First, as shown in FIG.
An insulating film 8 made of silicon oxide or the like is formed thereon, and FIG.
A lower conductive film 9 is formed of aluminum on the insulating film 8 as shown in FIG. Next, as shown in FIG. 10C, an insulating film 10 is formed of silicon oxide, silicon nitride, or the like so as to cover the lower conductive film 9, and FIG.
The opening 11 is opened as shown in FIG. Next, FIG.
As shown in (e), ITO is formed on the insulating film 10 as an upper conductive film 12 having a shape larger than the opening 11 and smaller than the lower conductive film 9 by vapor deposition and etching.
1, the upper conductive film 12 and the lower conductive film 9 are conducted. The lower conductive film 9 may be an aluminum alloy, a laminated film of a high melting point conductive film and aluminum (for example, a Ti / Al / Ti laminated film), Ta, Cr, or the like, in addition to aluminum.

【００２８】また、液晶パネル内を検査するための共通
検査配線１３への引き出し配線として、前記接続パッド
２の下層導電膜９を形成する際、同時に下層導電膜９と
同じ導電膜にて引き出し配線１４を形成する。引き出し
配線１４と共通検査配線１３の間に検査接続配線コンタ
クト１６を設けて、下層導電膜９と同じ膜位置にある引
き出し配線１４を上層導電膜１２と同じ膜位置にある検
査接続配線１５とを接続させる。その結果、引き出し配
線１４は、下層導電膜９を延長させたものであり、その
上部を絶縁膜１０が覆うようになっている。液晶パネル
内の検査後には、レーザーカット法等により検査接続配
線１５をカットし、共通検査配線１３と接続パッド２の
導通を切り離す。検査接続配線１５をＩＴＯで形成する
と、上層導電膜１２と同時に成膜することができる。ま
たその場合には、アルミニウム等で形成した場合に比べ
てカット時に破片の飛び散りが少ないため、破片による
不良を防ぐことができる。When forming the lower conductive film 9 of the connection pad 2 as a lead wiring to the common test wiring 13 for inspecting the inside of the liquid crystal panel, the lead wiring is formed by the same conductive film as the lower conductive film 9 at the same time. 14 is formed. An inspection connection wiring contact 16 is provided between the extraction wiring 14 and the common inspection wiring 13 so that the extraction wiring 14 at the same film position as the lower conductive film 9 is connected to the inspection connection wiring 15 at the same film position as the upper conductive film 12. Connect. As a result, the lead wiring 14 is an extension of the lower conductive film 9, and the upper part thereof is covered with the insulating film 10. After the inspection inside the liquid crystal panel, the inspection connection wiring 15 is cut by a laser cutting method or the like, and the conduction between the common inspection wiring 13 and the connection pad 2 is cut off. When the inspection connection wiring 15 is formed of ITO, it can be formed simultaneously with the upper conductive film 12. Further, in this case, the fragments are less likely to scatter during cutting than when formed of aluminum or the like, so that defects due to the fragments can be prevented.

【００２９】第一の実施の形態における各部分の大きさ
の例を図９に示す。開口部１１は一辺が４６μmの正方
形、半導体素子の突起電極４は一辺が５０μmの正方
形、引き出し配線１４の幅は６μmである。そして、半
導体素子の突起電極４と隣接する接続パッドの上層導電
膜１２との距離Ｈ１は２１μm、開口部１１と上層導電
膜１２の距離Ｈ２は５μm、開口部１１と下層導電膜９
の距離Ｈ３は８μmである。なお、パッドの開口部１１
は半導体素子の突起電極４より小さくても大きくても良
い。FIG. 9 shows an example of the size of each part in the first embodiment. The opening 11 is a square having a side of 46 μm, the protruding electrode 4 of the semiconductor element is a square having a side of 50 μm, and the width of the lead wiring 14 is 6 μm. The distance H1 between the projecting electrode 4 of the semiconductor element and the upper conductive film 12 of the connection pad adjacent thereto is 21 μm, the distance H2 between the opening 11 and the upper conductive film 12 is 5 μm, and the opening 11 and the lower conductive film 9
Is 8 μm. The opening 11 of the pad
May be smaller or larger than the protruding electrode 4 of the semiconductor element.

【００３０】次に、第一の基板１にＡＣＦ６を用いて半
導体素子５をＣＯＧ実装する場合の手順を説明する。半
導体素子５は、図１に示すように、実装領域に配される
接続パッド２にＡＣＦ６を介して実装される。まず、第
一の基板１の下に圧着ステージを配し、基板上の実装領
域にＡＣＦ６を貼り付け、装着機で半導体素子５を所定
の位置にあわせ、半導体素子５の上方から加熱及び加圧
して接着する。すると図２（ａ）に示すように、接続パ
ッド部分と半導体素子の突起電極４がＡＣＦの導電粒子
６ａを介して導通される。Next, a procedure for COG mounting the semiconductor element 5 on the first substrate 1 using the ACF 6 will be described. As shown in FIG. 1, the semiconductor element 5 is mounted on the connection pad 2 arranged in the mounting area via the ACF 6. First, a crimping stage is arranged under the first substrate 1, an ACF 6 is attached to a mounting area on the substrate, the semiconductor device 5 is adjusted to a predetermined position by a mounting machine, and heating and pressing are performed from above the semiconductor device 5. And glue. Then, as shown in FIG. 2A, the connection pad portion and the protruding electrode 4 of the semiconductor element are electrically connected via the conductive particles 6a of the ACF.

【００３１】ところが図１Ｂ−Ｂ’部及びＣ−Ｃ’部に
示すように、突起電極４が接続パッド２からずれて接着
されることもある。しかし本実施の形態の接続パッド２
であれば、図２（ｂ）に示すように接続パッド２からは
み出た突起電極４と隣接する接続パッド２の間に導電粒
子６ａが連なった場合でも段差部１０ａ，１０ｂに絶縁
膜１０があるため、隣接する接続パッド２に導電粒子６
ａを介してショートすることがない。また、図２（ｃ）
に示すように接続パッド２からはみ出た突起電極４と隣
接する引き出し配線１４の間に導電粒子６ａが偶然に連
なった場合でも、引き出し配線１４の上部に絶縁膜１０
が形成されているため、引き出し配線１４とショートす
ることがない。さらに、突起電極４が正常に実装された
場合において、接続パッド２と隣接する接続パッド２も
しくは引き出し配線１４との間に導電粒子６ａが偶然に
連なった場合でも、導電粒子６ａを介してショートする
ことがない。However, as shown in FIGS. 1B-B 'and C-C', the protruding electrode 4 may be displaced from the connection pad 2 and adhered. However, the connection pad 2 of the present embodiment
Then, as shown in FIG. 2B, even when the conductive particles 6a continue between the protruding electrode 4 protruding from the connection pad 2 and the adjacent connection pad 2, the insulating film 10 is present at the steps 10a and 10b. Therefore, the conductive particles 6
There is no short circuit through a. FIG. 2 (c)
As shown in FIG. 3, even when the conductive particles 6a are accidentally connected between the protruding electrode 4 protruding from the connection pad 2 and the adjacent lead wire 14, the insulating film 10
Is formed, there is no short circuit with the lead wiring 14. Furthermore, when the bump electrode 4 is normally mounted, even if the conductive particles 6a are accidentally connected between the connection pad 2 and the adjacent connection pad 2 or the lead-out wiring 14, a short circuit occurs via the conductive particles 6a. Nothing.

【００３２】また、上層導電膜１２形成時において、エ
ッチングのためのフォトレジストが下層導電膜９の段差
部分で厚くなり、露光されにくくなる（アンダー露光）
ため、フォトレジストが不要に残り、エッチング後に不
要なＩＴＯが絶縁膜１０上に残ることがある。その場合
においても、絶縁膜の段差部１０ａ，１０ｂにより、上
層導電膜１２とは絶縁され、かつ、下層導電膜９とも絶
縁膜１０により絶縁されているため、接続パッド２から
はみ出た突起電極４と隣接する接続パッド２の間に導電
粒子６ａが連なった場合でも、正常に実装された接続パ
ッド２に隣接する接続パッド２もしくは引き出し配線１
４との間に導電粒子６ａが偶然に連なった場合でも、導
電粒子６ａを介してショートすることがない。Further, when the upper conductive film 12 is formed, the photoresist for etching becomes thick at the step portion of the lower conductive film 9 and is hardly exposed (under exposure).
Therefore, the photoresist remains unnecessarily, and unnecessary ITO may remain on the insulating film 10 after the etching. Also in this case, since the step portions 10a and 10b of the insulating film are insulated from the upper conductive film 12 and are also insulated from the lower conductive film 9 by the insulating film 10, the projecting electrode 4 protruding from the connection pad 2 is formed. Even if the conductive particles 6a continue between the connection pads 2 adjacent to the connection pad 2, the connection pad 2 adjacent to the normally mounted connection pad 2 or the lead wiring 1
Even when the conductive particles 6a are accidentally connected between the conductive particles 6 and 4, the short-circuit does not occur via the conductive particles 6a.

【００３３】基板に半導体素子をＣＯＧにて実装する場
合、最近は突起電極や接続パッドのファインピッチ化に
対応するため、導電性接着剤としてＡＣＦ（異方性導電
膜）を使用することが多い。ＡＣＦ６は絶縁性を有する
接着剤中に導電粒子６ａが分散され、厚み方向（接続方
向）に導電性を有し、面方向（水平方向）に絶縁性を有
するもので、導電粒子６ａと接着剤から構成される。そ
の接続は基本的には加熱圧着であり、導電粒子６ａが電
気接続の機能を担当し、接着剤が圧接状態を保持する機
能を担当する。When a semiconductor element is mounted on a substrate by COG, recently, an ACF (anisotropic conductive film) is often used as a conductive adhesive in order to cope with a fine pitch of bump electrodes and connection pads. . The ACF 6 has conductive particles 6a dispersed in an insulating adhesive, has conductivity in the thickness direction (connection direction), and has insulation in the plane direction (horizontal direction). Consists of The connection is basically thermocompression bonding, in which the conductive particles 6a are responsible for the function of electrical connection, and the adhesive is responsible for the function of maintaining the pressed state.

【００３４】導電粒子６ａは、導電性粒子の表面に絶縁
性薄膜樹脂をコートしたもので、絶縁性薄膜樹脂は、Ａ
ＣＦの保護シートとしての役割を有するとともに、接続
方向では圧着力で破壊され下層の金属薄膜と電極が接触
して導通し、横方向では破壊されず導電性粒子６同士が
接触しても絶縁性が保たれるようになっている。すなわ
ち、ＡＣＦは、接着部に貼り付ける前は両面テープのよ
うな構成で供給され、接着部に接着剤層側を貼り付けた
後、セパレータを剥がし接着剤層を露出させ、その後半
導体素子を実装（加熱加圧）し、接着剤を硬化させ、本
来の接着力を得る。絶縁性薄膜樹脂としては、テフロン
（登録商標）やＰＥＴ（poly-ethylene terephtalatere
sin）が使用されている。接着剤としては、熱可塑性樹
脂の他に熱硬化性樹脂も使用されている。なお、導電性
粒子６には、高分子球の表面に金属薄膜をメッキしたも
のもある。The conductive particles 6a are obtained by coating the surface of conductive particles with an insulating thin-film resin.
In addition to having a role as a protective sheet for CF, it is broken by crimping force in the connection direction and is brought into contact with the underlying metal thin film to conduct electricity, and is not broken in the lateral direction and is insulative even when the conductive particles 6 contact each other. Is kept. That is, the ACF is supplied in the form of a double-sided tape before being attached to the adhesive portion, and after the adhesive layer side is attached to the adhesive portion, the separator is peeled off to expose the adhesive layer, and then the semiconductor element is mounted. (Heating and pressurizing) to cure the adhesive to obtain the original adhesive strength. Examples of the insulating thin film resin include Teflon (registered trademark) and PET (poly-ethylene terephtalatere).
sin) is used. As the adhesive, a thermosetting resin is used in addition to the thermoplastic resin. Some of the conductive particles 6 are obtained by plating a metal thin film on the surface of a polymer sphere.

【００３５】（第二の実施の形態）本実施の形態は、い
わゆる千鳥配置の接続パッドにおいて、隣接パッド２又
は引き出し配線１４の互いに近接する部分のみに前記の
露出した絶縁部分１０ａ，１０ｂを形成したものであ
る。互いに近接した部分が、最もショートする可能性が
高いからである。以下、具体的に図面を引用しながら説
明する。図７は、本実施の形態における接続パッドの配
置構成図であり、図７のＦ−Ｆ’における断面斜視図を
図８に示す。ガラス基板７上に酸化シリコン等による絶
縁膜８が形成されて、絶縁膜８の上に下層導電膜９がア
ルミニウムやアルミニウム合金等にて形成される。次に
下層導電膜９を覆うように絶縁膜１０を酸化シリコンや
窒化シリコン等にて形成し、フォトリソグラフィー等に
より開口部１１を開ける。以上の工程は第一の実施の形
態にて説明したものと同様のものである。さらに絶縁膜
１０の上に開口部１１を覆うように上層導電膜１２とし
てＩＴＯを蒸着法にて形成するが、その外周形状は、近
接する接続パッド２もしくは引き出し配線１４に近い部
分（図中符号９ａ）においては下層導電膜９より内側
（開口部寄り）に、その他の部分（図中符号１２ａ）に
おいては下層導電膜９より外側、つまり従来の形状とな
るように形成する。すると、上記１２ａ部には絶縁膜１
０が露出せず、上記１２ａ部以外の上層導電膜外周部に
は絶縁膜１０の段差部１０ａ，１０ｂが存在する。(Second Embodiment) In the present embodiment, the exposed insulating portions 10a and 10b are formed only in the portions of the connection pads in a so-called staggered arrangement that are adjacent to each other in the adjacent pad 2 or the lead-out wiring 14. It was done. This is because portions that are close to each other are most likely to be short-circuited. Hereinafter, a specific description will be given with reference to the drawings. FIG. 7 is a layout diagram of connection pads in the present embodiment, and FIG. 8 is a cross-sectional perspective view taken along line FF ′ of FIG. An insulating film 8 made of silicon oxide or the like is formed on a glass substrate 7, and a lower conductive film 9 is formed on the insulating film 8 using aluminum, an aluminum alloy, or the like. Next, an insulating film 10 is formed of silicon oxide, silicon nitride, or the like so as to cover the lower conductive film 9, and an opening 11 is opened by photolithography or the like. The above steps are the same as those described in the first embodiment. Further, ITO is formed as an upper conductive film 12 on the insulating film 10 as an upper conductive film 12 by an evaporation method so as to cover the opening 11, and its outer peripheral shape is a portion close to the adjacent connection pad 2 or the lead-out wiring 14 (reference numeral in the drawing). 9a), it is formed inside the lower conductive film 9 (closer to the opening), and in other portions (reference numeral 12a in the figure) outside the lower conductive film 9, that is, it is formed to have a conventional shape. Then, the insulating film 1 is formed in the portion 12a.
0 is not exposed, and steps 10a and 10b of the insulating film 10 exist in the outer peripheral portion of the upper conductive film other than the portion 12a.

【００３６】また、上記１２ａ部以外の部分について、
第一の実施の形態に示した数値にて作成すれば、半導体
素子５の突起電極４が半導体素子実装用の基板の対応す
る接続パッド２からずれた場合やＡＣＦ６の導電粒子６
ａが連なった場合でも確実に不要なショートを防ぐこと
ができる。また、第一の実施の形態と同様に、上層導電
膜１２形成時において不要なＩＴＯが残った場合でも、
絶縁膜の段差部１０ａ，１０ｂにより、確実に不要なシ
ョートを防ぐことができる。Further, for portions other than the 12a portion,
If it is created by the numerical values shown in the first embodiment, when the protruding electrode 4 of the semiconductor element 5 is displaced from the corresponding connection pad 2 of the substrate for mounting the semiconductor element, or when the conductive particles 6 of the ACF 6
Even when a is continuous, unnecessary short circuits can be reliably prevented. Further, similarly to the first embodiment, even when unnecessary ITO remains when the upper conductive film 12 is formed,
Unnecessary short circuits can be reliably prevented by the step portions 10a and 10b of the insulating film.

【００３７】以上、各実施の形態ではＣＯＧ実装に本発
明を適用した場合を説明したが、本発明はそれ以外の実
装方法や一般の半導体素子の実装にも広く適用可能であ
る。In the above embodiments, the case where the present invention is applied to COG mounting has been described. However, the present invention can be widely applied to other mounting methods and general semiconductor element mounting.

【００３８】[0038]

【発明の効果】本発明に係る半導体素子の実装構造は、
半導体素子を実装する接続パッドの辺縁及び引き出し配
線の上部に絶縁部分を設けることにより、実装時におけ
る不要なショートの危険性をなくすことが可能である。
また、その構造を持つ液晶表示装置は、歩留まり率及び
信頼性の高いものとすることが可能となる。The mounting structure of the semiconductor device according to the present invention is as follows.
By providing an insulating portion on the periphery of the connection pad on which the semiconductor element is mounted and above the lead wiring, it is possible to eliminate the risk of unnecessary short circuit during mounting.
Further, a liquid crystal display device having the structure can have a high yield rate and high reliability.

【００３９】[0039]

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の第一の実施の形態における半導体素子
の接続部の配置構成を示す図FIG. 1 is a diagram showing an arrangement configuration of a connection portion of a semiconductor element according to a first embodiment of the present invention.

【図２】本発明の第一の実施の形態における半導体素子
の接続パッド断面を示す図、（ａ）は図１におけるＡ−
Ａ’断面図であり、正常に突起電極が接着された状態を
示す図、（ｂ）は図１におけるＢ−Ｂ’断面図であり、
突起電極がずれて接着された状態を示す図、（ｃ）は図
１におけるＣ−Ｃ’断面図であり、突起電極がずれて接
着された状態を示す図FIG. 2 is a view showing a cross section of a connection pad of a semiconductor element according to the first embodiment of the present invention, and FIG.
FIG. 2A is a cross-sectional view showing a state where the protruding electrodes are normally bonded, FIG. 2B is a cross-sectional view taken along the line BB ′ in FIG.
FIG. 3C is a diagram showing a state where the protruding electrodes are shifted and adhered, and FIG. 3C is a cross-sectional view taken along the line CC ′ in FIG.

【図３】一般的なＣＯＧ実装工程の概略図FIG. 3 is a schematic diagram of a general COG mounting process.

【図４】従来の液晶表示装置における半導体素子の接続
部の配置構成を示す図FIG. 4 is a diagram showing an arrangement configuration of a connection portion of a semiconductor element in a conventional liquid crystal display device.

【図５】従来の液晶表示装置における半導体素子の接続
パッド断面を示す図FIG. 5 is a diagram showing a cross section of a connection pad of a semiconductor element in a conventional liquid crystal display device.

【図６】従来の液晶表示装置における半導体素子の接続
を示す図、（ａ）は半導体素子の接続を示す図、（ｂ）
は（ａ）におけるＤ−Ｄ’断面図であり、突起電極がず
れて接着された状態を示す図、（ｃ）は（ａ）における
Ｅ−Ｅ’断面図であり、突起電極がずれて接着された状
態を示す図6A and 6B are diagrams showing connection of a semiconductor element in a conventional liquid crystal display device, FIG. 6A is a diagram showing connection of a semiconductor element, and FIG.
FIG. 3A is a cross-sectional view taken along the line DD ′ in FIG. 3A, showing a state in which the protruding electrodes are shifted and bonded. FIG. 3C is a cross-sectional view taken along the line EE ′ in FIG. Diagram showing the state

【図７】本発明の第二の実施の形態における半導体素子
の接続部の配置構成を示す図FIG. 7 is a diagram showing an arrangement configuration of a connection portion of a semiconductor element according to a second embodiment of the present invention;

【図８】図７におけるＦ−Ｆ’断面斜視図であり、本発
明の第二の実施の形態における半導体素子の接続パッド
を示す図FIG. 8 is a perspective view of a section taken along line FF ′ in FIG. 7, showing connection pads of a semiconductor element according to the second embodiment of the present invention;

【図９】本発明の接続パッド及び引き出し配線の数値形
状の一例を示す図FIG. 9 is a diagram showing an example of a numerical shape of a connection pad and a lead wiring according to the present invention.

【図１０】本発明の接続パッドの形成工程を示す図、
（ａ）はガラス基板に絶縁膜を堆積させた図、（ｂ）は
下層導電膜を形成させた図、（ｃ）は絶縁膜を堆積させ
た図、（ｄ）は絶縁膜に開口部を形成させた図、（ｅ）
は上層導電膜を形成させた図FIG. 10 is a view showing a step of forming a connection pad according to the present invention;
(A) is a diagram in which an insulating film is deposited on a glass substrate, (b) is a diagram in which a lower conductive film is formed, (c) is a diagram in which an insulating film is deposited, and (d) is a diagram in which an opening is formed in the insulating film. Figure (e)
Shows the upper conductive film formed

【符号の説明】[Explanation of symbols]

１，７ 半導体実装用の基
板、 ２ 接続パッド、 ３ 液晶表示パネル（Ｌ
ＣＤ）、 ４ 半導体素子の突起電
極、 ５ 半導体素子、 ６ ＡＣＦ ６ａ 導電性粒子、 ８，１０ 絶縁膜、 １０ａ，１０ｂ 絶縁膜の段差部（絶
縁部分） ９ 下層導電膜、 １１ 開口部、 １２ 上層導電膜、 １３ 共通検査配線、 １４ 引き出し配線、 １５ 検査接続配線、 １６ 検査接続配線コンタ
クト1, 7 semiconductor mounting substrate, 2 connection pads, 3 liquid crystal display panel (L
CD, 4 projecting electrode of semiconductor element, 5 semiconductor element, 6 ACF 6a conductive particles, 8,10 insulating film, 10a, 10b step portion (insulating portion) of insulating film 9 lower conductive film, 11 opening, 12 upper layer Conductive film, 13 common inspection wiring, 14 lead-out wiring, 15 inspection connection wiring, 16 inspection connection wiring contact

───────────────────────────────────────────────────── フロントページの続き (72)発明者 藤田 光 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Ｆターム(参考） 2H092 GA33 GA35 GA41 GA43 GA48 GA49 GA60 HA12 JB77 NA16 NA29 5C094 AA42 AA43 BA03 BA43 CA19 DA15 EA04 EA07 5F044 KK11 LL09  ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hikaru Fujita 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F-term (reference) 2H092 GA33 GA35 GA41 GA43 GA48 GA49 GA60 HA12 JB77 NA16 NA29 5C094 AA42 AA43 BA03 BA43 CA19 DA15 EA04 EA07 5F044 KK11 LL09

Claims (7)

【特許請求の範囲】[Claims] 【請求項１】 接続パッドが形成された半導体実装用の
基板に、導電性を有する接着剤を介して、突起電極を有
する半導体素子が実装される半導体素子の実装構造にお
いて、 上記接続パッドに、導電性を有する接着剤を介して上記
対応する半導体素子の突起電極が接続されるべき接続パ
ッド以外の接続パッドとの導通を防止するための絶縁部
分が少なくとも設けられていることを特徴とする半導体
素子の実装構造。1. A mounting structure of a semiconductor element in which a semiconductor element having a protruding electrode is mounted on a semiconductor mounting substrate on which a connection pad is formed, via a conductive adhesive, wherein: A semiconductor having at least an insulating portion for preventing conduction with connection pads other than the connection pad to which the corresponding protruding electrode of the semiconductor element is to be connected via a conductive adhesive; Device mounting structure. 【請求項２】 接続パッドが形成された半導体実装用の
基板に、導電性を有する接着剤を介して、突起電極を有
する半導体素子が実装されるとともに、接続パッドから
検査用の引き出し配線が引き出された半導体素子の実装
構造において、 上記接続パッドに、導電性を有する接着剤を介して上記
引き出し配線との導通を防止するための絶縁部分が少な
くとも設けられていることを特徴とする半導体素子の実
装構造。2. A semiconductor element having a protruding electrode is mounted on a semiconductor mounting substrate on which a connection pad is formed via an adhesive having conductivity, and a lead wire for inspection is drawn out from the connection pad. In the semiconductor device mounting structure, the connection pad is provided with at least an insulating portion for preventing conduction with the lead-out wiring via a conductive adhesive. Mounting structure. 【請求項３】 前記接続パッドは、基板上に形成した下
層導電膜を覆うようにかつ下層導電膜の***部に下層
導電膜より小さい形状の開口部を有するように絶縁膜を
形成し、その上部に開口部より大きくかつ下層導電膜よ
り小さい形状の上層導電膜を形成し、絶縁膜の開口部を
介して上層導電膜と下層導電膜を導通させる構造をとる
ことにより、下層導電膜の外周辺縁に絶縁部分を段差状
に設けたことを特徴とする請求項１又は請求項２記載の
半導体素子の実装構造。3. An insulating film is formed on the connection pad so as to cover the lower conductive film formed on the substrate and to have an opening having a shape smaller than that of the lower conductive film in the upper central portion of the lower conductive film; An upper conductive film having a shape larger than the opening and smaller than the lower conductive film is formed on the upper conductive film, and the upper conductive film and the lower conductive film are electrically connected through the opening of the insulating film. The mounting structure of a semiconductor element according to claim 1, wherein an insulating portion is provided in a step shape at an outer peripheral edge. 【請求項４】 前記接続パッドが複数列で構成されると
ともに互いの列をずらして千鳥配置となっていることを
特徴とする請求項１乃至請求項３記載の半導体素子の実
装構造。4. The semiconductor element mounting structure according to claim 1, wherein said connection pads are formed in a plurality of rows and are arranged in a staggered manner with each other shifted. 【請求項５】 接続パッドが形成された半導体実装用の
基板に、導電性を有する接着剤を介して、突起電極を有
する半導体素子が実装されるとともに、接続パッドから
検査用の引き出し配線が引き出された半導体素子の実装
構造において、 上記引き出し配線に導電性を有する接着剤を介して上記
接続パッドとの導通を防止するための絶縁部分が少なく
とも設けられていることを特徴とする半導体素子の実装
構造。5. A semiconductor element having a protruding electrode is mounted on a semiconductor mounting substrate on which a connection pad is formed via an adhesive having conductivity, and a lead wire for inspection is drawn out from the connection pad. In the mounting structure of the semiconductor device, at least an insulating portion for preventing conduction with the connection pad via a conductive adhesive is provided on the lead-out wiring. Construction. 【請求項６】 前記接続パッドは少なくとも上層導電膜
と下層導電膜及びそれらの間の絶縁膜からなっており、
前記引き出し配線は接続パッドの下層導電膜から引き出
されるとともに、接続パッドの絶縁膜で覆われているこ
とを特徴とする請求項５記載の半導体素子の実装構造。6. The connection pad includes at least an upper conductive film, a lower conductive film, and an insulating film therebetween.
6. The semiconductor element mounting structure according to claim 5, wherein said lead-out wiring is drawn out from a lower conductive film of the connection pad and is covered with an insulating film of the connection pad. 【請求項７】 前記請求項１乃至請求項６記載の半導体
素子の実装構造を使用するものであって、配線パターン
が形成された半導体実装用の基板は、対向する基板間に
液晶が狭持された液晶パネルの一方の基板と一体とされ
た基板であることを特徴とする半導体素子の実装構造を
有する液晶表示装置。7. A semiconductor device mounting structure according to claim 1, wherein a liquid crystal is sandwiched between opposing substrates on a semiconductor mounting substrate on which a wiring pattern is formed. A liquid crystal display device having a mounting structure of a semiconductor element, wherein the liquid crystal display device is a substrate integrated with one substrate of a liquid crystal panel.
JP2000394189A 2000-12-26 2000-12-26 Package structure of semiconductor elements and liquid crystal display device having the structure Pending JP2002196703A (en)

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* Cited by examiner, † Cited by third party
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US7132689B2 (en) * 2003-04-03 2006-11-07 Lg.Philips Lcd Co., Ltd Liquid crystal display of horizontal electric field applying type and fabricating method thereof
JP2007293262A (en) * 2005-12-15 2007-11-08 Epson Imaging Devices Corp Electrooptical device, mounting assembly, method for producing electrooptical device, and electronic apparatus
JP2008028145A (en) * 2006-07-21 2008-02-07 Mitsubishi Electric Corp Mounting terminal board and display using the same
US9412803B2 (en) 2015-01-14 2016-08-09 Samsung Display Co., Ltd. Display device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7132689B2 (en) * 2003-04-03 2006-11-07 Lg.Philips Lcd Co., Ltd Liquid crystal display of horizontal electric field applying type and fabricating method thereof
US7553708B2 (en) * 2003-04-03 2009-06-30 Lg Display Co., Ltd. Fabricating method for a liquid crystal display of horizontal electric field applying type
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