JP2002190466A - Plasma-etching device and method for manufacturing semiconductor device - Google Patents

Plasma-etching device and method for manufacturing semiconductor device

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Publication number
JP2002190466A
JP2002190466A JP2000389199A JP2000389199A JP2002190466A JP 2002190466 A JP2002190466 A JP 2002190466A JP 2000389199 A JP2000389199 A JP 2000389199A JP 2000389199 A JP2000389199 A JP 2000389199A JP 2002190466 A JP2002190466 A JP 2002190466A
Authority
JP
Japan
Prior art keywords
ring
plasma etching
semiconductor wafer
etching apparatus
annular portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000389199A
Other languages
Japanese (ja)
Other versions
JP3393118B2 (en
Inventor
Heito Kin
丙東 金
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Leading Edge Technologies Inc
Original Assignee
Semiconductor Leading Edge Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Leading Edge Technologies Inc filed Critical Semiconductor Leading Edge Technologies Inc
Priority to JP2000389199A priority Critical patent/JP3393118B2/en
Priority to KR1020010048889A priority patent/KR100739569B1/en
Publication of JP2002190466A publication Critical patent/JP2002190466A/en
Application granted granted Critical
Publication of JP3393118B2 publication Critical patent/JP3393118B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32715—Workpiece holder
    • H01J37/32724—Temperature
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32623—Mechanical discharge control means
    • H01J37/32642—Focus rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • H01L21/6833—Details of electrostatic chucks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PROBLEM TO BE SOLVED: To assure a uniform etching rate on an overall surface of a semiconductor wafer in a plasma-etching apparatus. SOLUTION: The semiconductor wafer 10 is mounted on a lower electrode 14. An annular focusing ring 30 is disposed along the outer edge of the wafer 10. The ring 30 has a first ring 32, made of a quartz disposed at the outermost peripheral side, a second ring 34 made of a silicon disposed at an inside of the ring 32, and a third ring 35 disposed at the innermost peripheral side, so as to be superposed with the peripheral edge of the wafer 10. The ring 36 is constituted of a material, indicating a slow temperature rise, as compared with the silicon during executing of the plasma etching.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明はプラズマエッチング
装置および半導体装置の製造方法に係り、特に、半導体
ウェハの全面において均一なエッチングレートを確保す
るプラズマエッチング装置、並びにそのエッチング装置
を用いる半導体装置の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma etching apparatus and a method for manufacturing a semiconductor device, and more particularly to a plasma etching apparatus for securing a uniform etching rate over the entire surface of a semiconductor wafer, and a method for manufacturing a semiconductor device using the etching apparatus. About the method.

【０００２】[0002]

【従来の技術】図３（Ａ）は、従来のプラズマエッチン
グ装置の概要を説明するための正面透視図を示す。ま
た、図３（Ｂ）は、図３（Ａ）に示されるフォーカスリ
ングおよび半導体ウェハを平面視で表した図を示す。2. Description of the Related Art FIG. 3A is a front perspective view for explaining an outline of a conventional plasma etching apparatus. FIG. 3B shows a plan view of the focus ring and the semiconductor wafer shown in FIG. 3A.

【０００３】図３（Ａ）に示すように、従来のプラズマ
エッチング装置は、半導体ウェハ１０に対してプラズマ
エッチングを施すための処理室１２を備えている。処理
室１２の内部には、半導体ウェハ１０を保持する下部電
極１４が配置されている。下部電極１４の内部には、図
示しない直流電圧電源から所定の直流電圧の供給を受け
る静電吸着電極と、ＲＦ電源１６からＲＦ電力の供給を
受けるカソード電極とが内蔵されている（何れも図示せ
ず）。静電吸着電極は、直流電圧電源から直流電圧の供
給を受けることにより静電力を発生して半導体ウェハ１
０を吸着保持する。また、カソード電極は、ＲＦ電源１
６からＲＦ電力の供給を受けることにより、処理室１２
内部にプラズマを発生させるための磁場を生成する。As shown in FIG. 3A, a conventional plasma etching apparatus includes a processing chamber 12 for performing a plasma etching on a semiconductor wafer 10. A lower electrode 14 for holding the semiconductor wafer 10 is disposed inside the processing chamber 12. Inside the lower electrode 14, an electrostatic chucking electrode that receives a supply of a predetermined DC voltage from a DC voltage power supply (not shown) and a cathode electrode that receives a supply of RF power from an RF power supply 16 are incorporated. Not shown). The electrostatic chucking electrode generates an electrostatic force by receiving a DC voltage from a DC voltage power supply, and generates an electrostatic force.
0 is held by suction. The cathode electrode is an RF power source 1
6 is supplied with RF power from the processing chamber 12.
A magnetic field for generating plasma inside is generated.

【０００４】下部電極１４は、更に、図示しない冷却ガ
ス供給孔を備えている。この冷却ガス供給孔は、図示し
ない冷却ガス供給機構から供給されるヘリウムなどの冷
却ガスを半導体ウェハ１０の裏面に導くための通路であ
る。従来のプラズマエッチング装置は、プラズマエッチ
ングの実行中に、上記の冷却ガス供給孔および冷却ガス
供給機構（冷却機構）を用いて半導体ウェハ１０を冷却
することができる。The lower electrode 14 further has a cooling gas supply hole (not shown). The cooling gas supply hole is a passage for guiding a cooling gas such as helium supplied from a cooling gas supply mechanism (not shown) to the back surface of the semiconductor wafer 10. The conventional plasma etching apparatus can cool the semiconductor wafer 10 using the cooling gas supply hole and the cooling gas supply mechanism (cooling mechanism) during the execution of the plasma etching.

【０００５】処理室１２の上部には、処理室１２の内部
のエッチングガスを導入するためのガス供給部１８が設
けられている。従来のプラズマエッチング装置は、ガス
供給部１８によって処理室１２内部にエッチングガスを
導入し、更に、ＲＦ電源１６によってカソード電極にＲ
Ｆ電力を印加することにより、処理室１２内部にプラズ
マを発生させる。[0005] Above the processing chamber 12, a gas supply unit 18 for introducing an etching gas inside the processing chamber 12 is provided. In the conventional plasma etching apparatus, an etching gas is introduced into the processing chamber 12 by a gas supply unit 18, and an R power is supplied to a cathode electrode by an RF power supply 16.
Plasma is generated inside the processing chamber 12 by applying the F power.

【０００６】従来のプラズマエッチング装置は、下部電
極１４の上に、半導体ウェハ１０の外周を取り巻くよう
なフォーカスリング２０を備えている。フォーカスリン
グ２０は、プラズマの発生および維持に関する条件が、
半導体ウェハ１０の周縁付近とその中心付近とで大きく
異ならないように配置される部材である。従来のフォー
カスリング２０は、石英で構成される第１リング２２の
内周側に、シリコンで構成される第２リング２４を組み
込むことにより形成されている。[0006] The conventional plasma etching apparatus has a focus ring 20 surrounding the outer periphery of the semiconductor wafer 10 on the lower electrode 14. The focus ring 20 has conditions for generating and maintaining plasma.
These members are arranged so as not to be largely different between the vicinity of the periphery of the semiconductor wafer 10 and the vicinity of the center thereof. The conventional focus ring 20 is formed by incorporating a second ring 24 made of silicon on the inner peripheral side of a first ring 22 made of quartz.

【０００７】このようなフォーカスリング２０によれ
ば、半導体ウェハ１０の周縁付近におけるプラズマ条件
の急変を緩和することができる。従って、フォーカスリ
ング２０は、半導体ウェハ１０のエッチングレートを、
その全面において均一化するうえで有効である。According to such a focus ring 20, a sudden change in plasma conditions near the periphery of the semiconductor wafer 10 can be reduced. Accordingly, the focus ring 20 controls the etching rate of the semiconductor wafer 10 to
This is effective in making the entire surface uniform.

【０００８】[0008]

【発明が解決しようとする課題】しかし、従来のプラズ
マエッチング装置では、図２に示すように、半導体ウェ
ハ１０の最外周付近におけるエッチングレートを、その
中央付近におけるレートに合わせることはできない。こ
こで、図２は、従来のプラズマエッチング装置における
エッチングレートの不均一性を表す実験結果であり、そ
の縦軸がエッチングレート（縦軸）を表し、また、その
横軸が半導体ウェハの中心からの距離を表している。
尚、図２において、data1およびdata2は、それぞれ第１
テストピースの測定結果と、第２テストピースの測定結
果を表している。However, in the conventional plasma etching apparatus, as shown in FIG. 2, the etching rate near the outermost periphery of the semiconductor wafer 10 cannot be adjusted to the rate near the center thereof. Here, FIG. 2 shows an experimental result showing the non-uniformity of the etching rate in the conventional plasma etching apparatus, in which the vertical axis represents the etching rate (vertical axis) and the horizontal axis represents the center of the semiconductor wafer. Represents the distance.
In FIG. 2, data1 and data2 are the first data, respectively.
The measurement result of the test piece and the measurement result of the second test piece are shown.

【０００９】図２に示す測定結果より、従来のプラズマ
エッチング装置では、半導体ウェハ１０のエッチングレ
ートが、その最外周付近で急激に低下することが判る。
この結果は、ＲＦ電力を４５００Ｗとし、半導体ウェハ
１０の冷却温度を−２０℃とした場合の結果である。こ
の際、フォーカスリング２０の温度は第２リング２４の
位置（シリコンの位置）で２５０℃であり、一方、半導
体ウェハ１０の温度は１００℃であった。From the measurement results shown in FIG. 2, it can be seen that in the conventional plasma etching apparatus, the etching rate of the semiconductor wafer 10 sharply decreases near its outermost periphery.
This result is obtained when the RF power is 4500 W and the cooling temperature of the semiconductor wafer 10 is −20 ° C. At this time, the temperature of the focus ring 20 was 250 ° C. at the position of the second ring 24 (the position of silicon), while the temperature of the semiconductor wafer 10 was 100 ° C.

【００１０】このように、従来のプラズマエッチング装
置では、プラズマエッチングの実行中に、半導体ウェハ
１０とフォーカスリング２０の境界に大きな温度差が発
生する。このような温度差は、プラズマの発生および維
持に関する条件の均一性を乱す原因となる。従って、従
来のプラズマエッチング装置においては、上記の温度差
が、半導体ウェハ１０の最外周付近でエッチングレート
を急激に低下させている原因の一つと考えられる。As described above, in the conventional plasma etching apparatus, a large temperature difference occurs at the boundary between the semiconductor wafer 10 and the focus ring 20 during the execution of the plasma etching. Such a temperature difference causes a disturbance in uniformity of conditions for generation and maintenance of plasma. Therefore, in the conventional plasma etching apparatus, it is considered that the above-mentioned temperature difference is one of the causes of a sharp decrease in the etching rate near the outermost periphery of the semiconductor wafer 10.

【００１１】本発明は、上記のような課題を解決するた
めになされたもので、半導体ウェハとフォーカスリング
の境界における温度差を抑制して、半導体ウェハのエッ
チングレートをその全面においてほぼ均一にすることの
できるプラズマエッチング装置を提供することを第１の
目的とする。また、本発明は、上記のプラズマエッチン
グ装置を用いて半導体装置を製造する製造方法を提供す
ることを第２の目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and suppresses a temperature difference at a boundary between a semiconductor wafer and a focus ring to make the etching rate of the semiconductor wafer substantially uniform over the entire surface. It is a first object of the present invention to provide a plasma etching apparatus capable of performing the above. A second object of the present invention is to provide a manufacturing method for manufacturing a semiconductor device using the above plasma etching apparatus.

【００１２】[0012]

【課題を解決するための手段】請求項１記載の発明は、
処理室の中で半導体ウェハにプラズマエッチングを施す
装置であって、前記半導体ウェハを保持する静電吸着電
極と、前記静電吸着電極に直流電圧を供給する直流電源
と、前記静電吸着電極に保持された前記半導体ウェハの
裏面に冷却用ガスを導入する冷却機構と、前記半導体ウ
ェハの外縁に沿って設置される環状のフォーカスリング
と、前記処理室にエッチングガスを供給すると共に、そ
の内部圧力を制御するガス供給系と、前記処理室内部に
プラズマを発生させるプラズマ発生機構と、を備え、前
記フォーカスリングは、最も外周側に配置される石英製
の第１リングと、前記第１リングの内側に配置されるシ
リコン製の第２リングと、前記半導体ウェハの周縁と重
なるように、最も内周側に配置される第３リングとを含
み前記第３リングは、前記処理室の内部に前記プラズマ
が発生している状況下で、シリコンに比して緩やかな温
度上昇を示す所定材質で構成されることを特徴とする。According to the first aspect of the present invention,
An apparatus for performing plasma etching on a semiconductor wafer in a processing chamber, comprising: an electrostatic chucking electrode that holds the semiconductor wafer; a DC power supply that supplies a DC voltage to the electrostatic chucking electrode; A cooling mechanism for introducing a cooling gas to the back surface of the held semiconductor wafer, an annular focus ring provided along an outer edge of the semiconductor wafer, and an etching gas supplied to the processing chamber and an internal pressure of the processing chamber. And a plasma generating mechanism for generating plasma inside the processing chamber, wherein the focus ring is a first ring made of quartz arranged on the outermost side, A third ring including a second ring made of silicon disposed inside and a third ring disposed on the innermost side so as to overlap a peripheral edge of the semiconductor wafer; , In situations where the plasma inside the processing chamber is occurring, characterized in that it is composed of a predetermined material showing a gradual increase in temperature as compared with silicon.

【００１３】請求項２記載の発明は、請求項１記載のプ
ラズマエッチング装置であって、前記第３リングを構成
する所定材料は、フッ素系重合体であることを特徴とす
る。According to a second aspect of the present invention, in the plasma etching apparatus according to the first aspect, the predetermined material forming the third ring is a fluorine-based polymer.

【００１４】請求項３記載の発明は、請求項２記載のプ
ラズマエッチング装置であって、前記フッ素系重合体
は、テフロンまたはベスペル（何れもデュポン社製）で
あることを特徴とする。According to a third aspect of the present invention, there is provided the plasma etching apparatus according to the second aspect, wherein the fluoropolymer is Teflon or Vespel (both manufactured by DuPont).

【００１５】請求項４記載の発明は、請求項１乃至３の
何れか１項記載のプラズマエッチング装置であって、前
記第２リングは、第１の板厚を有する厚板環状部と、第
１の板厚に比して薄い第２の板厚を有する薄板環状部と
を備え、前記厚板環状部と前記薄板環状部とは、それら
の底面が同一面を形成し、前記厚板環状部が前記薄板環
状部の外周側に位置するように一体的に形成されてお
り、前記第３リングは、前記薄板環状部の上に、前記厚
板環状部の内壁と接するように配置されることを特徴と
する。According to a fourth aspect of the present invention, there is provided the plasma etching apparatus according to any one of the first to third aspects, wherein the second ring comprises a thick annular portion having a first thickness, A thin annular portion having a second thickness smaller than the thickness of the first annular portion, wherein the thick annular portion and the thin annular portion have the same bottom surface, The third ring is disposed on the thin-plate annular portion so as to be in contact with the inner wall of the thick-plate annular portion. It is characterized by the following.

【００１６】請求項５記載の発明は、請求項１乃至４の
何れか１項記載のプラズマエッチング装置であって、前
記第３リングは、０．５mm以上２．０mm以下の幅を有す
ることを特徴とする。According to a fifth aspect of the present invention, there is provided the plasma etching apparatus according to any one of the first to fourth aspects, wherein the third ring has a width of 0.5 mm or more and 2.0 mm or less. Features.

【００１７】請求項６記載の発明は、プラズマエッチン
グ工程を含む半導体装置の製造方法であって、前記プラ
ズマエッチング工程は、請求項１乃至６の何れか１項記
載のプラズマエッチング装置を用いて行われることを特
徴とする。According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device including a plasma etching step, wherein the plasma etching step is performed by using the plasma etching apparatus according to any one of the first to sixth aspects. It is characterized by being performed.

【００１８】[0018]

【発明の実施の形態】以下、図面を参照してこの発明の
実施の形態について説明する。尚、各図において共通す
る要素には、同一の符号を付して重複する説明を省略す
る。Embodiments of the present invention will be described below with reference to the drawings. Elements common to the drawings are denoted by the same reference numerals, and redundant description will be omitted.

【００１９】実施の形態１．図１（Ａ）は、本発明の実
施の形態１のプラズマエッチング装置の主要部の構造を
正面視で表した図を示す。また、図１（Ｂ）は、図１
（Ａ）に示すフォーカスリング３０および半導体ウェハ
１０を平面視で表した図を示す。本実施形態のプラズマ
エッチング装置は、フォーカスリング３０の構造を除
き、従来の装置（図３参照）と同様の構成を有してい
る。このため、ここでは、フォーカスリング３０の構成
を主に説明し、本実施形態の装置のうち、従来の装置と
重複する部分については、その説明を省略または簡略す
る。Embodiment 1 FIG. 1A is a diagram showing a structure of a main part of a plasma etching apparatus according to Embodiment 1 of the present invention in a front view. FIG. 1B is a view similar to FIG.
FIG. 2 shows a plan view of the focus ring 30 and the semiconductor wafer 10 shown in FIG. The plasma etching apparatus of the present embodiment has the same configuration as the conventional apparatus (see FIG. 3) except for the structure of the focus ring 30. For this reason, the configuration of the focus ring 30 will be mainly described here, and the description of the portions of the device of the present embodiment that overlap with the conventional device will be omitted or simplified.

【００２０】図１（Ａ）および図１（Ｂ）に示すよう
に、本実施形態において、フォーカスリング３０は、第
１リング３２、第２リング３４、および第３リング３６
を備えている。第１リング３２は、石英により構成され
ており、フォーカスリング３０の最外周に配置されてい
る。第２リング３４は、シリコンにより構成されてお
り、第１リング３２の内側に密着して配置されている。As shown in FIGS. 1A and 1B, in this embodiment, the focus ring 30 includes a first ring 32, a second ring 34, and a third ring 36.
It has. The first ring 32 is made of quartz, and is arranged on the outermost periphery of the focus ring 30. The second ring 34 is made of silicon, and is disposed in close contact with the inside of the first ring 32.

【００２１】第３リング３６は、本実施形態の主要部で
あり、処理室１２の内部でプラズマエッチングの処理に
付された場合に、シリコンに比して低い温度上昇速度
（単位時間当たりの温度上昇幅）を示す材質により構成
されている。第３リング３６は、例えば、フッ素系重合
体により、より具体的には、デュポン社製のテフロン或
いはベスペル（何れも商品名）により構成することがで
きる。The third ring 36 is a main part of the present embodiment, and has a lower rate of temperature rise (temperature per unit time) than silicon when subjected to plasma etching in the processing chamber 12. (A rising width). The third ring 36 can be made of, for example, a fluoropolymer, more specifically, Teflon or Vespel (both trade names) manufactured by DuPont.

【００２２】図１（Ａ）に示すように、第３リング３６
は、その一部が半導体ウェハ１０と重なるように構成さ
れている。すなわち、第３リング３６は、半導体ウェハ
１０の周縁部が第３リング上に位置するように形成され
ている。また、第３リング３６は、０．５mm以上２．０
mm以下の任意の幅、より好ましくは１．０mmの幅を有す
るように構成されている。As shown in FIG. 1A, the third ring 36
Is configured so that a part thereof overlaps the semiconductor wafer 10. That is, the third ring 36 is formed such that the periphery of the semiconductor wafer 10 is located on the third ring. The third ring 36 is 0.5 mm or more and 2.0 mm or more.
It is configured to have an arbitrary width of not more than mm, more preferably a width of 1.0 mm.

【００２３】上記の如く、プラズマエッチング処理の実
行中における第３リング３６の温度上昇速度は、シリコ
ンの温度上昇速度、すなわち、第２リング３４の温度上
昇速度に比して低速である。このため、本実施形態のプ
ラズマエッチング装置によれば、フォーカスリング３０
と半導体ウェハ１０の境界に生ずる温度差を、従来生じ
ていた温度差に比して小さくすることができる。As described above, the temperature rising speed of the third ring 36 during the execution of the plasma etching process is lower than the temperature rising speed of silicon, that is, the temperature rising speed of the second ring 34. Therefore, according to the plasma etching apparatus of the present embodiment, the focus ring 30
The temperature difference generated at the boundary between the semiconductor wafer 10 and the semiconductor wafer 10 can be made smaller than the temperature difference generated conventionally.

【００２４】例えば、プラズマを生成するためのＲＦ電
力が４５００Ｗであり、半導体ウェハ１０の冷却温度が
−２０℃である場合、従来のプラズマエッチング装置で
は、上記の如く、フォーカスリング２０（２５０℃）と
半導体ウェハ１０（１００℃）の境界に１５０℃の温度
差が発生する。これに対して、本実施形態では、上記の
条件の下では、第３リング３６の温度が１５０℃程度に
抑えられる。このため、フォーカスリング３０と半導体
ウェハ１０の境界に生ずる温度差は、５０℃程度とな
る。For example, when the RF power for generating plasma is 4500 W and the cooling temperature of the semiconductor wafer 10 is −20 ° C., the focus ring 20 (250 ° C.) is used in the conventional plasma etching apparatus as described above. A temperature difference of 150 ° C. occurs at the boundary between the semiconductor wafer 10 and the semiconductor wafer 10 (100 ° C.). On the other hand, in the present embodiment, the temperature of the third ring 36 is suppressed to about 150 ° C. under the above conditions. Therefore, a temperature difference generated at the boundary between the focus ring 30 and the semiconductor wafer 10 is about 50 ° C.

【００２５】プラズマの発生および維持に関する条件
は、フォーカスリング３０と半導体ウェハ１０の境界部
における温度差が小さいほど処理室１２内部で均一とな
る。このため、本実施形態のプラズマエッチング装置に
よれば、半導体ウェハ１０の周縁付近でエッチングレー
トが急激に低下するのを防止して、半導体ウェハ１０の
エッチングレートをその全面においてほぼ均一とするこ
とができる。The conditions for generation and maintenance of plasma become more uniform inside the processing chamber 12 as the temperature difference at the boundary between the focus ring 30 and the semiconductor wafer 10 becomes smaller. For this reason, according to the plasma etching apparatus of the present embodiment, it is possible to prevent the etching rate from decreasing rapidly near the periphery of the semiconductor wafer 10 and make the etching rate of the semiconductor wafer 10 substantially uniform over the entire surface. it can.

【００２６】ところで、プラズマエッチングの実行中
は、半導体ウェハ１０が削られることに伴って副生成物
が生成される。この副生成物は、比較的温度の低い部位
に堆積し易い特性を示す。このため、比較的温度の低い
第３リング３６が過度に大きな幅を有していると、第３
リング３６の近傍に副生成物が過剰に堆積するという不
都合が生ずる。一方、第３リング３６の幅が不必要に狭
いと、第３リング３６を設けたことによる効果を得るこ
とができない。By the way, during the execution of the plasma etching, by-products are generated as the semiconductor wafer 10 is shaved. This by-product has a characteristic of being easily deposited on a portion having a relatively low temperature. For this reason, if the relatively low temperature of the third ring 36 has an excessively large width,
There is a disadvantage that by-products are excessively deposited near the ring 36. On the other hand, if the width of the third ring 36 is unnecessarily small, the effect of providing the third ring 36 cannot be obtained.

【００２７】本実施形態では、上記の如く、第３リング
３６の幅が０．５mm以上２．０mm以内に規制されてい
る。このような幅を有する第３リング３６によれば、副
生成物の堆積に関して実質的な問題を発生させることな
く、処理室１２内のエッチングレートの均一性を高める
ことができる。このため、本実施形態のプラズマエッチ
ング装置によれば、第３リング３６を設けたことによる
不都合を伴うことなく、エッチングレートの均一性を高
めるという効果を得ることができる。In the present embodiment, as described above, the width of the third ring 36 is restricted to 0.5 mm or more and 2.0 mm or less. According to the third ring 36 having such a width, the uniformity of the etching rate in the processing chamber 12 can be increased without causing a substantial problem regarding the deposition of by-products. Therefore, according to the plasma etching apparatus of the present embodiment, it is possible to obtain the effect of improving the uniformity of the etching rate without inconvenience due to the provision of the third ring 36.

【００２８】実施の形態２．次に、図２（Ａ）および図
２（Ｂ）を参照して本発明の実施の形態２について説明
する。図２（Ａ）は、本発明の実施の形態２のプラズマ
エッチング装置の主要部の構造を正面視で表した図を示
す。また、図２（Ｂ）は、図２（Ａ）に示すフォーカス
リング４０および半導体ウェハ１０を平面視で表した図
を示す。本実施形態のプラズマエッチング装置は、フォ
ーカスリング４０の構造を除き、実施の形態１の装置と
同様の構成を有している。このため、ここでは、フォー
カスリング４０がフォーカスリング３０と異なる点のみ
を説明する。Embodiment 2 Next, a second embodiment of the present invention will be described with reference to FIGS. 2 (A) and 2 (B). FIG. 2A is a diagram showing a structure of a main part of a plasma etching apparatus according to a second embodiment of the present invention in a front view. FIG. 2B shows a plan view of the focus ring 40 and the semiconductor wafer 10 shown in FIG. 2A. The plasma etching apparatus of the present embodiment has the same configuration as the apparatus of the first embodiment except for the structure of the focus ring 40. Therefore, here, only the point that the focus ring 40 is different from the focus ring 30 will be described.

【００２９】図２（Ａ）に示すように、本実施形態の装
置が備えるフォーカスリング４０は、第１リング４０、
第２リング４２、および第３リング４４により構成され
ている。これらのリング４０，４２，４４は、それぞ
れ、実施の形態１の場合と同様に、石英、シリコン、お
よびフッ素系重合体により構成されている。As shown in FIG. 2A, the focus ring 40 provided in the apparatus of the present embodiment includes a first ring 40,
It is composed of a second ring 42 and a third ring 44. Each of these rings 40, 42, and 44 is made of quartz, silicon, and a fluorine-based polymer, as in the case of the first embodiment.

【００３０】ここで、第２リング４２は、第１の板厚を
有する厚板環状部４８と、第１の板厚に比して薄い第２
の板厚を有する薄板環状部５０とを備えている。厚板環
状部４８と薄板環状部５０とは、それらの底面が同一面
を形成し、更に、厚板環状部４８が薄板環状部５０の外
周側に位置するように一体的に形成されている。また、
第３リング４６は、薄板環状部５０の上に、厚板環状部
４８の内壁と接するように配置されている。Here, the second ring 42 has a thick plate annular portion 48 having a first plate thickness and a second ring portion 48 having a thickness smaller than the first plate thickness.
And a thin plate annular portion 50 having a plate thickness of The thick annular portion 48 and the thin annular portion 50 are integrally formed such that their bottom surfaces form the same plane, and the thick annular portion 48 is located on the outer peripheral side of the thin annular portion 50. . Also,
The third ring 46 is disposed on the thin plate annular portion 50 so as to be in contact with the inner wall of the thick plate annular portion 48.

【００３１】第３リング４６を構成するフッ素系重合体
と第２リング４４を構成するシリコンとは、電気的に異
なる特性を示す。また、第３リング４６は、従来のフォ
ーカスリング２０では用いられていなかった構成要素で
ある。従って、第３リング４６を新たにフォーカスリン
グ４０の構成要素とすると、第３リング４６の影響が何
らかの形で半導体ウェハ１０に及ぶことが考えられる。The fluorine polymer constituting the third ring 46 and the silicon constituting the second ring 44 exhibit electrically different characteristics. The third ring 46 is a component not used in the conventional focus ring 20. Therefore, when the third ring 46 is newly provided as a component of the focus ring 40, the influence of the third ring 46 may be exerted on the semiconductor wafer 10 in some form.

【００３２】フォーカスリング４０は、第３リング４６
の下に第２リングの薄板環状部５０（シリコン）を残存
させることにより、実施の形態１のフォーカスリング３
０に比して従来のフォーカスリング２０に近い構成を維
持しつつ、そのフォーカスリング３０と同じ表面状態を
実現している。このため、本実施形態のプラズマエッチ
ング装置によれば、従来のフォーカスリング２０によっ
て得られる効果を多大に残しつつ、エッチングレートの
均一化に関する効果を得ることができる。The focus ring 40 includes a third ring 46.
The thin ring portion 50 (silicon) of the second ring remains under the focus ring 3 of the first embodiment.
The same surface state as that of the focus ring 30 is realized while maintaining the configuration close to that of the conventional focus ring 20 as compared with 0. For this reason, according to the plasma etching apparatus of the present embodiment, it is possible to obtain the effect of making the etching rate uniform while greatly retaining the effect obtained by the conventional focus ring 20.

【００３３】上述の如く、実施の形態１または２のプラ
ズマエッチング装置によれば、半導体ウェハ上のエッチ
ングレートの均一性を高めることができる。このため、
それらの装置を用いた半導体製造方法によれば、一枚の
半導体ウェハから得ることのできる有効なチップ数を増
大させて、半導体装置の歩留まりを高めることができ
る。As described above, according to the plasma etching apparatus of the first or second embodiment, the uniformity of the etching rate on the semiconductor wafer can be improved. For this reason,
According to a semiconductor manufacturing method using such a device, the number of effective chips that can be obtained from one semiconductor wafer can be increased, and the yield of semiconductor devices can be increased.

【００３４】[0034]

【発明の効果】上述の如く、本発明のプラズマエッチン
グ装置によれば、フォーカスリングと半導体ウェハの境
界に生ずる温度差を抑制して、半導体ウェハ上のエッチ
ングレートの均一性を高めることができる。更に、本発
明の半導体装置の製造方法によれば、上記のプラズマエ
ッチング装置を用いることにより、半導体装置の歩留ま
りを高めることができる。As described above, according to the plasma etching apparatus of the present invention, the temperature difference generated at the boundary between the focus ring and the semiconductor wafer can be suppressed, and the uniformity of the etching rate on the semiconductor wafer can be improved. Further, according to the method for manufacturing a semiconductor device of the present invention, the yield of the semiconductor device can be increased by using the above-described plasma etching apparatus.

【図面の簡単な説明】[Brief description of the drawings]

【図１】 本発明の実施の形態１のプラズマエッチング
装置の主要部を表す図である。FIG. 1 is a diagram illustrating a main part of a plasma etching apparatus according to a first embodiment of the present invention.

【図２】 本発明の実施の形態２のプラズマエッチング
装置の主要部を表す図である。FIG. 2 is a diagram illustrating a main part of a plasma etching apparatus according to a second embodiment of the present invention.

【図３】 従来のプラズマエッチング装置の構成を表す
図である。FIG. 3 is a diagram illustrating a configuration of a conventional plasma etching apparatus.

【図４】 従来のプラズマエッチング装置の問題点を説
明するための図である。FIG. 4 is a diagram for explaining a problem of a conventional plasma etching apparatus.

【符号の説明】[Explanation of symbols]

１０ 半導体ウェハ １２ 処理室 １４ 下部電極 １６ ＲＦ電源 １８ ガス供給部 ３０；４０ フォーカスリング ３２；４２ 第１リング ３４；４４ 第２リング ３６；４６ 第３リング ４８ 厚板環状部 ５０ 薄板環状部 DESCRIPTION OF SYMBOLS 10 Semiconductor wafer 12 Processing chamber 14 Lower electrode 16 RF power supply 18 Gas supply part 30; 40 Focus ring 32; 42 First ring 34; 44 Second ring 36; 46 Third ring 48 Thick annular part 50 Thin annular part

Claims (6)

【特許請求の範囲】[Claims] 【請求項１】 処理室の中で半導体ウェハにプラズマエ
ッチングを施す装置であって、 前記半導体ウェハを保持する静電吸着電極と、 前記静電吸着電極に直流電圧を供給する直流電源と、 前記静電吸着電極に保持された前記半導体ウェハの裏面
に冷却用ガスを導入する冷却機構と、 前記半導体ウェハの外縁に沿って設置される環状のフォ
ーカスリングと、 前記処理室にエッチングガスを供給すると共に、その内
部圧力を制御するガス供給系と、 前記処理室内部にプラズマを発生させるプラズマ発生機
構と、を備え、 前記フォーカスリングは、 最も外周側に配置される石英製の第１リングと、 前記第１リングの内側に配置されるシリコン製の第２リ
ングと、 前記半導体ウェハの周縁と重なるように、最も内周側に
配置される第３リングとを含み前記第３リングは、前記
処理室の内部に前記プラズマが発生している状況下で、
シリコンに比して緩やかな温度上昇を示す所定材質で構
成されることを特徴とするプラズマエッチング装置。1. An apparatus for performing plasma etching on a semiconductor wafer in a processing chamber, comprising: an electrostatic chuck electrode for holding the semiconductor wafer; a DC power supply for supplying a DC voltage to the electrostatic chuck electrode; A cooling mechanism for introducing a cooling gas to the back surface of the semiconductor wafer held by the electrostatic chucking electrode; an annular focus ring provided along an outer edge of the semiconductor wafer; and an etching gas supplied to the processing chamber. A gas supply system for controlling the internal pressure thereof, and a plasma generation mechanism for generating plasma in the processing chamber, wherein the focus ring is a first ring made of quartz disposed on the outermost side, A second ring made of silicon disposed inside the first ring; and a third ring disposed most innermost so as to overlap with a peripheral edge of the semiconductor wafer. The third ring comprises, under the situation that the plasma inside the processing chamber is occurring,
A plasma etching apparatus comprising a predetermined material that shows a gradual rise in temperature as compared with silicon. 【請求項２】 前記第３リングを構成する所定材料は、
フッ素系重合体であることを特徴とする請求項１記載の
プラズマエッチング装置。2. The predetermined material constituting the third ring,
2. The plasma etching apparatus according to claim 1, wherein the apparatus is a fluoropolymer. 【請求項３】 前記フッ素系重合体は、テフロンまたは
ベスペル（何れもデュポン社製）であることを特徴とす
る請求項２記載のプラズマエッチング装置。3. The plasma etching apparatus according to claim 2, wherein the fluoropolymer is Teflon or Vespel (both are manufactured by DuPont). 【請求項４】 前記第２リングは、第１の板厚を有する
厚板環状部と、第１の板厚に比して薄い第２の板厚を有
する薄板環状部とを備え、 前記厚板環状部と前記薄板環状部とは、それらの底面が
同一面を形成し、前記厚板環状部が前記薄板環状部の外
周側に位置するように一体的に形成されており、 前記第３リングは、前記薄板環状部の上に、前記厚板環
状部の内壁と接するように配置されることを特徴とする
請求項１乃至３の何れか１項記載のプラズマエッチング
装置。4. The second ring includes a thick annular portion having a first thickness and a thin annular portion having a second thickness smaller than the first thickness. The plate annular portion and the thin plate annular portion are integrally formed such that their bottom surfaces form the same plane, and the thick plate annular portion is located on the outer peripheral side of the thin plate annular portion. 4. The plasma etching apparatus according to claim 1, wherein the ring is arranged on the thin plate annular portion so as to be in contact with an inner wall of the thick plate annular portion. 5. 【請求項５】 前記第３リングは、０．５mm以上２．０
mm以下の幅を有することを特徴とする請求項１乃至４の
何れか１項記載のプラズマエッチング装置。5. The third ring has a diameter of 0.5 mm or more and 2.0 mm or more.
The plasma etching apparatus according to any one of claims 1 to 4, wherein the plasma etching apparatus has a width of not more than mm. 【請求項６】 プラズマエッチング工程を含む半導体装
置の製造方法であって、 前記プラズマエッチング工程は、請求項１乃至６の何れ
か１項記載のプラズマエッチング装置を用いて行われる
ことを特徴とする製造方法。6. A method of manufacturing a semiconductor device including a plasma etching step, wherein the plasma etching step is performed using the plasma etching apparatus according to claim 1. Production method.
JP2000389199A 2000-12-21 2000-12-21 Plasma etching apparatus and method of manufacturing semiconductor device Expired - Fee Related JP3393118B2 (en)

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