JP2002118112A - Manufacturing method of semiconductor device having buried wiring structure - Google Patents
Manufacturing method of semiconductor device having buried wiring structureInfo
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- JP2002118112A JP2002118112A JP2000311724A JP2000311724A JP2002118112A JP 2002118112 A JP2002118112 A JP 2002118112A JP 2000311724 A JP2000311724 A JP 2000311724A JP 2000311724 A JP2000311724 A JP 2000311724A JP 2002118112 A JP2002118112 A JP 2002118112A
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- Prior art keywords
- insulating film
- wiring
- semiconductor device
- metal barrier
- wafer
- Prior art date
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置における
金属配線の形成法、並びに、該金属配線形成法を用いた
埋め込み配線構造を有する半導体装置に関する。The present invention relates to a method for forming a metal wiring in a semiconductor device and a semiconductor device having a buried wiring structure using the metal wiring forming method.
【０００２】[0002]
【従来の技術】ＩＣ、ＬＳＩ等の半導体装置は、高集積
化、微細化と共に配線遅延時間の低減が必要とされてい
る。配線遅延時間は、配線金属の抵抗と絶縁膜の電気容
量の積に比例することから、絶縁膜の比誘電率の低下と
共に、低抵抗の配線金属の利用が不可避である。このこ
とから、配線用金属としてＡｌよりも低抵抗であるＣｕ
へと移行しつつある。2. Description of the Related Art Semiconductor devices such as ICs and LSIs are required to have high integration and miniaturization and to reduce wiring delay time. Since the wiring delay time is proportional to the product of the resistance of the wiring metal and the capacitance of the insulating film, it is inevitable to use a low-resistance wiring metal along with a decrease in the dielectric constant of the insulating film. From this, Cu having lower resistance than Al as a metal for wiring is used.
Is shifting to.
【０００３】しかし、Ｃｕ原子は絶縁膜である酸化シリ
コン膜へ容易に拡散するため、トランジスタ特性の低下
と、絶縁膜の耐電圧を低下させる原因になっており、絶
縁膜とＣｕ配線との間にメタルバリアを形成し、Ｃｕ原
子の拡散を防止することが必要である。However, since Cu atoms easily diffuse into a silicon oxide film which is an insulating film, it causes a decrease in transistor characteristics and a decrease in withstand voltage of the insulating film. It is necessary to form a metal barrier to prevent the diffusion of Cu atoms.
【０００４】また、Ｃｕ表面は酸化し易いために、メタ
ルバリアによって絶縁膜中のＯ原子がＣｕに拡散し酸化
銅になることを阻止しなくてはいけない。Further, since the Cu surface is easily oxidized, it is necessary to prevent O atoms in the insulating film from diffusing into Cu and becoming copper oxide by a metal barrier.
【０００５】さらに、Ｃｕはハロゲン化物の蒸気圧が低
いため、Ａｌ系合金で用いられているハロゲン原子によ
るイオンエッチングが困難なことから、配線の形成には
絶縁膜に溝およびホールを形成した後、その溝およびホ
ールにメッキまたはスパッタによって銅を埋め込むダマ
シン構造をとっている。Further, since Cu has a low vapor pressure of a halide and is difficult to ion-etch with a halogen atom used in an Al-based alloy, wiring is formed after forming grooves and holes in an insulating film. And a damascene structure in which copper is buried in the grooves and holes by plating or sputtering.
【０００６】メッキを用いて多層配線するためには、不
均一に堆積したＣｕをＣＭＰ（Ｃhemical Ｍechanical
Ｐrocessing）によって平坦化させる技術が適用されて
いる。In order to perform multi-layer wiring using plating, unevenly deposited Cu is removed by CMP (Chemical Mechanical).
Technology for flattening by Processing is applied.
【０００７】この方法では、ウエハを研磨剤と化学物質
とを含むスラリを用いて研磨パッドで研磨するため、局
所的に大きな圧力が加わることから、Ｃｕとメタルバリ
アの間、および、Ｃｕと絶縁膜との間の接着力が高くな
いと、これらの界面で剥離が生じ易い。In this method, since a wafer is polished with a polishing pad using a slurry containing an abrasive and a chemical substance, a large pressure is locally applied. If the adhesive strength between the film and the film is not high, peeling is likely to occur at these interfaces.
【０００８】また、メッキで埋めたＣｕ膜は、密度の高
い均一な埋め込みになっていないことから、メッキ後に
２００〜４００℃でアニールされるが、このアニール工
程ではその歪みを解消するようにＣｕが動くことから、
絶縁膜／Ｃｕ／メタルバリアの界面で剥離が起こりき、
ボイドが生ずる。The Cu film buried by plating is annealed at 200 to 400 ° C. after plating because the film is not uniformly buried with high density. In this annealing step, the Cu film is removed so as to eliminate the distortion. Moves,
Peeling occurs at the interface of the insulating film / Cu / metal barrier,
Voids occur.
【０００９】絶縁膜は現在、酸化シリコンまたは炭化水
素を含む酸化シリコンが用いられており、これらの絶縁
膜は通常プラズマＣＶＤ（Ｃhemical Ｖapor Ｄepositi
on）やＳＯＧ（Ｓpin Ｏn Ｇlass）を用いて形成され
る。At present, silicon oxide or silicon oxide containing hydrocarbon is used for the insulating film, and these insulating films are usually formed by plasma CVD (Chemical Vapor Depositi).
on) or SOG (Spin On Glass).
【００１０】絶縁膜形成後、リソグラフィーとエッチン
グにより溝およびホールを形成するが、この工程におい
ては、一般に溝およびホールの形成後、水素でパージし
て大気中にウエハを出したときに、不純物が絶縁膜表面
に付着しないようにする。After the formation of the insulating film, grooves and holes are formed by lithography and etching. In this step, generally, after forming the grooves and holes, impurities are removed when the wafer is discharged into the atmosphere by purging with hydrogen. Do not adhere to the insulating film surface.
【００１１】例えば、水素でパージしなくても、空気中
にウエハを出した時点で、殆ど絶縁膜表面はＨまたはＯ
Ｈで終端され、表面エネルギーは低くなり、メタルバリ
アとして広く使われているＴａ，Ｔｉ，Ｍｏ，Ｃｒ，Ｚ
ｒ，Ｈｆ、および、これらのホウ化物，窒化物のいずれ
とも接着性は良好とは云えない。For example, even when the wafer is taken out into air without purging with hydrogen, almost the surface of the insulating film is H or O
Terminated by H, the surface energy is reduced, and Ta, Ti, Mo, Cr, Z widely used as a metal barrier
Neither r nor Hf, nor any of these borides and nitrides has good adhesion.
【００１２】またこの中で、より接着性の良いメタルバ
リアを使うことになるが、Ｃｕに接着性の良いメタルバ
リアと、酸化シリコンに代表される絶縁膜に接着性の良
いメタルバリアとでは異なるために、前記メタルバリア
としては２，３種の金属を層構造にして用いている。Among these, a metal barrier having better adhesion is used, but a metal barrier having good adhesion to Cu is different from a metal barrier having good adhesion to an insulating film represented by silicon oxide. Therefore, two or three kinds of metals are used in a layer structure as the metal barrier.
【００１３】しかし、スパッタリングで層構造を形成し
ようとすると斑ができ、層間剥がれの原因になる。ま
た、メタルバリア層が厚くなることから、Ｃｕよりも高
抵抗の部分が増え、Ｃｕに替えたことによる抵抗の低減
効果が減少し、Ｃｕを使うメリットがあまりない。ま
た、従来の一層のメタルバリアでは、アニールやＣＭＰ
によって銅とメタルバリアとの間が剥離して、導通不良
の原因を招くことになる。However, when a layer structure is formed by sputtering, spots are formed, which causes peeling between layers. Further, since the thickness of the metal barrier layer is increased, a portion having a higher resistance than Cu is increased, the effect of reducing the resistance by replacing with Cu is reduced, and there is not much merit of using Cu. In addition, in the conventional one layer metal barrier, annealing or CMP
As a result, the copper and the metal barrier are separated from each other, which causes a conduction failure.
【００１４】[0014]
【発明が解決しようとする課題】Ａｌ，Ｃｕの金属配線
の上に被覆膜を形成して、該膜に配線の接続孔を形成
し、接続孔にＷを埋め込む際の上記配線とＷとの導電性
を良好にして、選択ＣＶＤを可能にするため、上記接続
孔にＷを埋め込む前に接続孔の底部のＣｕ面を不活性ガ
スプラズマに曝す技術が知られている（特開平９−８２
７９８号公報，特開平９−２２８９６号公報）。A coating film is formed on an Al or Cu metal wiring, a connection hole for the wiring is formed in the film, and the wiring and the W when the W is embedded in the connection hole are formed. In order to improve the conductivity of the semiconductor device and to enable selective CVD, a technique is known in which the Cu surface at the bottom of the connection hole is exposed to an inert gas plasma before W is buried in the connection hole (Japanese Patent Laid-Open Publication No. 9-1997). 82
798, JP-A-9-22896).
【００１５】しかし、この方法ではＣｕの拡散を防ぐた
めのバリアメタルの接着性が考慮されていない。また、
上記孔の側壁部のダングリングボンドは、終端により消
滅させるものである。However, this method does not consider the adhesion of a barrier metal for preventing the diffusion of Cu. Also,
The dangling bond on the side wall of the hole disappears at the end.
【００１６】本発明の目的は、メタルバリアとシリコン
系絶縁膜との接着不良に基づくアニールやＣＭＰ（Ｃhe
mical Ｍechanical Ｐrocessing）を含む多層構造の剥
離に基づく、非導通の原因となるメタルバリアとシリコ
ン系絶縁膜との接着特性を向上した半導体装置の提供に
ある。An object of the present invention is to provide annealing or CMP (Cheap) based on poor adhesion between a metal barrier and a silicon-based insulating film.
It is an object of the present invention to provide a semiconductor device which has improved adhesion characteristics between a metal barrier and a silicon-based insulating film which cause non-conduction based on peeling of a multi-layer structure including mical mechanical processing.
【００１７】[0017]
【課題を解決するための手段】本発明は、メタルバリア
とシリコン系絶縁膜の接着特性を向上させるために、絶
縁膜に不活性ガスによるスパッタリング、または、Ａｒ
Ｆエキシマレーザ照射（１９３ｎｍ）を行い、絶縁膜の
表面にＳｉ，Ｏのダングリングボンドを形成することに
より、メタルバリアとシリコン系絶縁膜の接着性を上げ
て、両者の界面での剥離を防ぎ、配線の信頼性を向上す
る、埋め込み配線構造を有する半導体装置の製法にあ
る。According to the present invention, in order to improve the adhesion characteristics between a metal barrier and a silicon-based insulating film, sputtering using an inert gas or Ar
Irradiation of F excimer laser (193 nm) to form dangling bonds of Si and O on the surface of the insulating film, thereby increasing the adhesiveness between the metal barrier and the silicon-based insulating film and preventing separation at the interface between the two. And a method of manufacturing a semiconductor device having a buried wiring structure for improving the reliability of wiring.
【００１８】[0018]
【発明の実施の形態】本発明では、半導体基板上に絶縁
膜を形成した後、リソグラフィーとエッチングにより溝
とホールを形成する。In the present invention, after forming an insulating film on a semiconductor substrate, grooves and holes are formed by lithography and etching.
【００１９】溝とホールの形成後は、チャンバ内でＨ2
パージを行なって、新生表面をＨで終端した後、スパッ
タリング装置のチャンバ内にウエハを移す。なお、スパ
ッタリング装置を真空に保ったままでウエハを移動させ
る場合は、絶縁膜表面をＨで終端させる必要はないが、
空気に触れる場合は、空気中の不純物が付着するのを防
ぐためＨで終端することが望ましい。After the formation of the grooves and holes, H 2 is formed in the chamber.
After purging and terminating the nascent surface with H, the wafer is transferred into the chamber of the sputtering apparatus. When the wafer is moved while the sputtering apparatus is kept in a vacuum, it is not necessary to terminate the insulating film surface with H,
When contacting with air, it is desirable to terminate with H in order to prevent impurities in the air from adhering.
【００２０】チャンバ内でウエハ表面を不活性ガスによ
るスパッタリング、または、ＡｒＦエキシマレーザをウ
エハ表面に照射し、Ｓｉ，Ｏ等のダングリングボンドを
形成し絶縁膜表面を活性化させる。In the chamber, the surface of the insulating film is activated by sputtering the surface of the wafer with an inert gas or irradiating the surface of the wafer with an ArF excimer laser to form dangling bonds of Si, O or the like.
【００２１】この絶縁膜表面の活性化の工程と、メタル
バリアの形成工程とが真空のままでウエハを移動できる
ときは、絶縁膜表面の活性化をスパッタリング装置内で
行う必要はない。When the step of activating the surface of the insulating film and the step of forming the metal barrier can move the wafer in a vacuum state, it is not necessary to activate the surface of the insulating film in the sputtering apparatus.
【００２２】その後、必要に応じて加熱やレーザ照射等
により、メタルバリアを溝およびホール内に均一に流動
させる。真空を保ったままスパッタリングによりＣｕを
２０〜５０ｎｍ程度の膜厚に堆積させ後、Ｃｕメッキを
施し、溝およびホールを埋める。次に、本発明を実施例
に基づき説明する。Thereafter, the metal barrier is caused to flow uniformly in the grooves and holes by heating, laser irradiation, or the like, if necessary. After depositing Cu to a thickness of about 20 to 50 nm by sputtering while maintaining a vacuum, Cu plating is performed to fill the grooves and holes. Next, the present invention will be described based on examples.
【００２３】〔実施例 １〕図１に示すように、半導体
基板１上にＳｉＯＣＨ3とメタノールとの混合溶液を塗
布し、焼成することで酸化メチルシリコン２の膜を形成
後、フォトレジストを載せ、リソグラフィー技術により
パターンマスクを形成（図示省略）する。[Embodiment 1] As shown in FIG. 1, a mixed solution of SiOCH 3 and methanol is applied on a semiconductor substrate 1 and baked to form a film of methyl silicon oxide 2 and then a photoresist is placed thereon. Then, a pattern mask is formed by lithography (not shown).
【００２４】これを酸素、または、窒素とフロン系ガス
によりエッチングして溝を形成し、Ｈ2をチャンバ内で
パージしてスパッタリング装置に運ぶまでの間に、不純
物が着かないよう絶縁膜表面をＨで終端する（図１
（ａ））。This is etched with oxygen or nitrogen and a chlorofluorocarbon gas to form a groove, and H 2 is purged in a chamber and the surface of the insulating film is prevented from being contaminated by impurities before being transported to a sputtering apparatus. Terminate at H (Fig. 1
(A)).
【００２５】スパッタリング装置内に移した上記ウエハ
は、真空を保ったままＡｒＦエキシマレーザでウエハ表
面を照射し、表面にＳｉ、Ｏ等のダングリングボンドを
形成する。これにＣｒをターゲットとして、Ａｒガス圧
０.５Ｐａ、基板温度２００℃、ＤＣ電力８ｋＷでスパ
ッタリングを行い、厚さ５０ｎｍのＣｒ膜から成るメタ
ルバリア３を形成する（図１（ｂ））。The wafer transferred into the sputtering apparatus is irradiated with an ArF excimer laser on the surface of the wafer while maintaining a vacuum, and dangling bonds such as Si and O are formed on the surface. Then, sputtering is performed using Cr as a target at an Ar gas pressure of 0.5 Pa, a substrate temperature of 200 ° C., and a DC power of 8 kW to form a metal barrier 3 made of a Cr film having a thickness of 50 nm (FIG. 1B).
【００２６】次いで、真空を保ったままＣｕをターゲッ
トとして、Ａｒガス、圧力０.５Ｐａ、基板温度２５０
℃、ＤＣ電力１０ｋＷの条件で、約２０ｎｍのＣｕ膜で
被覆した後、メッキにより溝に銅４を埋め込む（図１
（ｃ））。Next, while maintaining the vacuum, using Cu as a target, Ar gas, pressure 0.5 Pa, substrate temperature 250
After covering with a Cu film of about 20 nm at a temperature of 10 ° C. and DC power of 10 kW, copper 4 is embedded in the groove by plating (FIG. 1).
(C)).
【００２７】次に、２００℃のオーブンでアニールし、
ＣＭＰによってウエハ表面を平坦化する（図１
（ｄ））。このウエハの断面をＳＥＭ写真で観察したと
ころＣｕ，メタルバリア、絶縁膜の各界面間の剥がれは
生じていなかった。Next, annealing in an oven at 200 ° C.
The wafer surface is planarized by CMP (FIG. 1)
(D)). Observation of the cross section of this wafer with an SEM photograph revealed that no peeling occurred between the interfaces of Cu, the metal barrier, and the insulating film.
【００２８】〔実施例 ２〕実施例１と同様にして、半
導体基板１上に絶縁膜２を形成し、リソグラフィーとエ
ッチングによりホールを形成する。その後、スパッタリ
ング装置内でＡｒをターゲットに当てずに直接ウエハに
当てることにより膜表面をエッチングし、Ｓｉ，Ｏ等の
ダングリングボンドを形成する。[Embodiment 2] As in Embodiment 1, an insulating film 2 is formed on a semiconductor substrate 1, and holes are formed by lithography and etching. After that, the film surface is etched by directly applying Ar to the wafer without being applied to the target in the sputtering apparatus, thereby forming dangling bonds such as Si and O.
【００２９】次いで、Ｔａをターゲットとして、Ａｒガ
ス圧０.８Ｐａ、基板温度２００℃、ＤＣ電力８ｋＷ
で、Ａｒガスを用いて厚さ５０ｎｍのＴａ膜を形成し
た。Then, using Ta as a target, an Ar gas pressure of 0.8 Pa, a substrate temperature of 200 ° C., and a DC power of 8 kW
Then, a Ta film having a thickness of 50 nm was formed using Ar gas.
【００３０】真空を保ったままＣｕをターゲットとして
圧力０.５Ｐａ、基板温℃２５０℃、ＤＣ電力１０ｋＷ
でＡｒガスを用いて約２０ｎｍのＣｕ膜の被膜を形成
後、メッキによりホールを埋め込む。While maintaining the vacuum, Cu was used as a target at a pressure of 0.5 Pa, a substrate temperature of 250 ° C., and a DC power of 10 kW.
After forming a film of a Cu film of about 20 nm using Ar gas, holes are filled by plating.
【００３１】次に、２００℃のオーブンでアニールし、
ＣＭＰによってウエハ表面を平坦化した。ＳＥＭ写真で
このウエハの断面を観察したところ、各界面間の剥がれ
は生じていなかった。Next, annealing is performed in an oven at 200 ° C.
The wafer surface was flattened by CMP. Observation of the cross section of this wafer with an SEM photograph revealed that no peeling occurred between the interfaces.
【００３２】〔比較例 １〕実施例１と同様に、半導体
基板１上に絶縁膜２を形成後、リソグラフィーとエッチ
ングで溝を形成し、Ｈ2パージを行なってＨで絶縁膜表
面を終端する。Comparative Example 1 In the same manner as in Example 1, after forming an insulating film 2 on a semiconductor substrate 1, a groove is formed by lithography and etching, and H 2 purge is performed to terminate the insulating film surface with H. .
【００３３】このウエハに、前処理なしにＣｒをターゲ
ットとし、Ａｒガス圧０.５Ｐａ、基板温度２００℃、
ＤＣ電力８ｋＷでスパッタリングを行い、厚さ５０ｎｍ
のＣｒ膜を形成する。Without subjecting the wafer to Cr as a target, the wafer was subjected to an Ar gas pressure of 0.5 Pa, a substrate temperature of 200 ° C.
Sputtering with DC power 8kW, thickness 50nm
Is formed.
【００３４】次いで、真空を保ったままＣｕをターゲッ
トとし、Ａｒガス圧０.５Ｐａ、基板温度２５０℃、Ｄ
Ｃ電力１０ｋＷで約２０ｎｍのＣｕ膜で被覆後、メッキ
により溝を埋め込む。Then, while maintaining the vacuum, Cu was used as a target, the Ar gas pressure was 0.5 Pa, the substrate temperature was 250 ° C., and D
After covering with a Cu film of about 20 nm at a C power of 10 kW, the groove is filled by plating.
【００３５】２００℃のオーブンでアニールし、ＣＭＰ
によりウエハ表面を平坦化後、このウエハの断面をＳＥ
Ｍ写真で観察したところ、絶縁膜とメタルバリアとの間
に剥離が起こり、ボイドが生じていた。Anneal in an oven at 200 ° C., CMP
After the surface of the wafer is flattened by
Observation with an M-photograph revealed that peeling occurred between the insulating film and the metal barrier, resulting in voids.
【００３６】〔比較例 ２〕実施例２と同様に、半導体
基板１上に絶縁膜２を形成後、リソグラフィーとエッチ
ングでホールを形成し、Ｈ2パージを行なってＨで絶縁
膜表面を終端する。Comparative Example 2 In the same manner as in Example 2, after forming the insulating film 2 on the semiconductor substrate 1, holes are formed by lithography and etching, and H 2 purge is performed to terminate the insulating film surface with H. .
【００３７】このウエハに前処理なしにＴａをターゲッ
トに用い、Ａｒガス圧０.５Ｐａ、基板温度２００℃、
ＤＣ電力８ｋＷでスパッタリングを行い、厚さ５０ｎｍ
のＴａ膜を形成する。次いで、真空を保ったままＣｕを
ターゲットとして、Ａｒガス圧０.５Ｐａ、基板温度２
５０℃、ＤＣ電力１０ｋＷで約２０ｎｍにＣｕ膜で被覆
後、メッキによりホールを埋め込む。Using Ta as a target for this wafer without pretreatment, Ar gas pressure of 0.5 Pa, substrate temperature of 200 ° C.
Sputtering with DC power 8kW, thickness 50nm
Is formed. Then, while maintaining the vacuum, using Cu as a target, an Ar gas pressure of 0.5 Pa, a substrate temperature of 2
After covering with a Cu film to about 20 nm at 50 ° C. and DC power of 10 kW, holes are buried by plating.
【００３８】２００℃のオーブンでアニールし、ＣＭＰ
によりウエハ表面を平坦化後、このウエハの断面をＳＥ
Ｍ写真で観察したところ、絶縁膜とメタルバリアとの間
に剥離が起こり、ボイドが生じていた。Anneal in an oven at 200 ° C.
After the surface of the wafer is flattened by
Observation with an M-photograph revealed that peeling occurred between the insulating film and the metal barrier, resulting in voids.
【００３９】〔比較例 ３〕実施例１と同様に、半導体
基板１上に絶縁膜２を形成後、リソグラフィーとエッチ
ングで溝を形成し、Ｈ2パージを行なってＨで絶縁膜表
面を終端する。Comparative Example 3 In the same manner as in Example 1, after forming the insulating film 2 on the semiconductor substrate 1, a groove is formed by lithography and etching, and H 2 purge is performed to terminate the insulating film surface with H. .
【００４０】このウエハに前処理なしにＭｏをターゲッ
トに用い、Ａｒガス圧０.５Ｐａ、基板温度２００℃、
ＤＣ電力８ｋＷでスパッタリングを行い、厚さ５０ｎｍ
のＭｏ膜を形成する。Using Mo as a target for this wafer without pretreatment, an Ar gas pressure of 0.5 Pa, a substrate temperature of 200 ° C.
Sputtering with DC power 8kW, thickness 50nm
Is formed.
【００４１】次いで、真空を保ったままＣｕをターゲッ
トとして、Ａｒガス圧０.５Ｐａ、基板温度２５０℃、
ＤＣ電力１０ｋＷで２０ｎｍ程度にＣｕ膜で被覆後、メ
ッキにより溝を埋め込む。Next, while maintaining a vacuum, using Cu as a target, an Ar gas pressure of 0.5 Pa, a substrate temperature of 250 ° C.
After covering with a Cu film to about 20 nm at a DC power of 10 kW, the groove is filled by plating.
【００４２】２００℃のオーブンでアニールし、ＣＭＰ
によりウエハ表面を平坦化する。このウエハの断面をＳ
ＥＭ写真で観察したところ、絶縁膜とメタルバリアとの
間に剥離が起こり、ボイドが生じていた。Anneal in an oven at 200 ° C., CMP
To planarize the wafer surface. The cross section of this wafer is S
Observation with an EM photograph revealed that peeling occurred between the insulating film and the metal barrier, and that a void was generated.
【００４３】〔比較例 ４〕実施例１と同様に、半導体
基板１上に絶縁膜２を形成後、リソグラフィーとエッチ
ングで溝を形成し、Ｈ2パージを行なってＨで絶縁膜表
面を終端する。[Comparative Example 4] As in Example 1, after forming an insulating film 2 on a semiconductor substrate 1, a groove is formed by lithography and etching, and H 2 purge is performed to terminate the insulating film surface with H. .
【００４４】このウエハに前処理なしにＨｆをターゲッ
トとして、Ａｒガス圧０.５Ｐａ、基板温度２００℃、
ＤＣ電力８ｋＷでスパッタリングを行い、厚さ５０ｎｍ
のＣｒ膜を形成する。An Ar gas pressure of 0.5 Pa, a substrate temperature of 200.degree.
Sputtering with DC power 8kW, thickness 50nm
Is formed.
【００４５】次いで、真空を保ったままＨｆをターゲッ
トとして、Ａｒガス圧０.５Ｐａ、基板温度２５０℃、
ＤＣ電力１０ｋＷで２０ｎｍ程度にＣｕ膜で被覆した
後、メッキにより溝を埋め込む。Next, while maintaining the vacuum, using Hf as a target, an Ar gas pressure of 0.5 Pa, a substrate temperature of 250 ° C.
After covering with a Cu film to about 20 nm at a DC power of 10 kW, the groove is filled by plating.
【００４６】２００℃のオーブンでアニールし、ＣＭＰ
によりウエハ表面を平坦化する。このウエハの断面をＳ
ＥＭ写真で観察したところ、絶縁膜とメタルバリアとの
間に剥離が起こり、ボイドが生じていた。Anneal in an oven at 200 ° C., CMP
To planarize the wafer surface. The cross section of this wafer is S
Observation with an EM photograph revealed that peeling occurred between the insulating film and the metal barrier, and that a void was generated.
【００４７】〔比較例 ５〕実施例１と同様に、半導体
基板１上に絶縁膜２を形成後、リソグラフィーとエッチ
ングで溝を形成し、Ｈ2パージを行なってＨで絶縁膜表
面を終端する。Comparative Example 5 In the same manner as in Example 1, after forming the insulating film 2 on the semiconductor substrate 1, a groove is formed by lithography and etching, and H 2 purge is performed to terminate the insulating film surface with H. .
【００４８】このウエハに前処理なしにＨｆをターゲッ
トとして、圧力０.８Ｐａ、基板温度２００℃、ＤＣ電
力８ｋＷで、Ａｒガスを用いて厚さ５０ｎｍのＨｆ膜を
形成する。An Hf film having a thickness of 50 nm is formed on this wafer at a pressure of 0.8 Pa, a substrate temperature of 200 ° C., a DC power of 8 kW and Ar gas using Hf as a target without any pretreatment.
【００４９】次いで、真空を保ったままＣｕをターゲッ
トとしてＡｒガス圧０.５Ｐａ、基板温度２５０℃、Ｄ
Ｃ電力１０ｋＷで約２０ｎｍにＣｕ膜で被膜させた後、
メッキにより溝を埋め込む。Next, while maintaining a vacuum, using Cu as a target, an Ar gas pressure of 0.5 Pa, a substrate temperature of 250 ° C.,
After coating with a Cu film to about 20 nm at a C power of 10 kW,
The groove is buried by plating.
【００５０】２００℃のオーブンでアニールし、ＣＭＰ
によりウエハ表面を平坦化後、ＳＥＭ写真でこのウエハ
の断面を観察したところ、絶縁膜とメタルバリアとの間
に剥がれが起こり、ボイドが生じていた。Anneal in an oven at 200 ° C.
After the wafer surface was flattened, the cross section of the wafer was observed with an SEM photograph. As a result, peeling occurred between the insulating film and the metal barrier, and voids were generated.
【００５１】実施例１，２と比較例１〜５とから分かる
ように、Ａｒによる絶縁膜表面のエッチング、または、
ＡｒＦエキシマレーザ照射、あるいは、ＳｉＯ2系のタ
ーゲットを用い、ＳｉＯ2系の膜を絶縁膜表面に新たに
形成した場合は、それぞれのメタルバリアとの接着性は
良好で、アニールとＣＭＰ後でも絶縁膜とメタルバリア
との間に剥がれは生じない。しかし、メタルバリアをス
パッタする前にこれらの処理を行わない場合は剥がれを
生ずる。As can be seen from Examples 1 and 2 and Comparative Examples 1 to 5, etching of the insulating film surface with Ar, or
When ArF excimer laser irradiation or a SiO 2 -based target is used and a SiO 2 -based film is newly formed on the insulating film surface, the adhesion to each metal barrier is good, and the insulation is maintained even after annealing and CMP. No peeling occurs between the film and the metal barrier. However, if these processes are not performed before the metal barrier is sputtered, peeling occurs.
【００５２】従って、メタルバリアをスパッタする前
に、絶縁膜表面を活性化する工程を入れることにより、
配線の信頼性を向上できると云う効果がある。Therefore, before the metal barrier is sputtered, a step of activating the surface of the insulating film is provided.
There is an effect that the reliability of the wiring can be improved.
【００５３】比較例１〜５で作製した銅配線を有する半
導体装置に対し、実施例１，２で作製した銅配線を有す
る半導体装置では、全工程を終えた後での非導通による
不良の割合を８５％以上回避できることを確認した。In contrast to the semiconductor device having the copper wiring manufactured in Comparative Examples 1 to 5, in the semiconductor device having the copper wiring manufactured in Examples 1 and 2, the percentage of defects due to non-conduction after completing all the steps. It was confirmed that 85% or more could be avoided.
【００５４】[0054]
【発明の効果】本発明では、メタルバリアをスパッタリ
ングによって形成する前にＡｒによる絶縁膜表面のスパ
ッタリング、または、ＡｒＦエキシマレーザ照射によ
り、配線用溝およびホールの表面にダングリングボンド
を形成することにより、メタルバリアとの接着性を高め
ることができる。According to the present invention, before the metal barrier is formed by sputtering, the dangling bond is formed on the surface of the wiring groove and the hole by Ar sputtering of the insulating film surface or by ArF excimer laser irradiation. , The adhesion to the metal barrier can be enhanced.
【００５５】これにより、その製造工程におけるＣＭＰ
やアニールと云った界面間に歪み応力が加わる工程にも
耐え得るため、信頼性の高い半導体装置を得ることがで
きる。As a result, CMP in the manufacturing process
Since it can withstand a process in which strain stress is applied between interfaces such as annealing and annealing, a highly reliable semiconductor device can be obtained.
【図１】本発明の一実施例の工程を説明する模式断面図
である。FIG. 1 is a schematic cross-sectional view illustrating a process of one embodiment of the present invention.
１…半導体基板、２…絶縁膜、３…メタルバリア、４…
銅。DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Insulating film, 3 ... Metal barrier, 4 ...
copper.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 田子 一農 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 Ｆターム(参考） 5F033 HH11 HH17 HH21 MM01 MM12 MM13 PP15 PP26 PP33 QQ09 QQ11 QQ48 QQ54 QQ73 RR25 SS22 XX14 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazunori Tago 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture F-term in Hitachi Research Laboratory, Hitachi Ltd. 5F033 HH11 HH17 HH21 MM01 MM12 MM13 PP15 PP26 PP33 QQ09 QQ11 QQ48 QQ54 QQ73 RR25 SS22 XX14
Claims (3)
配線用溝およびホールを形成する工程と、前記配線用溝
およびホールの表面（ホール内の側面と底面）をメタル
バリアにより被覆する工程との間に、配線用溝およびホ
ールの表面を活性化させる工程を含む埋め込み配線構造
を有する半導体装置の製法。1. After forming an insulating film on a semiconductor substrate,
Activating the surfaces of the wiring grooves and holes between the step of forming the wiring grooves and holes and the step of covering the surfaces (side surfaces and bottom surfaces in the holes) of the wiring grooves and holes with a metal barrier A method for manufacturing a semiconductor device having a buried wiring structure including steps.
化させる工程が、不活性ガスプラズマに曝すか、また
は、ＡｒＦエキシマレーザ（１９３ｎｍ）を照射してダ
ングリングボンドを形成する請求項１に記載の埋め込み
配線構造を有する半導体装置の製法。2. The method according to claim 1, wherein the step of activating the surface of the wiring groove and the hole forms a dangling bond by exposing to an inert gas plasma or irradiating an ArF excimer laser (193 nm). A method of manufacturing a semiconductor device having the embedded wiring structure according to the above.
成した埋め込み配線構造を有する半導体装置。3. A semiconductor device having an embedded wiring structure formed by the method according to claim 1.
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|---|---|---|---|
| JP2000311724A JP2002118112A (en) | 2000-10-05 | 2000-10-05 | Manufacturing method of semiconductor device having buried wiring structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000311724A JP2002118112A (en) | 2000-10-05 | 2000-10-05 | Manufacturing method of semiconductor device having buried wiring structure |
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| Publication Number | Publication Date |
|---|---|
| JP2002118112A true JP2002118112A (en) | 2002-04-19 |
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ID=18791441
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|---|---|---|---|
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004134771A (en) * | 2002-09-17 | 2004-04-30 | Advanced Lcd Technologies Development Center Co Ltd | Interconnection, method for forming the interconnection, thin-film transistor and indicating device |
| JP2004335847A (en) * | 2003-05-09 | 2004-11-25 | Mitsubishi Electric Corp | Method for manufacturing semiconductor integrated circuit wafer |
| JP2005340478A (en) * | 2004-05-26 | 2005-12-08 | Toshiba Corp | Manufacturing method of semiconductor device |
| US7563705B2 (en) | 2002-02-14 | 2009-07-21 | Nec Electronics Corporation | Manufacturing method of semiconductor device |
| WO2010147141A1 (en) * | 2009-06-16 | 2010-12-23 | 東京エレクトロン株式会社 | Film deposition method, pretreatment device, and treating system |
-
2000
- 2000-10-05 JP JP2000311724A patent/JP2002118112A/en not_active Withdrawn
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7563705B2 (en) | 2002-02-14 | 2009-07-21 | Nec Electronics Corporation | Manufacturing method of semiconductor device |
| JP2004134771A (en) * | 2002-09-17 | 2004-04-30 | Advanced Lcd Technologies Development Center Co Ltd | Interconnection, method for forming the interconnection, thin-film transistor and indicating device |
| JP4495428B2 (en) * | 2002-09-17 | 2010-07-07 | 株式会社 液晶先端技術開発センター | Method for forming thin film transistor |
| JP2004335847A (en) * | 2003-05-09 | 2004-11-25 | Mitsubishi Electric Corp | Method for manufacturing semiconductor integrated circuit wafer |
| JP2005340478A (en) * | 2004-05-26 | 2005-12-08 | Toshiba Corp | Manufacturing method of semiconductor device |
| JP4660119B2 (en) * | 2004-05-26 | 2011-03-30 | 株式会社東芝 | Manufacturing method of semiconductor device |
| WO2010147141A1 (en) * | 2009-06-16 | 2010-12-23 | 東京エレクトロン株式会社 | Film deposition method, pretreatment device, and treating system |
| US8865590B2 (en) | 2009-06-16 | 2014-10-21 | Tokyo Electron Limited | Film forming method, pretreatment device, and processing system |
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